Post by MacroMachines » Sat Feb 11, 2017 3:03 am

1) it is very useful to have the ability to access blocks of memory without inherent circulating buffer addressing. I do agree that most common applications of delays, reverbs, and pitch shifting can benefit from the ease of simply writing and reading from a different point in the block. However, some of my favorite DSP techniques require a bit more control of the memory usage. For one, I recently created a pitch harmonizer that finds wave-cycles of 2 zero crossing pairs and uses the duration to shift the incoming pitch into a strictly tuned harmonic interval (IE. play any note in and the processing locks the pitch to a C# with the same formant/texture, thus making automated harmonies around vocals or specific chord qualities around a solo performance guitar lead, this could of course be used for auto-tune as well).

Another technique I have been finding very rich territory is a form of PSOLA or granular processing, and aside from its experimental uses can be central to creating infinite sustain effects. I have some tests of this on my instagram:



https://www.instagram.com/p/BNf9BNIAS4j ... romachines

this effect uses a trick that took me a while to fully perfect, in which I cancel out the inherent delay memory address circulation using a counter register and bitwise OR-ing a precise value beyond the resolution of the 11 bit SOF offset coefficient. I then have to make a second counter which adds the same bit and resets read points using either XOR or SKP instructions, essentially a ramp LFO but with more flexibility and precision. If there were simply an opcode to deactivate circulation, or better yet, one that directly addresses a position in memory without using the circulation phasor, this would make such techniques easier to access, and open up a fair bit of possibilities.



2) if I am not mistaken, It appears that the current spec sheet is using the same size of overall delay RAM, and I though I have been happy with the results of this <1second memory space, I suggest adding as much as possible to offer potential long looping style delays. Alternately having the ability to either add external RAM expansion readily (ideally with flexible size options, or possibly FRAM for non volatile looping/sampling).



3) the ability to set pot input hysteresis levels, even if only a couple options (say none/20ms/60ms/120ms? or just the ability to turn it off? its easy enough to add lowpass in code, and very difficult to regain speedy response . The 100ms constant of the FV-1 is just a bit too high for quality pitch sequencing. I have found ways around this, but I believe it would be nice to lower the inherent hysterisis to 20ms at least.

Ok coolmaybe it will come together in time for a mark2 or second tier product line in a year and a half or so, that would be rad.Ive been getting some very interesting things with the FV-1, I think I have found some useful techniques. I would like to put forth a couple suggestions here if I may, in light of caviats I have been finding in the FV-1 limitations:I very much look forward to this. built in EEPROM is pretty sweet, ++ on the 6 pots! Im very curious what will be possible with I2S. I have an ARM/ i2s codec prototype that would make a great companion.Cheers!