The advent of photonic technologies, in particular in the area of optical signalling, coupled with advances made in nanofabrication capabilities has created a growing need for practical all-photonic memories3,7,8,9,10. Such memories are essential to supercharge computational performance in serial computers by speeding up the von Neumann bottleneck, that is, the information traffic jam between the processor and memory. This bottleneck limits the speed of almost all processors today, and has already led to the introduction of multicore processor architectures and drives the search for viable on-chip optical interconnects. However, shuttling information optically from the processor to electronic memories is not efficient at present, because electrical signals have to be converted to optical signals and vice versa. Information transfer and storage exclusively by optical means is therefore highly desirable because of the inherently large bandwidth1,3, low residual crosstalk and high speed of optical information transfer. On a chip this has been challenging to achieve, because practical photonic memories would need to retain information for long periods of time and require full integration with the ancillary electronic circuitry, thus requiring compatibility with semiconductor processing11.

Phase-change materials (PCMs) are ideal candidates for all-optical memories. They have already been the subject of intense research and development over the last decade, but in the context of electronic memories12,13,14. A striking and functional feature of these materials is the high contrast between the crystalline and amorphous phases of both their electrical and optical properties15,16. In particular, chalcogenide-based PCMs have the ability to switch between these two states in response to appropriate heat stimuli (crystallization) or melt-quenching processes (amorphization)17. These PCMs, mainly tellurides and antimonides, can be switched on a subnanosecond timescale15,18 with high reproducibility, enabling ultrafast operation over 1012 switching cycles14,16 using current-generation materials. (With new and improved materials, such as the so-called phase-change superlattice materials19, even better performance is expected in the future.) In addition, at normal operating temperatures the states are highly stable for years15,20, a key requirement for a truly non-volatile memory. These beneficial properties of PCMs have already led to prominent commercial applications in optical data storage such as rewritable optical discs (in DVD and Blu-ray formats)21 and more recently for use in optoelectronic modulation and display applications in the visible spectrum22.

Many PCMs show a significant change in refractive index in the visible regime and even larger changes in the near-infrared wavelength regime, which is the spectral region of choice for telecommunication applications23,24,25,26. Here, by using such nanoscale PCMs embedded in nanophotonic circuits, we demonstrate that fast and repeatable all-optical, multi-level, multi-bit, non-volatile memory operations, with wavelength division multiplexed (WDM) access, can be achieved on a chip at telecommunications wavelengths compatible with on-chip optical interconnects. In contrast to free-space optical implementations where PCM cells are switched with a focused laser in the far field, our devices are operated in the optical near field, in analogy to plasmonic devices. Our waveguide integrated memory cells are therefore not restricted in size by the diffraction limit of the input light and can hence be miniaturized to nanoscale dimensions. We use the well-studied alloy Ge 2 Sb 2 Te 5 (GST) because of its data retention capabilities15,17 and high state discrimination23 down to nanoscale cell sizes, which enables dense packaging and low-power memory switching. In our devices, data are stored in a nanoscale GST cell placed directly on top of a nanophotonic waveguide. Both writing into the memory cell and readout of the stored information is carried out via evanescent coupling to the PCM and is thus not subject to the diffraction limit. Also, because this is done directly within the waveguide using nanosecond optical pulses, our approach provides a promising route towards fast all-optical data storage in photonic circuits.

The geometry of our memory cell and the operating principle are shown schematically in Fig. 1a. Information is stored in the GST (yellow region) by making use of evanescent coupling between light travelling along the waveguide and the GST element. This interaction results in the absorption of optical power due to the non-vanishing complex refractive index of the GST. As illustrated in Fig. 1b, the crystalline state (which we term ‘Level 0’) exhibits higher attenuation and thus less optical transmission than the amorphous state (‘Level 1’). Therefore, stored data are encoded in the amount of light transmitted through (along) the waveguide (that is, exiting the end of the waveguide) and can be read out with low-power optical pulses (red trace in Fig. 1a). The phase state of the memory element influences the optical properties of the propagating light field and therefore the waveguide mode profile, as illustrated for the simulated transverse electric (TE) mode in Fig. 1d. In the crystalline state, the PCM is more absorptive, thus pulling the light towards the GST cell and leading to strong attenuation of the passing optical signal. In the amorphous phase, on the other hand, the absorption is reduced and the GST film does not attenuate the waveguide transmission to the same degree. Writing into the memory or erasing the stored information is achieved by inducing a phase transition with a more intense light pulse (blue arrows in Fig. 1b, Write/Erase). If the energy absorbed by the GST is high enough to heat it to its transition temperature, these pulses can initiate either amorphization (Write) or crystallization (Erase). For amorphization, the GST is melted and then cooled rapidly to preserve this disordered state. Heating the GST above the crystallization temperature (but below the melting temperature) for a few nanoseconds15 enables recovery of the atomic ordering and thus crystallization. Our scheme is thus the photonic equivalent of resistive memories, whereby transmission (equivalent to conduction) is modulated by varying the absorptive state (conductivity) of the material, and is different from the phenomenon used in conventional optical storage (where reflectivity is modulated). In this Letter we describe three distinct and key aspects of our devices: (1) an all photonic non-volatile memory element, (2) the addressing of several disjoint elements using wavelength multiplexing to deliver multi-bit access, and (3) the storage of multi-levels of memory in a single memory cell, including single-shot read and write.

Figure 1: Operation principle of the all-optical on-chip memory device. a, Information is stored in the phase state of the GST section on top of the nanophotonic waveguide. Both reading and writing of the memory can be performed with ultrashort optical pulses because the guided light interacts with the GST via its evanescent field. In the readout, data are encoded in the amount of optical transmission through (along) the waveguide because the two crystallographic states of the GST exhibit a high contrast in optical absorption. b, As shown in the level scheme, less optical power is transmitted through the waveguide if the GST is in the crystalline state (Level 0) than when it is in the amorphous state (Level 1). Memory is written (Write) and erased (Erase) with intense optical pulses that initiate a phase transition within the GST. c, Scanning electron microscope image of a fabricated device with a footprint of 0.4 × 0.4 µm2. d, Waveguide cross-section with simulated TE optical mode evanescently coupled to amorphous GST. Full size image

The fabricated on-chip memory elements are operated using an optical pump–probe set-up as described in the Methods and Supplementary Section 1. Both writing and erasing of the memory are performed with nanosecond light pulses generated off-chip (for experimental expediency only) with an electro-optical modulator (EOM) and subsequently coupled into the on-chip waveguides. Readout is performed both with subnanosecond readout pulses (500 ps, generated with the EOM) and with continuous-wave (c.w.) light, in both cases with at least one order of magnitude less power than the Write pulse. To separate the readout (λ probe = 1,570 nm) from the Write/Erase pulses (λ pump = 1,560 nm), a colour-selective filter (Pritel TFA-1550) with a spectral extinction ratio in excess of 40 dB is used. Further suppression of the pump light is achieved by letting the pump and probe light waves counterpropagate through the photonic circuitry.

Figure 2a shows the change in readout transmission upon repeated switching between the crystalline (low transmission) and amorphous (high transmission) states of the GST. Each event that results in a change in transmission (termed ‘switching’ hereon) represents the single-shot readout of the state (Levels 0 or 1). The results demonstrate unequivocal binary data storage in our photonic memory chips, with good reversibility and high transmission contrast. As illustrated in Fig. 2b, the switching process is highly reproducible over 50 cycles with a measured confidence interval (shaded area) of ±7.1%. The low-transmission state (Level 0) is initially prepared from the fully crystallized phase in such a way that reversibility of the operation is ensured (Methods). However, the absolute transmission at Level 1 is determined by the switching energy employed, which defines the final level of amorphization, and the GST dimension along the waveguide, which defines the modulation depth. In Fig. 2, to ensure high transmission contrast between the amorphous and crystalline states we use a cell of 5 µm length. With this device, a change in readout transmission of 21% is achieved using a single 100 ns write pulse of 533 pJ energy. Because the GST cell absorbs nearly 80.7% of the pulse in the crystalline state (derived from a measured optical attenuation of −7.14 dB past the device), this corresponds to a switching energy of 430 pJ. Further demonstrations of binary operation were realized by using devices with smaller GST lengths and lower Write pulse energy, as described in Supplementary Section 5. In particular, a modulation depth up to 58.2% and binary operation with pulses as short as 10 ns with switching energies of 13.4 pJ (Supplementary Section 4) has been achieved. The data in Fig. 2 demonstrate the non-volatility of our memory over a period of several minutes (see time bar in Fig. 2a). In Supplementary Section 8 we confirm that the phase state is preserved over a much longer period, up to at least three months. Indeed, extrapolating from the well-studied data retention properties of GST15,20, our all-optical memory can be expected to remain non-volatile on a timescale of years.

Figure 2: Reversible and reproducible single-shot switching. a, Demonstration of binary memory operation between the crystalline (lower, Level 0) and amorphous (upper, Level 1) state of a 5 µm GST device with a total change in readout transmission of 21%. The Write step (blue) is initiated by a single 100 ns pulse, whereas for the Erase step (red), a fixed sequence of six consecutive 100 ns pulses with decreasing powers is used (Methods and Supplementary Section 4). Time scale bar, 1 min. b, Multiple repetitions of the same switching cycle as in a. The dark and light shaded areas represent one and two standard deviations, respectively. c, TEM image of a cross-section through a memory cell in the crystalline state. d, Fourier analysis of the TEM image for the memory device in the crystalline state in c, showing clear features of the ordered lattice structure. e, Fourier analysis of TEM data from a device optically switched into the amorphous state, showing a pronounced halo expected for the amorphous phase. Full size image

In the present devices, amorphous GST exhibits nearly five times lower optical attenuation than crystalline GST. This conveniently allows the use of pulses within the same energy range when switching back and forth between states. One pulse can initially induce amorphization, while a second identical pulse will either keep the same state or partially crystallize the PCM device, because the resulting Joule heating leads to lower temperatures for the second pulse compared to the first one (because the GST is in the amorphous phase after the first pulse) and melting may not take place. For the Erase process to go back to Level 0, a train of consecutive pulses is used with gradually decreasing power, as described in the Methods.

The optical switching of our memory element was further confirmed by high-resolution transmission electron microscopy (HRTEM). We prepared devices in both the amorphous and crystalline phases using the optical switching processes outlined above. A thin lamella along the direction of propagation in the waveguide was cut through the GST section for TEM imaging, as described in the Methods and Supplementary Section 7. In the images, the deposited GST layer and the indium tin oxide (ITO) layer can be seen (indicated in Fig. 2c). The measured thickness for each layer is ∼10 nm, as expected from the deposition rates. The HRTEM image in Fig. 2c also clearly shows the crystalline phase written into (the GST element of) this device. To further illustrate the crystal order, the Fourier transform of Fig. 2c is shown in Fig. 2d, where the diffractogram reveals the features of cubic GST. Figure 2d shows a diffractogram of the device written into the amorphous state, where the presence of only diffuse halos confirms amorphization (for an HRTEM image of a device in the amorphous state see Supplementary Section 7).

Besides repeatability, speed is an integral part of all memory devices, and the speed at which Read, Write and Erase operations can be achieved in a single memory element is important. In our photonics memory cell, the readout relies on photon absorption because information is encoded in the amount of power transmitted through the waveguide. Hence, the readout can be performed on picosecond timescales and is therefore not a crucial bottleneck to achieving high-speed operation. On the other hand, Write and Erase are linked both to amorphization and crystallization times, which are intrinsic properties of the GST cell and have been reported to take place at picosecond18 (amorphization) and nanosecond to subnanosecond27 (crystallization) timescales, respectively. In our case, the writing speed (amorphization) is the more stringent requirement as it determines how quickly information can be stored. As outlined above, we were able to switch with pulses as short as 10 ns. To determine how fast our memory might be operated, we monitored the phase transition by performing time-resolved measurements during optical switching. The observed transient behaviour is presented in Supplementary Fig. 7, where we analyse the switching dynamics and the speed of the PCM photonic memory. As well as the length of the Write pulse, the speed of the device is also limited by the post-excitation relaxation time (which we call the dead time). For 700 ps Write pulses we obtain an operation speed of 800 MHz (taking pulse length and dead time into account). Further details of this analysis are presented in Supplementary Section 3, from which we expect that writing speeds of a few gigahertz can be achieved by using picosecond instead of nanosecond pulses28.

We now take our memory concept a step further by illustrating how single-cell access in a multi-bit, multi-wavelength device can be realized. The simplicity of our all-optical memory approach, with a PCM storage element coupled evanescently to a waveguide, makes it fully compatible with on-chip nanophotonic circuitry, so allowing for easy integration and exploitation of a wide range of commonly used optical signal processing techniques such as WDM approaches. Here, we show a wavelength-multiplexed integrated multi-bit architecture with ultrafast readout and up to 10 dB modulation depth. Our approach relies on the wavelength-filtering property of on-chip optical cavities, which enables wavelength-selective addressing of individual, non-volatile memory elements (wavelength selectivity via the use of optical cavities was demonstrated recently by Kuramochi et al.3 for volatile memories with a storage ‘lifetime’ in the nanosecond range; our device, in contrast, demonstrates this in a non-volatile memory with a nominal lifetime counted in years).

We demonstrate that three memory cells can be wavelength-selectively operated (that is, written, erased and read) through one single waveguide by embedding GST elements (footprint of 1 × 1 µm2) into three ring resonators coupled to the waveguide, as shown in Fig. 3a. Because cavity internal interference prevents off-resonance wavelengths from entering a ring, only light close to resonance can be used to switch or read out the respective memory cell. Wavelength-selective operation is thus made possible by slightly detuning the ring resonances, which can, for example, be achieved by designing the ring radii differently. By doing so, we observe, as presented in Fig. 3b, groups of three clearly separated resonance peaks in the device transmission. To switch the individual memory cells we thus use laser pulses at 1,560.1, 1,561.5 and 1,563.35 nm, respectively. Write is carried out with a single 10 ns pulse, while repeatability is again ensured by performing Erase with a train of consecutive 50 ns pulses of decreasing energy. Figure 3c shows the individual changes in the three resonances upon switching, a result of the modified refractive index of the GST elements. The left panel of Fig. 3c demonstrates that the initial state is recovered after one Write/Erase cycle, and the right panel clearly shows that each memory element can be addressed individually (the pulse on resonance leads to amorphization of the respective GST element, while the other memory cell is clearly unaffected). Figure 3d further shows that each memory entry can be read out individually with 500 ps pulses, with a pulse energy of 0.48 ± 0.03 pJ. Here, pulses at three distinct wavelengths (1,560.0, 1,561.45 and 1,563.3 nm, respectively) are used to probe the cell transmission (and thus the memory entry) of the cavity at the respective wavelength. The readout pulses are red-detuned from the wavelength of the pump pulse onto the slope of the cavity resonance to maximize the readout contrast upon switching. We achieve a modulation depth of 3 dB on switching each individual memory cell while at the same time the readout level of the non-addressed memory elements does not change. In Supplementary Section 6 we further show that, with this approach, modulation depths exceeding 10 dB are possible.

Figure 3: A multi-bit, multi-wavelength architecture. a, Scanning electron microscope micrograph of the device under test. Light is coupled in and out of the on-chip circuitry by means of the focusing grating couplers at the lower left and right. The GST elements of 1 × 1 µm2 footprint are embedded (dotted circles) within the (false-coloured) ring resonators, which are all separated from the central waveguide by a gap of 300 nm. Three different ring radii are used to ensure spectral separation of the cavity resonances. b, In device transmission, groups of three distinct resonances, corresponding to the respectively coloured rings, are observed. Using optical pulses close to resonance (indicated by coloured arrows), each cell is addressed selectively. c, The changes in transmission for an individual element after Write/Erase cycling (left panel). Cells can be individually addressed, leaving other cells unaffected (right panel). d, Wavelength-selective readout of individual cells using 500 ps pulses. Switching of a memory cell modifies exclusively the transmitted power of the pulse at the corresponding readout wavelength. Each trace is normalized to its initial readout level. The horizontal dotted lines indicate potential decision levels between the two states. Full size image

We next discuss the potential of our optical cell for future high-density data storage by reducing the overall dimensions of the memory element and using multi-level access (that is, storing multiple bits per memory element) in a single cell. The smallest realized memory element has a footprint of 0.25 µm2 (Supplementary Fig. 7a, inset). We expect that even smaller cells could be operated in accordance with recent reports on electrical PCM-based devices14,29. Here, we show that our memory element not only has a small footprint, but is also capable of multi-level storage in a single cell, using simple but extremely effective write/erase and read techniques. Using optical Write/Erase pulses with varying pulse energy we are able to freely and reliably move between these intermediate levels with high repeatability. This multi-level operation relies on the freely accessible intermediate crystallographic states of the GST, that is, states with a mixture of crystalline and amorphous regions. These mixed states exhibit optical transmission properties lying between those of the Level 1 and Level 0 shown in Fig. 1b. The number of additional memory levels can be defined by tailoring the degree of crystallization within a single cell. Such multi-level operation is demonstrated in Fig. 4a–c for four clearly distinct levels. The presented data are recorded in a 5-µm-long PCM element, with each transition between levels being initiated by a single 100 ns light pulse. Four clearly distinguishable levels are reached with pulses P i of level-specific energies in the range 465–585 pJ (see figure caption for details). In Fig. 4a these levels were reached in a serial manner, and subsequently the Erase operation was carried out from Level 3. The same bit levels were also shown to be accessible in a random order, as shown in Fig. 4b. Here, the Erase operation (that is, a return to Level 0) was not only possible from the highest transmission state, but from any intermediate level (as shown in Fig. 4c). These results demonstrate that both Write and Erase operations, to and from any level, are possible with high accuracy, allowing reliable multi-bit memory operation. This exciting aspect of our photonic memories is particularly attractive because such arbitrary transitions are very difficult to achieve in electronic memories employing PCMs, where iterative write-and-erase algorithms involving multiple (typically 3–5) write/read(/re-write) cycles are needed to achieve a predefined level, adversely affecting the overall write speed and power consumption30.

Figure 4: Multi-level operation of the all-photonic memory element. a–c, Four clearly distinguishable levels are reached with 100 ns Write pulses P i of level-specific energy E P1 = 465 ± 13 pJ, E P2 = 524 ± 14 pJ and E P3 = 585 ± 14 pJ in a 5 µm GST device. The Erase step consists of a train of pulses with decreasing energy as described in Supplementary Section 4. Levels are shown to be accessible in consecutive (a) or arbitrary (b) ascending order by the respective Write pulses P i . Each level can also be independently reached and erased (c). Scale bars in a–c, 20 s. d, Reducing the confidence interval of each level (shaded area) by increasing the readout power by a factor of 10 enables the device in a–c to be operated with eight levels. This also implies a renormalization in transmission that leads to different figures for the change in readout. In addition, it is shown that each level can be reached from a higher level by applying a partial Erase, denoted R n−m (Supplementary Section 4). Therefore, each level can be accessed directly from any other level. The energies for the pulses P i are those leading to level i in e, following the same colour scheme (E P1 = 372 ± 12 pJ, E P2 = 415 ± 13 pJ, E P3 = 465 ± 13 pJ, E P4 = 524 ± 14 pJ, E P5 = 561 ± 14 pJ, E P6 = 585 ± 14 pJ and E P7 = 601 ± 15 pJ). e, Relation between used pulse energy, addressed level and corresponding change in readout transmission for the Write operations used in d. Error bars show uncertainty in level attainability. Full size image

The number of possible levels in a memory cell is limited by the separation (difference in transmission) between the highest and lowest state and the required confidence interval of an intermediate level. The former can be increased by using either a larger memory cell or higher pulse energies. The confidence interval, on the other hand, is mainly limited by the minor variations in the switching and by the signal-to-noise ratio (SNR) of the readout measurement. The number of memory levels can therefore be increased by just using a higher readout power, ensuring a better SNR (within limits). This is demonstrated in Fig. 4d, where we demonstrate eight levels of state discrimination (that is, three bits per cell) within a single photonic memory cell. Each level corresponds to a partial crystalline state, presenting a specific change in transmission by applying pulses with varying energies as presented in Fig. 4e. The individual levels are reached with pulses P i of level-specific energies in the range 372–601 pJ (see figure caption for details). In Fig. 4d it can also be observed that the difference between the transmissions of any two consecutive levels is much higher than the uncertainty marked by the colour-coded background. In Fig. 4d it is also demonstrated that each level can be reached from both directions, that is, with an amorphization as well as a crystallization step. This implies that any level is accessible from all others, with very accurate control of the transmission levels and remarkable repeatability (as seen by the accurate re-writing of Levels 1–4 in Fig. 4d), just by applying the appropriate Write or Erase pulse. Such capabilities provide a huge leap forward in terms of functionality and will be crucial for the realization of practicable photonic memories.

Finally, we address another crucial aspect of data storage, that is, energy consumption per bit. Because in our memory cell both writing and erasing rely on phase transitions of the PCM, the switching energy is given by the amount of energy that is required to heat the GST above the melting (amorphization) or glass transition (crystallization) temperatures, respectively. Therefore, the energy consumption is directly related to the volume of the memory element and readout contrast. This relationship between switching energy and readout contrast is shown in Fig. 4e. In binary operation we achieved a readout contrast of 21% with 430 pJ switching energy (cf. Fig. 2). On the other hand, we measured switching energies as low as 13.4 pJ for a reduced contrast of 0.7%, which still enabled clear distinction of the two levels (Supplementary Section 5). In addition, we estimate that energy consumption can be improved by up to one order of magnitude by operating the memory with subnanosecond instead of tens-of-nanoseconds pulses. In our thermo-optical analysis in Supplementary Section 2 we observe that the portion of absorbed energy that gets lost due to thermal diffusion increases significantly with increasing pulse length. Therefore, shorter and more intense pulses are also beneficial in terms of energy requirements by quickly heating up the PCM to the required transition temperature while reducing thermal diffusion losses.

In this very first prototype of our photonic PCM-based memory, the energy consumption and speed achieved in our experiments compares well with pre-existing electrical counterparts. For example, current commercial PCM-based electrical memories (at the 45 nm node) typically require write pulses of 50–100 ns duration and read pulses of 10 ns (considerably longer than the 10 ns/500 ps write/read for our photonic memory), as well as 5–10 pJ write energy (cf. ∼13 pJ here). Although research-level devices improve on such performance figures (for example, 3.4 pJ write energy and 20 ns write pulses in ref. 14), the performance of our photonic memories can also be further improved by operating them with shorter pulses and by moving to devices with smaller footprint, as well as through the development of new materials with faster and lower-temperature switching. Higher SNR to improve the readout contrast could also be obtained with the use of optical cavities, which would also reduce switching energies as discussed theoretically previously26. To reduce the device footprint, alternative architectures such as plasmonic antennas could be explored. Alternatively, scaling down is plausible by using photonic circuitry operating at shorter wavelengths (therefore, narrower waveguides) or by using PCMs with a higher difference in refractive index in the C- and L-band. In this way, small devices will lead to reasonably good contrasts. Although our multi-bit access is achieved with microring resonators with relatively large footprints, alternative technologies such as an ultra-compact on-chip optical multiplexer/demultiplexer31,32 can be used for size reduction. In addition, optical cavities with smaller mode volume, such as photonic crystal devices, would localize the interaction volume of the optical mode with the memory element further, and thus lead to a smaller system size for wavelength-selective memory access.

In conclusion, we have demonstrated the first prototype of an integrated, all-photonic, truly non-volatile memory that provides multi-level (here eight level) storage in a single cell together with multi-bit (here three bit) WDM access (via a single waveguide). Our approach uses low-dimensional phase-change (GST) memory elements integrated with silicon nitride waveguides. The memory elements are switched between memory states by evanescent coupling to light travelling along such waveguides and are thus not restricted in size by the diffraction limit. Furthermore, we show the ability to switch readily and directly between the multiple memory levels, with accurate control of the readout signal and excellent repeatability (capabilities that require complex iteration-based algorithms in electronic phase change memories). We also demonstrate the capability for fast (∼500 ps), low-power (∼480 fJ), single-shot readout of the memory state, as well as repeated (×100) write/erase cycling while maintaining high readout contrast. Our hybrid phase change–photonic framework is fully scalable: large arrays of all-optical memory elements are envisioned that can be conveniently addressed, using WDM techniques, through on-chip waveguides. Such attributes are essential for the realization of a number of novel applications, including new forms of non-conventional (non von Neumann) computation33,34 and practical on-chip optical interconnects (although for the latter, an increased switching endurance beyond that currently achievable with GST would be beneficial). These very first experimental results are not only promising, but demonstrate significantly more potential than existing integrated optical memories (high-speed access, multi-level single-shot write and read, wavelength selectivity as well as low power) and thus set the stage for further exciting new developments in phase change photonics.