fn set_baud_rate(&mut self, baud_rate: BaudRate) {
        // TWAI is clocked from the APB_CLK according to Table 6-4 [ESP32C3 Reference Manual](https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf)
        // Included timings are all for 80MHz so assert that we are running at 80MHz.
        #[cfg(not(any(esp32h2, esp32c6)))]
        {
            let apb_clock = crate::clock::Clocks::get().apb_clock;
            assert!(apb_clock.as_mhz() == 80);
        }

        // Unpack the baud rate timings and convert them to the values needed for the
        // register. Many of the registers have a minimum value of 1 which is
        // represented by having zero bits set, therefore many values need to
        // have 1 subtracted from them before being stored into the register.
        let timing = baud_rate.timing();

        #[cfg_attr(not(esp32), allow(unused_mut))]
        let mut prescaler = timing.baud_rate_prescaler;

        #[cfg(esp32)]
        {
            // From <https://github.com/espressif/esp-idf/blob/6e5a178b3120dced7fa5c29c655cc22ea182df3d/components/soc/esp32/register/soc/twai_struct.h#L79>
            // and <https://github.com/espressif/esp-idf/blob/6e5a178b3120dced7fa5c29c655cc22ea182df3d/components/hal/esp32/include/hal/twai_ll.h#L528-L534>:
            if timing.baud_rate_prescaler > 128 {
                // Enable /2 baudrate divider by setting `brp_div`.
                // `brp_div` is not an interrupt, it will prescale BRP by 2. Only available on
                // ESP32 Revision 2 or later. Reserved otherwise.
                self.regs().int_ena().modify(|_, w| w.brp_div().set_bit());
                prescaler = timing.baud_rate_prescaler / 2;
            } else {
                // Disable /2 baudrate divider by clearing brp_div.
                self.regs().int_ena().modify(|_, w| w.brp_div().clear_bit());
            }
        }

        let prescale = (prescaler / 2) - 1;
        let sjw = timing.sync_jump_width - 1;
        let tseg_1 = timing.tseg_1 - 1;
        let tseg_2 = timing.tseg_2 - 1;
        let triple_sample = timing.triple_sample;

        // Set up the prescaler and sync jump width.
        self.regs().bus_timing_0().modify(|_, w| unsafe {
            w.baud_presc().bits(prescale as _);
            w.sync_jump_width().bits(sjw)
        });

        // Set up the time segment 1, time segment 2, and triple sample.
        self.regs().bus_timing_1().modify(|_, w| unsafe {
            w.time_seg1().bits(tseg_1);
            w.time_seg2().bits(tseg_2);
            w.time_samp().bit(triple_sample)
        });

        // disable CLKOUT
        self.regs()
            .clock_divider()
            .modify(|_, w| w.clock_off().set_bit());
    }
Set the bitrate of the bus.

Note: The timings currently assume a APB_CLK of 80MHz.
esp-hal/src/twai/mod.rs