pub fn flush_tx(&mut self) -> Result<(), Error> {
        self.regs().ep1_conf().modify(|_, w| w.wr_done().set_bit());

        // FIXME: raw register access
        while self.regs().ep1_conf().read().bits() & 0b011 == 0b000 {
            // wait
        }

        Ok(())
    }
Flush the output FIFO and block until it has been sent
esp-hal/src/usb_serial_jtag.rs