pub fn enable_core1_sp_monitor(&mut self, lower_bound: u32, upper_bound: u32) {
        self.regs()
            .core_1_sp_min
            .write(|w| w.core_1_sp_min().bits(lower_bound));

        self.regs()
            .core_1_sp_max
            .write(|w| w.core_1_sp_max().bits(upper_bound));

        self.regs().core_1_montr_ena.modify(|_, w| {
            w.core_1_sp_spill_min_ena()
                .set_bit()
                .core_1_sp_spill_max_ena()
                .set_bit()
        });

        self.clear_core1_sp_monitor_interrupt();

        self.regs().core_1_intr_ena.modify(|_, w| {
            w.core_1_sp_spill_max_intr_ena()
                .set_bit()
                .core_1_sp_spill_min_intr_ena()
                .set_bit()
        });
    }
Enable SP monitoring on secondary core. When the SP exceeds the
`lower_bound` or `upper_bound` threshold, the module will record the PC
pointer and generate an interrupt.
esp-hal/src/assist_debug.rs