pub fn set_timeout(&mut self, stage: RwdtStage, timeout: Duration) {
        let rtc_cntl = LP_WDT::regs();

        let timeout_raw = (timeout.as_millis() * (RtcClock::cycles_to_1ms() as u64)) as u32;
        self.set_write_protection(false);

        unsafe {
            #[cfg(esp32)]
            match stage {
                RwdtStage::Stage0 => rtc_cntl
                    .wdtconfig1()
                    .modify(|_, w| w.wdt_stg0_hold().bits(timeout_raw)),
                RwdtStage::Stage1 => rtc_cntl
                    .wdtconfig2()
                    .modify(|_, w| w.wdt_stg1_hold().bits(timeout_raw)),
                RwdtStage::Stage2 => rtc_cntl
                    .wdtconfig3()
                    .modify(|_, w| w.wdt_stg2_hold().bits(timeout_raw)),
                RwdtStage::Stage3 => rtc_cntl
                    .wdtconfig4()
                    .modify(|_, w| w.wdt_stg3_hold().bits(timeout_raw)),
            };

            #[cfg(any(esp32c6, esp32h2))]
            match stage {
                RwdtStage::Stage0 => rtc_cntl.config1().modify(|_, w| {
                    w.wdt_stg0_hold()
                        .bits(timeout_raw >> (1 + Efuse::rwdt_multiplier()))
                }),
                RwdtStage::Stage1 => rtc_cntl.config2().modify(|_, w| {
                    w.wdt_stg1_hold()
                        .bits(timeout_raw >> (1 + Efuse::rwdt_multiplier()))
                }),
                RwdtStage::Stage2 => rtc_cntl.config3().modify(|_, w| {
                    w.wdt_stg2_hold()
                        .bits(timeout_raw >> (1 + Efuse::rwdt_multiplier()))
                }),
                RwdtStage::Stage3 => rtc_cntl.config4().modify(|_, w| {
                    w.wdt_stg3_hold()
                        .bits(timeout_raw >> (1 + Efuse::rwdt_multiplier()))
                }),
            };

            #[cfg(not(any(esp32, esp32c6, esp32h2)))]
            match stage {
                RwdtStage::Stage0 => rtc_cntl.wdtconfig1().modify(|_, w| {
                    w.wdt_stg0_hold()
                        .bits(timeout_raw >> (1 + Efuse::rwdt_multiplier()))
                }),
                RwdtStage::Stage1 => rtc_cntl.wdtconfig2().modify(|_, w| {
                    w.wdt_stg1_hold()
                        .bits(timeout_raw >> (1 + Efuse::rwdt_multiplier()))
                }),
                RwdtStage::Stage2 => rtc_cntl.wdtconfig3().modify(|_, w| {
                    w.wdt_stg2_hold()
                        .bits(timeout_raw >> (1 + Efuse::rwdt_multiplier()))
                }),
                RwdtStage::Stage3 => rtc_cntl.wdtconfig4().modify(|_, w| {
                    w.wdt_stg3_hold()
                        .bits(timeout_raw >> (1 + Efuse::rwdt_multiplier()))
                }),
            };
        }

        self.set_write_protection(true);
    }
Configure timeout value in ms for the selected stage.
esp-hal/src/rtc_cntl/mod.rs