pub(crate) fn revert_trng() {
    let sens = crate::peripherals::SENS::regs();
    let i2s0 = crate::peripherals::I2S0::regs();
    let apb_ctrl = crate::peripherals::APB_CTRL::regs();

    unsafe {
        i2s0.conf().modify(|_, w| w.rx_start().clear_bit());

        i2s0.conf().modify(|_, w| w.rx_reset().set_bit());

        i2s0.conf().modify(|_, w| w.rx_reset().clear_bit());

        i2s0.conf2().modify(|_, w| {
            w.camera_en()
                .clear_bit()
                .lcd_en()
                .clear_bit()
                .data_enable_test_en()
                .clear_bit()
                .data_enable()
                .clear_bit()
        });

        sens.sar_read_ctrl()
            .modify(|_, w| w.sar1_dig_force().clear_bit());

        sens.sar_read_ctrl2()
            .modify(|_, w| w.sar2_dig_force().clear_bit());

        sens.sar_start_force()
            .modify(|_, w| w.sar2_en_test().clear_bit());

        apb_ctrl.apb_saradc_ctrl().modify(|_, w| {
            w.saradc_sar2_mux()
                .clear_bit()
                .saradc_sar_sel()
                .clear_bit()
                .saradc_data_to_i2s()
                .clear_bit()
        });

        sens.sar_meas_wait2()
            .modify(|_, w| w.force_xpd_sar().bits(0));

        apb_ctrl
            .apb_saradc_fsm()
            .modify(|_, w| w.saradc_start_wait().bits(8));
    }
}
Disable true randomness. Unlocks `ADC` peripheral.
esp-hal/src/soc/esp32/trng.rs