pub fn clear_core1_sp_monitor_interrupt(&mut self) {
        self.regs().core_1_intr_clr.write(|w| {
            w.core_1_sp_spill_max_clr()
                .set_bit()
                .core_1_sp_spill_min_clr()
                .set_bit()
        });
    }
Clear SP monitoring interrupt on secondary core.
esp-hal/src/assist_debug.rs