pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) {
        unsafe {
            PLIC_MX::regs().mxint_enable().modify(|r, w| {
                let old = r.cpu_mxint_enable().bits();
                let new = old | (1 << (which as isize));
                w.cpu_mxint_enable().bits(new)
            });
        }
    }
Enable a CPU interrupt

# Safety

Make sure there is an interrupt handler registered.
esp-hal/src/interrupt/riscv.rs