fn read_next_from_fifo(&self) -> u8 {
        fn access_fifo_register<R>(f: impl Fn() -> R) -> R {
            // https://docs.espressif.com/projects/esp-chip-errata/en/latest/esp32/03-errata-description/esp32/cpu-subsequent-access-halted-when-get-interrupted.html
            cfg_if::cfg_if! {
                if #[cfg(esp32)] {
                    crate::interrupt::free(f)
                } else {
                    f()
                }
            }
        }

        let fifo_reg = self.regs().fifo();
        cfg_if::cfg_if! {
            if #[cfg(esp32s2)] {
                // On the ESP32-S2 we need to use PeriBus2 to read the FIFO:
                let fifo_reg = unsafe {
                    &*fifo_reg.as_ptr().cast::<u8>().add(0x20C00000).cast::<crate::pac::uart0::FIFO>()
                };
            }
        }

        access_fifo_register(|| fifo_reg.read().rxfifo_rd_byte().bits())
    }
Reads one byte from the RX FIFO.

If the FIFO is empty, the value of the returned byte is not specified.
esp-hal/src/uart.rs