\section{Resonator Design}

\begin{figure*}
	\centering
	\includegraphics[width=0.97\linewidth]{figures/device_overview_v5}
	\caption{\textbf{(a)} Cross-section of one period of the FinFET resonator , modeled in COMSOL, with inset highlighting Si fin (dark green) and epitaxial raised source and drain with silicide (blue) \cite{noauthor_comsol_nodate}. Metal and contact layers highlighted in orange and dark gray and dielectric layers left uncolored (light gray). The target mode is defined primarily along the x-direction via the 180 degree phase constraint due to differential drive and sense. \textbf{(b)} Top down view of device shows the central sense transistors with five pairs of capacitors on either side allowing for differential drive, capped on either end by termination (ten gates in the actual devices, abbreviated to three in the figure) and surrounded by a ground ring. First level metal M1 is used for routing within the structure while higher level metals in Mx and Cx (not shown for clarity in this diagram) rest above this routing in either continuous plate or PnC form. The Kx layer represents higher level metal layers used for device to pad routing. \textbf{(c)} Resonator electrical test scheme with DC biasing provided by standalone SMUs, routed through internal PNA bias tees.  }
	\label{fig:deviceoverview}
\end{figure*}

The designed resonator structure, shown in Fig. \ref{fig:deviceoverview}, is fully integrated in the GlobalFoundries 14LPP process and occupies a space of 9 µm x 15 µm \cite{globalfoundries_12lp_2018}. The device is a four port network, with output of the resonator taken as the differential transconductance (Eq. \ref{eq:gmdd}), which is a function of three main items: the electrical to acoustic transduction efficiency in the drive transistors, the acoustic energy confinement and amplification in the resonance cavity, and the acoustic to drain current conversion in the output transistors. The first of these items, drive transduction, is electrostatic due to the 14 nm fabrication process used, although the potential for future piezoelectric drive using CMOS compatible thin film ferroelectrics exists \cite{trentzsch_28nm_2016,he2020tunable,he2019switchable}. The third of these, acoustic-to-drain current conversion, is also largely a function of the process and materials used in device fabrication. While this conversion will be examined utilizing a simplified model, the initial device design is focused on maximizing acoustic energy confinement by varying gate length, termination scheme, and back-end-of-line (BEOL) confinement conditions.

\begin{equation}\label{eq:gmdd}
	g_{mdd} = \frac{i_d}{v_d} = Y_{dd21}-Y_{dd12}
\end{equation}

\subsection{BEOL Phononic Confinement}

Fig. \ref{fig:deviceoverview}(c) depicts a 3D unit cell of the resonator with a 14 nm wide FinFET at the front-end-of-line (FEOL) and periodically arranged metal blocks at the BEOL, categorized into Mx and Cx layers as shown based on thickness and minimum lateral feature sizes. The target resonant mode for the unreleased resonator is along the length direction of the fin transistors. To obtain lower insertion loss and higher quality factor, the radiated acoustic energy needs to be concentrated at the MOS capacitor drive transducers and the sensing transistors. Compared to more traditional suspended resonators, this represents a challenge in the unreleased resonant body transistor design in the commercial CMOS processes.

Integrating a phononic crystal (PnC) at the BEOL of the standard CMOS process and leveraging the mechanical bandgaps of such structures has proven to be an effective tool to confine the energy and boost resonance quality factor \cite{he2020tunable,bahr_theory_2015}. As shown by M1 in \ref{fig:deviceoverview}(b), these periodic metals are uniform along the length (y direction) of the transistor gates (orthogonal to the fin direction) within the resonant cavity. 

In order to study and optimize the bandgap induced by the phononic crystals, several 2D simulations were performed in COMSOL Multiphysics. Specifically, by mapping the real coordinates to reciprocal coordinates and searching for the eigenmodes along the first irreducible Brillouin zone in the 2D reciprocal lattice, a 130 nm by 60 nm PnC (such as can be designed within the constraints of the Mx layers in the 14 nm process) yields a calculated bandgap from 8 GHz to 12 GHz (shown in Fig. \ref{fig:DR}(b)). 
To further confine the elastic energy, a separate PnC designed under Cx metal layer design rules is also considered for a subset of devices. The corresponding dispersion relationship is shown in Fig. \ref{fig:DR}(c). A mechanical bandgap is then obtained between 7.6 GHz and 10.7 GHz which overlaps with the bandgap induced by the Mx metal PnC.
Together, these PnC designs indicate elastic waves with a frequency of 8 GHz to 12 GHz can be prohibited from propagating into the BEOL. If coupled with a waveguided mode with differential drive that exhibits a large momentum ($k_x = \pi/a$) at a frequency below the sound cone for the bulk silicon substrate, these modes can be confined laterally towards the driving/sensing transistors, with modes from 8 to 10.7 GHz showing the greatest confinement \cite{bahr_theory_2015}. For an in-depth analysis on the acoustic modes in this device, readers are referred to \cite{rawat_analysis_2021}.

\subsection{Resonant Cavity Termination}
 While the PnCs in the main resonant cavity enhance energy confinement and wave reflection from the BEOL, there also exists wave scattering at the two ends of the resonator. Reducing this scattering further increases the horizontal confinement, reduces the insertion loss, and hence increases the Q. The adiabatic theorem in photonic waveguide design is leveraged here, which states that when the wave is propagated down the waveguide, scattering will vanish because of the limitation of sufficiently slow perturbation \cite{meade1995photonic}. Therefore, the key to reduce this scattering is to introduce different units as terminations at the two ends for slower transitions. The unit cell for all the PnC structures in the major termination section throughout the paper is kept as 150 nm x 60 nm.
 
 While all measured devices have ten terminating gates at each end of the cavity, two types of cavity termination spacings are explored to provide acoustic confinement in the lateral direction. These include abrupt and gradual termination schemes. The abrupt termination refers to the scenario where a terminating periodic array with constant pitch shifted from that of the resonance cavity array is immediately adjacent to the main resonance region. In this case, the gate length of the termination immediately transitions to the $L_{term}$ value given in Fig. \ref{fig:rfoverview}(a) and stays  constant until the end of the device. As such, the guided waves are abruptly transitioned from the main cavity towards the ends. In the gradual termination scenario, the main resonant cavity periodicity adiabatically transitions from $L_{gate}$ to the terminating array periodicity $L_{term}$, resulting in a termination gate length gradually transitioning from 80 to 140 nm. This serves to reduce scattering from the two ends and boost the Q \cite{bahr2015theory}. These two schemes are depicted in Fig. \ref{fig:rfoverview}(c).


\subsection{FinFET Sensing}

To understand the conversion from stress to drain current in the sense transistors, modulation of three separate FET properties is examined: oxide capacitance, channel mobility due to piezoresistivity, and silicon bandgap. 
For ease of visualization, an initial analysis is performed with the source-referenced simplified strong-inversion model with $\alpha=1$ (the traditional "square-law model", or SPICE level 1) \footnote{This model has only a handful of parameters to describe device operation, as opposed to the more advanced BSIM models used commonly in industry, which include many empirically fit parameters to give the best device models for commercial applications \cite{noauthor_bsim_nodate}. This simplified model is used with the understanding that the derivation, while not capturing a variety of short channel effects that influence modern transistor behaviour, will provide a more intuitive understanding into the basics of active FET sensing.} \cite{tsividis_operation_2010}:

\begin{equation}
	I_d = \mu C_{ox} \frac{W}{L}\Big((V_{GS}-V_T)V_{DS} - \frac{V_{DS}^2}{2}\Big)
\end{equation}
where $I_d$ is the drain current, $\mu$ is the carrier mobility, $C_{ox}$ is the gate capacitance, $V_{DS}$ and $V_{GS}$ are the drain-to-source and gate-to-source bias, respectively, $W$ and $L$ are the channel width and length, and $V_T$ is the threshold voltage required for significant channel conduction.

Capacitance modulation in these devices is the same mechanism used in electrostatic drive of these devices, except that rather than sensing the gate current directly, the capacitance modulation is being amplified through transistor action into a change in drain current. The piezoresistive effect, whereby the semiconductor carrier mobility is modulated through stress in the transistor channel, likewise appears as a multiplier on the transistor drain current. Semiconductor bandgap modulation, on the other hand, largely effects the threshold voltage of the transistor. For a complete derivation of these effects, the reader is directed to the derivation in Appendix \ref{sec:derivation}.
Modified to include the effects of stress on $\mu$, $C_{ox}'$, and $V_T$ (modeled as $\mu(\sigma) = \mu_0+\Delta \mu$), the original expression for current in the linear region becomes the following:

\begin{multline} \label{eq:id_stressfet}
	I_d(\sigma)	= (\mu_0 C_{ox0}' +\mu_0 \Delta C_{ox}' + C_{ox0}'\Delta \mu + \Delta \mu\Delta C_{ox}')  *\frac{W}{L}\Big((V_{GS}-V_{T0})V_{DS} - \frac{V_{DS}^2}{2}\Big) \\
	-\Delta V_T V_{DS} \frac{W}{L} (\mu_0 C_{ox0}' +\mu_0 \Delta C_{ox}' + C_{ox0}'\Delta \mu + \Delta \mu\Delta C_{ox}')
\end{multline}
where
\begin{multline} \label{eq:deltaid_stressfet}
	\Delta I_d(\sigma)	= (\mu_0 \Delta C_{ox}' + C_{ox0}'\Delta \mu + \Delta \mu\Delta C_{ox}') *\frac{W}{L}\Big((V_{GS}-V_{T0})V_{DS} - \frac{V_{DS}^2}{2}\Big) \\
	-\Delta V_T V_{DS} \frac{W}{L} (\mu_0 C_{ox0}' +\mu_0 \Delta C_{ox}' + C_{ox0}'\Delta \mu + \Delta \mu\Delta C_{ox}')
\end{multline}

Likewise, in saturation

\begin{equation}
	I_{d0} = \mu C_{ox} \frac{W}{2L}\Big((V_{GS}-V_T)^2\big(1+\lambda[V_{DS}-(V_{GS}-V_{T0})]\big)\Big)
\end{equation}
where $\lambda$ represents the channel length modulation coefficient (0.05 to 0.25 typical) and 

\begin{multline}
	\Delta I_d 
	= (\mu_0 \Delta C_{ox}' + C_{ox0}'\Delta \mu + \Delta \mu\Delta C_{ox}')
	*\frac{W}{2L}\Big((V_{GS}-V_T)^2(1+\lambda(V_{DS} - V_{GS} + V_{T}))\Big) \\
	\hspace{13mm}- \frac{W}{2L} (\mu_0 C_{ox0} +\mu_0 \Delta C_{ox} + C_{ox0}\Delta \mu + \Delta \mu\Delta C_{ox}) \Bigg[ \hfill \\ 
	\hspace{27mm}\Delta V_T \Big[\lambda(V_{GS}-V_{T0})^2 - 2(V_{GS}-V_{T0}) 
	*\Big(1+\lambda\big[V_{DS}-(V_{GS}-V_{T0})\big]\Big)\Big] \hfill \\ 
	\hspace{23mm}+ \Delta V_T^2 \Big[\Big(1+\lambda\big[V_{DS}-(V_{GS}-V_{T0})\big]\Big) - 2\lambda(V_{GS}-V_{T0})\Big] \hfill \\
	\hspace{23mm}+ \Delta V_T^3 [\lambda]  \Bigg] \hfill 
\end{multline}

For modern sub-micron devices, carriers do not exhibit constant mobility but rather undergo velocity saturation at high fields. A simplified way to model this analytically is through a piece-wise equation
\begin{equation}
	v_d = \begin{cases}
		\frac{\mu |E_x|}{1+|E_x|/E_{sat}} \quad,\quad |E_x| < E_{sat} \\
		v_{sat}\hfill,\quad |E_x| > E_{sat}
	\end{cases}
\end{equation}
which, solved at $v_d = v_{sat}$, gives
\begin{equation} \label{eq:esat}
	E_{sat} = \frac{2v_{sat}}{\mu}
\end{equation}
and leads to a modified expression for drain current
\begin{equation}
	I_d = \begin{cases}
		\mu C_{ox} \cfrac{W}{L}\cfrac{1}{1+\cfrac{V_{DS}}{E_{sat}L}}\Big((V_{GS}-V_T)V_{DS} - \frac{V_{DS}^2}{2}\Big) \quad,\quad V_{DS} < V_{DSsat} \\ \\
		C_{ox} W v_{sat}\cfrac{(V_{GS}-V_T)^2}{(V_{GS}-V_T)+E_{sat}(L-\Delta L)} \hfill,\quad V_{DS} > V_{DSsat}
	\end{cases}
\end{equation}
where
\begin{equation}
	V_{DSsat} = \frac{(V_{GS}-V_T)E_{sat}L}{(V_{GS}-V_T)+E_{sat}L}.
\end{equation}

An important nuance for acoustic resonators is that both the saturation velocity and the change in mobility (piezoresistive effect) are related to the change in carrier effective mass caused by acoustic deformation of the crystal lattice - saturation velocity by $m^{*-1/2}$ and mobility by a factor between $m^{*-1/2}$ and $m^{*-5/2}$, depending on doping (for a detailed analysis, see Appendix \ref{sec:mobility}). This relation means that, while DC current may saturate, the AC piezoresistive effect can still change drain current to an extent, even in the saturation region. For this reason, a compound model is utilized that incorporates velocity saturation in the calculation of DC drain current but allows mobility to vary freely. Under this approach, the contribution to RF output from both electrostatic forces and mobility modulation should scale linearly with drain current. The contribution from any threshold voltage shift is seen to be related to drain bias only in the linear regime and is scaled by the impact of mobility and capacitance changes. In the saturation regime, on the other hand, the threshold voltage shift is primarily a function of gate bias and is modified by drain bias only through channel length modulation. These expressions for $\Delta I_d$ represent one half of the device transfer function $g_{mdd}$, discussed in Eq. \ref{eq:gmdd}, with the other half being given by the voltage-to-strain conversion and subsequent strain confinement/resonance. While direct measurement of strain in the solid-state resonator in the front end of line poses a challenge, all three of these aspects are subsequently investigated using measured electrical results.

\section{Results and Discussion}

DC results, shown as an example for the 80 nm gate length device A1 in Appendix \ref{sec:sup_figs}, indicate that the sense transistors in all devices were working as intended. The large current values of approximately 2 mA when gate and drain are biased at $V_{dd}$ are due to the parallel DC connection of the two sense transistors and large effective width of the individual transistors, where 40 fins span the resonance cavity (in y-direction) and are electrically connected in parallel. 

\subsection{Analysis of Design Variations}

\begin{figure*}
	\centering
	\includegraphics[width=1\linewidth]{figures/sample_overview_v5}
	\caption{\textbf{(a)} Depiction of the termination schemes investigated for use at the ends of the resonant cavity. \textbf{(b)} Phononic crystal structure, with various investigated pitches. \textbf{(c)} Device design variations and \textbf{(d)} their experimentally measured differential transconductance at $V_D=0.6$ V, $V_G=0.8$ V, $V_{DR}=0.8$ V. \textbf{(e)} Target mode, simulated in COMSOL, with stress concentrated in finFET channel and confined by the BEOL metal layers.}
	\label{fig:rfoverview}
\end{figure*}

While DC results were similar for all devices (outside expected differences due to gate length), resonance mode confinement was highly dependent on the design variations studied. A summary of all measured devices as well as a comparison of their differential transconductance spectra from 9.5 to 13.5 GHz are shown in Fig. \ref{fig:rfoverview}. From these data, it is evident that phononic crystal confinement in the Mx layers results in significantly improved quality factor and maximum transconductance. Also visible is the role the type of termination has in defining the center frequency of nearby spurious modes in the device. 

\begin{table*}[]
	\renewcommand{\arraystretch}{1.3}
	\caption{ANOVA Results for Peak Fits}
	\label{tab:anova_results}
	\centering
	\resizebox{\textwidth}{!}{%
	\begin{tabular}{|c|c|c||c|c|c|c|c|c||c|}
		\hline
		\multicolumn{2}{|c|}{\scriptsize{95\% Confidence Intervals} } & \multirow{2}{*}{n} & \multicolumn{2}{c|}{Frequency [Hz]} & \multicolumn{2}{c|}{Height [nS]} & \multicolumn{2}{c||}{Q} & \multirow{2}{*}{Samples} \\
		\cline{4-9}
		\multicolumn{2}{|c|}{\scriptsize{Significant results in bold.}} &  & Mean & Std. Error & Mean & Std. Error & Mean & Std. Error &  \\
		\hhline{|==|=||=|=|=|=|=|=||=|}
		\rule[-1ex]{0pt}{2.5ex} \multirow{3}{*}{PnC Confinement} & Mx, Cx & 413 & 11.27 G & 52.8 M & \textbf{451.1} & \textbf{30.6} & \textbf{44.32} & \textbf{1.68} & \multirow{3}{*}{\shortstack{A1-A4, B0-B1\\ (L$_{gate}$=80 nm)}} \\
		\cline{2-9}
		\rule[-1ex]{0pt}{2.5ex}  & Mx Only & 368 & 11.22 G & 55.9 M & \textbf{379.4} & \textbf{32.5} & \textbf{37.55} & \textbf{1.78} &  \\
		\cline{2-9}
		\rule[-1ex]{0pt}{2.5ex}  & Plates & 276 & 11.26 G & 64.6 M & \textbf{203.6} & \textbf{37.5} & \textbf{19.88} & \textbf{2.05} &  \\
		\hline
		\rule[-1ex]{0pt}{2.5ex} \multirow{2}{*}{Termination} & Abrupt & 1289 & \textbf{11.16 G} & \textbf{33.4 M} & \textbf{301.6} & \textbf{13.9} & \textbf{24.21} & \textbf{0.795} & \multirow{2}{*}{All} \\
		\cline{2-9}
		\rule[-1ex]{0pt}{2.5ex}  & Gradual & 1145 & \textbf{11.29 G} & \textbf{35.4 M} & \textbf{352.4} & \textbf{14.7} & \textbf{ 31.71} & \textbf{0.843} &  \\
		\hline
		\rule[-1ex]{0pt}{2.5ex} \multirow{2}{*}{L$_{gate}$} & 80 nm & 30 & \textbf{11.66 G} & \textbf{23.0 M} & 1,866 & 153 & 84.8 & 4.40 & \multirow{2}{*}{\shortstack{A3-A6 \\ Q$>$25, Height$>$500 nS}} \\
		\cline{2-9}
		\rule[-1ex]{0pt}{2.5ex}  & 106 nm & 30 & \textbf{10.71 G} & \textbf{23.0 M} & 1,651 & 153 & 87.1 & 4.40 &  \\
		\hline
	\end{tabular}}
\end{table*}


These differences are quantified in Table \ref{tab:anova_results}, where the center frequency, quality factor, and height of resonant peaks in $g_{mdd}$ are compared for the three design splits after elimination of high-error peak fit ($\approx$5\% of data overall). For termination, this process is straightforward as there exists an abrupt and gradually terminated copy of every device. The resulting analysis indicates an increased transconductance in gradual transition devices (352 nS) vs. abruptly terminated ones (302 nS), with a corresponding increase in average quality factor (32 vs. 24). In addition to this enhancement, average resonance center frequency was shown to decrease slightly from 11.29 to 11.16 GHz, driven by the downward shift in the left-most peak of the high-$Q$ cluster of modes seen in PnC-confined devices. 

To investigate phononic crystal confinement, analysis was limited to designs with 80 nm gate length (A1-A4 and B0-B1) and the confinement treated as a three-level categorical factor. This analysis showed no significant change in center frequency of the modes, but it did show significantly improved transconductance (204, 379, 451 nS) and quality factor (20, 38, 44) with increasing layers of phononic crystal confinement. These trends are highlighted in Fig. \ref{fig:peakfitresults} along with an example of the peak fitting results used for parameter extraction.

\begin{figure*}
	\centering
	\includegraphics[width=0.9\linewidth]{figures/peakfit_results_v2}
	\caption{ \textbf{(a)}: Output of peak fit algorithm for one of the 392 individual measurements evaluated. Peak fits with error above 0.025 were filtered (120 out of 2554 peaks) and then design splits were evaluated by comparing means and performing ANOVA between appropriate samples. The most significant process variation, BEOL confinement, is shown in \textbf{(b)}, with complete results given in Table \ref{tab:anova_results}. In addition to increasing average peak height and $Q$ across a range of drive and drain biases, it is also evident that an Mx-PnC greatly increases the maximum peak height, from under 1 µS to 4.5 µS for the highest-performing resonator. \textbf{(c)} shows Q and amplitude of fit resonance peaks, filtered by a minimum $Q$ of 25 and height of 750 nS, with each dot indicating a peak of the correspondingly colored device under a single bias condition. Transconductance variations at the same frequency show the dependence of the resonance on electrical biases. Also evident is the change in center frequency due to gate length, and splitting from two to three distinct modes with gradual termination, as first shown in Fig. \ref{fig:rfoverview}. }
	\label{fig:peakfitresults}
\end{figure*}

Compared to the other factors studied, L$_{gate}$ is unique in that it is the primary design variable for selecting center frequency due to the mode being defined by source/drain spacing. This means that the different values studied dramatically change the cavity shape and thus all peaks detected in the studied frequency span of 9.5 to 13.5 GHz cannot be used in the analysis, as they are not present in this range in all devices. To overcome this, a much smaller comparison of A3 and A4 (L$_{gate}$=80 nm) to A5 and A6 (L$_{gate}$=106 nm) was performed using only the prominent modes with transconductance above 500 nS and $Q$ above 25 that were present towards the center of the spectra. The downside of this approach is that gate length is confounded with a change in phononic crystal design that is necessary for the different device geometries due to design rule challenges. Despite this, the fact that confinement method showed no significant change in center frequency for 80 nm devices points towards this shift being dominated by gate length as would be expected.

As the device with the highest performance, resonator A2 was selected for further analysis, with the maximum transconductance of the $\approx$11.75 GHz mode examined as a function of device biasing. This was done at a drive bias of $V_{dd}$, as $g_{mdd}$ was seen to increase linearly with the increase in MOS capacitance at higher drive bias (see Appendix \ref{sec:sup_figs}). The dependence of $g_{mdd}$ on sense transistor biasing, shown in Fig. \ref{fig:exp_vs_sim}, highlights that device transconductance, as expected, is modulated in a manner consistent with piezoresistive and bandgap modulation. While transistor parameters are of the correct order of magnitude in the reported data fit, they vary slightly from real-world values due to the simplified model used. For example, the square law model does not accurately capture subthreshold (accumulation and weak inversion) behaviour, and thus the fit favors a slightly lower Vt to more closely fit bias currents near zero. This, in turn, leads to an overestimation of current at higher biases, which is compensated by a lower than expected value for mobility and a slightly larger equivalent oxide thickness. On the AC side, the fit is hindered by the presence of a noise floor in the s-parameter measurements that may obscure lower peak levels. This, along with the poor near-threshold characteristics of the square law model, contributes to the fitting error at lower values of $g_{mdd}$. Moving away from the square law model to a more advanced model such as that derived by Taur et al. that captures all regions of operation may decrease this error \cite{taur_continuous_2004}. Likewise, adopting band-structure simulations of silicon as a result of acoustic deformation could provide a unified source of mobility and threshold voltage changes in the transistor, at the expense of increased computation requirements.

For NMOS devices oriented in the <110> direction, the negative piezoresistive coefficients ensure that the contribution of the threshold voltage shift and mobility is additive. If fRBT devices are implemented with PMOS devices or in processes with different fin orientations, care should be taken to ensure that the dominant stress-dependent effects do not compete against each other. This may not be as much of an issue for long channel RBT devices, as piezoresistive modulation dominates for long channel devices that are not supply voltage constrained. 

\begin{figure*}
	\centering
	\includegraphics[width=1\linewidth]{figures/exp_vs_sim.png}
	\caption{\textbf{(a)} Simulated contributions to $\Delta I_D$ from bandgap modulation (threshold voltage), piezoresistive modulation (mobility), electrostatic modulation (oxide capacitance), and cross-term. For short channel devices that are supply voltage constrained, bandgap and piezoresistive modulation are of similar magnitudes and dominate over electrostatic terms.  \textbf{(b)} These two terms, along with the overall drain current modulation, are plotted against DC bias current of the sense transistor (X-axis) for simulated (top) and experimental (bottom) devices. Gate bias is shown by marker color (blue to yellow) and ranges from 0.4 to 0.8 by 0.1 V. Drain bias is represented with marker size, moving from small to large as bias increases from 0.1 to 0.8 by 0.1 V. The large cluster of points with equal gate biases and similar drain currents indicate saturation mode operation for those bias conditions with channel length modulation. The mobility term is linear with drain current, whereas the threshold voltage term due to bandgap modulation has both a flat \textbf{(i)} region in the linear regime with no $V_G$ dependence for constant $V_D$ and a slight $V_D$ dependence \textbf{(ii)} for constant $V_G$ in the saturation regime. Experimental data shows roughly linear dependence of drain current on gate voltage (a hallmark of velocity saturation \cite{tsividis_operation_2010} vs. the $V_G^2$ dependence of the long channel model). Some deviation between the model fit and experimental results can be seen at high drain bias and low gate bias, which may be indicative of mobility degradation due to vertical fields, which is not modeled currently. Otherwise, experimental results show a similar shape to that of the simulated device, indicating the dominance of both piezoresistive and bandgap modulation in the experimental resonator. \textbf{(c)} Model fit to experimental results ($\mu=79$ cm$^2$/Vs, equivalent oxide thickness=1.6 nm, $V_t$=0.206 V, $v_{sat}$=1.83*10$^7$ cm/s, $\lambda$=0.47, $W$ = 3 um, total stress=1 MPa). A basin-hopping algorithm is used to find a global minimum fit for the DC transistor parameters, which are then fixed for the AC fit, achieved by varying stress.}
	\label{fig:exp_vs_sim}
\end{figure*}

The highest magnitude peak fit occurred in device A2 (L$_{gate}$ of 80 nm, gradually terminated, dual PnC) at 11.73 GHz with a differential transconductance of 4.49 µS and a $Q$ of 69.8, for an $f*Q$ product of 8.19*10$^{11}$ at drain, gate, and drive biases of 0.6, 0.8, and 0.8 V, respectively. While previous unreleased resonators in the 32 SOI process have achieved an $f*Q$ product of $3.8*10^{13}$ with phononic confinement at 3.3 GHz, these 14 nm devices exhibit 50x higher transconductance and show an almost 3x improvement in Q over a similar frequency measured mode in 32 SOI devices \cite{bahr_optimization_2016, marathe_resonant_2014}. Compared to some contemporary resonators in the X and adjacent K$_\textrm{u}$ (12-18 GHz) bands in Table \ref{tab:lit_comparison}, the unreleased devices in this work achieve moderate $f*Q$ in a commercially available process in an area smaller than comparable released devices. This, combined with the fact that the devices are integrated in the front-end-of-line of a commercial CMOS advanced technology node, opens the door for tight logic integration with minimum routing (and associated parasitics). Additionally, if process design rule challenges can be overcome, this performance can be achieved across a band of frequencies by varying gate length and phononic crystal design.

\begin{table*}
	\renewcommand{\arraystretch}{1.3}
	\centering
	\caption{Comparison with Contemporaneously Reported X and K$_\textrm{u}$ Band Resonators}
	\label{tab:lit_comparison}
	\begin{tabular}{|c|c|c|c|c|c|c|}
		\hline
		Ref & $f_0$ [GHz] & $Q$ & $f_0 * Q$ & Technology & Released & Area [um$^2$] \\
		\hline
		\textbf{This Work} & 11.7 & 69.8 & 8.2*10$^{11}$ & 14LPP & No & 135 \\
		\hline
		\cite{marathe_resonant_2014} & 11.5 & 24 & 2.8*10$^{11}$ & 32SOI  & No & 15 \\
		\hline
		\cite{chen_high-q_2019} & 8.8 & 750 & 6.6*10$^{12}$ & Custom AlN & Yes & 6,500 \\
		\hline
		\cite{assylbekova_11_2020} & 11.1 & 615 & 6.8*10$^{12}$ & Custom AlN & Yes & 675 \\
		\hline
		\cite{yang_1060-ghz_2020} & 13.0 & 282 & 3.7*10$^{12}$ & Custom LiNbO3 & Yes & 2,000 \\
		\hline
		\cite{abouyoussef_quad_2018} & 14.5 & 400 & 5.8*10$^{12}$ & PCB Microstrip  & - & 27,000,000 \\
		\hline
	\end{tabular}
\end{table*}

\section{Conclusion}

This work provides an in-depth experimental investigation into the influence of several design parameters on the performance of unreleased Resonant Fin Transistors in standard 14nm FinFET technology. Phononic crystal confinement, shown experimentally here to be the most important variation in improving unreleased resonator performance (2.2x improvement on average), provides significant opportunity for integrating acoustic devices into standard CMOS platforms. The highest performing resonator, a gradually terminated 80 nm gate length device with both Mx and Cx phononic crystal confinement, shows a transconductance amplitude and $Q$ of 4.49 µS and 69.8 respectively, with an $f*Q$ product of 8.19*10$^{11}$. At the same time, an analytical model has been demonstrated that predicts resonator performance across sense transistor biasing conditions, utilizing a combined velocity saturated current at DC and unsaturated mobility variation at AC, where acoustic perturbation of carrier effective mass modulates saturation velocity and mobility simultaneously. This highlights the importance of understanding the assumptions that go into developing advanced electrical models for short channel transistors, which may not accurately depict effects present in active electromechanical devices. While creating these phononic confinement schemes in a standard process with strict design rules poses a unique challenge, we have established a methodical way to predict and design resonator performance across multiple CMOS platforms. This technology combined with parallel advancements in CMOS-compatible ferroelectric and piezoelectric thin films, presents the opportunity to develop compact, low-cost, CMOS-integrated, and electrically-controllable resonators with no additional packaging required, opening the door for acoustic processing alongside traditional electronics in advanced CMOS nodes.

