\section{Introduction}\label{sec:introduction}}
\else
\section{Introduction}
\label{sec:introduction}
\fi




\IEEEPARstart{T}{his} demo file is intended to serve as a ``starter file''
for IEEE Computer Society journal papers produced under \LaTeX\ using
IEEEtran.cls version 1.8b and later.
I wish you the best of success.

\hfill mds
 
\hfill August 26, 2015

\subsection{Subsection Heading Here}
Subsection text here.


\subsubsection{Subsubsection Heading Here}
Subsubsection text here.













\section{Conclusion}
The conclusion goes here.








\appendices
\section{Proof of the First Zonklar Equation}
Appendix one text goes here.

\section{}
Appendix two text goes here.


\ifCLASSOPTIONcompsoc
 
  \section*{Acknowledgments}
\else
 
  \section*{Acknowledgment}
\fi


The authors would like to thank...


\ifCLASSOPTIONcaptionsoff
  \newpage
\fi






\section{Introduction}
This demo file is intended to serve as a ``starter file''
for IEEE Computer Society conference papers produced under \LaTeX\ using
IEEEtran.cls version 1.8b and later.
I wish you the best of success.

\hfill mds
 
\hfill August 26, 2015

\subsection{Subsection Heading Here}
Subsection text here.


\subsubsection{Subsubsection Heading Here}
Subsubsection text here.













\section{Conclusion}
The conclusion goes here.







\ifCLASSOPTIONcompsoc
 
  \section*{Acknowledgments}
\else
 
  \section*{Acknowledgment}
\fi


The authors would like to thank...








\section{Introduction}\label{sec:introduction}}





 
\IEEEPARstart{T}{he} amount of unstructured data processing from numerous modern computing platforms from mobile to the cloud is increasing rapidly, requiring an efficient framework to mitigate the gap between processor and memory system and accomplish the computational and storage demands of the current computing system even in advanced multi-core processors. Besides, nowadays, memories consume a significant power and chip area, becoming the computing system's main bottleneck. Moreover, continual scaling down in technology introduces immense challenges such as notable power consumption, substantial process variation, crucial transistor’s sensitivity with different operating conditions, etc., to the conventional memory chips. Existing mainstream volatile memory chips, i.e., static RAM (SRAM) and dynamic RAM (DRAM), suffer from density, scalability, memory persistency, and leakage issues. Besides, current non-volatile memory (NVM) chips (e.g., Flash) suffer from endurance and performance problems. These limitations make existing memory chips incompetent for delivering ever-increasing demands of power-efficient, high-performance systems with the growing number of cores and dataset sizes \cite{DRAM_limit}. 

Fortunately, data-intensive emerging applications in computer vision, graphics, multimedia, recognition, data mining, data-driven inference, and machine learning exhibit intrinsic error resilience property provide scopes of producing acceptable quality outputs even with data or computation approximations \cite{AC_survey}. By leveraging such applications' intrinsic error tolerance nature, approximate computing (AC) attains performance and power improvement by orders of magnitude using software, architecture, and circuit-level techniques \cite{AC_Han, AC_survey}. Therefore, these intrinsic characteristics of applications endow producing good-enough quality results even in noisy or slightly erroneous imprecise inputs. Hence, attracting great interest in designing or implementing approximate memories by relaxing the strict constraints in a controlled manner on data integrity, in turn, saves significant power consumption as well as improves performance notably.  

MRAM chip has significant potential to turn into a dominant universal memory (cache or main memory) technology due to its promising scopes such as non-volatility, scalability, high speed and fast access latencies, unlimited endurance, ultralow-power operation, CMOS compatibility, high density, reliability, near-zero leakage, almost zero static power, thermal robustness, and radiation hardness \cite{Survey_Ghosh}. These advantageous features make MRAM suitable to integrate into most of the systems. Therefore, MRAM can be an attractive candidate for energy efficiency on-chip memory. However, the higher write current for a sufficiently long duration is required for proper magnetic switching during the write operation still limits their overall energy efficiency. Several promising research has been performed on the circuit, device, and architecture levels to improve the energy efficiency of MRAM \cite{STT_Roy, STT_Jog, Hybrid_cache, AC_Tahoori}. This paper proposes a new dimension of MRAM-based approximate approach to attain significant power savings by introducing a small number of errors that most error-resilient applications can endure.

The major challenge in AC is managing the approximations to achieve the most favorable application quality vs. energy trade-off. Most AC-based prior works are focused on processing or logic circuits and can be categorized based on the targeted memory hierarchy level \cite{Flikker, AC_dram, AC_SRAM_Roy, AC_STT_Roy, AC_SRAM, AC_Load}. These works focus on (i) secondary storage and main memory \cite{Flikker, AC_dram}, (ii) application-specific memory designs \cite{AC_SRAM_Roy, AC_STT_Roy}, and (iii) CMOS memory-based approximate cache architecture \cite{AC_SRAM, AC_Load}. However, the existing MRAM-based AC framework is mostly simulation-based, requires extension in either new instruction set architecture (ISA) or enhancement in cache replacement policies along with device-circuit-architecture remodeling \cite{AC_STT_Roy, AC_Tahoori}. Hence, these MRAM-based AC frameworks can not be easily integrated into the existing computing system due to the above-mentioned strict requirements. The previous contributions inspirit the need for real memory implementation and build the foundation of the proposed MRAM-based AC framework using consumer-off-the-shelf (COTS) MRAM chips, which require minimal or no additional hardware, is robust against environmental fluctuations. Towards this end, our proposed system-level MRAM-based experimental AC framework yields significant power benefits for small probabilities of write failures by exploiting write latency variations of COTS MRAM chips. 

This paper presents a new approach to constructing an approximate MRAM framework. We also introduce a data allocation scheme based on the cell characterization algorithm for the proposed framework. The core idea is that at sub-optimal write latency, MRAM addresses can be split into accurate and approximate addresses through extensive error characterization of COTS toggle MRAM chips. The correlation between the obtained errors and the application-level output quality guides the proper allocation of application data to MRAM addresses. The more straightforward implementation of the proposed mechanism results in a better power-quality trade-off. In summary, the key contributions of this work are as follows.

\vspace{-0.2cm}
\begin{itemize}
  \item {We reduce the write enable ($\overline{W}$) time from the manufacturer's recommended value during the write operation to introduce errors. We perform an extensive characterization of these errors using COTS Everspin toggle MRAM chips \cite{everspin} to improve write power efficiency by exploiting the applications' error-resilient nature. The characterization results are used to derive key insights about memory errors — for example, toggling from '1` $\rightarrow$ '0` and '0` $\rightarrow$ '1` are mutually exclusive.}
  \item {Insights obtained from the characterization guide us in constructing a systematic data allocation scheme based on the application requirements to store critical and approximate data considering the occurrence and properties of MRAM errors by writing different intuitive and non-intuitive input data patterns. Subsequently, approximate data can be stored in the approximate addresses, whereas critical data must be allocated in entirely accurate memory addresses.} 
  \item {We analyze a detailed trade-off between the application-level output accuracy and system-level performance/power gains by determining optimal write latency.}
  \item {We implement our AC framework using our custom memory controller implemented on Xilinx Artix 7 (XC7A35T-1C) FPGA to manipulate different timing latency of a couple of emerging memories \cite{Alchitry}. Our experimental results demonstrate a significant improvement in the power-quality trade-off and show an average maximum write current savings of $\sim$$66\%$ with minimal or no loss in application quality.}
\end{itemize}
\vspace{-0.2cm}

The rest of the paper is organized as follows. Sect. \ref{sec:rel_work} provides an overview of related prior work. Sect. \ref{sec:back} briefly overviews the organization and operating principle of MRAM chips and related preliminaries of cache writing policies. Sect. \ref{sec:method} presents the proposed AC framework, including the cell characterization algorithm. Sect. \ref{sec:result} explains the experimental setup and exhibits obtained results. Sect. \ref{sec:discuss} discusses the characterization and memory overhead required to store the erroneous memory addresses and critical data protection. Finally, Sect. \ref{sec:end} concludes the article.

\vspace{-0.3cm}
\section{Related Work} \label{sec:rel_work}

This work correlates two distinct research areas \textendash~ emerging MRAM memories with approximate computing. Previous simulation-based MRAM-related work focuses on addressing spintronic memories' high write energy while preserving accurate read/write operations to achieve energy-efficient on-chip memories using the circuit, architectural, and device-level techniques \cite{STT_Kim, STT_Chatterjee, hybrid_Wu, hybrid_wang, STT_zhou, STT_cache_Roy, STT_Jog}. In \cite{STT_Kim}, using the bit-line voltage clamping technique, MRAM write-current asymmetry is mitigated at the circuit level to achieve the goal. Besides, in \cite{STT_Chatterjee}, a co-design methodology focusing on the bit-cell access transistor and the supply voltage is proposed to improve energy efficiency. Moreover, the MRAM cell's actual switching time detection technique is proposed to cease the unnecessary current flow immediately after a complete write \cite{stt_japan, STT_zhou}. Significant write energy reduction is achieved for such techniques; however, the overall write latency remains the same. On the other hand, at the architectural level, in \cite{hybrid_Wu,hybrid_wang}, the proposed hybrid CMOS-spintronic cache can selectively direct the write-intensive memory blocks to the CMOS portion while keeping the remaining blocks in the spintronic part to address the write-inefficiency of the spintronic memories. Besides, redundant memory writes are eliminated by comparing the previously stored data before the write operation \cite{STT_zhou} or tracking dirty data at a finer granularity \cite{STT_cache_Roy}. In addition, in \cite{stt_emre}, significant write margin reduction is achieved by exploiting incomplete write operations, and the incomplete bits are processed through robust Error Correction Codes (ECCs) at the cost of large decoding latencies (impairing the memory read latency). Furthermore, at the device level, in \cite{STT_Jog, stt_intel}, volatile spintronic memory is proposed by relaxing the non-volatility property (data-retention-time) or the current to overcome high write latency and energy issues of STT-MRAMs alongside the proposed refresh techniques can avoid data retention errors at the cost of higher error rate. Besides, in \cite{stt_smith}, the thermal stability factor \cite{tsf}, which defines the stability of the free layer's magnetic orientation against thermal noise, is reduced to address extreme write margin at the cost of higher overall failure rate and retention time. 

On the other hand, the previous AC-based framework explores different layers of abstraction spanning software or circuits, architectures, and algorithms to reduce the consumed energy in processing cores/accelerators. Introducing errors in the memory subsystem is an effective way of exploiting the applications' intrinsic error resilience. However, we concentrate on prior works related to approximate memories since that aligns with this work. Prior works on approximate DRAMs \cite{Flikker, AC_dram} relax their refresh rate to inject retention errors in the saved or read data contents in exchange for refresh power savings. On the other hand, \cite{AC_PCM} proposes approximate multilevel PCMs that can (i) reduce the number of programming pulses to inject write errors in exchange for energy savings and (ii) perform partial error correction on the most significant bits of the worn-out blocks. However, spintronic memories require exploring new techniques due to the in-applicability of the mentioned approximation mechanisms. Moreover, \cite{AC_STT_Roy} proposes simulation-based enhanced architectural and software approximate design models by accessing cells in the memory arrays with different current levels depending on application requirements at the cost of higher read/write error rates, that can (i) specify acceptable error probabilities for groups of bits within the word by controlling the quality of the read/write operations (ii) regulate (by software) the numerical significance of errors incurred during approximate load/store operations. However, this work entirely ignores the process variation effect. The process variation in spintronic memories affects both the MTJ cell and CMOS transistor parameters, which, in turn, impacts the parameters associated with read/write operations such as switching current, thermal stability factor, transistor's output current, etc. Consequently, the output accuracy at the architecture level will vary considerably with process variation due to these different and lower read/write access current levels. Furthermore, in \cite{AC_Tahoori}, another simulation-based new approximate spintronic on-chip memory design is proposed by relaxing both device and circuit parameters of spintronic memories by increasing various failure rates such as read disturb, retention and read decision failures, along with write errors to improve energy consumption and performance.

In contrast, our work renders an power-quality trade-off through a real memory implementation by employing COTS MRAM chips that (i) require minimal or no additional hardware, (ii) are robust against environmental fluctuations, and (iii) achieve power and performance improvements over and beyond the previous techniques, which is the key uniqueness of the proposed work.

\vspace{-0.3cm}
\section{Background} \label{sec:back}

\subsection{MRAM: Preliminaries}

The core element of toggle MRAM is the Magnetic tunnel junction (MTJ) that uses the Savtchenko switching \cite{toggle_mram} property by creating a rotating field with the sequential identical write current pulses to store both data states (high and low). The 1T-1MTJ MRAM bit cell comprises two ferromagnetic layers separated by a thin dielectric tunnel oxide ($\ce{AlOx}$ or $\ce{MgO}$) layer, built using advanced thin-film processing technology (shown in Fig. \ref{fig:MRAMcell}). One layer’s magnetic orientation is permanently fixed, commonly referred to as the reference (or fixed) magnetic layer (RML). In contrast, the other layer’s magnetization can freely be oriented depending on the magnetic field and known as the free magnetic layer (FML). The FML is composed of $\ce{NiFe}$ synthetic antiferromagnet (SAF). The substantially higher magnetic anisotropy of RML compared to FML ascertains stable magnetization direction of FML during memory read/write operation. The resistance states determine the bit which is going to store in the memory array. When both the FML and RML are aligned in the same direction (a large current passed from SelectLine (SL) to BitLine (BL) through the barrier layer), the MTJ produces low electrical resistance. On the other hand, when their magnetic field orientation is opposite, the resistance becomes extremely large; hence, almost no current or only a weak current flows through the barrier layer. Therefore,  the MTJ exhibits high electrical resistance.

\begin{figure*}[ht!]
    \centering
    \captionsetup{justification=centering, margin= 0.5cm}
    \begin{subfigure}[t]{0.35\textwidth}
        \centering
        \includegraphics[trim=0cm 10.5cm 20cm 0cm, clip, width=0.9\textwidth]{Figures/MRAM_toggle.pdf}
        \caption{}
        \label{fig:MRAMcell}
    \end{subfigure}%
    \begin{subfigure}[t]{0.35\textwidth}
        \centering
        \includegraphics[trim=0cm 7.5cm 14cm 0cm, clip, width = 0.9\textwidth]{Figures/Cell_Res.pdf}
        \caption{}
        \label{fig:cell_res}
    \end{subfigure}%
    \begin{subfigure}[t]{0.26\textwidth}
        \centering
       
        \includegraphics[trim=0cm 10cm 18cm 3.5cm, clip, width = 0.9\textwidth]{Figures/Cell_Res3.pdf}
        \caption{}
        \label{fig:TMR}
    \end{subfigure}
    \vspace{-0.3cm}  
    \caption{(a) Toggle MRAM cell structure with MTJ. (b) Schematic representation of Gaussian resistance ($R_{Low}$ and $R_{High}$ states) distribution of larger-sized MTJ array \cite{toggle_mram}. (c) Principle of tunneling magnetoresistance (TMR) \cite{TMR}.}
    \label{fig:MRAM}
\vspace{-0.3cm}    
\end{figure*}

Writing a bit in the magnetic field-driven toggle MRAM array requires passing a high write current ($I_w$) for changing FML's magnetic orientation \cite{toggle_mram}. The applied $I_w$ to the write lines, placed on top and bottom of the MTJ devices (see Fig. \ref{fig:MRAMcell}), creates an auxiliary magnetic field that changes the FML direction in the required position. Contrastingly, the RML's direction is strongly coupled with an anti-ferromagnet \cite{toggle_mram}. During the write operation, the memory circuit performs a pre-read operation to determine the state of the target bit and execute a toggle pulse (if required) to change the state of the bit if the desired state is not the same as the targeted state. Consequently, it reduces the overall power consumption and improves power efficiency. However, this increases the total write cycle time (including an additional read operation).

A small bias voltage (far below the device's breakdown voltage) is applied across the MRAM cell during the read cycle. Depending on parallel ($R_{Low}$) or anti-parallel ($R_{High}$) magnetic orientation, a current sensing circuitry that is attached with the MRAM cell experiences different current and latches the appropriate logic (`0' or `1') comparing with the reference resistance ($R_{Ref}$) shown in Fig. \ref{fig:cell_res}. The random resistance variation effect of a larger-sized MRAM array read circuitry is illustrated in Fig. \ref{fig:cell_res}. The accepted bits are those whose statistical separation is greater than $5\sigma$ from the mean, where $\sigma$ is the standard deviation. The accuracy of the read circuitry entirely depends on determining the actual resistance state in the tail region (useable resistance change, $\Delta R_{Use}$) of the distribution. For robust operation, less noise-sensitive, and high-speed read operation with normal process variation, large $\Delta R_{Use}$, and significantly more than $12\sigma$ separation are crucial \cite{toggle_mram}. Furthermore, the width of resistance distribution varies from cell to cell because of manufacturing process variations. Besides, the quality, size, and level of in-homogeneity of the MTJ tunnel barrier significantly impact larger relative bit-to-bit resistance variation \cite{toggle_mram}. Therefore, a thicker tunnel barrier ($\sim1nm$) is essential to maintain the resistance level of the MTJ in the kilo $\Omega$ range for minimizing the series resistance effect from the isolation transistor \cite{toggle_mram}, where $\Omega$ is the SI unit of resistance.

Magnetic state-based data storage has several advantages over charge-based storage, i.e., non-destructive read operation, no leakage during magnetic polarization, unlimited read/write endurance, no wear-out due to no movement of electrons/atoms during the switching process of magnetic polarization, etc. \cite{toggle_mram2}. Besides, Savtchenko switching-based MRAM arrays possess several important performance characteristics, such as lower write error rate and fast read/write cycle ($35 ns$). Less sensitivity to external fields makes them less sensitive to manufacturing process variations \cite{toggle_engel}. However, from Fig. \ref{fig:TMR}, 
we observe that the change in resistance due to the change in the induced magnetic field is steep in a certain region (the green region on Fig. \ref{fig:TMR}). In this region, a slight change in the induced magnetic field may cause a drastic change in resistance states and alter the decision of the read circuitry. Therefore, manufacturers define timing parameters for all commercial memory chips for reliable write/read operation of the memories against a wide range of operating conditions. For toggle MRAM, three different control parameters can govern the write operation of the MRAM chip: write enable ($\overline{W}$), chip enable ($\overline{E}$), and upper/lower byte enable ($\overline{UB}$/$\overline{LB}$) signals \cite{everspin}. A simplified version of the write enable ($\overline{W}$) controlled write operation of the MRAM chip is shown in Fig. \ref{fig:Everspin}.     

\begin{figure}[ht!]
\vspace{-0.3cm}
    \centering
    \captionsetup{justification=centering, margin= 0cm}
    \includegraphics[trim=0cm 11.5cm 10cm 0.5cm, clip, width = 0.4\textwidth]{Figures/Write_cycle.pdf}
    \vspace{-0.3cm}
    \caption{Write enable ($\overline{W}$) controlled write cycle of MRAM.}
    \label{fig:Everspin}
\end{figure}

Here,

$t_{WC}$ = \textit{write cycle time}, i.e., the time period to complete full write operation in a particular address.

$t_{W}$ = \textit{write~pulse~width}, i.e., the time period for which the $\overline{W}$ pin is kept activated. 

$t_{WR}$ = \textit{write~recovery~time}, i.e., the time to complete the write operation after the $\overline{W}$ pin is deactivated. 

$t_{DV}$ = \textit{valid~data~to~end~of write}, i.e., the time for which the valid data need to be available in the data I/O before the $\overline{W}$ pin is deactivated.  

If the output enable ($\overline{G}$) becomes active simultaneously or after $\overline{W}$ is activated, the output will remain in the high impedance state. After all three write control parameters ($\overline{E}$, $\overline{W}$, or $\overline{UB}$/$\overline{LB}$) become disabled, the $\overline{G}$ signal must remain in the steady-state high for at least $2 ns$. Reducing any of these timing parameters can improve the speed and reduce power consumption but may lead to faulty operation. The write timing parameter $t_{W}$ is manipulated in this work to introduce errors during the $\overline{W}$-controlled write operation.



\vspace{-0.3cm}
\subsection{Read vs. Write Latency}

\vspace{-0.05cm}
MRAM has the potential to be used both as the main memory and the cache. Due to the technology limitation, the MRAM is still much slower than the most commonly used SRAM cache ($\sim$$35ns$ access time on MRAM vs. $\sim$$2 \textendash 20ns$ access time on SRAM cache). Hence, in this section, we will keep our discussion limited by considering MRAM as the main memory. However, it is worth mentioning that our proposed reducing \textit{MRAM write latency} strategy will also improve the system performance, even if it is used as a cache.

In a computer system, the main memory is only accessed when there is a cache miss (read/write miss). Usually, recovering a read miss is a direct procedure; i.e., when a read miss occurs, the corresponding memory block (usually consists of multiple data words) of the main memory is copied directly to the cache. However, by taking proper caution at the software level, one can maximize the cache hit rate and hide the read access latency of the main memory. For example, in a modern computer processor, the average cache miss rate is $<$8\% for most use-cases \cite{Kumar_cache}. On the other hand, handling a write miss is more complex. Usually, most of the modern processors use either of the following two policies- (i) write-through policy with write allocation, (ii) write back policy with no-write allocation \cite{hennessy_Archi}. In the first policy, when a write miss occurs, the corresponding data are directly modified both on the cache and the main memory. Although this procedure is much simpler, it requires a long time to proceed; hence, it is not used in high-end processors. On the contrary, the second policy is a three-step procedure- (i) at first, the corresponding memory block is copied from the main memory to the cache, (ii) then, the processor only updates the target word in the newly copied cache block, (iii) lastly, when the cache is required to be evicted, the corresponding memory block is written back to the main memory. However, both cache miss policies become more complex if some of the memory resources are shared by the multiple processor cores (e.g., L2/L3 caches and the main memory) and require a dedicated cache coherency protocol. As the write miss recovery procedure is more complex than the read miss, the write miss penalty is much higher than the read miss penalty. Moreover, the write miss penalty might become a critical bottleneck for write-intensive program performance (e.g., iterative weight updating on neural networks). Hence, in this work, we aim to reduce such penalties by improving the write access time of MRAMs.


Furthermore, big data applications allow data approximation to some extent, motivating us to develop an AC framework to investigate the trade-off between application-level acceptable output accuracy vs. system-level power/performance gain in the memory system.
\vspace{-0.3cm}

\section{Approximate MRAM Framework} \label{sec:method}

Random Savtchenko switching property is exploited at the reduced timing parameter in our proposed methodology to obtain data approximation at the application level. At reduced \textit{write pulse width}, $t_{W}$, of toggle MRAM (see Fig. \ref{fig:Everspin}),  all memory cells do not receive sufficient write current and time to toggle into the intended stable state. These random variations are created in the MTJ storage element due to the process variation and the non-uniform distribution of the current pulse within the chip, which hinders performing an appropriate write operation in all memory cells. That is why the manufacturer specifies a set of timing parameters for reliable read/write operations. Hence, violation in any of these manufacturer-recommended timing parameters may cause erroneous/faulty outputs during the read/write operation. If the $t_{W}$ is insufficient, there is a high chance that FML cannot align perfectly with the RML (either same or opposite direction) and might be settled on an intermediate position, resulting in leading the cell resistance being halfway between $R_{Low}$ and $R_{High}$ \cite{TMR}. Therefore, at reduced $t_{W}$, if the resultant cell resistance falls around the $\Delta R_{Use}$ region of the resistance distribution (see Fig. \ref{fig:cell_res}) curve, the cell will show indeterministic characteristics and generate erroneous bits.

Several steps are involved in our proposed scheme. At the reduced $t_{W}$ , MRAM chips create errors, and the total number of errors differs at different reduced $t_{W}$ values. At first, we select the most suitable reduced $t_{W}$ value. This selected $t_{W}$ aims to generate erroneous bits at a tolerable range for the error-resilient applications. Second, we propose a cell selection algorithm to characterize all MRAM cells from a set of measurements by writing a specific data pattern that produces maximum error compared with other data patterns to identify the erroneous (approximate) and error-free (accurate) memory cells/addresses for the AC framework. These two steps must be performed only once to choose the appropriate number of MRAM cells/addresses. Finally, we collect data by writing all necessary data patterns into the entire memory to gain valuable insights about the bit errors' frequency, significance, and nature.

\vspace{-0.3cm}
\subsection{Appropriate Reduced Time Selection}

Appropriate reduced time selection is essential for obtaining the most favorable trade-off between application quality and power savings. Towards this end, the experimental results reveal that some of the memory cells provide erroneous outputs if the data is written at the reduced timing parameters \cite{mram_trng}. The number of these error-prone cells varies within the write pulse activation time range t = [0, $t_{W}$]. The total number of erroneous bit cells is counted by changing the $t_{W}$ and  writing different input data patterns at different $t_{W}$. The main objective is to determine a suitable $t_{W}$ for which the acceptable amount of erroneous bits is achieved. The number of erroneous cells is calculated from all achievable reduced write timing parameters in the next step. Finally, we propose an algorithm to characterize the erroneous memory cells for the AC framework using the timing parameter for which the sustainable amount of error bits is obtained.

\vspace{-0.3cm}
\subsection{Erroneous Address Selection} \label{subsec:cell_char}

Our experimental result manifests that only a few memory cells, hence addresses are error-prone at a specific sub-optimal write latency. To locate these cells, we characterize MRAM memory cells by writing different intuitive (solid) and nonintuitive (random, checkerboard, and striped) input data patterns to the entire memory cells at the reduced write enable time, $t_{W}$, and read back the entire memory contents with appropriate timing parameters a total of $N$ times. Larger $N$ provides better characterization results, also increases the computation time for characterization.

Theoretically, reduced write operation reduces the current flowing through the MTJ storage elements; hence, the magnetic direction (\textit{parallel (P)} $\rightarrow$ \textit{anti-parallel (AP)} or vice versa) toggling time increases significantly \cite{redu_write}. Switching from \textit{P} to \textit{AP} is more vulnerable to reduced write operation due to enhanced switching delay, leading to write failure. Likewise, from preliminary MRAM characterization with different data patterns and different reduced  $t_{W}$, we observe the followings:

\vspace{-0.2cm}
\begin{enumerate}
  \item {Error patterns and their nature and frequency depend entirely on the input data pattern to be written and vary with different memory chips.}
  \item {Experimental results also manifest that the write operation at the reduced $t_{W}$ produces comparatively more erroneous data for \textit{solid} \texttt{0x0000} data patterns.}
  \item {Silicon results further reveal that errors occur due to random variations in the MRAM having no relation to its internal hardware implementation.}
\end{enumerate}
\vspace{-0.2cm}

Furthermore, error patterns from the sample measurements reveal that
allocating data randomly to the MRAM at reduced $t_{W}$ can degrade application-level output quality and cause complete or partial application failure, necessitating a systematic method to track the errors on different addresses and allocate the application data according to their criticality. Toward this end, we split the entire memory space into accurate and approximate addresses based on the error characteristics to efficiently allocate addresses of different applications to tolerate different error amounts for generating acceptable output quality. These accurate addresses can be coalesced logically into a required contiguous entirely accurate memory chunk by only tracking the approximate addresses for critical data allocation (devoid of any error) by noting the error characteristics.

For the proposed AC framework, addresses that contain erroneous cells need to be filtered. At first, we discover all erroneous cells, hence addresses, at the reduced $t_{W}$ from ($N$) measurements using the data pattern that produces maximum errors. Next, we count and locate the total number of bit errors (if any) in each memory address, comparing the data to be written at reduced $t_W$ and reading back the written data at the appropriate timing parameter, and categorize them (lines 1 - 9 of Algo. \ref{alg:mramChar}) accordingly taking the union of the error-prone addresses that occur across different measurements. The pseudo-code for erroneous address selection and accumulation (strategy 1) and sorting (strategy 2) is shown in Algorithm \ref{alg:mramChar}. The sorting of erroneous addresses is performed based on the stored data (\textit{sD}) and intended data to be written (\textit{oD}) (lines 11 - 18). The entire AC framework methodology is split into two phases: the training and evaluation phase. In the training phase, error-prone addresses are accumulated from $N$ measurements using the most erroneous input data pattern. In the evaluation phase, error statistics and output quality is analyzed using different input data patterns and test big data applications.  

\vspace{-0.3cm}
\begin{algorithm}[ht!]
\SetAlgoLined
    \KwData{
        $N$: \note{Number of total measurements.} \break 
        $A$: \note{Set of addresses in MRAM.} \break
        $\mathcal{E_A}$: \note{Set of total erroneous addresses from $N$ measurements.} \break
        $wL$: \note{Word Length} \break
        $oD$: \note{$(A \times wL)$ matrix containing data intended to write each memory cells} \break
        $sD$: \note{$(A \times wL)$ matrix containing data stored to each memory cells at reduced $t_W$} \break
        $\mathcal{E_A^Q}$: \note{$\mathcal{E_A}$ where higher value of $\mathcal{Q}$ represents lower quality level at reduced $t_W$.}}
    
    \KwResult{\note{Characterized MRAM}}
    \tcp{Initialization} 
    $\mathcal{E_A} = \{ \}; \mathcal{E_A^Q} = \{ \};$ \break
    \For{$i = 1$ to $N$}{
        \tcp{Strategy 1}
         \ForEach{a $\in$ A}{
          \If{check\_error (a)}{
            \If{a $ \notin \mathcal{E_A}$}{ 
                $\mathcal{E_A} = \mathcal{E_A} \cup \{a\}$\;
                }
            }
         }
    }
    $\mathcal{E_A^Q} = sort\_addr(sD, \mathcal{E_A});$ \tcp{Only for Strategy 2}
    \BlankLine
    \SetKwFunction{FFunc}{sort\_addr}
    \SetKwProg{Fn}{Function}{:}{}
    \Fn{\FFunc{$sD, \mathcal{E_A}$}}{
        $oD = empty()$\;
        $oD = init()$; \tcp{Initialize} \break
        $x = bitwise\_xor(oD, sD)$\;
        $x = bin2Dec(x,dim=2)$\;
        $idx = argsort(x)$\;
        $\mathcal{E_A}^{sort} = \mathcal{E_A}[idx]$\;
        \KwRet $\mathcal{E_A}^{sort}$}
 \caption{Pseudo-code for accumulating erroneous addresses through  error characterization}
 \label{alg:mramChar}
\end{algorithm}
\vspace{-0.3cm}

In strategy 2, we sort all the error-prone MRAM addresses in ascending order with decreasing (increasing) quality (number of errors) according to the total number of bit errors present in each word based on the occurrence and bit positions of the errors. A larger number of bit errors at the most significant bits (MSB) position denote higher application quality degradation; therefore, those addresses are assigned to lower-level positions. Besides, bytes/half-words can also be chosen instead of words (if required) as the error granularity. This decision depends entirely on the stored data's nature and can be trivially extended. Fig. \ref{fig:errAddrSel} depicts the sorting strategy. Data allocation is performed to each address in the sorted order, i.e., data is first assigned to the least erroneous addresses and later to addresses with higher errors ensuring that at reduced $t_W$ the stored data always incurs the least amount of errors. However, each application's critical data allocation requires to be performed to entirely accurate addresses. Experimental results reveal that the obtained enormous amount of accurate addresses is sufficient for most of the applications. Next, approximate data can be allocated to either accurate (based on availability) or erroneous addresses sorted according to the number of errors. As (i) sorting the erroneous addresses require extra overhead and complexity and (ii) most of the big data applications, the performance of strategy 1 is sufficient enough (see Sect. \ref{subsec:res_C}), so we propose strategy 2 in this work for any further performance enhancement (if required) for any potential suitable future error-resilient applications. 

\begin{figure}[ht!]
\vspace{-0.4cm}
    \centering
    \captionsetup{justification=centering, margin= 0.5cm}
    \includegraphics[trim=0cm 10cm 20.5cm 0cm, clip, width = 0.38\textwidth]{Figures/err_addr_sort.pdf}
    \vspace{-0.3cm}
    \caption{Strategy 2 for sorting erroneous addresses.}
    \label{fig:errAddrSel}
\vspace{-0.3cm}
\end{figure}

\vspace{-0.3cm}
\section{Experimental Setup, Results, \& Analysis} \label{sec:result}

The preliminary analysis is performed over ten (2 chips from each \textit{MR0A16ACYS35, MR0A16AYS35, MR1A16AYS35 MR2A16ACYS35, MR2A16AYS35} models) 16-bit parallel interfaced differently sized ($1 Mb - 4 Mb$) memory chips to verify our proposed scheme. These chips belong to Everspin technologies. Table \ref{Tab:MRAM_Char} captures the key features of the memory chips. Among them, five chips are selected randomly to perform extensive analysis to verify our observations' true universality. The characterization is performed using our custom memory controller implemented on the Alchitry Au development board containing \textit{Xilinx Artix 7 (XC7A35T-1C)} FPGA to manipulate different timing latency of a couple of emerging memories \cite{Alchitry}. The temperature (low/high) experiments were performed by placing the memory socket that holds the memory chip in \textit{Temptronic ATS-605 ThermoStream} to maintain a uniform temperature. Furthermore, the current analysis was performed using a $100 MHz$ \textit{Siglent CP5030A} current probe and monitored with a $1 GHz$ \textit{Siglent SDS5104X} oscilloscope. 

According to Sect. \ref{subsec:cell_char}, the generated errors are pattern-dependent at reduced write operation. Hence to determine the suitable pattern, a total of 5-set measurement data is collected with seventeen different intuitive (solid) and non-intuitive (random, checkerboard, and striped) 16-bit input data patterns: (\texttt{0xFFFF, 0xAAAA,0x5555, 0x0000}) from each ten memory chips. We observed that the \textit{solid} \texttt{0x0000} pattern produces comparatively high erroneous bits than other data patterns. Based on the observation, we can conclude that the \textit{parallel (anti-parallel)} configuration is the logic state '1' (state '0'). Next, to characterize the MRAM cells (discussed in Sect. \ref{subsec:cell_char}), we collected a total of 50-set measurement data with only a \textit{solid} \texttt{0x0000} input pattern from the randomly selected five memory chips. We chose the value of $t_W$, $33.3\%$ of the recommended $t_W$, for this work to obtain approximate writes. However, our selected value of $t_W$ can generate a sufficient number of accurate addresses (moderate number of incorrect outputs) for the proposed framework.

\begin{table}[ht!]
\caption{MRAM Chip Specifications \cite{everspin}.}
\setcellgapes{2pt
\captionsetup{justification=centering, margin= 0cm}
\vspace{-0.3cm}
\makegapedcells
\centering
\setlength\tabcolsep{2pt} 
\resizebox{0.41\textwidth}{!}
{
    \begin{tabular}{|l|r|}
    \hline
    \multicolumn{1}{|c|}{Parameter} & \multicolumn{1}{c|}{Standard Value} \\ \hline
    Capacity, Supply Voltage                        & 1 - 4 Mbit, 3.3 V                 \\ \hline
    Read/Write Cycle ($t_{WC}$)     & 35 ns                      \\ \hline
    Write Pulse Width ($t_W$)       & 15 ns                      \\ \hline
    Write Recovery Time ($t_{WR}$)  & 12 ns                      \\ \hline
    Valid Data to end of Write ($t_{DV}$) & 10 ns                      \\ \hline
    Address/Data Bus Length         & 16 - 18/16                 \\ \hline
    Retention Time                  & \textgreater 20 years      \\ \hline
    AC stand by Current             & 18–28 mA                   \\ \hline
    AC Active Current (Read/Write)  & 55–80 mA/105–165 mA        \\ \hline
    \end{tabular}
}
\label{Tab:MRAM_Char}
\end{table}

Analyzing results from the conducted experiments validate our proposed scheme's novelty and provide interesting insights. The results are divided into four broad subsections. In the first part, we manifest the quality (number of erroneous cells/addresses) power (write current) trade-off for selecting the reduced $t_W$ appropriately, a universal trait in any approximate computing mechanism. The second part presents the characterization results in detail applying Algo. \ref{alg:mramChar}. The third part shows how the output quality is affected when data is written into the memory with different initialized values and with or without applying the proposed address selection strategy (strategy 1 of Algo. \ref{alg:mramChar}). We also show that our approach results in significantly higher power savings than many popular (non) volatile memory-based prior works \cite{AC_Tahoori, Flikker, AC_dram, AC_STT_Roy}. Moreover, an efficient implementation of a memory controller can further improve the overall performance of our proposed framework. Note that all results presented in the Sects. \ref{subsec:res_B} and \ref{subsec:res_C} are obtained at room temperature ($26^{\circ}C$). Finally, the fourth part describes the results obtained using the approximate MRAM subject to environmental and memory chip variations. 

\subsection{Selection of \texorpdfstring{$t_W$}{Lg}}\label{subsec:res_A}

An extensive analysis is performed to determine the error profile, such as frequency, location of the bit errors, comparing the behavior of the faulty/erroneous outputs at different reduced $t_W$ values using \textit{solid} \texttt{0x0000} data pattern. We reduce the $t_W$ value from $15 ns$ (manufacturer's recommended) to  $10 ns$, $5 ns$, and $2.5 ns$, respectively. Due to the experimental setup limitations, we are incapable of reducing the $t_W$ value any further. At $t_W$ = $2.5 ns$, the total number of failed bit count falls within $25.59\% - 37.30\%$, which is sufficient for TRNG or PUF analysis \cite{mram_trng} but not suitable for data approximation. However, at $t_W$ = $5 ns$ and $10 ns$, the obtained total failed bits are almost negligible ($< 5\%$ and $< 1\%$, respectively) for all ten chips. Hence, we choose $t_W$ = $5 ns$ (considering the number of failed bit counts) to characterize erroneous cells to notably enhance system performance and power savings. Fig. \ref{fig:Curr_Ana} portrays the write current observed in different $t_W$ values. It shows that a suitable decrease in $t_W$ decreases notable power consumption by maintaining a sufficient number (see Table \ref{Tab:Char1}) of accurate addresses (and hence output quality).

\subsection{Characterization of Error-Prone Cells}\label{subsec:res_B}

The cell characterization of MRAM is performed according to Sect. \ref{subsec:cell_char} with $N = 50$ temporal measurements. \textit{Solid} \texttt{0x0000} is used as the write data pattern. Moreover, the entire memory is reset with the \textit{solid} \texttt{0xFFFF} data pattern before every measurement to erase the trace of previously written data. In Table \ref{Tab:Char1}, the first two rows show the statistics of erroneous MRAM addresses and bits after performing the proposed cell characterization algorithm (strategy 1 of Algo. \ref{alg:mramChar}). Here, $\mathcal{E_A} (\mathcal{E_B})$is the percentage of total erroneous addresses (bits) from 50 temporal measurements (obtained through characterization). The results manifest that the total number of erroneous bits obtained at reduced $t_W$ ($2.5 ns$) varies from chip to chip. Besides, only a few addresses hold these erroneous bits. The rest of the rows represent erroneous addresses (bits) from different data patterns and to which extent they belong to $\mathcal{E_A} (\mathcal{E_B})$. Here, $\mathcal{M_A} (\mathcal{M_B})$ is the percentage of total erroneous addresses (bits) from a specific data pattern, and $\mathcal{C_A} (\mathcal{C_B})$ is the percentage of $\mathcal{M_A} (\mathcal{M_B})$ belongs to $\mathcal{E_A} (\mathcal{E_B})$.

We observe that the maximum erroneous addresses (bits) range from different memory chips are only $[5.33\%,~26.41\%] ~ ([3.89\%,~22.06\%])$ after performing characterization at $t_W = 5 ns$. This indicates that $\sim$$75\%$ ($\sim$$78\%$) of the addresses (bits) are entirely accurate, resulting in negligible or no loss in output quality. As the percentage of erroneous addresses is fairly small ($\sim$$25\%$) regardless of memory size,  storage overhead is minimal for storing these few memory addresses' information.

For pattern \texttt{0xAAAA} or \texttt{0x5555}, we do not observe any error for any data pattern. Base on the internal architecture of MRAM, there might be different reasons behind not getting any error. For example, if all of the I/O buffers are driven by the same power rail, the inrush current caused by the I/O buffers should be lower for these specific data patterns as only 8 out of 16 bits experience the switching \cite{inrush}. Hence, the overall timing characteristics might be improved \cite{inrush}. Moreover, the obtained erroneous addresses, $\mathcal{M_A}$ (bits, $\mathcal{M_B}$) in reduced $t_W$ are in the range $[0.16\%,~6.04\%]~([0.08\%,~3.30\%])$ for any other data patterns considering all memory chips, while most of these belong/close to the lower limit. Besides, our proposed characterization technique covers most erroneous addresses, $\mathcal{C_A}$ (bits, $\mathcal{C_B}$) for all data patterns. Although the lowest covered erroneous addresses, $\mathcal{C_A}$ (bits, $\mathcal{C_B}$) is $1.74\%~(2.76\%)$ for the \textit{solid} \texttt{0xFFFF} data pattern; however, a closer observation reveals that \textit{solid} \texttt{0xFFFF} data pattern produces only $0.26\%~(0.23\%)$ error addresses (bits) which itself is negligible ($< 0.5\%$). This insignificant number of errors can be overlooked for any big data application.

\vspace{-0.3cm}
\subsection{Evaluation}\label{subsec:res_C}

We use the most common and popular metrics, signal-to-noise ratio (SNR) and mean squared error (MSE), between the approximated image and the original image to evaluate and measure the acceptability of the application output quality. The SNR and MSE are calculated using the following equations (Eqs. \ref{eqn:snr} and \ref{eqn:mse}) based on the original image, $f(i,j)$, and the approximated image, $\hat{f}(i,j)$, obtained after performing the proposed approximate framework. Note that the size of the images is $M \times N$.  

\begin{table}[ht!]
\caption{Error Characteristics.}
\setcellgapes{1pt
\captionsetup{justification=centering, margin= 0cm}
\vspace{-0.3cm}
\makegapedcells
\centering
\setlength\tabcolsep{5pt} 
\resizebox{0.48\textwidth}{!}
{
    \begin{tabular}{|c|c|c|c|c|c|c|c|}
    \hline
    \multicolumn{2}{|c|}{Sample Chip\footnotemark}                                                                & (\%) & C1    & C2    & C3    & C4    & C5    \\ \hline
    \multicolumn{2}{|c|}{\multirow{2}{*}{Characterization}}                                          & $\mathcal{E_A}$ & 22.41 & 26.41 & 10.34 & 8.36  & 5.33  \\ \cline{3-8} 
    \multicolumn{2}{|c|}{}                                                                           & $\mathcal{E_B}$ & 10.49 & 22.06 & 7.60  & 5.15  & 3.89  \\ \hline
    \multirow{8}{*}{Solid}                                                   & \multirow{4}{*}{\texttt{FFFF}} & $\mathcal{M_A}$ & 0.26  & 0.26  & 0     & 0     & 0     \\ \cline{3-8} 
                                                                             &                       & $\mathcal{M_B}$ & 0.11  & 0.23  & 0     & 0     & 0     \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_A}$ & 1.74  & 60.81 & ----  & ----  & ----  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_B}$ & 2.76  & 54.39 & ----  & ----  & ----  \\ \cline{2-8} 
                                                                             & \multirow{4}{*}{\texttt{0000}} & $\mathcal{M_A}$ & 2.52  & 6.04  & 1.83  & 2.04  & 1.29  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{M_B}$ & 0.83  & 3.30  & 1.25  & 1.36  & 0.86  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_A}$ & 96.92 & 99.28 & 95.26 & 86.23 & 94.34 \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_B}$ & 85.48 & 98.36 & 94.37 & 80.73 & 91.5  \\ \hline
    \multirow{8}{*}{\begin{tabular}[c]{@{}c@{}}Row\\ Striped\end{tabular}}    & \multirow{4}{*}{\texttt{FFFF}} & $\mathcal{M_A}$ & 1.99  & 3.52  & 0.72  & 0.82  & 0.62  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{M_B}$ & 0.67  & 2.13  & 0.53  & 0.56  & 0.47  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_A}$ & 97.78 & 99.55 & 95.2  & 92.87 & 95.78 \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_B}$ & 90.9  & 98.34 & 94.42 & 91.43 & 94.11 \\ \cline{2-8} 
                                                                             & \multirow{4}{*}{\texttt{0000}} & $\mathcal{M_A}$ & 0.75  & 2.63  & 0.94  & 1.09  & 0.67  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{M_B}$ & 0.18  & 1.25  & 0.61  & 0.68  & 0.40  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_A}$ & 97.77 & 99.45 & 96.8  & 84.29 & 94.03 \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_B}$ & 83.07 & 98.55 & 96.02 & 76.87 & 90.46 \\ \hline
    \multirow{8}{*}{\begin{tabular}[c]{@{}c@{}}Column\\ Striped\end{tabular}} & \multirow{4}{*}{\texttt{FFFF}} & $\mathcal{M_A}$ & 1.68  & 0     & 1.06  & 1.27  & 0.89  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{M_B}$ & 0.67  & 0    & 0.71  & 0.79  & 0.60  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_A}$ & 87.4  & ---   & 93.13 & 90.23 & 89.82 \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_B}$ & 74.8  & ---   & 92.75 & 89.73 & 88.73 \\ \cline{2-8} 
                                                                             & \multirow{4}{*}{\texttt{0000}} & $\mathcal{M_A}$ & 1.37  & 1.18  & 0.32  & 0.37  & 0.22  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{M_B}$ & 0.54  & 0.94  & 0.19  & 0.20  & 0.12  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_A}$ & 46.99 & 90.73 & 51.74 & 32.89 & 34.93 \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_B}$ & 47.51 & 93.23 & 51.25 & 29.09 & 35.42 \\ \hline
    \multirow{8}{*}{\begin{tabular}[c]{@{}c@{}}Checker-\\ board\end{tabular}} &
      \multirow{4}{*}{\texttt{FFFF}} &
      $\mathcal{M_A}$ &
      1.59 &
      3.05 &
      0.71 &
      0.84 &
      0.61 \\ \cline{3-8} 
                                                                             &                       & $\mathcal{M_B}$ & 0.60  & 1.77  & 0.51  & 0.53  & 0.41  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_A}$ & 76.3  & 96.02 & 83.44 & 74.97 & 79.47 \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_B}$ & 68.07 & 93.81 & 83.96 & 76.62 & 80.64 \\ \cline{2-8} 
                                                                             & \multirow{4}{*}{\texttt{0000}} & $\mathcal{M_A}$ & 1.25  & 2.96  & 0.64  & 0.75  & 0.49  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{M_B}$ & 0.59  & 1.55  & 0.40  & 0.42  & 0.29  \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_A}$ & 62.61 & 96.02 & 85.71 & 83.54 & 81.54 \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_B}$ & 60.43 & 93.62 & 83.97 & 82.49 & 79.89 \\ \hline
    \multirow{4}{*}{\begin{tabular}[c]{@{}c@{}}Any\\ Pattern\footnotemark\end{tabular}} &
      \multirow{4}{*}{\begin{tabular}[c]{@{}c@{}}\texttt{5555} /\\ \texttt{AAAA}\end{tabular}} &
      $\mathcal{M_A}$ &
      0 &
      0 &
      0 &
      0 &
      0 \\ \cline{3-8} 
                                                                             &                       & $\mathcal{M_B}$ & 0     & 0     & 0     & 0     & 0     \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_A}$ & ----  & ----  & ----  & ---   & ---   \\ \cline{3-8} 
                                                                             &                       & $\mathcal{C_B}$ & ----  & ----  & ----  & ---   & ---   \\ \hline
    \multicolumn{2}{|c|}{\multirow{4}{*}{Random}}                                                    & $\mathcal{\mathcal{M_A}}$ & 0.27  & 0.28  & 0.22  & 0.19  & 0.16  \\ \cline{3-8} 
    \multicolumn{2}{|c|}{}                                                                           & $\mathcal{M_B}$ & 0.13  & 0.13  & 0.11  & 0.42  & 0.08  \\ \cline{3-8} 
    \multicolumn{2}{|c|}{}                                                                           & $\mathcal{C_A}$ & 34.83 & 68.94 & 13.97 & 10.18 & 10.12 \\ \cline{3-8} 
    \multicolumn{2}{|c|}{}                                                                           & $\mathcal{C_B}$ & 20.99 & 62.47 & 11.5  & 7.55  & 8.02  \\ \hline
    \multicolumn{8}{l}{$^{\mathrm{*}}$NB. —- not performed as no error occurred at reduced $t_W$ for} \\
    \multicolumn{8}{l}{ corresponding data patterns.}
    \end{tabular}
}
\label{Tab:Char1}
\vspace{-0.6cm}
\end{table}
\footnotetext[1]{C1: MR0A16AYS35, C2: MR1A16AYS35, C3\&C4: MR2A16ACYS35, C5: MR2A16AYS35. C1,C2\&C5: Commercial Grade (Temp. range [$0^{\circ}C,~70^{\circ}C$]); C3\&C4: Industrial Grade (Temp. range [$-40^{\circ}C,~85^{\circ}C$]).}
\footnotetext[2]{Solid/ Striped/ Checkerboard.}


\vspace{-0.3cm}
\begin{equation}\label{eqn:snr}
    \begin{split}
    SNR = \frac{\sum_{i = 1}^{M}\sum_{j = 1}^{N}\hat{f}(i,j)^{2}} 
    {\sum_{i = 1}^{M}\sum_{j = 1}^{N}[\hat{f}(i,j) - f(i,j)]^2}
    \end{split}
\end{equation}

\begin{equation}\label{eqn:mse}
    MSE = \frac{1}{MN}\sum_{i = 1}^{M}\sum_{j = 1}^{N}[\hat{f}(i,j) - f(i,j)]^2
\end{equation}

The value of SNR and MSE measures the image's quality in image processing applications, evaluating the proposed scheme's effectiveness. A minimum SNR value is required for such applications for the approximated image where the human brain and eyes can differentiate between the approximated and original image. A lower (higher) SNR (MSE) value is considered as unacceptable output quality and vice versa. The SNR and MSE measurements reveal the degree to which an application could produce satisfactory and reasonable output at reduced $t_W$ for approximate applications and determine the achievable limits of the performance and power improvements for MRAM technology. Fig. \ref{fig:img_proc} shows the original and approximate output image quality (represented quantitatively by SNR and MSE) with and without applying the proposed addresses selection technique (strategy 1 of Algo. \ref{alg:mramChar}), considering two different initialization states. The SNR (MSE) of the image is infinite (zero) means it does not have any errors relative to the original image output. Observing the images and the related SNR and MSE reveals the appropriateness of the proposed technique through improved application quality. Note that the test image pixels are allocated in entirety to each of the required memory addresses. 

\begin{figure*}[ht!]
    \centering
    \captionsetup{justification=centering, margin= 0cm}
    \begin{subfigure}[t]{0.5\textwidth}
        \centering
        \includegraphics[trim=0cm 5cm 10cm 0cm, clip, width=0.99\textwidth]{Figures/mr3ch1.pdf}
        \caption{}
        \label{fig:mr3ch1}
    \end{subfigure}%
    \begin{subfigure}[t]{0.5\textwidth}
        \centering
        \includegraphics[trim=0cm 5cm 10cm 0cm, clip, width = 0.99\textwidth]{Figures/mr4ch2.pdf}
        \caption{}
        \label{fig:mr4ch2}
    \end{subfigure}
    \vspace{-0.3cm}
    \caption{(a) Commercial (b) industrial-grade MRAM. \nth{1} column of (a) and (b) represents: original image (90 × 90) which is written to the MRAM; \nth{2} \& \nth{3} columns represent: the entire memory is initialized with all 1's before writing the image at reduced $t_W$ then reading back the memory contents without and with address selection respectively; \nth{4} column represents: the entire memory is initialized with all 0's before writing the image at reduced $t_W$ then reading back the memory contents without address selection.}
    \label{fig:img_proc}
    \vspace{-0.3cm}
\end{figure*}

Moreover, we evaluate the effectiveness of applying the address selection technique. The results depict the influence of address selection on application quality, which is necessary to understand the impact of approximate data placement in memory addresses. This, in turn, is useful to comprehend how application quality changes with initialized values. In Fig. \ref{fig:img_proc}, the \nth{2} \& \nth{3} columns show the read-back image without and with applying the address selection technique, respectively. It is evident that the image quality improvement obtained using the proposed address selection technique is substantially better than without applying the technique, underscoring the need for the proposed address selection. However, as switching from '1` $\rightarrow$ '0` is more vulnerable at reduced $t_W$, requiring more write current for the prolonged duration; hence, initializing the entire memory with all 1's requires address selection technique to attain negligible or no loss in the output quality. Contrarily, initializing the entire memory with all 0's does not require an address selection technique to obtain the same level of output quality. Furthermore, we also observe that commercial-grade MRAM is more vulnerable to reduced $t_W$ than industrial-grade MRAM due to internal MRAM architecture. Therefore, without applying the address selection technique in industrial-grade MRAMs, we notice a negligible loss in the output quality.

\begin{figure}[ht!]
    \centering
    \captionsetup{justification=centering, margin= 0cm}
    \includegraphics[trim=0cm 8.5cm 25.5cm 0cm, clip, width=0.3\textwidth]{Figures/cp_0a.pdf}
    \vspace{-0.3cm}
    \caption{Write current analysis using \textit{solid} \texttt{0x0000} pattern.}
    \label{fig:Curr_Ana}
\vspace{-0.3cm}
\end{figure}

We next present the result that demonstrates the obtained power efficiency. To measure the write current, hence, power, we use a current probe and oscilloscope. However, the analog bandwidth of the current probe is $100 MHz$; hence, the resolution of the current probe is greater than $10ns$. Therefore, we are incapable of measuring the accurate write current at reduced $t_W = 5ns$. Due to the absence of proper equipment, we relied on the measurement supported by our current probe to measure the write current concerning a prolonged write cycle time ($60ns$ $>$ standard $15ns$). Fig. \ref{fig:Curr_Ana} portrays the write current analysis for the \textit{solid} \texttt{0x0000} pattern, which produces the maximum number of errors in the reduced write operation. The \nth{1} half of the signal shows the consumed current during the write operation, and the \nth{2} half shows the discharge current. Here the normalized current values at points $t_{0ns}, t_{5ns}$, and $t_{20ns}$ are $0, 0.34$, and $1$, respectively. The temporal distance between points $t_{0ns}$ and $t_{5ns}$ is $5ns$ (reduced $t_W$ used in our proposed scheme), and $t_{0ns}$ and $t_{20ns}$ is $20ns$ ($>$ standard $t_W = 15ns$ for COTS MRAM). As $p \propto i^2$, where $p =$ power and $i =$ current, hence the obtained power reduction is $p_{red}= \frac{(1^2-0.34^2)}{1^2} = 0.88$, illustrating the effectiveness of the proposed framework to achieve power benefits through approximations.

\vspace{-0.3cm}
\subsection{Effect of Environmental and Chip Variations}\label{subsec:res_D}

Random thermal fluctuations and process variation exacerbate the intrinsic stochasticity of the magnetic orientation switching of MRAM cells; hence, significantly varies the switching time of the cell over the entire memory array. Therefore, the MRAM write failure rate increase significantly as temperature increases \cite{Ferdaus2021}. To incorporate the temperature effect, hence, covering maximum erroneous addresses, we can perform the characterization at a high temperature compared with the maximum operating temperature used during normal execution. Our observation is that errors occurring at a lower temperature are a subset of those occurring at high temperatures; therefore, guaranteeing no additional bit errors in the lower temperature range. The highest temperature used for characterization can be determined within the manufacturer's recommended value covering all MRAM models (in our case, $65^{\circ}C$), suitable for commercial applications. In our experiments, the characterization and evaluation are performed at room temperature ($26^{\circ}C$). To demonstrate the temperature effect on MRAM errors, we evaluate results for both high ($65^{\circ}C$) and low ($20^{\circ}C$) temperatures and compare them with room temperature ($26^{\circ}C$). The temperature range is chosen within the manufacturer's recommended value, which is $[ 0^{\circ}C,~70^{\circ}C]$ suitable for all memory models used in the experiment. 

We observe that the total number of errors and erroneous addresses increase with higher temperatures. However, no significant change is observed in the total number of erroneous addresses at low temperature ($20^{\circ}C$) and temperature range up to $45^{\circ}C$ (see Fig. \ref{fig:img_proc_ht}). As the thermal noise becomes low at low temperatures, it has less impact on the reduced operation. Therefore, only results at $65^{\circ}C$ temperature (worst case) are shown in Table \ref{Tab:Char_ht} as the obtained errors are insignificant at low temperatures. The obtained erroneous addresses, $\mathcal{M_A}$ (bits, $\mathcal{M_B}$) at $65^{\circ}C$ in reduced $t_W$ are in the range $[0.002\%,~16.00\%]~([0.002\%,~8.98\%])$ for any data patterns (except \texttt{0xAAAA} or \texttt{0x5555}) considering all memory chips. Comparing with the nominal operating condition (Table \ref{Tab:Char1}), we observe a maximum of $\sim$$1.65\times$ ($\sim$$1.72\times$) increase in the erroneous addresses (bits) at $65^{\circ}C$ temperature. Contrarily, the obtained erroneous addresses, $\mathcal{M_A}$ (bits, $\mathcal{M_B}$) at $20^{\circ}C$ in reduced $t_W$ are in the range $[0.0004\%,~3.89\%]~([0.0001\%,~2.21\%])$ for any data patterns considering all memory chips. Comparing with the nominal operating condition (Table \ref{Tab:Char1}), we observe a maximum of $\sim$$0.36\times$ ($\sim$$0.33\times$) decrease in the erroneous addresses (bits) at $20^{\circ}C$ temperature. Although a detailed assessment is not performed, the obtained results reveal that the errors occurred at lower temperatures are a subset of the errors at high temperature. 

Furthermore, to observe the impact of external magnetic field (M-Field), we collected a set of test data sequence at room temperature ($26^{\circ}C$) with an $\sim$$8mT$ external M-Field by applying a constant rare earth magnetic source generated from a set of permanent magnets in six different orientations of 3D coordinates. However, no significant change is observed in the total number of erroneous cells with ($\sim$$8mT$) external M-Field. The obtained erroneous addresses, $\mathcal{M_A}$ (bits, $\mathcal{M_B}$) in reduced $t_W$ are in the range $[0.005\%,~7.60\%]~([0.0002\%,~4.52\%])$ for any data patterns considering all memory chips. Comparing with the nominal operating condition (Table \ref{Tab:Char1}), we observe a maximum of $\sim$$0.26\times$ ($\sim$$0.37\times$) increase in the erroneous addresses (bits). Hence, we can conclude that the external M-Field does not significantly impact the number of error occurrences.  

The silicon results from five different memory models of three different sizes show that the statistics of erroneous cells are different for different memory models, shown in Tables \ref{Tab:Char1} and \ref{Tab:Char_ht}. These sources of variations come from architectural as well as both inter- and intra-chip dissimilarities due to the random process variation, which is the key source of any memory chips' randomness. Furthermore, data collected from different FPGAs verify that the memory controllers do not influence the proposed framework.

\begin{table}[ht!]
\caption{Error Statistics at High Temperature.}
\setcellgapes{1pt
\captionsetup{justification=centering, margin= 0cm}
\vspace{-0.3cm}
\makegapedcells
\centering
\setlength\tabcolsep{5pt} 
\resizebox{0.48\textwidth}{!}
{
   \begin{tabular}{|c|c|c|c|c|c|c|c|}
    \hline
    \multicolumn{2}{|c|}{Sample Chip} & (\%) & C1    & C2    & C3    & C4    & C5    \\ \hline
    \multirow{8}{*}{Solid} &
      \multirow{4}{*}{\texttt{FFFF}} &
      $\mathcal{M_A}$ &
      0.002 &
      0.09 &
      0 &
      0 &
      0 \\ \cline{3-8} 
          &                           & $\mathcal{M_B}$ & 0.002 & 0.02  & 0     & 0     & 0     \\ \cline{3-8} 
          &                           & $\mathcal{C_A}$ & 100   & 5.79  & ----  & ----  & ----  \\ \cline{3-8} 
          &                           & $\mathcal{C_B}$ & 100   & 16.77 & ----  & ----  & ----  \\ \cline{2-8} 
          & \multirow{4}{*}{\texttt{0000}}     & $\mathcal{M_A}$ & 16.00 & 13.53 & 7.55  & 2.73  & 0.94  \\ \cline{3-8} 
          &                           & $\mathcal{M_B}$ & 6.31  & 7.54  & 4.30  & 0.56  & 0.22  \\ \cline{3-8} 
          &                           & $\mathcal{C_A}$ & 39.70 & 77.63 & 10.72 & 11.77 & 21.8  \\ \cline{3-8} 
          &                           & $\mathcal{C_B}$ & 26.59 & 74.68 & 7.93  & 17.07 & 32.54 \\ \hline
    \multirow{8}{*}{\begin{tabular}[c]{@{}c@{}}Row\\ Striped\end{tabular}} &
      \multirow{4}{*}{\texttt{FFFF}} &
      $\mathcal{M_A}$ &
      12.83 &
      6.92 &
      4.63 &
      1.61 &
      0.33 \\ \cline{3-8} 
          &                           & $\mathcal{M_B}$ & 6.05  & 3.87  & 1.85  & 0.35  & 0.12  \\ \cline{3-8} 
          &                           & $\mathcal{C_A}$ & 47.39 & 81.38 & 13.84 & 15.64 & 38.17 \\ \cline{3-8} 
          &                           & $\mathcal{C_B}$ & 32.07 & 79.25 & 13.31 & 21.56 & 42.08 \\ \cline{2-8} 
          & \multirow{4}{*}{\texttt{0000}}     & $\mathcal{M_A}$ & 12.79 & 5.74  & 2.87  & 1.01  & 0.167 \\ \cline{3-8} 
          &                           & $\mathcal{M_B}$ & 5.61  & 3.07  & 1.33  & 0.21  & 0.07  \\ \cline{3-8} 
          &                           & $\mathcal{C_A}$ & 30.32 & 78.44 & 6.74  & 5.91  & 14.65 \\ \cline{3-8} 
          &                           & $\mathcal{C_B}$ & 18.65 & 73.35 & 3.11  & 9.61  & 22.77 \\ \hline
    \multirow{8}{*}{\begin{tabular}[c]{@{}c@{}}Column\\ Striped\end{tabular}} &
      \multirow{4}{*}{\texttt{FFFF}} &
      $\mathcal{M_A}$ &
      15.56 &
      9.93 &
      3.55 &
      1.02 &
      0.273 \\ \cline{3-8} 
          &                           & $\mathcal{M_B}$ & 8.98  & 5.41  & 1.04  & 0.24  & 0.12  \\ \cline{3-8} 
          &                           & $\mathcal{C_A}$ & 47.66 & 74.21 & 12.32 & 16.07 & 48.42 \\ \cline{3-8} 
          &                           & $\mathcal{C_B}$ & 27.41 & 68.75 & 15.01 & 23.16 & 53.61 \\ \cline{2-8} 
          & \multirow{4}{*}{\texttt{0000}}     & $\mathcal{M_A}$ & 3.15  & 2.13  & 2.55  & 0.83  & 0.23  \\ \cline{3-8} 
          &                           & $\mathcal{M_B}$ & 0.76  & 0.93  & 0.68  & 0.15  & 0.09  \\ \cline{3-8} 
          &                           & $\mathcal{C_A}$ & 28.25 & 95.81 & 9.32  & 14.93 & 36.38 \\ \cline{3-8} 
          &                           & $\mathcal{C_B}$ & 41.57 & 94.11 & 14.83 & 23.5  & 37.36 \\ \hline
    \multirow{8}{*}{\begin{tabular}[c]{@{}c@{}}Checker-\\ board\end{tabular}} &
      \multirow{4}{*}{\texttt{FFFF}} &
      $\mathcal{M_A}$ &
      9.40 &
      5.93 &
      3.34 &
      0.84 &
      0.23 \\ \cline{3-8} 
          &                           & $\mathcal{M_B}$ & 4.75  & 3.21  & 0.86  & 0.20  & 0.11  \\ \cline{3-8} 
          &                           & $\mathcal{C_A}$ & 50.53 & 80.52 & 12.11 & 17.01 & 48.17 \\ \cline{3-8} 
          &                           & $\mathcal{C_B}$ & 33.8  & 75.31 & 16.94 & 26.46 & 53.5  \\ \cline{2-8} 
          & \multirow{4}{*}{\texttt{0000}}     & $\mathcal{M_A}$ & 9.10  & 5.96  & 3.37  & 0.89  & 0.25  \\ \cline{3-8} 
          &                           & $\mathcal{M_B}$ & 4.37  & 3.06  & 0.93  & 0.19  & 0.11  \\ \cline{3-8} 
          &                           & $\mathcal{C_A}$ & 40.51 & 78.21 & 8.82  & 14.67 & 41.71 \\ \cline{3-8} 
          &                           & $\mathcal{C_B}$ & 24.48 & 71.84 & 12.77 & 22.76 & 41.62 \\ \hline
    \multirow{4}{*}{\begin{tabular}[c]{@{}c@{}}Any\\ Pattern\end{tabular}} &
      \multirow{4}{*}{\begin{tabular}[c]{@{}c@{}}\texttt{5555}/\\ \texttt{AAAA}\end{tabular}} &
      $\mathcal{M_A}$ &
      0 &
      0 &
      0 &
      0 &
      0 \\ \cline{3-8} 
          &                           & $\mathcal{M_B}$ & 0     & 0     & 0     & 0     & 0     \\ \cline{3-8} 
          &                           & $\mathcal{C_A}$ & ----  & ----  & ----  & ----  & ----  \\ \cline{3-8} 
          &                           & $\mathcal{C_B}$ & ----  & ----  & ----  & ----  & ----  \\ \hline
    \multicolumn{2}{|c|}{\multirow{4}{*}{Random}} &
      $\mathcal{M_A}$ &
      0.13 &
      0.23 &
      0.01 &
      0.005 &
      0.008 \\ \cline{3-8} 
    \multicolumn{2}{|c|}{}            & $\mathcal{M_B}$ & 0.04  & 0.09  & 0.01  & 0.002 & 0.002 \\ \cline{3-8} 
    \multicolumn{2}{|c|}{}            & $\mathcal{C_A}$ & 59.09 & 72.97 & 31.43 & 38.46 & 38.1  \\ \cline{3-8} 
    \multicolumn{2}{|c|}{}            & $\mathcal{C_B}$ & 33.16 & 63.81 & 36.3  & 40.48 & 41.58 \\ \hline
    \multicolumn{8}{l}{$^{\mathrm{*}}$NB. —- not performed as no error occurred at reduced $t_W$ for} \\
    \multicolumn{8}{l}{ corresponding data patterns.}
    \end{tabular}
}
\label{Tab:Char_ht}
\vspace{-0.3cm}
\end{table}


\vspace{-0.3cm}
\subsection{Data Pattern Dependency}

The characterization analysis was also performed with intuitive, such as solid and non-intuitive data patterns such as checkerboard, striped, and random to consider the effect of data pattern dependency. Taking the union of the errors resulting from each data pattern can further improve the fault coverage during the worst case. However, only a marginal improvement is observed for the chips used for experiments using different data patterns over the \textit{solid} \texttt{0x0000} data pattern. Besides, Table \ref{Tab:Char1} shows that a vast portion of the erroneous addresses generated from different data patterns belongs to those erroneous addresses obtained through the address selection strategy from error characterization using \textit{solid} \texttt{0x0000} data pattern described in strategy 1 of Algo. \ref{alg:mramChar}. Furthermore, it is essential to note that the acquired erroneous addresses heavily depend on the training data and frequency characteristics. Hence, it becomes imperative to select the training data and frequency judiciously.

\vspace{-0.3cm}
\subsection{Summary of Results}

Overall, we draw the following main conclusions from the results.
\vspace{-0.2cm}
\begin{enumerate}
    \item {The reduction of the MRAM chip's \textit{write~pulse~width} ($t_W$) can be used to achieve maximum write current savings of $\sim$$66\%$ (hence, power-saving of $\sim$$88\%$) with virtually no loss in output quality for error-resilient applications.}
    \item {The cell characterization is performed once in a lifetime before deploying the MRAM in the computing system. However, the judicial selection is required for the training data and frequency to perform characterization.}
    \item {The output quality degradation occurs when approximate application data are placed at addresses containing both erroneous and error-free (without address selection) due to the bit errors present in erroneous addresses in the case when the entire memory initialized with all 1's before writing. However, with the proposed address selection strategy, we can achieve almost $100\%$ of output quality.}
    \item {Contrarily, the same applications retain almost $100\%$ of quality even when put into addresses containing both erroneous and error-free in the case when the entire memory initialized with all 0's before writing.}
    \item {Commercial-grade MRAM is more vulnerable to reduced $t_W$ than industrial-grade MRAM due to internal MRAM architecture.}
    \item {Errors that occurred at lower temperatures are a subset of the errors at high temperatures.}
\end{enumerate}
\vspace{-0.2cm}


\vspace{-0.3cm}
\section{Discussions} \label{sec:discuss}

\subsection{Storage and Performance Overheads}

Our proposed framework requires allocating application data (critical and then approximate) to first error-free addresses and move forward to erroneous addresses based on the required application accuracy. We used a similar approach proposed in \cite{AC_dram}; however, our approach is simpler as the access policy of DRAM and MRAM is entirely different, and we do not require quality-wise erroneous address sorting. Note that the following strategy needs to be performed only for high-accuracy applications when no more accurate addresses are available. For this purpose, a custom memory allocator is required to track the erroneous addresses obtained from the characterization step. Next, based on the application requirements, it will allocate the user annotated critical and approximate data into virtual addresses using a critical bit for each address. Operating systems (OS) usually accomplish the mapping of virtual to physical addresses through a page table. Hence, in our proposed scenario, the OS has to perform this additional responsibility of assigning virtual to physical addresses belonging to error-free (accurate) and erroneous addresses depending on the application requirement.

The OS and the memory management unit (MMU) require additional logic to implement the proposed addresses selection strategy.
\begin{figure*}[ht!]
    \centering
    \captionsetup{justification=centering, margin= 0.5cm}
    \begin{subfigure}[t]{0.4\textwidth}
        \centering
        \includegraphics[trim=0cm 5cm 16cm 0cm, clip, width=0.99\textwidth]{Figures/mr3ch1_ht.pdf}
        \caption{}
        \label{fig:mr3ch1_ht}
    \end{subfigure}%
    \begin{subfigure}[t]{0.4\textwidth}
        \centering
        \includegraphics[trim=0cm 5cm 16cm 0cm, clip, width = 0.99\textwidth]{Figures/mr4ch2_ht.pdf}
        \caption{}
        \label{fig:mr4ch2_ht}
    \end{subfigure}
    \vspace{-0.3cm}
    \caption[]{(a) Commercial (b) industrial-grade MRAM. \nth{1} column of (a) and (b) represents the original image (90 × 90) which is written to the MRAM; \nth{2} \& \nth{3} columns represent: the entire memory is initialized with all 1's before writing the image at reduced $t_W$ then reading back the memory contents without and with address selection respectively at $45^{\circ}C$\footnotemark}
    \label{fig:img_proc_ht}
\vspace{-0.3cm}
\end{figure*}
\footnotetext{While working on the image experiment, we do not have access to the mentioned ThermoStream; hence unable to reach $65^{\circ}C$ (used for characterization). In the revised version, we are planning to show image results at $65^{\circ}C$.}
Towards this end, first, the OS can track the erroneous addresses using a custom data structure (consisting of critical bits).
Then, at the start-up phase, the OS can utilize the custom data structure to modify the core map and subsequently utilize this modified mapping function to translate virtual to a physical address. 
Note that the modified mapping is used in conjunction with the original core map. 
Before performing virtual to physical address mapping, first, the OS will check whether the virtual address is critical or not for the required application. If it is critical, the OS will check for the error-free address based on the application requirement as specified by the system designer. In addition to that, one can use additional flag bits on the cache memory (similar to the \textit{valid} bit) to identify if a data block is erroneous or accurate. This flag bit can be directly copied from the custom data structure in parallel to the main memory operations. The OS can utilize this flag bit during the memory allocation for further optimization.
For the proposed framework, it is expected that the OS will completely automate the entire allocation process.
Hence, hardware and OS support are essential for adapting approximate MRAM to reality in sophisticated high-end embedded computing systems. Note that, for a 1GByte main memory (with 32Byte block size), the size of the custom data structure would be 4MByte.
It is worth mentioning that the latency and energy overheads for the MRAM characterization are negligible as the characterization needs to be performed only once before deploying the MRAM in the computing system.

\vspace{-0.3cm} 
\subsection{Critical Data Protection: MRAM as a Cache}

A significant challenge of approximate storage usage is: most of the highly amenable approximate computing paradigm applications also have a mixture of control data (i.e., critical data) that is intolerable to any errors. Hence imposing approximation on these data makes them unreliable. For example, the instruction cache requires to be entirely error-free. Various solutions are proposed to protect the critical data part \cite{AC_Tahoori}. The critical data size is minimal comparing with the non-critical counterpart. Hence, designing a heterogeneous data cache memory array with different static (design-time) and dynamic (runtime) configurations to make critical data error-resilient guarantees error-free operation. However, this requires (i) fabrication parameters modification (ii) complex cache controller for proper data allocation in different arrays. Contrarily, a more straightforward solution for critical data protection is either using multiple copies of this data content or an error correction code (ECC), where data protection is performed through additional check bit(s). However, the overhead due to the additional bit-cells for the mentioned approaches is minimal for these significantly smaller critical data sizes \cite{AC_Tahoori}. Besides, considerably lower write accesses to the instruction cache help the critical data protection considerably more manageable for our proposed framework.












\vspace{-0.1cm}
\section{Conclusion} \label{sec:end}

This paper proposes an efficient approximate computing framework to evaluate the applicability of non-volatile COTS MRAM, a promising candidate for future computing platforms, through memory address's error characterization by utilizing the internal write latency variation of MRAM to improve the power efficiency. Our methodology provides an optimal system-level implementation yielding a favorable performance and power vs. quality trade-off for error-resilient applications by devising efficient segregation strategies for the erroneous addresses allocating approximate and critical data during page mapping systematically. Our experimental results reveal that MRAM-based memory system can achieve substantial power and performance benefits for negligible or no loss in application output quality. Furthermore, other emerging memory technologies can also adopt the proposed address selection strategy, a promising framework aspect.












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