static void conditional_interrupt(DBDMA_channel *ch)

{

    dbdma_cmd *current = &ch->current;

    uint16_t intr;

    uint16_t sel_mask, sel_value;

    uint32_t status;

    int cond;



    DBDMA_DPRINTF("conditional_interrupt\n");



    intr = le16_to_cpu(current->command) & INTR_MASK;



    switch(intr) {

    case INTR_NEVER:  /* don't interrupt */

        return;

    case INTR_ALWAYS: /* always interrupt */

        qemu_irq_raise(ch->irq);

        return;

    }



    status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;



    sel_mask = (be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) >> 16) & 0x0f;

    sel_value = be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) & 0x0f;



    cond = (status & sel_mask) == (sel_value & sel_mask);



    switch(intr) {

    case INTR_IFSET:  /* intr if condition bit is 1 */

        if (cond)

            qemu_irq_raise(ch->irq);

        return;

    case INTR_IFCLR:  /* intr if condition bit is 0 */

        if (!cond)

            qemu_irq_raise(ch->irq);

        return;

    }

}

static void conditional_interrupt(DBDMA_channel *ch)

{

    dbdma_cmd *current = &ch->current;

    uint16_t intr;

    uint16_t sel_mask, sel_value;

    uint32_t status;

    int cond;



    DBDMA_DPRINTF("conditional_interrupt\n");



    intr = le16_to_cpu(current->command) & INTR_MASK;



    switch(intr) {

    case INTR_NEVER:  

        return;

    case INTR_ALWAYS: 

        qemu_irq_raise(ch->irq);

        return;

    }



    status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;



    sel_mask = (be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) >> 16) & 0x0f;

    sel_value = be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) & 0x0f;



    cond = (status & sel_mask) == (sel_value & sel_mask);



    switch(intr) {

    case INTR_IFSET:  

        if (cond)

            qemu_irq_raise(ch->irq);

        return;

    case INTR_IFCLR:  

        if (!cond)

            qemu_irq_raise(ch->irq);

        return;

    }

}

static void FUNC_0(DBDMA_channel *VAR_0)

{

    dbdma_cmd *current = &VAR_0->current;

    uint16_t intr;

    uint16_t sel_mask, sel_value;

    uint32_t status;

    int VAR_1;



    DBDMA_DPRINTF("FUNC_0\n");



    intr = le16_to_cpu(current->command) & INTR_MASK;



    switch(intr) {

    case INTR_NEVER:  

        return;

    case INTR_ALWAYS: 

        qemu_irq_raise(VAR_0->irq);

        return;

    }



    status = be32_to_cpu(VAR_0->regs[DBDMA_STATUS]) & DEVSTAT;



    sel_mask = (be32_to_cpu(VAR_0->regs[DBDMA_INTR_SEL]) >> 16) & 0x0f;

    sel_value = be32_to_cpu(VAR_0->regs[DBDMA_INTR_SEL]) & 0x0f;



    VAR_1 = (status & sel_mask) == (sel_value & sel_mask);



    switch(intr) {

    case INTR_IFSET:  

        if (VAR_1)

            qemu_irq_raise(VAR_0->irq);

        return;

    case INTR_IFCLR:  

        if (!VAR_1)

            qemu_irq_raise(VAR_0->irq);

        return;

    }

}

static void FUNC_0(DBDMA_channel *VAR_0)
{ dbdma_cmd *current = &VAR_0->current; uint16_t intr; uint16_t sel_mask, sel_value; uint32_t status; int VAR_1; DBDMA_DPRINTF("FUNC_0\n"); intr = le16_to_cpu(current->command) & INTR_MASK; switch(intr) { case INTR_NEVER:
return; case INTR_ALWAYS:
qemu_irq_raise(VAR_0->irq); return; } status = be32_to_cpu(VAR_0->regs[DBDMA_STATUS]) & DEVSTAT; sel_mask = (be32_to_cpu(VAR_0->regs[DBDMA_INTR_SEL]) >> 16) & 0x0f; sel_value = be32_to_cpu(VAR_0->regs[DBDMA_INTR_SEL]) & 0x0f; VAR_1 = (status & sel_mask) == (sel_value & sel_mask); switch(intr) { case INTR_IFSET:
if (VAR_1)
qemu_irq_raise(VAR_0->irq); return; case INTR_IFCLR:
if (!VAR_1)
qemu_irq_raise(VAR_0->irq); return; } }