static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,

                                  int destidx, int element, TCGMemOp memop)

{

    int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE);

    switch (memop) {

    case MO_8:

        tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);

        break;

    case MO_16:

        tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);

        break;

    case MO_32:

        tcg_gen_st_i32(tcg_src, cpu_env, vect_off);

        break;

    default:

        g_assert_not_reached();

    }

}

static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,

                                  int destidx, int element, TCGMemOp memop)

{

    int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE);

    switch (memop) {

    case MO_8:

        tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);

        break;

    case MO_16:

        tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);

        break;

    case MO_32:

        tcg_gen_st_i32(tcg_src, cpu_env, vect_off);

        break;

    default:

        g_assert_not_reached();

    }

}

static void FUNC_0(DisasContext *VAR_0, TCGv_i32 VAR_1,

                                  int VAR_2, int VAR_3, TCGMemOp VAR_4)

{

    int VAR_5 = vec_reg_offset(VAR_2, VAR_3, VAR_4 & MO_SIZE);

    switch (VAR_4) {

    case MO_8:

        tcg_gen_st8_i32(VAR_1, cpu_env, VAR_5);

        break;

    case MO_16:

        tcg_gen_st16_i32(VAR_1, cpu_env, VAR_5);

        break;

    case MO_32:

        tcg_gen_st_i32(VAR_1, cpu_env, VAR_5);

        break;

    default:

        g_assert_not_reached();

    }

}

static void FUNC_0(DisasContext *VAR_0, TCGv_i32 VAR_1,
int VAR_2, int VAR_3, TCGMemOp VAR_4)
{ int VAR_5 = vec_reg_offset(VAR_2, VAR_3, VAR_4 & MO_SIZE); switch (VAR_4) { case MO_8:
tcg_gen_st8_i32(VAR_1, cpu_env, VAR_5); break; case MO_16:
tcg_gen_st16_i32(VAR_1, cpu_env, VAR_5); break; case MO_32:
tcg_gen_st_i32(VAR_1, cpu_env, VAR_5); break; default:
g_assert_not_reached(); } }