static int xen_pt_cmd_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,

                                uint16_t *val, uint16_t dev_value,

                                uint16_t valid_mask)

{

    XenPTRegInfo *reg = cfg_entry->reg;

    uint16_t writable_mask = 0;

    uint16_t throughable_mask = 0;

    uint16_t emu_mask = reg->emu_mask;



    if (s->is_virtfn) {

        emu_mask |= PCI_COMMAND_MEMORY;

    }



    /* modify emulate register */

    writable_mask = ~reg->ro_mask & valid_mask;

    cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);



    /* create value for writing to I/O device register */

    throughable_mask = ~emu_mask & valid_mask;



    if (*val & PCI_COMMAND_INTX_DISABLE) {

        throughable_mask |= PCI_COMMAND_INTX_DISABLE;

    } else {

        if (s->machine_irq) {

            throughable_mask |= PCI_COMMAND_INTX_DISABLE;

        }

    }



    *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);



    return 0;

}

static int xen_pt_cmd_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,

                                uint16_t *val, uint16_t dev_value,

                                uint16_t valid_mask)

{

    XenPTRegInfo *reg = cfg_entry->reg;

    uint16_t writable_mask = 0;

    uint16_t throughable_mask = 0;

    uint16_t emu_mask = reg->emu_mask;



    if (s->is_virtfn) {

        emu_mask |= PCI_COMMAND_MEMORY;

    }



    

    writable_mask = ~reg->ro_mask & valid_mask;

    cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);



    

    throughable_mask = ~emu_mask & valid_mask;



    if (*val & PCI_COMMAND_INTX_DISABLE) {

        throughable_mask |= PCI_COMMAND_INTX_DISABLE;

    } else {

        if (s->machine_irq) {

            throughable_mask |= PCI_COMMAND_INTX_DISABLE;

        }

    }



    *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);



    return 0;

}

    XenPTRegInfo *reg = cfg_entry->reg;     uint16_t emu_mask = reg->emu_mask;     if (s->is_virtfn) {         emu_mask |= PCI_COMMAND_MEMORY;     return 0;     uint16_t emu_mask = reg->emu_mask;     if (s->is_virtfn) {         emu_mask |= PCI_COMMAND_MEMORY;     throughable_mask = ~emu_mask & valid_mask;
static int FUNC_0(XenPCIPassthroughState *VAR_0, XenPTReg *VAR_1,

                                uint16_t *VAR_2, uint16_t VAR_3,

                                uint16_t VAR_4)

{

    XenPTRegInfo *reg = VAR_1->reg;

    uint16_t writable_mask = 0;

    uint16_t throughable_mask = 0;

    uint16_t emu_mask = reg->emu_mask;



    if (VAR_0->is_virtfn) {

        emu_mask |= PCI_COMMAND_MEMORY;

    }



    

    writable_mask = ~reg->ro_mask & VAR_4;

    VAR_1->data = XEN_PT_MERGE_VALUE(*VAR_2, VAR_1->data, writable_mask);



    

    throughable_mask = ~emu_mask & VAR_4;



    if (*VAR_2 & PCI_COMMAND_INTX_DISABLE) {

        throughable_mask |= PCI_COMMAND_INTX_DISABLE;

    } else {

        if (VAR_0->machine_irq) {

            throughable_mask |= PCI_COMMAND_INTX_DISABLE;

        }

    }



    *VAR_2 = XEN_PT_MERGE_VALUE(*VAR_2, VAR_3, throughable_mask);



    return 0;

}

static int FUNC_0(XenPCIPassthroughState *VAR_0, XenPTReg *VAR_1,
uint16_t *VAR_2, uint16_t VAR_3,
uint16_t VAR_4)
{ XenPTRegInfo *reg = VAR_1->reg; uint16_t writable_mask = 0; uint16_t throughable_mask = 0; uint16_t emu_mask = reg->emu_mask; if (VAR_0->is_virtfn) { emu_mask |= PCI_COMMAND_MEMORY; } writable_mask = ~reg->ro_mask & VAR_4; VAR_1->data = XEN_PT_MERGE_VALUE(*VAR_2, VAR_1->data, writable_mask); throughable_mask = ~emu_mask & VAR_4; if (*VAR_2 & PCI_COMMAND_INTX_DISABLE) { throughable_mask |= PCI_COMMAND_INTX_DISABLE; } else { if (VAR_0->machine_irq) { throughable_mask |= PCI_COMMAND_INTX_DISABLE; } } *VAR_2 = XEN_PT_MERGE_VALUE(*VAR_2, VAR_3, throughable_mask); return 0; }