static void zynq_xadc_write(void *opaque, hwaddr offset, uint64_t val,

                            unsigned size)

{

    ZynqXADCState *s = (ZynqXADCState *)opaque;

    int reg = offset / 4;

    int xadc_reg;

    int xadc_cmd;

    int xadc_data;



    if (!zynq_xadc_check_offset(reg, false)) {

        qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid write access "

                      "to addr %" HWADDR_PRIx "\n", offset);

        return;

    }



    switch (reg) {

    case CFG:

        s->regs[CFG] = val;

        break;

    case INT_STS:

        s->regs[INT_STS] &= ~val;

        break;

    case INT_MASK:

        s->regs[INT_MASK] = val & INT_ALL;

        break;

    case CMDFIFO:

        xadc_cmd  = extract32(val, 26,  4);

        xadc_reg  = extract32(val, 16, 10);

        xadc_data = extract32(val,  0, 16);



        if (s->regs[MCTL] & MCTL_RESET) {

            qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Sending command "

                          "while comm channel held in reset: %" PRIx32 "\n",

                          (uint32_t) val);

            break;

        }



        if (xadc_reg > ZYNQ_XADC_NUM_ADC_REGS && xadc_cmd != CMD_NOP) {

            qemu_log_mask(LOG_GUEST_ERROR, "read/write op to invalid xadc "

                          "reg 0x%x\n", xadc_reg);

            break;

        }



        switch (xadc_cmd) {

        case CMD_READ:

            xadc_push_dfifo(s, s->xadc_regs[xadc_reg]);

            break;

        case CMD_WRITE:

            s->xadc_regs[xadc_reg] = xadc_data;

            /* fallthrough */

        case CMD_NOP:

            xadc_push_dfifo(s, 0);

            break;

        }

        break;

    case MCTL:

        s->regs[MCTL] = val & 0x00fffeff;

        break;

    }

    zynq_xadc_update_ints(s);

}

static void zynq_xadc_write(void *opaque, hwaddr offset, uint64_t val,

                            unsigned size)

{

    ZynqXADCState *s = (ZynqXADCState *)opaque;

    int reg = offset / 4;

    int xadc_reg;

    int xadc_cmd;

    int xadc_data;



    if (!zynq_xadc_check_offset(reg, false)) {

        qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid write access "

                      "to addr %" HWADDR_PRIx "\n", offset);

        return;

    }



    switch (reg) {

    case CFG:

        s->regs[CFG] = val;

        break;

    case INT_STS:

        s->regs[INT_STS] &= ~val;

        break;

    case INT_MASK:

        s->regs[INT_MASK] = val & INT_ALL;

        break;

    case CMDFIFO:

        xadc_cmd  = extract32(val, 26,  4);

        xadc_reg  = extract32(val, 16, 10);

        xadc_data = extract32(val,  0, 16);



        if (s->regs[MCTL] & MCTL_RESET) {

            qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Sending command "

                          "while comm channel held in reset: %" PRIx32 "\n",

                          (uint32_t) val);

            break;

        }



        if (xadc_reg > ZYNQ_XADC_NUM_ADC_REGS && xadc_cmd != CMD_NOP) {

            qemu_log_mask(LOG_GUEST_ERROR, "read/write op to invalid xadc "

                          "reg 0x%x\n", xadc_reg);

            break;

        }



        switch (xadc_cmd) {

        case CMD_READ:

            xadc_push_dfifo(s, s->xadc_regs[xadc_reg]);

            break;

        case CMD_WRITE:

            s->xadc_regs[xadc_reg] = xadc_data;

            

        case CMD_NOP:

            xadc_push_dfifo(s, 0);

            break;

        }

        break;

    case MCTL:

        s->regs[MCTL] = val & 0x00fffeff;

        break;

    }

    zynq_xadc_update_ints(s);

}

        if (xadc_reg > ZYNQ_XADC_NUM_ADC_REGS && xadc_cmd != CMD_NOP) {
static void FUNC_0(void *VAR_0, hwaddr VAR_1, uint64_t VAR_2,

                            unsigned VAR_3)

{

    ZynqXADCState *s = (ZynqXADCState *)VAR_0;

    int VAR_4 = VAR_1 / 4;

    int VAR_5;

    int VAR_6;

    int VAR_7;



    if (!zynq_xadc_check_offset(VAR_4, false)) {

        qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid write access "

                      "to addr %" HWADDR_PRIx "\n", VAR_1);

        return;

    }



    switch (VAR_4) {

    case CFG:

        s->regs[CFG] = VAR_2;

        break;

    case INT_STS:

        s->regs[INT_STS] &= ~VAR_2;

        break;

    case INT_MASK:

        s->regs[INT_MASK] = VAR_2 & INT_ALL;

        break;

    case CMDFIFO:

        VAR_6  = extract32(VAR_2, 26,  4);

        VAR_5  = extract32(VAR_2, 16, 10);

        VAR_7 = extract32(VAR_2,  0, 16);



        if (s->regs[MCTL] & MCTL_RESET) {

            qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Sending command "

                          "while comm channel held in reset: %" PRIx32 "\n",

                          (uint32_t) VAR_2);

            break;

        }



        if (VAR_5 > ZYNQ_XADC_NUM_ADC_REGS && VAR_6 != CMD_NOP) {

            qemu_log_mask(LOG_GUEST_ERROR, "read/write op to invalid xadc "

                          "VAR_4 0x%x\n", VAR_5);

            break;

        }



        switch (VAR_6) {

        case CMD_READ:

            xadc_push_dfifo(s, s->xadc_regs[VAR_5]);

            break;

        case CMD_WRITE:

            s->xadc_regs[VAR_5] = VAR_7;

            

        case CMD_NOP:

            xadc_push_dfifo(s, 0);

            break;

        }

        break;

    case MCTL:

        s->regs[MCTL] = VAR_2 & 0x00fffeff;

        break;

    }

    zynq_xadc_update_ints(s);

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1, uint64_t VAR_2,
unsigned VAR_3)
{ ZynqXADCState *s = (ZynqXADCState *)VAR_0; int VAR_4 = VAR_1 / 4; int VAR_5; int VAR_6; int VAR_7; if (!zynq_xadc_check_offset(VAR_4, false)) { qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid write access "
"to addr %" HWADDR_PRIx "\n", VAR_1); return; } switch (VAR_4) { case CFG:
s->regs[CFG] = VAR_2; break; case INT_STS:
s->regs[INT_STS] &= ~VAR_2; break; case INT_MASK:
s->regs[INT_MASK] = VAR_2 & INT_ALL; break; case CMDFIFO:
VAR_6  = extract32(VAR_2, 26,  4); VAR_5  = extract32(VAR_2, 16, 10); VAR_7 = extract32(VAR_2,  0, 16); if (s->regs[MCTL] & MCTL_RESET) { qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Sending command "
"while comm channel held in reset: %" PRIx32 "\n",
(uint32_t) VAR_2); break; } if (VAR_5 > ZYNQ_XADC_NUM_ADC_REGS && VAR_6 != CMD_NOP) { qemu_log_mask(LOG_GUEST_ERROR, "read/write op to invalid xadc "
"VAR_4 0x%x\n", VAR_5); break; } switch (VAR_6) { case CMD_READ:
xadc_push_dfifo(s, s->xadc_regs[VAR_5]); break; case CMD_WRITE:
s->xadc_regs[VAR_5] = VAR_7; case CMD_NOP:
xadc_push_dfifo(s, 0); break; } break; case MCTL:
s->regs[MCTL] = VAR_2 & 0x00fffeff; break; } zynq_xadc_update_ints(s); }