int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,

                  target_ulong *raddr, int *flags, bool exc)

{

    int r = -1;

    uint8_t *sk;



    *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;

    vaddr &= TARGET_PAGE_MASK;



    if (!(env->psw.mask & PSW_MASK_DAT)) {

        *raddr = vaddr;

        r = 0;

        goto out;

    }



    switch (asc) {

    case PSW_ASC_PRIMARY:

        PTE_DPRINTF("%s: asc=primary\n", __func__);

        r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags,

                               rw, exc);

        break;

    case PSW_ASC_HOME:

        PTE_DPRINTF("%s: asc=home\n", __func__);

        r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags,

                               rw, exc);

        break;

    case PSW_ASC_SECONDARY:

        PTE_DPRINTF("%s: asc=secondary\n", __func__);

        /*

         * Instruction: Primary

         * Data: Secondary

         */

        if (rw == MMU_INST_FETCH) {

            r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],

                                   raddr, flags, rw, exc);

            *flags &= ~(PAGE_READ | PAGE_WRITE);

        } else {

            r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs[7],

                                   raddr, flags, rw, exc);

            *flags &= ~(PAGE_EXEC);

        }

        break;

    case PSW_ASC_ACCREG:

    default:

        hw_error("guest switched to unknown asc mode\n");

        break;

    }



 out:

    /* Convert real address -> absolute address */

    *raddr = mmu_real2abs(env, *raddr);



    if (*raddr <= ram_size) {

        sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];

        if (*flags & PAGE_READ) {

            *sk |= SK_R;

        }



        if (*flags & PAGE_WRITE) {

            *sk |= SK_C;

        }

    }



    return r;

}

int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,

                  target_ulong *raddr, int *flags, bool exc)

{

    int r = -1;

    uint8_t *sk;



    *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;

    vaddr &= TARGET_PAGE_MASK;



    if (!(env->psw.mask & PSW_MASK_DAT)) {

        *raddr = vaddr;

        r = 0;

        goto out;

    }



    switch (asc) {

    case PSW_ASC_PRIMARY:

        PTE_DPRINTF("%s: asc=primary\n", __func__);

        r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags,

                               rw, exc);

        break;

    case PSW_ASC_HOME:

        PTE_DPRINTF("%s: asc=home\n", __func__);

        r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags,

                               rw, exc);

        break;

    case PSW_ASC_SECONDARY:

        PTE_DPRINTF("%s: asc=secondary\n", __func__);

        







        if (rw == MMU_INST_FETCH) {

            r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],

                                   raddr, flags, rw, exc);

            *flags &= ~(PAGE_READ | PAGE_WRITE);

        } else {

            r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs[7],

                                   raddr, flags, rw, exc);

            *flags &= ~(PAGE_EXEC);

        }

        break;

    case PSW_ASC_ACCREG:

    default:

        hw_error("guest switched to unknown asc mode\n");

        break;

    }



 out:

    

    *raddr = mmu_real2abs(env, *raddr);



    if (*raddr <= ram_size) {

        sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];

        if (*flags & PAGE_READ) {

            *sk |= SK_R;

        }



        if (*flags & PAGE_WRITE) {

            *sk |= SK_C;

        }

    }



    return r;

}

    if (*raddr <= ram_size) {
int FUNC_0(CPUS390XState *VAR_0, target_ulong VAR_1, int VAR_2, uint64_t VAR_3,

                  target_ulong *VAR_4, int *VAR_5, bool VAR_6)

{

    int VAR_7 = -1;

    uint8_t *sk;



    *VAR_5 = PAGE_READ | PAGE_WRITE | PAGE_EXEC;

    VAR_1 &= TARGET_PAGE_MASK;



    if (!(VAR_0->psw.mask & PSW_MASK_DAT)) {

        *VAR_4 = VAR_1;

        VAR_7 = 0;

        goto out;

    }



    switch (VAR_3) {

    case PSW_ASC_PRIMARY:

        PTE_DPRINTF("%s: VAR_3=primary\n", __func__);

        VAR_7 = mmu_translate_asce(VAR_0, VAR_1, VAR_3, VAR_0->cregs[1], VAR_4, VAR_5,

                               VAR_2, VAR_6);

        break;

    case PSW_ASC_HOME:

        PTE_DPRINTF("%s: VAR_3=home\n", __func__);

        VAR_7 = mmu_translate_asce(VAR_0, VAR_1, VAR_3, VAR_0->cregs[13], VAR_4, VAR_5,

                               VAR_2, VAR_6);

        break;

    case PSW_ASC_SECONDARY:

        PTE_DPRINTF("%s: VAR_3=secondary\n", __func__);

        







        if (VAR_2 == MMU_INST_FETCH) {

            VAR_7 = mmu_translate_asce(VAR_0, VAR_1, PSW_ASC_PRIMARY, VAR_0->cregs[1],

                                   VAR_4, VAR_5, VAR_2, VAR_6);

            *VAR_5 &= ~(PAGE_READ | PAGE_WRITE);

        } else {

            VAR_7 = mmu_translate_asce(VAR_0, VAR_1, PSW_ASC_SECONDARY, VAR_0->cregs[7],

                                   VAR_4, VAR_5, VAR_2, VAR_6);

            *VAR_5 &= ~(PAGE_EXEC);

        }

        break;

    case PSW_ASC_ACCREG:

    default:

        hw_error("guest switched to unknown VAR_3 mode\n");

        break;

    }



 out:

    

    *VAR_4 = mmu_real2abs(VAR_0, *VAR_4);



    if (*VAR_4 <= ram_size) {

        sk = &VAR_0->storage_keys[*VAR_4 / TARGET_PAGE_SIZE];

        if (*VAR_5 & PAGE_READ) {

            *sk |= SK_R;

        }



        if (*VAR_5 & PAGE_WRITE) {

            *sk |= SK_C;

        }

    }



    return VAR_7;

}

int FUNC_0(CPUS390XState *VAR_0, target_ulong VAR_1, int VAR_2, uint64_t VAR_3,
target_ulong *VAR_4, int *VAR_5, bool VAR_6)
{ int VAR_7 = -1; uint8_t *sk; *VAR_5 = PAGE_READ | PAGE_WRITE | PAGE_EXEC; VAR_1 &= TARGET_PAGE_MASK; if (!(VAR_0->psw.mask & PSW_MASK_DAT)) { *VAR_4 = VAR_1; VAR_7 = 0; goto out; } switch (VAR_3) { case PSW_ASC_PRIMARY:
PTE_DPRINTF("%s: VAR_3=primary\n", __func__); VAR_7 = mmu_translate_asce(VAR_0, VAR_1, VAR_3, VAR_0->cregs[1], VAR_4, VAR_5,
VAR_2, VAR_6); break; case PSW_ASC_HOME:
PTE_DPRINTF("%s: VAR_3=home\n", __func__); VAR_7 = mmu_translate_asce(VAR_0, VAR_1, VAR_3, VAR_0->cregs[13], VAR_4, VAR_5,
VAR_2, VAR_6); break; case PSW_ASC_SECONDARY:
PTE_DPRINTF("%s: VAR_3=secondary\n", __func__); if (VAR_2 == MMU_INST_FETCH) { VAR_7 = mmu_translate_asce(VAR_0, VAR_1, PSW_ASC_PRIMARY, VAR_0->cregs[1],
VAR_4, VAR_5, VAR_2, VAR_6); *VAR_5 &= ~(PAGE_READ | PAGE_WRITE); } else { VAR_7 = mmu_translate_asce(VAR_0, VAR_1, PSW_ASC_SECONDARY, VAR_0->cregs[7],
VAR_4, VAR_5, VAR_2, VAR_6); *VAR_5 &= ~(PAGE_EXEC); } break; case PSW_ASC_ACCREG:
default:
hw_error("guest switched to unknown VAR_3 mode\n"); break; } out:
*VAR_4 = mmu_real2abs(VAR_0, *VAR_4); if (*VAR_4 <= ram_size) { sk = &VAR_0->storage_keys[*VAR_4 / TARGET_PAGE_SIZE]; if (*VAR_5 & PAGE_READ) { *sk |= SK_R; } if (*VAR_5 & PAGE_WRITE) { *sk |= SK_C; } } return VAR_7; }