static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)

{

    TCGv tmp;

    int cpn = (insn >> 16) & 0xf;

    int cpm = insn & 0xf;

    int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);



    if (!arm_feature(env, ARM_FEATURE_V6K))

        return 0;



    if (!(cpn == 13 && cpm == 0))

        return 0;



    if (insn & ARM_CP_RW_BIT) {

        switch (op) {

        case 2:

            tmp = load_cpu_field(cp15.c13_tls1);

            break;

        case 3:

            tmp = load_cpu_field(cp15.c13_tls2);

            break;

        case 4:

            tmp = load_cpu_field(cp15.c13_tls3);

            break;

        default:

            return 0;

        }

        store_reg(s, rd, tmp);



    } else {

        tmp = load_reg(s, rd);

        switch (op) {

        case 2:

            store_cpu_field(tmp, cp15.c13_tls1);

            break;

        case 3:

            store_cpu_field(tmp, cp15.c13_tls2);

            break;

        case 4:

            store_cpu_field(tmp, cp15.c13_tls3);

            break;

        default:

            dead_tmp(tmp);

            return 0;

        }

    }

    return 1;

}

static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)

{

    TCGv tmp;

    int cpn = (insn >> 16) & 0xf;

    int cpm = insn & 0xf;

    int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);



    if (!arm_feature(env, ARM_FEATURE_V6K))

        return 0;



    if (!(cpn == 13 && cpm == 0))

        return 0;



    if (insn & ARM_CP_RW_BIT) {

        switch (op) {

        case 2:

            tmp = load_cpu_field(cp15.c13_tls1);

            break;

        case 3:

            tmp = load_cpu_field(cp15.c13_tls2);

            break;

        case 4:

            tmp = load_cpu_field(cp15.c13_tls3);

            break;

        default:

            return 0;

        }

        store_reg(s, rd, tmp);



    } else {

        tmp = load_reg(s, rd);

        switch (op) {

        case 2:

            store_cpu_field(tmp, cp15.c13_tls1);

            break;

        case 3:

            store_cpu_field(tmp, cp15.c13_tls2);

            break;

        case 4:

            store_cpu_field(tmp, cp15.c13_tls3);

            break;

        default:

            dead_tmp(tmp);

            return 0;

        }

    }

    return 1;

}

            dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);             dead_tmp(tmp);
static int FUNC_0(CPUState *VAR_0, DisasContext *VAR_1, uint32_t VAR_2, uint32_t VAR_3)

{

    TCGv tmp;

    int VAR_4 = (VAR_2 >> 16) & 0xf;

    int VAR_5 = VAR_2 & 0xf;

    int VAR_6 = ((VAR_2 >> 5) & 7) | ((VAR_2 >> 18) & 0x38);



    if (!arm_feature(VAR_0, ARM_FEATURE_V6K))

        return 0;



    if (!(VAR_4 == 13 && VAR_5 == 0))

        return 0;



    if (VAR_2 & ARM_CP_RW_BIT) {

        switch (VAR_6) {

        case 2:

            tmp = load_cpu_field(cp15.c13_tls1);

            break;

        case 3:

            tmp = load_cpu_field(cp15.c13_tls2);

            break;

        case 4:

            tmp = load_cpu_field(cp15.c13_tls3);

            break;

        default:

            return 0;

        }

        store_reg(VAR_1, VAR_3, tmp);



    } else {

        tmp = load_reg(VAR_1, VAR_3);

        switch (VAR_6) {

        case 2:

            store_cpu_field(tmp, cp15.c13_tls1);

            break;

        case 3:

            store_cpu_field(tmp, cp15.c13_tls2);

            break;

        case 4:

            store_cpu_field(tmp, cp15.c13_tls3);

            break;

        default:

            dead_tmp(tmp);

            return 0;

        }

    }

    return 1;

}

static int FUNC_0(CPUState *VAR_0, DisasContext *VAR_1, uint32_t VAR_2, uint32_t VAR_3)
{ TCGv tmp; int VAR_4 = (VAR_2 >> 16) & 0xf; int VAR_5 = VAR_2 & 0xf; int VAR_6 = ((VAR_2 >> 5) & 7) | ((VAR_2 >> 18) & 0x38); if (!arm_feature(VAR_0, ARM_FEATURE_V6K))
return 0; if (!(VAR_4 == 13 && VAR_5 == 0))
return 0; if (VAR_2 & ARM_CP_RW_BIT) { switch (VAR_6) { case 2:
tmp = load_cpu_field(cp15.c13_tls1); break; case 3:
tmp = load_cpu_field(cp15.c13_tls2); break; case 4:
tmp = load_cpu_field(cp15.c13_tls3); break; default:
return 0; } store_reg(VAR_1, VAR_3, tmp); } else { tmp = load_reg(VAR_1, VAR_3); switch (VAR_6) { case 2:
store_cpu_field(tmp, cp15.c13_tls1); break; case 3:
store_cpu_field(tmp, cp15.c13_tls2); break; case 4:
store_cpu_field(tmp, cp15.c13_tls3); break; default:
dead_tmp(tmp); return 0; } } return 1; }