static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,

                       int rd, int rs, int rt)

{

    const char *opn = "arith";

    TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);

    TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);



    if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB

       && opc != OPC_DADD && opc != OPC_DSUB) {

        /* If no destination, treat it as a NOP.

           For add & sub, we must generate the overflow exception when needed. */

        MIPS_DEBUG("NOP");

        goto out;

    }

    gen_load_gpr(t0, rs);

    /* Specialcase the conventional move operation. */

    if (rt == 0 && (opc == OPC_ADDU || opc == OPC_DADDU

                    || opc == OPC_SUBU || opc == OPC_DSUBU)) {

        gen_store_gpr(t0, rd);

        goto out;

    }

    gen_load_gpr(t1, rt);

    switch (opc) {

    case OPC_ADD:

        {

            TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);

            TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);

            int l1 = gen_new_label();



            save_cpu_state(ctx, 1);

            tcg_gen_ext32s_tl(r_tmp1, t0);

            tcg_gen_ext32s_tl(r_tmp2, t1);

            tcg_gen_add_tl(t0, r_tmp1, r_tmp2);



            tcg_gen_xor_tl(r_tmp1, r_tmp1, t1);

            tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);

            tcg_gen_xor_tl(r_tmp2, t0, t1);

            tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);

            tcg_temp_free(r_tmp2);

            tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);

            tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);

            tcg_temp_free(r_tmp1);

            /* operands of same sign, result different sign */

            generate_exception(ctx, EXCP_OVERFLOW);

            gen_set_label(l1);



            tcg_gen_ext32s_tl(t0, t0);

        }

        opn = "add";

        break;

    case OPC_ADDU:

        tcg_gen_ext32s_tl(t0, t0);

        tcg_gen_ext32s_tl(t1, t1);

        tcg_gen_add_tl(t0, t0, t1);

        tcg_gen_ext32s_tl(t0, t0);

        opn = "addu";

        break;

    case OPC_SUB:

        {

            TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);

            TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);

            int l1 = gen_new_label();



            save_cpu_state(ctx, 1);

            tcg_gen_ext32s_tl(r_tmp1, t0);

            tcg_gen_ext32s_tl(r_tmp2, t1);

            tcg_gen_sub_tl(t0, r_tmp1, r_tmp2);



            tcg_gen_xor_tl(r_tmp2, r_tmp1, t1);

            tcg_gen_xor_tl(r_tmp1, r_tmp1, t0);

            tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);

            tcg_temp_free(r_tmp2);

            tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);

            tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);

            tcg_temp_free(r_tmp1);

            /* operands of different sign, first operand and result different sign */

            generate_exception(ctx, EXCP_OVERFLOW);

            gen_set_label(l1);



            tcg_gen_ext32s_tl(t0, t0);

        }

        opn = "sub";

        break;

    case OPC_SUBU:

        tcg_gen_ext32s_tl(t0, t0);

        tcg_gen_ext32s_tl(t1, t1);

        tcg_gen_sub_tl(t0, t0, t1);

        tcg_gen_ext32s_tl(t0, t0);

        opn = "subu";

        break;

#if defined(TARGET_MIPS64)

    case OPC_DADD:

        {

            TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);

            TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);

            int l1 = gen_new_label();



            save_cpu_state(ctx, 1);

            tcg_gen_mov_tl(r_tmp1, t0);

            tcg_gen_add_tl(t0, t0, t1);



            tcg_gen_xor_tl(r_tmp1, r_tmp1, t1);

            tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);

            tcg_gen_xor_tl(r_tmp2, t0, t1);

            tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);

            tcg_temp_free(r_tmp2);

            tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);

            tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);

            tcg_temp_free(r_tmp1);

            /* operands of same sign, result different sign */

            generate_exception(ctx, EXCP_OVERFLOW);

            gen_set_label(l1);

        }

        opn = "dadd";

        break;

    case OPC_DADDU:

        tcg_gen_add_tl(t0, t0, t1);

        opn = "daddu";

        break;

    case OPC_DSUB:

        {

            TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);

            TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);

            int l1 = gen_new_label();



            save_cpu_state(ctx, 1);

            tcg_gen_mov_tl(r_tmp1, t0);

            tcg_gen_sub_tl(t0, t0, t1);



            tcg_gen_xor_tl(r_tmp2, r_tmp1, t1);

            tcg_gen_xor_tl(r_tmp1, r_tmp1, t0);

            tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);

            tcg_temp_free(r_tmp2);

            tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);

            tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);

            tcg_temp_free(r_tmp1);

            /* operands of different sign, first operand and result different sign */

            generate_exception(ctx, EXCP_OVERFLOW);

            gen_set_label(l1);

        }

        opn = "dsub";

        break;

    case OPC_DSUBU:

        tcg_gen_sub_tl(t0, t0, t1);

        opn = "dsubu";

        break;

#endif

    case OPC_SLT:

        gen_op_lt(t0, t1);

        opn = "slt";

        break;

    case OPC_SLTU:

        gen_op_ltu(t0, t1);

        opn = "sltu";

        break;

    case OPC_AND:

        tcg_gen_and_tl(t0, t0, t1);

        opn = "and";

        break;

    case OPC_NOR:

        tcg_gen_or_tl(t0, t0, t1);

        tcg_gen_not_tl(t0, t0);

        opn = "nor";

        break;

    case OPC_OR:

        tcg_gen_or_tl(t0, t0, t1);

        opn = "or";

        break;

    case OPC_XOR:

        tcg_gen_xor_tl(t0, t0, t1);

        opn = "xor";

        break;

    case OPC_MUL:

        tcg_gen_ext32s_tl(t0, t0);

        tcg_gen_ext32s_tl(t1, t1);

        tcg_gen_mul_tl(t0, t0, t1);

        tcg_gen_ext32s_tl(t0, t0);

        opn = "mul";

        break;

    case OPC_MOVN:

        {

            int l1 = gen_new_label();



            tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);

            gen_store_gpr(t0, rd);

            gen_set_label(l1);

        }

        opn = "movn";

        goto print;

    case OPC_MOVZ:

        {

            int l1 = gen_new_label();



            tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);

            gen_store_gpr(t0, rd);

            gen_set_label(l1);

        }

        opn = "movz";

        goto print;

    case OPC_SLLV:

        tcg_gen_ext32u_tl(t0, t0);

        tcg_gen_ext32u_tl(t1, t1);

        tcg_gen_andi_tl(t0, t0, 0x1f);

        tcg_gen_shl_tl(t0, t1, t0);

        tcg_gen_ext32s_tl(t0, t0);

        opn = "sllv";

        break;

    case OPC_SRAV:

        tcg_gen_ext32s_tl(t1, t1);

        tcg_gen_andi_tl(t0, t0, 0x1f);

        tcg_gen_sar_tl(t0, t1, t0);

        tcg_gen_ext32s_tl(t0, t0);

        opn = "srav";

        break;

    case OPC_SRLV:

        switch ((ctx->opcode >> 6) & 0x1f) {

        case 0:

            tcg_gen_ext32u_tl(t1, t1);

            tcg_gen_andi_tl(t0, t0, 0x1f);

            tcg_gen_shr_tl(t0, t1, t0);

            tcg_gen_ext32s_tl(t0, t0);

            opn = "srlv";

            break;

        case 1:

            /* rotrv is decoded as srlv on non-R2 CPUs */

            if (env->insn_flags & ISA_MIPS32R2) {

                int l1 = gen_new_label();

                int l2 = gen_new_label();



                tcg_gen_andi_tl(t0, t0, 0x1f);

                tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);

                {

                    TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);

                    TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);



                    tcg_gen_trunc_tl_i32(r_tmp1, t0);

                    tcg_gen_trunc_tl_i32(r_tmp2, t1);

                    tcg_gen_rotr_i32(r_tmp1, r_tmp1, r_tmp2);

                    tcg_temp_free(r_tmp1);

                    tcg_temp_free(r_tmp2);

                    tcg_gen_br(l2);

                }

                gen_set_label(l1);

                tcg_gen_mov_tl(t0, t1);

                gen_set_label(l2);

                opn = "rotrv";

            } else {

                tcg_gen_ext32u_tl(t1, t1);

                tcg_gen_andi_tl(t0, t0, 0x1f);

                tcg_gen_shr_tl(t0, t1, t0);

                tcg_gen_ext32s_tl(t0, t0);

                opn = "srlv";

            }

            break;

        default:

            MIPS_INVAL("invalid srlv flag");

            generate_exception(ctx, EXCP_RI);

            break;

        }

        break;

#if defined(TARGET_MIPS64)

    case OPC_DSLLV:

        tcg_gen_andi_tl(t0, t0, 0x3f);

        tcg_gen_shl_tl(t0, t1, t0);

        opn = "dsllv";

        break;

    case OPC_DSRAV:

        tcg_gen_andi_tl(t0, t0, 0x3f);

        tcg_gen_sar_tl(t0, t1, t0);

        opn = "dsrav";

        break;

    case OPC_DSRLV:

        switch ((ctx->opcode >> 6) & 0x1f) {

        case 0:

            tcg_gen_andi_tl(t0, t0, 0x3f);

            tcg_gen_shr_tl(t0, t1, t0);

            opn = "dsrlv";

            break;

        case 1:

            /* drotrv is decoded as dsrlv on non-R2 CPUs */

            if (env->insn_flags & ISA_MIPS32R2) {

                int l1 = gen_new_label();

                int l2 = gen_new_label();



                tcg_gen_andi_tl(t0, t0, 0x3f);

                tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);

                {

                    tcg_gen_rotr_tl(t0, t1, t0);

                    tcg_gen_br(l2);

                }

                gen_set_label(l1);

                tcg_gen_mov_tl(t0, t1);

                gen_set_label(l2);

                opn = "drotrv";

            } else {

                tcg_gen_andi_tl(t0, t0, 0x3f);

                tcg_gen_shr_tl(t0, t1, t0);

                opn = "dsrlv";

            }

            break;

        default:

            MIPS_INVAL("invalid dsrlv flag");

            generate_exception(ctx, EXCP_RI);

            break;

        }

        break;

#endif

    default:

        MIPS_INVAL(opn);

        generate_exception(ctx, EXCP_RI);

        goto out;

    }

    gen_store_gpr(t0, rd);

 print:

    MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);

 out:

    tcg_temp_free(t0);

    tcg_temp_free(t1);

}

static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,

                       int rd, int rs, int rt)

{

    const char *opn = "arith";

    TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);

    TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);



    if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB

       && opc != OPC_DADD && opc != OPC_DSUB) {

        



        MIPS_DEBUG("NOP");

        goto out;

    }

    gen_load_gpr(t0, rs);

    

    if (rt == 0 && (opc == OPC_ADDU || opc == OPC_DADDU

                    || opc == OPC_SUBU || opc == OPC_DSUBU)) {

        gen_store_gpr(t0, rd);

        goto out;

    }

    gen_load_gpr(t1, rt);

    switch (opc) {

    case OPC_ADD:

        {

            TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);

            TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);

            int l1 = gen_new_label();



            save_cpu_state(ctx, 1);

            tcg_gen_ext32s_tl(r_tmp1, t0);

            tcg_gen_ext32s_tl(r_tmp2, t1);

            tcg_gen_add_tl(t0, r_tmp1, r_tmp2);



            tcg_gen_xor_tl(r_tmp1, r_tmp1, t1);

            tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);

            tcg_gen_xor_tl(r_tmp2, t0, t1);

            tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);

            tcg_temp_free(r_tmp2);

            tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);

            tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);

            tcg_temp_free(r_tmp1);

            

            generate_exception(ctx, EXCP_OVERFLOW);

            gen_set_label(l1);



            tcg_gen_ext32s_tl(t0, t0);

        }

        opn = "add";

        break;

    case OPC_ADDU:

        tcg_gen_ext32s_tl(t0, t0);

        tcg_gen_ext32s_tl(t1, t1);

        tcg_gen_add_tl(t0, t0, t1);

        tcg_gen_ext32s_tl(t0, t0);

        opn = "addu";

        break;

    case OPC_SUB:

        {

            TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);

            TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);

            int l1 = gen_new_label();



            save_cpu_state(ctx, 1);

            tcg_gen_ext32s_tl(r_tmp1, t0);

            tcg_gen_ext32s_tl(r_tmp2, t1);

            tcg_gen_sub_tl(t0, r_tmp1, r_tmp2);



            tcg_gen_xor_tl(r_tmp2, r_tmp1, t1);

            tcg_gen_xor_tl(r_tmp1, r_tmp1, t0);

            tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);

            tcg_temp_free(r_tmp2);

            tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);

            tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);

            tcg_temp_free(r_tmp1);

            

            generate_exception(ctx, EXCP_OVERFLOW);

            gen_set_label(l1);



            tcg_gen_ext32s_tl(t0, t0);

        }

        opn = "sub";

        break;

    case OPC_SUBU:

        tcg_gen_ext32s_tl(t0, t0);

        tcg_gen_ext32s_tl(t1, t1);

        tcg_gen_sub_tl(t0, t0, t1);

        tcg_gen_ext32s_tl(t0, t0);

        opn = "subu";

        break;

#if defined(TARGET_MIPS64)

    case OPC_DADD:

        {

            TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);

            TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);

            int l1 = gen_new_label();



            save_cpu_state(ctx, 1);

            tcg_gen_mov_tl(r_tmp1, t0);

            tcg_gen_add_tl(t0, t0, t1);



            tcg_gen_xor_tl(r_tmp1, r_tmp1, t1);

            tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);

            tcg_gen_xor_tl(r_tmp2, t0, t1);

            tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);

            tcg_temp_free(r_tmp2);

            tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);

            tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);

            tcg_temp_free(r_tmp1);

            

            generate_exception(ctx, EXCP_OVERFLOW);

            gen_set_label(l1);

        }

        opn = "dadd";

        break;

    case OPC_DADDU:

        tcg_gen_add_tl(t0, t0, t1);

        opn = "daddu";

        break;

    case OPC_DSUB:

        {

            TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);

            TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);

            int l1 = gen_new_label();



            save_cpu_state(ctx, 1);

            tcg_gen_mov_tl(r_tmp1, t0);

            tcg_gen_sub_tl(t0, t0, t1);



            tcg_gen_xor_tl(r_tmp2, r_tmp1, t1);

            tcg_gen_xor_tl(r_tmp1, r_tmp1, t0);

            tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);

            tcg_temp_free(r_tmp2);

            tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);

            tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);

            tcg_temp_free(r_tmp1);

            

            generate_exception(ctx, EXCP_OVERFLOW);

            gen_set_label(l1);

        }

        opn = "dsub";

        break;

    case OPC_DSUBU:

        tcg_gen_sub_tl(t0, t0, t1);

        opn = "dsubu";

        break;

#endif

    case OPC_SLT:

        gen_op_lt(t0, t1);

        opn = "slt";

        break;

    case OPC_SLTU:

        gen_op_ltu(t0, t1);

        opn = "sltu";

        break;

    case OPC_AND:

        tcg_gen_and_tl(t0, t0, t1);

        opn = "and";

        break;

    case OPC_NOR:

        tcg_gen_or_tl(t0, t0, t1);

        tcg_gen_not_tl(t0, t0);

        opn = "nor";

        break;

    case OPC_OR:

        tcg_gen_or_tl(t0, t0, t1);

        opn = "or";

        break;

    case OPC_XOR:

        tcg_gen_xor_tl(t0, t0, t1);

        opn = "xor";

        break;

    case OPC_MUL:

        tcg_gen_ext32s_tl(t0, t0);

        tcg_gen_ext32s_tl(t1, t1);

        tcg_gen_mul_tl(t0, t0, t1);

        tcg_gen_ext32s_tl(t0, t0);

        opn = "mul";

        break;

    case OPC_MOVN:

        {

            int l1 = gen_new_label();



            tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);

            gen_store_gpr(t0, rd);

            gen_set_label(l1);

        }

        opn = "movn";

        goto print;

    case OPC_MOVZ:

        {

            int l1 = gen_new_label();



            tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);

            gen_store_gpr(t0, rd);

            gen_set_label(l1);

        }

        opn = "movz";

        goto print;

    case OPC_SLLV:

        tcg_gen_ext32u_tl(t0, t0);

        tcg_gen_ext32u_tl(t1, t1);

        tcg_gen_andi_tl(t0, t0, 0x1f);

        tcg_gen_shl_tl(t0, t1, t0);

        tcg_gen_ext32s_tl(t0, t0);

        opn = "sllv";

        break;

    case OPC_SRAV:

        tcg_gen_ext32s_tl(t1, t1);

        tcg_gen_andi_tl(t0, t0, 0x1f);

        tcg_gen_sar_tl(t0, t1, t0);

        tcg_gen_ext32s_tl(t0, t0);

        opn = "srav";

        break;

    case OPC_SRLV:

        switch ((ctx->opcode >> 6) & 0x1f) {

        case 0:

            tcg_gen_ext32u_tl(t1, t1);

            tcg_gen_andi_tl(t0, t0, 0x1f);

            tcg_gen_shr_tl(t0, t1, t0);

            tcg_gen_ext32s_tl(t0, t0);

            opn = "srlv";

            break;

        case 1:

            

            if (env->insn_flags & ISA_MIPS32R2) {

                int l1 = gen_new_label();

                int l2 = gen_new_label();



                tcg_gen_andi_tl(t0, t0, 0x1f);

                tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);

                {

                    TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);

                    TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);



                    tcg_gen_trunc_tl_i32(r_tmp1, t0);

                    tcg_gen_trunc_tl_i32(r_tmp2, t1);

                    tcg_gen_rotr_i32(r_tmp1, r_tmp1, r_tmp2);

                    tcg_temp_free(r_tmp1);

                    tcg_temp_free(r_tmp2);

                    tcg_gen_br(l2);

                }

                gen_set_label(l1);

                tcg_gen_mov_tl(t0, t1);

                gen_set_label(l2);

                opn = "rotrv";

            } else {

                tcg_gen_ext32u_tl(t1, t1);

                tcg_gen_andi_tl(t0, t0, 0x1f);

                tcg_gen_shr_tl(t0, t1, t0);

                tcg_gen_ext32s_tl(t0, t0);

                opn = "srlv";

            }

            break;

        default:

            MIPS_INVAL("invalid srlv flag");

            generate_exception(ctx, EXCP_RI);

            break;

        }

        break;

#if defined(TARGET_MIPS64)

    case OPC_DSLLV:

        tcg_gen_andi_tl(t0, t0, 0x3f);

        tcg_gen_shl_tl(t0, t1, t0);

        opn = "dsllv";

        break;

    case OPC_DSRAV:

        tcg_gen_andi_tl(t0, t0, 0x3f);

        tcg_gen_sar_tl(t0, t1, t0);

        opn = "dsrav";

        break;

    case OPC_DSRLV:

        switch ((ctx->opcode >> 6) & 0x1f) {

        case 0:

            tcg_gen_andi_tl(t0, t0, 0x3f);

            tcg_gen_shr_tl(t0, t1, t0);

            opn = "dsrlv";

            break;

        case 1:

            

            if (env->insn_flags & ISA_MIPS32R2) {

                int l1 = gen_new_label();

                int l2 = gen_new_label();



                tcg_gen_andi_tl(t0, t0, 0x3f);

                tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);

                {

                    tcg_gen_rotr_tl(t0, t1, t0);

                    tcg_gen_br(l2);

                }

                gen_set_label(l1);

                tcg_gen_mov_tl(t0, t1);

                gen_set_label(l2);

                opn = "drotrv";

            } else {

                tcg_gen_andi_tl(t0, t0, 0x3f);

                tcg_gen_shr_tl(t0, t1, t0);

                opn = "dsrlv";

            }

            break;

        default:

            MIPS_INVAL("invalid dsrlv flag");

            generate_exception(ctx, EXCP_RI);

            break;

        }

        break;

#endif

    default:

        MIPS_INVAL(opn);

        generate_exception(ctx, EXCP_RI);

        goto out;

    }

    gen_store_gpr(t0, rd);

 print:

    MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);

 out:

    tcg_temp_free(t0);

    tcg_temp_free(t1);

}

static void FUNC_0 (CPUState *VAR_0, DisasContext *VAR_1, uint32_t VAR_2,

                       int VAR_3, int VAR_4, int VAR_5)

{

    const char *VAR_6 = "arith";

    TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);

    TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);



    if (VAR_3 == 0 && VAR_2 != OPC_ADD && VAR_2 != OPC_SUB

       && VAR_2 != OPC_DADD && VAR_2 != OPC_DSUB) {

        



        MIPS_DEBUG("NOP");

        goto out;

    }

    gen_load_gpr(t0, VAR_4);

    

    if (VAR_5 == 0 && (VAR_2 == OPC_ADDU || VAR_2 == OPC_DADDU

                    || VAR_2 == OPC_SUBU || VAR_2 == OPC_DSUBU)) {

        gen_store_gpr(t0, VAR_3);

        goto out;

    }

    gen_load_gpr(t1, VAR_5);

    switch (VAR_2) {

    case OPC_ADD:

        {

            TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);

            TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);

            int VAR_8 = gen_new_label();



            save_cpu_state(VAR_1, 1);

            tcg_gen_ext32s_tl(r_tmp1, t0);

            tcg_gen_ext32s_tl(r_tmp2, t1);

            tcg_gen_add_tl(t0, r_tmp1, r_tmp2);



            tcg_gen_xor_tl(r_tmp1, r_tmp1, t1);

            tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);

            tcg_gen_xor_tl(r_tmp2, t0, t1);

            tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);

            tcg_temp_free(r_tmp2);

            tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);

            tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, VAR_8);

            tcg_temp_free(r_tmp1);

            

            generate_exception(VAR_1, EXCP_OVERFLOW);

            gen_set_label(VAR_8);



            tcg_gen_ext32s_tl(t0, t0);

        }

        VAR_6 = "add";

        break;

    case OPC_ADDU:

        tcg_gen_ext32s_tl(t0, t0);

        tcg_gen_ext32s_tl(t1, t1);

        tcg_gen_add_tl(t0, t0, t1);

        tcg_gen_ext32s_tl(t0, t0);

        VAR_6 = "addu";

        break;

    case OPC_SUB:

        {

            TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);

            TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);

            int VAR_8 = gen_new_label();



            save_cpu_state(VAR_1, 1);

            tcg_gen_ext32s_tl(r_tmp1, t0);

            tcg_gen_ext32s_tl(r_tmp2, t1);

            tcg_gen_sub_tl(t0, r_tmp1, r_tmp2);



            tcg_gen_xor_tl(r_tmp2, r_tmp1, t1);

            tcg_gen_xor_tl(r_tmp1, r_tmp1, t0);

            tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);

            tcg_temp_free(r_tmp2);

            tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);

            tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, VAR_8);

            tcg_temp_free(r_tmp1);

            

            generate_exception(VAR_1, EXCP_OVERFLOW);

            gen_set_label(VAR_8);



            tcg_gen_ext32s_tl(t0, t0);

        }

        VAR_6 = "sub";

        break;

    case OPC_SUBU:

        tcg_gen_ext32s_tl(t0, t0);

        tcg_gen_ext32s_tl(t1, t1);

        tcg_gen_sub_tl(t0, t0, t1);

        tcg_gen_ext32s_tl(t0, t0);

        VAR_6 = "subu";

        break;

#if defined(TARGET_MIPS64)

    case OPC_DADD:

        {

            TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);

            TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);

            int VAR_8 = gen_new_label();



            save_cpu_state(VAR_1, 1);

            tcg_gen_mov_tl(r_tmp1, t0);

            tcg_gen_add_tl(t0, t0, t1);



            tcg_gen_xor_tl(r_tmp1, r_tmp1, t1);

            tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);

            tcg_gen_xor_tl(r_tmp2, t0, t1);

            tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);

            tcg_temp_free(r_tmp2);

            tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);

            tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, VAR_8);

            tcg_temp_free(r_tmp1);

            

            generate_exception(VAR_1, EXCP_OVERFLOW);

            gen_set_label(VAR_8);

        }

        VAR_6 = "dadd";

        break;

    case OPC_DADDU:

        tcg_gen_add_tl(t0, t0, t1);

        VAR_6 = "daddu";

        break;

    case OPC_DSUB:

        {

            TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);

            TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);

            int VAR_8 = gen_new_label();



            save_cpu_state(VAR_1, 1);

            tcg_gen_mov_tl(r_tmp1, t0);

            tcg_gen_sub_tl(t0, t0, t1);



            tcg_gen_xor_tl(r_tmp2, r_tmp1, t1);

            tcg_gen_xor_tl(r_tmp1, r_tmp1, t0);

            tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);

            tcg_temp_free(r_tmp2);

            tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);

            tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, VAR_8);

            tcg_temp_free(r_tmp1);

            

            generate_exception(VAR_1, EXCP_OVERFLOW);

            gen_set_label(VAR_8);

        }

        VAR_6 = "dsub";

        break;

    case OPC_DSUBU:

        tcg_gen_sub_tl(t0, t0, t1);

        VAR_6 = "dsubu";

        break;

#endif

    case OPC_SLT:

        gen_op_lt(t0, t1);

        VAR_6 = "slt";

        break;

    case OPC_SLTU:

        gen_op_ltu(t0, t1);

        VAR_6 = "sltu";

        break;

    case OPC_AND:

        tcg_gen_and_tl(t0, t0, t1);

        VAR_6 = "and";

        break;

    case OPC_NOR:

        tcg_gen_or_tl(t0, t0, t1);

        tcg_gen_not_tl(t0, t0);

        VAR_6 = "nor";

        break;

    case OPC_OR:

        tcg_gen_or_tl(t0, t0, t1);

        VAR_6 = "or";

        break;

    case OPC_XOR:

        tcg_gen_xor_tl(t0, t0, t1);

        VAR_6 = "xor";

        break;

    case OPC_MUL:

        tcg_gen_ext32s_tl(t0, t0);

        tcg_gen_ext32s_tl(t1, t1);

        tcg_gen_mul_tl(t0, t0, t1);

        tcg_gen_ext32s_tl(t0, t0);

        VAR_6 = "mul";

        break;

    case OPC_MOVN:

        {

            int VAR_8 = gen_new_label();



            tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, VAR_8);

            gen_store_gpr(t0, VAR_3);

            gen_set_label(VAR_8);

        }

        VAR_6 = "movn";

        goto print;

    case OPC_MOVZ:

        {

            int VAR_8 = gen_new_label();



            tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, VAR_8);

            gen_store_gpr(t0, VAR_3);

            gen_set_label(VAR_8);

        }

        VAR_6 = "movz";

        goto print;

    case OPC_SLLV:

        tcg_gen_ext32u_tl(t0, t0);

        tcg_gen_ext32u_tl(t1, t1);

        tcg_gen_andi_tl(t0, t0, 0x1f);

        tcg_gen_shl_tl(t0, t1, t0);

        tcg_gen_ext32s_tl(t0, t0);

        VAR_6 = "sllv";

        break;

    case OPC_SRAV:

        tcg_gen_ext32s_tl(t1, t1);

        tcg_gen_andi_tl(t0, t0, 0x1f);

        tcg_gen_sar_tl(t0, t1, t0);

        tcg_gen_ext32s_tl(t0, t0);

        VAR_6 = "srav";

        break;

    case OPC_SRLV:

        switch ((VAR_1->opcode >> 6) & 0x1f) {

        case 0:

            tcg_gen_ext32u_tl(t1, t1);

            tcg_gen_andi_tl(t0, t0, 0x1f);

            tcg_gen_shr_tl(t0, t1, t0);

            tcg_gen_ext32s_tl(t0, t0);

            VAR_6 = "srlv";

            break;

        case 1:

            

            if (VAR_0->insn_flags & ISA_MIPS32R2) {

                int VAR_8 = gen_new_label();

                int VAR_8 = gen_new_label();



                tcg_gen_andi_tl(t0, t0, 0x1f);

                tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, VAR_8);

                {

                    TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);

                    TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);



                    tcg_gen_trunc_tl_i32(r_tmp1, t0);

                    tcg_gen_trunc_tl_i32(r_tmp2, t1);

                    tcg_gen_rotr_i32(r_tmp1, r_tmp1, r_tmp2);

                    tcg_temp_free(r_tmp1);

                    tcg_temp_free(r_tmp2);

                    tcg_gen_br(VAR_8);

                }

                gen_set_label(VAR_8);

                tcg_gen_mov_tl(t0, t1);

                gen_set_label(VAR_8);

                VAR_6 = "rotrv";

            } else {

                tcg_gen_ext32u_tl(t1, t1);

                tcg_gen_andi_tl(t0, t0, 0x1f);

                tcg_gen_shr_tl(t0, t1, t0);

                tcg_gen_ext32s_tl(t0, t0);

                VAR_6 = "srlv";

            }

            break;

        default:

            MIPS_INVAL("invalid srlv flag");

            generate_exception(VAR_1, EXCP_RI);

            break;

        }

        break;

#if defined(TARGET_MIPS64)

    case OPC_DSLLV:

        tcg_gen_andi_tl(t0, t0, 0x3f);

        tcg_gen_shl_tl(t0, t1, t0);

        VAR_6 = "dsllv";

        break;

    case OPC_DSRAV:

        tcg_gen_andi_tl(t0, t0, 0x3f);

        tcg_gen_sar_tl(t0, t1, t0);

        VAR_6 = "dsrav";

        break;

    case OPC_DSRLV:

        switch ((VAR_1->opcode >> 6) & 0x1f) {

        case 0:

            tcg_gen_andi_tl(t0, t0, 0x3f);

            tcg_gen_shr_tl(t0, t1, t0);

            VAR_6 = "dsrlv";

            break;

        case 1:

            

            if (VAR_0->insn_flags & ISA_MIPS32R2) {

                int VAR_8 = gen_new_label();

                int VAR_8 = gen_new_label();



                tcg_gen_andi_tl(t0, t0, 0x3f);

                tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, VAR_8);

                {

                    tcg_gen_rotr_tl(t0, t1, t0);

                    tcg_gen_br(VAR_8);

                }

                gen_set_label(VAR_8);

                tcg_gen_mov_tl(t0, t1);

                gen_set_label(VAR_8);

                VAR_6 = "drotrv";

            } else {

                tcg_gen_andi_tl(t0, t0, 0x3f);

                tcg_gen_shr_tl(t0, t1, t0);

                VAR_6 = "dsrlv";

            }

            break;

        default:

            MIPS_INVAL("invalid dsrlv flag");

            generate_exception(VAR_1, EXCP_RI);

            break;

        }

        break;

#endif

    default:

        MIPS_INVAL(VAR_6);

        generate_exception(VAR_1, EXCP_RI);

        goto out;

    }

    gen_store_gpr(t0, VAR_3);

 print:

    MIPS_DEBUG("%s %s, %s, %s", VAR_6, regnames[VAR_3], regnames[VAR_4], regnames[VAR_5]);

 out:

    tcg_temp_free(t0);

    tcg_temp_free(t1);

}

static void FUNC_0 (CPUState *VAR_0, DisasContext *VAR_1, uint32_t VAR_2,
int VAR_3, int VAR_4, int VAR_5)
{ const char *VAR_6 = "arith"; TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL); TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL); if (VAR_3 == 0 && VAR_2 != OPC_ADD && VAR_2 != OPC_SUB
&& VAR_2 != OPC_DADD && VAR_2 != OPC_DSUB) { MIPS_DEBUG("NOP"); goto out; } gen_load_gpr(t0, VAR_4); if (VAR_5 == 0 && (VAR_2 == OPC_ADDU || VAR_2 == OPC_DADDU
|| VAR_2 == OPC_SUBU || VAR_2 == OPC_DSUBU)) { gen_store_gpr(t0, VAR_3); goto out; } gen_load_gpr(t1, VAR_5); switch (VAR_2) { case OPC_ADD:
{ TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL); TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL); int VAR_8 = gen_new_label(); save_cpu_state(VAR_1, 1); tcg_gen_ext32s_tl(r_tmp1, t0); tcg_gen_ext32s_tl(r_tmp2, t1); tcg_gen_add_tl(t0, r_tmp1, r_tmp2); tcg_gen_xor_tl(r_tmp1, r_tmp1, t1); tcg_gen_xori_tl(r_tmp1, r_tmp1, -1); tcg_gen_xor_tl(r_tmp2, t0, t1); tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2); tcg_temp_free(r_tmp2); tcg_gen_shri_tl(r_tmp1, r_tmp1, 31); tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, VAR_8); tcg_temp_free(r_tmp1); generate_exception(VAR_1, EXCP_OVERFLOW); gen_set_label(VAR_8); tcg_gen_ext32s_tl(t0, t0); } VAR_6 = "add"; break; case OPC_ADDU:
tcg_gen_ext32s_tl(t0, t0); tcg_gen_ext32s_tl(t1, t1); tcg_gen_add_tl(t0, t0, t1); tcg_gen_ext32s_tl(t0, t0); VAR_6 = "addu"; break; case OPC_SUB:
{ TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL); TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL); int VAR_8 = gen_new_label(); save_cpu_state(VAR_1, 1); tcg_gen_ext32s_tl(r_tmp1, t0); tcg_gen_ext32s_tl(r_tmp2, t1); tcg_gen_sub_tl(t0, r_tmp1, r_tmp2); tcg_gen_xor_tl(r_tmp2, r_tmp1, t1); tcg_gen_xor_tl(r_tmp1, r_tmp1, t0); tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2); tcg_temp_free(r_tmp2); tcg_gen_shri_tl(r_tmp1, r_tmp1, 31); tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, VAR_8); tcg_temp_free(r_tmp1); generate_exception(VAR_1, EXCP_OVERFLOW); gen_set_label(VAR_8); tcg_gen_ext32s_tl(t0, t0); } VAR_6 = "sub"; break; case OPC_SUBU:
tcg_gen_ext32s_tl(t0, t0); tcg_gen_ext32s_tl(t1, t1); tcg_gen_sub_tl(t0, t0, t1); tcg_gen_ext32s_tl(t0, t0); VAR_6 = "subu"; break; #if defined(TARGET_MIPS64)
case OPC_DADD:
{ TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL); TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL); int VAR_8 = gen_new_label(); save_cpu_state(VAR_1, 1); tcg_gen_mov_tl(r_tmp1, t0); tcg_gen_add_tl(t0, t0, t1); tcg_gen_xor_tl(r_tmp1, r_tmp1, t1); tcg_gen_xori_tl(r_tmp1, r_tmp1, -1); tcg_gen_xor_tl(r_tmp2, t0, t1); tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2); tcg_temp_free(r_tmp2); tcg_gen_shri_tl(r_tmp1, r_tmp1, 63); tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, VAR_8); tcg_temp_free(r_tmp1); generate_exception(VAR_1, EXCP_OVERFLOW); gen_set_label(VAR_8); } VAR_6 = "dadd"; break; case OPC_DADDU:
tcg_gen_add_tl(t0, t0, t1); VAR_6 = "daddu"; break; case OPC_DSUB:
{ TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL); TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL); int VAR_8 = gen_new_label(); save_cpu_state(VAR_1, 1); tcg_gen_mov_tl(r_tmp1, t0); tcg_gen_sub_tl(t0, t0, t1); tcg_gen_xor_tl(r_tmp2, r_tmp1, t1); tcg_gen_xor_tl(r_tmp1, r_tmp1, t0); tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2); tcg_temp_free(r_tmp2); tcg_gen_shri_tl(r_tmp1, r_tmp1, 63); tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, VAR_8); tcg_temp_free(r_tmp1); generate_exception(VAR_1, EXCP_OVERFLOW); gen_set_label(VAR_8); } VAR_6 = "dsub"; break; case OPC_DSUBU:
tcg_gen_sub_tl(t0, t0, t1); VAR_6 = "dsubu"; break; #endif
case OPC_SLT:
gen_op_lt(t0, t1); VAR_6 = "slt"; break; case OPC_SLTU:
gen_op_ltu(t0, t1); VAR_6 = "sltu"; break; case OPC_AND:
tcg_gen_and_tl(t0, t0, t1); VAR_6 = "and"; break; case OPC_NOR:
tcg_gen_or_tl(t0, t0, t1); tcg_gen_not_tl(t0, t0); VAR_6 = "nor"; break; case OPC_OR:
tcg_gen_or_tl(t0, t0, t1); VAR_6 = "or"; break; case OPC_XOR:
tcg_gen_xor_tl(t0, t0, t1); VAR_6 = "xor"; break; case OPC_MUL:
tcg_gen_ext32s_tl(t0, t0); tcg_gen_ext32s_tl(t1, t1); tcg_gen_mul_tl(t0, t0, t1); tcg_gen_ext32s_tl(t0, t0); VAR_6 = "mul"; break; case OPC_MOVN:
{ int VAR_8 = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, VAR_8); gen_store_gpr(t0, VAR_3); gen_set_label(VAR_8); } VAR_6 = "movn"; goto print; case OPC_MOVZ:
{ int VAR_8 = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, VAR_8); gen_store_gpr(t0, VAR_3); gen_set_label(VAR_8); } VAR_6 = "movz"; goto print; case OPC_SLLV:
tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); tcg_gen_andi_tl(t0, t0, 0x1f); tcg_gen_shl_tl(t0, t1, t0); tcg_gen_ext32s_tl(t0, t0); VAR_6 = "sllv"; break; case OPC_SRAV:
tcg_gen_ext32s_tl(t1, t1); tcg_gen_andi_tl(t0, t0, 0x1f); tcg_gen_sar_tl(t0, t1, t0); tcg_gen_ext32s_tl(t0, t0); VAR_6 = "srav"; break; case OPC_SRLV:
switch ((VAR_1->opcode >> 6) & 0x1f) { case 0:
tcg_gen_ext32u_tl(t1, t1); tcg_gen_andi_tl(t0, t0, 0x1f); tcg_gen_shr_tl(t0, t1, t0); tcg_gen_ext32s_tl(t0, t0); VAR_6 = "srlv"; break; case 1:
if (VAR_0->insn_flags & ISA_MIPS32R2) { int VAR_8 = gen_new_label(); int VAR_8 = gen_new_label(); tcg_gen_andi_tl(t0, t0, 0x1f); tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, VAR_8); { TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); tcg_gen_trunc_tl_i32(r_tmp1, t0); tcg_gen_trunc_tl_i32(r_tmp2, t1); tcg_gen_rotr_i32(r_tmp1, r_tmp1, r_tmp2); tcg_temp_free(r_tmp1); tcg_temp_free(r_tmp2); tcg_gen_br(VAR_8); } gen_set_label(VAR_8); tcg_gen_mov_tl(t0, t1); gen_set_label(VAR_8); VAR_6 = "rotrv"; } else { tcg_gen_ext32u_tl(t1, t1); tcg_gen_andi_tl(t0, t0, 0x1f); tcg_gen_shr_tl(t0, t1, t0); tcg_gen_ext32s_tl(t0, t0); VAR_6 = "srlv"; } break; default:
MIPS_INVAL("invalid srlv flag"); generate_exception(VAR_1, EXCP_RI); break; } break; #if defined(TARGET_MIPS64)
case OPC_DSLLV:
tcg_gen_andi_tl(t0, t0, 0x3f); tcg_gen_shl_tl(t0, t1, t0); VAR_6 = "dsllv"; break; case OPC_DSRAV:
tcg_gen_andi_tl(t0, t0, 0x3f); tcg_gen_sar_tl(t0, t1, t0); VAR_6 = "dsrav"; break; case OPC_DSRLV:
switch ((VAR_1->opcode >> 6) & 0x1f) { case 0:
tcg_gen_andi_tl(t0, t0, 0x3f); tcg_gen_shr_tl(t0, t1, t0); VAR_6 = "dsrlv"; break; case 1:
if (VAR_0->insn_flags & ISA_MIPS32R2) { int VAR_8 = gen_new_label(); int VAR_8 = gen_new_label(); tcg_gen_andi_tl(t0, t0, 0x3f); tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, VAR_8); { tcg_gen_rotr_tl(t0, t1, t0); tcg_gen_br(VAR_8); } gen_set_label(VAR_8); tcg_gen_mov_tl(t0, t1); gen_set_label(VAR_8); VAR_6 = "drotrv"; } else { tcg_gen_andi_tl(t0, t0, 0x3f); tcg_gen_shr_tl(t0, t1, t0); VAR_6 = "dsrlv"; } break; default:
MIPS_INVAL("invalid dsrlv flag"); generate_exception(VAR_1, EXCP_RI); break; } break; #endif
default:
MIPS_INVAL(VAR_6); generate_exception(VAR_1, EXCP_RI); goto out; } gen_store_gpr(t0, VAR_3); print:
MIPS_DEBUG("%s %s, %s, %s", VAR_6, regnames[VAR_3], regnames[VAR_4], regnames[VAR_5]); out:
tcg_temp_free(t0); tcg_temp_free(t1); }