void do_interrupt(CPUARMState *env)

{

    uint32_t addr;

    uint32_t mask;

    int new_mode;

    uint32_t offset;



    if (IS_M(env)) {

        do_interrupt_v7m(env);

        return;

    }

    /* TODO: Vectored interrupt controller.  */

    switch (env->exception_index) {

    case EXCP_UDEF:

        new_mode = ARM_CPU_MODE_UND;

        addr = 0x04;

        mask = CPSR_I;

        if (env->thumb)

            offset = 2;

        else

            offset = 4;

        break;

    case EXCP_SWI:

        if (semihosting_enabled) {

            /* Check for semihosting interrupt.  */

            if (env->thumb) {

                mask = lduw_code(env->regs[15] - 2) & 0xff;

            } else {

                mask = ldl_code(env->regs[15] - 4) & 0xffffff;

            }

            /* Only intercept calls from privileged modes, to provide some

               semblance of security.  */

            if (((mask == 0x123456 && !env->thumb)

                    || (mask == 0xab && env->thumb))

                  && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {

                env->regs[0] = do_arm_semihosting(env);

                return;

            }

        }

        new_mode = ARM_CPU_MODE_SVC;

        addr = 0x08;

        mask = CPSR_I;

        /* The PC already points to the next instruction.  */

        offset = 0;

        break;

    case EXCP_BKPT:

        /* See if this is a semihosting syscall.  */

        if (env->thumb && semihosting_enabled) {

            mask = lduw_code(env->regs[15]) & 0xff;

            if (mask == 0xab

                  && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {

                env->regs[15] += 2;

                env->regs[0] = do_arm_semihosting(env);

                return;

            }

        }

        env->cp15.c5_insn = 2;

        /* Fall through to prefetch abort.  */

    case EXCP_PREFETCH_ABORT:

        new_mode = ARM_CPU_MODE_ABT;

        addr = 0x0c;

        mask = CPSR_A | CPSR_I;

        offset = 4;

        break;

    case EXCP_DATA_ABORT:

        new_mode = ARM_CPU_MODE_ABT;

        addr = 0x10;

        mask = CPSR_A | CPSR_I;

        offset = 8;

        break;

    case EXCP_IRQ:

        new_mode = ARM_CPU_MODE_IRQ;

        addr = 0x18;

        /* Disable IRQ and imprecise data aborts.  */

        mask = CPSR_A | CPSR_I;

        offset = 4;

        break;

    case EXCP_FIQ:

        new_mode = ARM_CPU_MODE_FIQ;

        addr = 0x1c;

        /* Disable FIQ, IRQ and imprecise data aborts.  */

        mask = CPSR_A | CPSR_I | CPSR_F;

        offset = 4;

        break;

    default:

        cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);

        return; /* Never happens.  Keep compiler happy.  */

    }

    /* High vectors.  */

    if (env->cp15.c1_sys & (1 << 13)) {

        addr += 0xffff0000;

    }

    switch_mode (env, new_mode);

    env->spsr = cpsr_read(env);

    /* Clear IT bits.  */

    env->condexec_bits = 0;

    /* Switch to the new mode, and to the correct instruction set.  */

    env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;

    env->uncached_cpsr |= mask;

    /* this is a lie, as the was no c1_sys on V4T/V5, but who cares

     * and we should just guard the thumb mode on V4 */

    if (arm_feature(env, ARM_FEATURE_V4T)) {

        env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;

    }

    env->regs[14] = env->regs[15] + offset;

    env->regs[15] = addr;

    env->interrupt_request |= CPU_INTERRUPT_EXITTB;

}

void do_interrupt(CPUARMState *env)

{

    uint32_t addr;

    uint32_t mask;

    int new_mode;

    uint32_t offset;



    if (IS_M(env)) {

        do_interrupt_v7m(env);

        return;

    }

    

    switch (env->exception_index) {

    case EXCP_UDEF:

        new_mode = ARM_CPU_MODE_UND;

        addr = 0x04;

        mask = CPSR_I;

        if (env->thumb)

            offset = 2;

        else

            offset = 4;

        break;

    case EXCP_SWI:

        if (semihosting_enabled) {

            

            if (env->thumb) {

                mask = lduw_code(env->regs[15] - 2) & 0xff;

            } else {

                mask = ldl_code(env->regs[15] - 4) & 0xffffff;

            }

            



            if (((mask == 0x123456 && !env->thumb)

                    || (mask == 0xab && env->thumb))

                  && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {

                env->regs[0] = do_arm_semihosting(env);

                return;

            }

        }

        new_mode = ARM_CPU_MODE_SVC;

        addr = 0x08;

        mask = CPSR_I;

        

        offset = 0;

        break;

    case EXCP_BKPT:

        

        if (env->thumb && semihosting_enabled) {

            mask = lduw_code(env->regs[15]) & 0xff;

            if (mask == 0xab

                  && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {

                env->regs[15] += 2;

                env->regs[0] = do_arm_semihosting(env);

                return;

            }

        }

        env->cp15.c5_insn = 2;

        

    case EXCP_PREFETCH_ABORT:

        new_mode = ARM_CPU_MODE_ABT;

        addr = 0x0c;

        mask = CPSR_A | CPSR_I;

        offset = 4;

        break;

    case EXCP_DATA_ABORT:

        new_mode = ARM_CPU_MODE_ABT;

        addr = 0x10;

        mask = CPSR_A | CPSR_I;

        offset = 8;

        break;

    case EXCP_IRQ:

        new_mode = ARM_CPU_MODE_IRQ;

        addr = 0x18;

        

        mask = CPSR_A | CPSR_I;

        offset = 4;

        break;

    case EXCP_FIQ:

        new_mode = ARM_CPU_MODE_FIQ;

        addr = 0x1c;

        

        mask = CPSR_A | CPSR_I | CPSR_F;

        offset = 4;

        break;

    default:

        cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);

        return; 

    }

    

    if (env->cp15.c1_sys & (1 << 13)) {

        addr += 0xffff0000;

    }

    switch_mode (env, new_mode);

    env->spsr = cpsr_read(env);

    

    env->condexec_bits = 0;

    

    env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;

    env->uncached_cpsr |= mask;

    



    if (arm_feature(env, ARM_FEATURE_V4T)) {

        env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;

    }

    env->regs[14] = env->regs[15] + offset;

    env->regs[15] = addr;

    env->interrupt_request |= CPU_INTERRUPT_EXITTB;

}

                mask = lduw_code(env->regs[15] - 2) & 0xff;                 mask = ldl_code(env->regs[15] - 4) & 0xffffff;             mask = lduw_code(env->regs[15]) & 0xff;
void FUNC_0(CPUARMState *VAR_0)

{

    uint32_t addr;

    uint32_t mask;

    int VAR_1;

    uint32_t offset;



    if (IS_M(VAR_0)) {

        do_interrupt_v7m(VAR_0);

        return;

    }

    

    switch (VAR_0->exception_index) {

    case EXCP_UDEF:

        VAR_1 = ARM_CPU_MODE_UND;

        addr = 0x04;

        mask = CPSR_I;

        if (VAR_0->thumb)

            offset = 2;

        else

            offset = 4;

        break;

    case EXCP_SWI:

        if (semihosting_enabled) {

            

            if (VAR_0->thumb) {

                mask = lduw_code(VAR_0->regs[15] - 2) & 0xff;

            } else {

                mask = ldl_code(VAR_0->regs[15] - 4) & 0xffffff;

            }

            



            if (((mask == 0x123456 && !VAR_0->thumb)

                    || (mask == 0xab && VAR_0->thumb))

                  && (VAR_0->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {

                VAR_0->regs[0] = do_arm_semihosting(VAR_0);

                return;

            }

        }

        VAR_1 = ARM_CPU_MODE_SVC;

        addr = 0x08;

        mask = CPSR_I;

        

        offset = 0;

        break;

    case EXCP_BKPT:

        

        if (VAR_0->thumb && semihosting_enabled) {

            mask = lduw_code(VAR_0->regs[15]) & 0xff;

            if (mask == 0xab

                  && (VAR_0->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {

                VAR_0->regs[15] += 2;

                VAR_0->regs[0] = do_arm_semihosting(VAR_0);

                return;

            }

        }

        VAR_0->cp15.c5_insn = 2;

        

    case EXCP_PREFETCH_ABORT:

        VAR_1 = ARM_CPU_MODE_ABT;

        addr = 0x0c;

        mask = CPSR_A | CPSR_I;

        offset = 4;

        break;

    case EXCP_DATA_ABORT:

        VAR_1 = ARM_CPU_MODE_ABT;

        addr = 0x10;

        mask = CPSR_A | CPSR_I;

        offset = 8;

        break;

    case EXCP_IRQ:

        VAR_1 = ARM_CPU_MODE_IRQ;

        addr = 0x18;

        

        mask = CPSR_A | CPSR_I;

        offset = 4;

        break;

    case EXCP_FIQ:

        VAR_1 = ARM_CPU_MODE_FIQ;

        addr = 0x1c;

        

        mask = CPSR_A | CPSR_I | CPSR_F;

        offset = 4;

        break;

    default:

        cpu_abort(VAR_0, "Unhandled exception 0x%x\n", VAR_0->exception_index);

        return; 

    }

    

    if (VAR_0->cp15.c1_sys & (1 << 13)) {

        addr += 0xffff0000;

    }

    switch_mode (VAR_0, VAR_1);

    VAR_0->spsr = cpsr_read(VAR_0);

    

    VAR_0->condexec_bits = 0;

    

    VAR_0->uncached_cpsr = (VAR_0->uncached_cpsr & ~CPSR_M) | VAR_1;

    VAR_0->uncached_cpsr |= mask;

    



    if (arm_feature(VAR_0, ARM_FEATURE_V4T)) {

        VAR_0->thumb = (VAR_0->cp15.c1_sys & (1 << 30)) != 0;

    }

    VAR_0->regs[14] = VAR_0->regs[15] + offset;

    VAR_0->regs[15] = addr;

    VAR_0->interrupt_request |= CPU_INTERRUPT_EXITTB;

}

void FUNC_0(CPUARMState *VAR_0)
{ uint32_t addr; uint32_t mask; int VAR_1; uint32_t offset; if (IS_M(VAR_0)) { do_interrupt_v7m(VAR_0); return; } switch (VAR_0->exception_index) { case EXCP_UDEF:
VAR_1 = ARM_CPU_MODE_UND; addr = 0x04; mask = CPSR_I; if (VAR_0->thumb)
offset = 2; else
offset = 4; break; case EXCP_SWI:
if (semihosting_enabled) { if (VAR_0->thumb) { mask = lduw_code(VAR_0->regs[15] - 2) & 0xff; } else { mask = ldl_code(VAR_0->regs[15] - 4) & 0xffffff; } if (((mask == 0x123456 && !VAR_0->thumb)
|| (mask == 0xab && VAR_0->thumb))
&& (VAR_0->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { VAR_0->regs[0] = do_arm_semihosting(VAR_0); return; } } VAR_1 = ARM_CPU_MODE_SVC; addr = 0x08; mask = CPSR_I; offset = 0; break; case EXCP_BKPT:
if (VAR_0->thumb && semihosting_enabled) { mask = lduw_code(VAR_0->regs[15]) & 0xff; if (mask == 0xab
&& (VAR_0->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { VAR_0->regs[15] += 2; VAR_0->regs[0] = do_arm_semihosting(VAR_0); return; } } VAR_0->cp15.c5_insn = 2; case EXCP_PREFETCH_ABORT:
VAR_1 = ARM_CPU_MODE_ABT; addr = 0x0c; mask = CPSR_A | CPSR_I; offset = 4; break; case EXCP_DATA_ABORT:
VAR_1 = ARM_CPU_MODE_ABT; addr = 0x10; mask = CPSR_A | CPSR_I; offset = 8; break; case EXCP_IRQ:
VAR_1 = ARM_CPU_MODE_IRQ; addr = 0x18; mask = CPSR_A | CPSR_I; offset = 4; break; case EXCP_FIQ:
VAR_1 = ARM_CPU_MODE_FIQ; addr = 0x1c; mask = CPSR_A | CPSR_I | CPSR_F; offset = 4; break; default:
cpu_abort(VAR_0, "Unhandled exception 0x%x\n", VAR_0->exception_index); return; } if (VAR_0->cp15.c1_sys & (1 << 13)) { addr += 0xffff0000; } switch_mode (VAR_0, VAR_1); VAR_0->spsr = cpsr_read(VAR_0); VAR_0->condexec_bits = 0; VAR_0->uncached_cpsr = (VAR_0->uncached_cpsr & ~CPSR_M) | VAR_1; VAR_0->uncached_cpsr |= mask; if (arm_feature(VAR_0, ARM_FEATURE_V4T)) { VAR_0->thumb = (VAR_0->cp15.c1_sys & (1 << 30)) != 0; } VAR_0->regs[14] = VAR_0->regs[15] + offset; VAR_0->regs[15] = addr; VAR_0->interrupt_request |= CPU_INTERRUPT_EXITTB; }