static void omap_pwl_write(void *opaque, target_phys_addr_t addr,

                           uint64_t value, unsigned size)

{

    struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;



    if (size != 1) {

        return omap_badwidth_write8(opaque, addr, value);

    }



    switch (offset) {

    case 0x00:	/* PWL_LEVEL */

        s->level = value;

        omap_pwl_update(s);

        break;

    case 0x04:	/* PWL_CTRL */

        s->enable = value & 1;

        omap_pwl_update(s);

        break;

    default:

        OMAP_BAD_REG(addr);

        return;

    }

}

static void omap_pwl_write(void *opaque, target_phys_addr_t addr,

                           uint64_t value, unsigned size)

{

    struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;



    if (size != 1) {

        return omap_badwidth_write8(opaque, addr, value);

    }



    switch (offset) {

    case 0x00:	

        s->level = value;

        omap_pwl_update(s);

        break;

    case 0x04:	

        s->enable = value & 1;

        omap_pwl_update(s);

        break;

    default:

        OMAP_BAD_REG(addr);

        return;

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                           uint64_t VAR_2, unsigned VAR_3)

{

    struct omap_pwl_s *VAR_4 = (struct omap_pwl_s *) VAR_0;

    int VAR_5 = VAR_1 & OMAP_MPUI_REG_MASK;



    if (VAR_3 != 1) {

        return omap_badwidth_write8(VAR_0, VAR_1, VAR_2);

    }



    switch (VAR_5) {

    case 0x00:	

        VAR_4->level = VAR_2;

        omap_pwl_update(VAR_4);

        break;

    case 0x04:	

        VAR_4->enable = VAR_2 & 1;

        omap_pwl_update(VAR_4);

        break;

    default:

        OMAP_BAD_REG(VAR_1);

        return;

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ struct omap_pwl_s *VAR_4 = (struct omap_pwl_s *) VAR_0; int VAR_5 = VAR_1 & OMAP_MPUI_REG_MASK; if (VAR_3 != 1) { return omap_badwidth_write8(VAR_0, VAR_1, VAR_2); } switch (VAR_5) { case 0x00:
VAR_4->level = VAR_2; omap_pwl_update(VAR_4); break; case 0x04:
VAR_4->enable = VAR_2 & 1; omap_pwl_update(VAR_4); break; default:
OMAP_BAD_REG(VAR_1); return; } }