static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
                            uint64_t val, unsigned size)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    int vector = offset / PCI_MSIX_ENTRY_SIZE;
    pci_set_long(dev->msix_table_page + offset, val);
    msix_handle_mask_update(dev, vector);
static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
                            uint64_t val, unsigned size)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    int vector = offset / PCI_MSIX_ENTRY_SIZE;
    pci_set_long(dev->msix_table_page + offset, val);
    msix_handle_mask_update(dev, vector);
static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
                            uint64_t VAR_2, unsigned VAR_3)
{
    PCIDevice *dev = VAR_0;
    unsigned int VAR_4 = VAR_1 & (MSIX_PAGE_SIZE - 1) & ~0x3;
    int VAR_5 = VAR_4 / PCI_MSIX_ENTRY_SIZE;
    pci_set_long(dev->msix_table_page + VAR_4, VAR_2);
    msix_handle_mask_update(dev, VAR_5);
static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ PCIDevice *dev = VAR_0; unsigned int VAR_4 = VAR_1 & (MSIX_PAGE_SIZE - 1) & ~0x3; int VAR_5 = VAR_4 / PCI_MSIX_ENTRY_SIZE; pci_set_long(dev->msix_table_page + VAR_4, VAR_2); msix_handle_mask_update(dev, VAR_5);