static void pl011_write(void *opaque, hwaddr offset,

                        uint64_t value, unsigned size)

{

    PL011State *s = (PL011State *)opaque;

    unsigned char ch;



    switch (offset >> 2) {

    case 0: /* UARTDR */

        /* ??? Check if transmitter is enabled.  */

        ch = value;

        if (s->chr)

            qemu_chr_fe_write(s->chr, &ch, 1);

        s->int_level |= PL011_INT_TX;

        pl011_update(s);

        break;

    case 1: /* UARTCR */

        s->cr = value;

        break;

    case 6: /* UARTFR */

        /* Writes to Flag register are ignored.  */

        break;

    case 8: /* UARTUARTILPR */

        s->ilpr = value;

        break;

    case 9: /* UARTIBRD */

        s->ibrd = value;

        break;

    case 10: /* UARTFBRD */

        s->fbrd = value;

        break;

    case 11: /* UARTLCR_H */

        /* Reset the FIFO state on FIFO enable or disable */

        if ((s->lcr ^ value) & 0x10) {

            s->read_count = 0;

            s->read_pos = 0;

        }

        s->lcr = value;

        pl011_set_read_trigger(s);

        break;

    case 12: /* UARTCR */

        /* ??? Need to implement the enable and loopback bits.  */

        s->cr = value;

        break;

    case 13: /* UARTIFS */

        s->ifl = value;

        pl011_set_read_trigger(s);

        break;

    case 14: /* UARTIMSC */

        s->int_enabled = value;

        pl011_update(s);

        break;

    case 17: /* UARTICR */

        s->int_level &= ~value;

        pl011_update(s);

        break;

    case 18: /* UARTDMACR */

        s->dmacr = value;

        if (value & 3) {

            qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n");

        }

        break;

    default:

        qemu_log_mask(LOG_GUEST_ERROR,

                      "pl011_write: Bad offset %x\n", (int)offset);

    }

}

static void pl011_write(void *opaque, hwaddr offset,

                        uint64_t value, unsigned size)

{

    PL011State *s = (PL011State *)opaque;

    unsigned char ch;



    switch (offset >> 2) {

    case 0: 

        

        ch = value;

        if (s->chr)

            qemu_chr_fe_write(s->chr, &ch, 1);

        s->int_level |= PL011_INT_TX;

        pl011_update(s);

        break;

    case 1: 

        s->cr = value;

        break;

    case 6: 

        

        break;

    case 8: 

        s->ilpr = value;

        break;

    case 9: 

        s->ibrd = value;

        break;

    case 10: 

        s->fbrd = value;

        break;

    case 11: 

        

        if ((s->lcr ^ value) & 0x10) {

            s->read_count = 0;

            s->read_pos = 0;

        }

        s->lcr = value;

        pl011_set_read_trigger(s);

        break;

    case 12: 

        

        s->cr = value;

        break;

    case 13: 

        s->ifl = value;

        pl011_set_read_trigger(s);

        break;

    case 14: 

        s->int_enabled = value;

        pl011_update(s);

        break;

    case 17: 

        s->int_level &= ~value;

        pl011_update(s);

        break;

    case 18: 

        s->dmacr = value;

        if (value & 3) {

            qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n");

        }

        break;

    default:

        qemu_log_mask(LOG_GUEST_ERROR,

                      "pl011_write: Bad offset %x\n", (int)offset);

    }

}

        s->cr = value;
static void FUNC_0(void *VAR_0, hwaddr VAR_1,

                        uint64_t VAR_2, unsigned VAR_3)

{

    PL011State *s = (PL011State *)VAR_0;

    unsigned char VAR_4;



    switch (VAR_1 >> 2) {

    case 0: 

        

        VAR_4 = VAR_2;

        if (s->chr)

            qemu_chr_fe_write(s->chr, &VAR_4, 1);

        s->int_level |= PL011_INT_TX;

        pl011_update(s);

        break;

    case 1: 

        s->cr = VAR_2;

        break;

    case 6: 

        

        break;

    case 8: 

        s->ilpr = VAR_2;

        break;

    case 9: 

        s->ibrd = VAR_2;

        break;

    case 10: 

        s->fbrd = VAR_2;

        break;

    case 11: 

        

        if ((s->lcr ^ VAR_2) & 0x10) {

            s->read_count = 0;

            s->read_pos = 0;

        }

        s->lcr = VAR_2;

        pl011_set_read_trigger(s);

        break;

    case 12: 

        

        s->cr = VAR_2;

        break;

    case 13: 

        s->ifl = VAR_2;

        pl011_set_read_trigger(s);

        break;

    case 14: 

        s->int_enabled = VAR_2;

        pl011_update(s);

        break;

    case 17: 

        s->int_level &= ~VAR_2;

        pl011_update(s);

        break;

    case 18: 

        s->dmacr = VAR_2;

        if (VAR_2 & 3) {

            qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n");

        }

        break;

    default:

        qemu_log_mask(LOG_GUEST_ERROR,

                      "FUNC_0: Bad VAR_1 %x\n", (int)VAR_1);

    }

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ PL011State *s = (PL011State *)VAR_0; unsigned char VAR_4; switch (VAR_1 >> 2) { case 0:
VAR_4 = VAR_2; if (s->chr)
qemu_chr_fe_write(s->chr, &VAR_4, 1); s->int_level |= PL011_INT_TX; pl011_update(s); break; case 1:
s->cr = VAR_2; break; case 6:
break; case 8:
s->ilpr = VAR_2; break; case 9:
s->ibrd = VAR_2; break; case 10:
s->fbrd = VAR_2; break; case 11:
if ((s->lcr ^ VAR_2) & 0x10) { s->read_count = 0; s->read_pos = 0; } s->lcr = VAR_2; pl011_set_read_trigger(s); break; case 12:
s->cr = VAR_2; break; case 13:
s->ifl = VAR_2; pl011_set_read_trigger(s); break; case 14:
s->int_enabled = VAR_2; pl011_update(s); break; case 17:
s->int_level &= ~VAR_2; pl011_update(s); break; case 18:
s->dmacr = VAR_2; if (VAR_2 & 3) { qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n"); } break; default:
qemu_log_mask(LOG_GUEST_ERROR,
"FUNC_0: Bad VAR_1 %x\n", (int)VAR_1); } }