e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size)

{

    E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;

    struct e1000_rx_desc desc;

    dma_addr_t base;

    unsigned int n, rdt;

    uint32_t rdh_start;

    uint16_t vlan_special = 0;

    uint8_t vlan_status = 0, vlan_offset = 0;

    uint8_t min_buf[MIN_BUF_SIZE];

    size_t desc_offset;

    size_t desc_size;

    size_t total_size;



    if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))

        return -1;



    /* Pad to minimum Ethernet frame length */

    if (size < sizeof(min_buf)) {

        memcpy(min_buf, buf, size);

        memset(&min_buf[size], 0, sizeof(min_buf) - size);

        buf = min_buf;

        size = sizeof(min_buf);

    }



    if (!receive_filter(s, buf, size))

        return size;



    if (vlan_enabled(s) && is_vlan_packet(s, buf)) {

        vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));

        memmove((uint8_t *)buf + 4, buf, 12);

        vlan_status = E1000_RXD_STAT_VP;

        vlan_offset = 4;

        size -= 4;

    }



    rdh_start = s->mac_reg[RDH];

    desc_offset = 0;

    total_size = size + fcs_len(s);

    if (!e1000_has_rxbufs(s, total_size)) {

            set_ics(s, 0, E1000_ICS_RXO);

            return -1;

    }

    do {

        desc_size = total_size - desc_offset;

        if (desc_size > s->rxbuf_size) {

            desc_size = s->rxbuf_size;

        }

        base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];

        pci_dma_read(&s->dev, base, &desc, sizeof(desc));

        desc.special = vlan_special;

        desc.status |= (vlan_status | E1000_RXD_STAT_DD);

        if (desc.buffer_addr) {

            if (desc_offset < size) {

                size_t copy_size = size - desc_offset;

                if (copy_size > s->rxbuf_size) {

                    copy_size = s->rxbuf_size;

                }

                pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr),

                              buf + desc_offset + vlan_offset, copy_size);

            }

            desc_offset += desc_size;

            desc.length = cpu_to_le16(desc_size);

            if (desc_offset >= total_size) {

                desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;

            } else {

                /* Guest zeroing out status is not a hardware requirement.

                   Clear EOP in case guest didn't do it. */

                desc.status &= ~E1000_RXD_STAT_EOP;

            }

        } else { // as per intel docs; skip descriptors with null buf addr

            DBGOUT(RX, "Null RX descriptor!!\n");

        }

        pci_dma_write(&s->dev, base, &desc, sizeof(desc));



        if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])

            s->mac_reg[RDH] = 0;

        s->check_rxov = 1;

        /* see comment in start_xmit; same here */

        if (s->mac_reg[RDH] == rdh_start) {

            DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",

                   rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);

            set_ics(s, 0, E1000_ICS_RXO);

            return -1;

        }

    } while (desc_offset < total_size);



    s->mac_reg[GPRC]++;

    s->mac_reg[TPR]++;

    /* TOR - Total Octets Received:

     * This register includes bytes received in a packet from the <Destination

     * Address> field through the <CRC> field, inclusively.

     */

    n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;

    if (n < s->mac_reg[TORL])

        s->mac_reg[TORH]++;

    s->mac_reg[TORL] = n;



    n = E1000_ICS_RXT0;

    if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])

        rdt += s->mac_reg[RDLEN] / sizeof(desc);

    if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>

        s->rxbuf_min_shift)

        n |= E1000_ICS_RXDMT0;



    set_ics(s, 0, n);



    return size;

}

e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size)

{

    E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;

    struct e1000_rx_desc desc;

    dma_addr_t base;

    unsigned int n, rdt;

    uint32_t rdh_start;

    uint16_t vlan_special = 0;

    uint8_t vlan_status = 0, vlan_offset = 0;

    uint8_t min_buf[MIN_BUF_SIZE];

    size_t desc_offset;

    size_t desc_size;

    size_t total_size;



    if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))

        return -1;



    

    if (size < sizeof(min_buf)) {

        memcpy(min_buf, buf, size);

        memset(&min_buf[size], 0, sizeof(min_buf) - size);

        buf = min_buf;

        size = sizeof(min_buf);

    }



    if (!receive_filter(s, buf, size))

        return size;



    if (vlan_enabled(s) && is_vlan_packet(s, buf)) {

        vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));

        memmove((uint8_t *)buf + 4, buf, 12);

        vlan_status = E1000_RXD_STAT_VP;

        vlan_offset = 4;

        size -= 4;

    }



    rdh_start = s->mac_reg[RDH];

    desc_offset = 0;

    total_size = size + fcs_len(s);

    if (!e1000_has_rxbufs(s, total_size)) {

            set_ics(s, 0, E1000_ICS_RXO);

            return -1;

    }

    do {

        desc_size = total_size - desc_offset;

        if (desc_size > s->rxbuf_size) {

            desc_size = s->rxbuf_size;

        }

        base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];

        pci_dma_read(&s->dev, base, &desc, sizeof(desc));

        desc.special = vlan_special;

        desc.status |= (vlan_status | E1000_RXD_STAT_DD);

        if (desc.buffer_addr) {

            if (desc_offset < size) {

                size_t copy_size = size - desc_offset;

                if (copy_size > s->rxbuf_size) {

                    copy_size = s->rxbuf_size;

                }

                pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr),

                              buf + desc_offset + vlan_offset, copy_size);

            }

            desc_offset += desc_size;

            desc.length = cpu_to_le16(desc_size);

            if (desc_offset >= total_size) {

                desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;

            } else {

                



                desc.status &= ~E1000_RXD_STAT_EOP;

            }

        } else { 

            DBGOUT(RX, "Null RX descriptor!!\n");

        }

        pci_dma_write(&s->dev, base, &desc, sizeof(desc));



        if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])

            s->mac_reg[RDH] = 0;

        s->check_rxov = 1;

        

        if (s->mac_reg[RDH] == rdh_start) {

            DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",

                   rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);

            set_ics(s, 0, E1000_ICS_RXO);

            return -1;

        }

    } while (desc_offset < total_size);



    s->mac_reg[GPRC]++;

    s->mac_reg[TPR]++;

    







    n = s->mac_reg[TORL] + size +  4;

    if (n < s->mac_reg[TORL])

        s->mac_reg[TORH]++;

    s->mac_reg[TORL] = n;



    n = E1000_ICS_RXT0;

    if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])

        rdt += s->mac_reg[RDLEN] / sizeof(desc);

    if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>

        s->rxbuf_min_shift)

        n |= E1000_ICS_RXDMT0;



    set_ics(s, 0, n);



    return size;

}

FUNC_0(NetClientState *VAR_0, const uint8_t *VAR_1, size_t VAR_2)

{

    E1000State *s = DO_UPCAST(NICState, VAR_0, VAR_0)->opaque;

    struct e1000_rx_desc VAR_3;

    dma_addr_t base;

    unsigned int VAR_4, VAR_5;

    uint32_t rdh_start;

    uint16_t vlan_special = 0;

    uint8_t vlan_status = 0, vlan_offset = 0;

    uint8_t min_buf[MIN_BUF_SIZE];

    size_t desc_offset;

    size_t desc_size;

    size_t total_size;



    if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))

        return -1;



    

    if (VAR_2 < sizeof(min_buf)) {

        memcpy(min_buf, VAR_1, VAR_2);

        memset(&min_buf[VAR_2], 0, sizeof(min_buf) - VAR_2);

        VAR_1 = min_buf;

        VAR_2 = sizeof(min_buf);

    }



    if (!receive_filter(s, VAR_1, VAR_2))

        return VAR_2;



    if (vlan_enabled(s) && is_vlan_packet(s, VAR_1)) {

        vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(VAR_1 + 14)));

        memmove((uint8_t *)VAR_1 + 4, VAR_1, 12);

        vlan_status = E1000_RXD_STAT_VP;

        vlan_offset = 4;

        VAR_2 -= 4;

    }



    rdh_start = s->mac_reg[RDH];

    desc_offset = 0;

    total_size = VAR_2 + fcs_len(s);

    if (!e1000_has_rxbufs(s, total_size)) {

            set_ics(s, 0, E1000_ICS_RXO);

            return -1;

    }

    do {

        desc_size = total_size - desc_offset;

        if (desc_size > s->rxbuf_size) {

            desc_size = s->rxbuf_size;

        }

        base = rx_desc_base(s) + sizeof(VAR_3) * s->mac_reg[RDH];

        pci_dma_read(&s->dev, base, &VAR_3, sizeof(VAR_3));

        VAR_3.special = vlan_special;

        VAR_3.status |= (vlan_status | E1000_RXD_STAT_DD);

        if (VAR_3.buffer_addr) {

            if (desc_offset < VAR_2) {

                size_t copy_size = VAR_2 - desc_offset;

                if (copy_size > s->rxbuf_size) {

                    copy_size = s->rxbuf_size;

                }

                pci_dma_write(&s->dev, le64_to_cpu(VAR_3.buffer_addr),

                              VAR_1 + desc_offset + vlan_offset, copy_size);

            }

            desc_offset += desc_size;

            VAR_3.length = cpu_to_le16(desc_size);

            if (desc_offset >= total_size) {

                VAR_3.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;

            } else {

                



                VAR_3.status &= ~E1000_RXD_STAT_EOP;

            }

        } else { 

            DBGOUT(RX, "Null RX descriptor!!\VAR_4");

        }

        pci_dma_write(&s->dev, base, &VAR_3, sizeof(VAR_3));



        if (++s->mac_reg[RDH] * sizeof(VAR_3) >= s->mac_reg[RDLEN])

            s->mac_reg[RDH] = 0;

        s->check_rxov = 1;

        

        if (s->mac_reg[RDH] == rdh_start) {

            DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\VAR_4",

                   rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);

            set_ics(s, 0, E1000_ICS_RXO);

            return -1;

        }

    } while (desc_offset < total_size);



    s->mac_reg[GPRC]++;

    s->mac_reg[TPR]++;

    







    VAR_4 = s->mac_reg[TORL] + VAR_2 +  4;

    if (VAR_4 < s->mac_reg[TORL])

        s->mac_reg[TORH]++;

    s->mac_reg[TORL] = VAR_4;



    VAR_4 = E1000_ICS_RXT0;

    if ((VAR_5 = s->mac_reg[RDT]) < s->mac_reg[RDH])

        VAR_5 += s->mac_reg[RDLEN] / sizeof(VAR_3);

    if (((VAR_5 - s->mac_reg[RDH]) * sizeof(VAR_3)) <= s->mac_reg[RDLEN] >>

        s->rxbuf_min_shift)

        VAR_4 |= E1000_ICS_RXDMT0;



    set_ics(s, 0, VAR_4);



    return VAR_2;

}

FUNC_0(NetClientState *VAR_0, const uint8_t *VAR_1, size_t VAR_2)
{ E1000State *s = DO_UPCAST(NICState, VAR_0, VAR_0)->opaque; struct e1000_rx_desc VAR_3; dma_addr_t base; unsigned int VAR_4, VAR_5; uint32_t rdh_start; uint16_t vlan_special = 0; uint8_t vlan_status = 0, vlan_offset = 0; uint8_t min_buf[MIN_BUF_SIZE]; size_t desc_offset; size_t desc_size; size_t total_size; if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
return -1; if (VAR_2 < sizeof(min_buf)) { memcpy(min_buf, VAR_1, VAR_2); memset(&min_buf[VAR_2], 0, sizeof(min_buf) - VAR_2); VAR_1 = min_buf; VAR_2 = sizeof(min_buf); } if (!receive_filter(s, VAR_1, VAR_2))
return VAR_2; if (vlan_enabled(s) && is_vlan_packet(s, VAR_1)) { vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(VAR_1 + 14))); memmove((uint8_t *)VAR_1 + 4, VAR_1, 12); vlan_status = E1000_RXD_STAT_VP; vlan_offset = 4; VAR_2 -= 4; } rdh_start = s->mac_reg[RDH]; desc_offset = 0; total_size = VAR_2 + fcs_len(s); if (!e1000_has_rxbufs(s, total_size)) { set_ics(s, 0, E1000_ICS_RXO); return -1; } do { desc_size = total_size - desc_offset; if (desc_size > s->rxbuf_size) { desc_size = s->rxbuf_size; } base = rx_desc_base(s) + sizeof(VAR_3) * s->mac_reg[RDH]; pci_dma_read(&s->dev, base, &VAR_3, sizeof(VAR_3)); VAR_3.special = vlan_special; VAR_3.status |= (vlan_status | E1000_RXD_STAT_DD); if (VAR_3.buffer_addr) { if (desc_offset < VAR_2) { size_t copy_size = VAR_2 - desc_offset; if (copy_size > s->rxbuf_size) { copy_size = s->rxbuf_size; } pci_dma_write(&s->dev, le64_to_cpu(VAR_3.buffer_addr),
VAR_1 + desc_offset + vlan_offset, copy_size); } desc_offset += desc_size; VAR_3.length = cpu_to_le16(desc_size); if (desc_offset >= total_size) { VAR_3.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM; } else { VAR_3.status &= ~E1000_RXD_STAT_EOP; } } else { DBGOUT(RX, "Null RX descriptor!!\VAR_4"); } pci_dma_write(&s->dev, base, &VAR_3, sizeof(VAR_3)); if (++s->mac_reg[RDH] * sizeof(VAR_3) >= s->mac_reg[RDLEN])
s->mac_reg[RDH] = 0; s->check_rxov = 1; if (s->mac_reg[RDH] == rdh_start) { DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\VAR_4",
rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]); set_ics(s, 0, E1000_ICS_RXO); return -1; } } while (desc_offset < total_size); s->mac_reg[GPRC]++; s->mac_reg[TPR]++; VAR_4 = s->mac_reg[TORL] + VAR_2 +  4; if (VAR_4 < s->mac_reg[TORL])
s->mac_reg[TORH]++; s->mac_reg[TORL] = VAR_4; VAR_4 = E1000_ICS_RXT0; if ((VAR_5 = s->mac_reg[RDT]) < s->mac_reg[RDH])
VAR_5 += s->mac_reg[RDLEN] / sizeof(VAR_3); if (((VAR_5 - s->mac_reg[RDH]) * sizeof(VAR_3)) <= s->mac_reg[RDLEN] >>
s->rxbuf_min_shift)
VAR_4 |= E1000_ICS_RXDMT0; set_ics(s, 0, VAR_4); return VAR_2; }