static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,

                             int element, TCGMemOp memop)

{

    int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE);

    switch (memop) {

    case MO_8:

        tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);

        break;

    case MO_16:

        tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);

        break;

    case MO_32:

        tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);

        break;

    case MO_8|MO_SIGN:

        tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);

        break;

    case MO_16|MO_SIGN:

        tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);

        break;

    case MO_32|MO_SIGN:

        tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);

        break;

    case MO_64:

    case MO_64|MO_SIGN:

        tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);

        break;

    default:

        g_assert_not_reached();

    }

}

static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,

                             int element, TCGMemOp memop)

{

    int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE);

    switch (memop) {

    case MO_8:

        tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);

        break;

    case MO_16:

        tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);

        break;

    case MO_32:

        tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);

        break;

    case MO_8|MO_SIGN:

        tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);

        break;

    case MO_16|MO_SIGN:

        tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);

        break;

    case MO_32|MO_SIGN:

        tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);

        break;

    case MO_64:

    case MO_64|MO_SIGN:

        tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);

        break;

    default:

        g_assert_not_reached();

    }

}

static void FUNC_0(DisasContext *VAR_0, TCGv_i64 VAR_1, int VAR_2,

                             int VAR_3, TCGMemOp VAR_4)

{

    int VAR_5 = vec_reg_offset(VAR_2, VAR_3, VAR_4 & MO_SIZE);

    switch (VAR_4) {

    case MO_8:

        tcg_gen_ld8u_i64(VAR_1, cpu_env, VAR_5);

        break;

    case MO_16:

        tcg_gen_ld16u_i64(VAR_1, cpu_env, VAR_5);

        break;

    case MO_32:

        tcg_gen_ld32u_i64(VAR_1, cpu_env, VAR_5);

        break;

    case MO_8|MO_SIGN:

        tcg_gen_ld8s_i64(VAR_1, cpu_env, VAR_5);

        break;

    case MO_16|MO_SIGN:

        tcg_gen_ld16s_i64(VAR_1, cpu_env, VAR_5);

        break;

    case MO_32|MO_SIGN:

        tcg_gen_ld32s_i64(VAR_1, cpu_env, VAR_5);

        break;

    case MO_64:

    case MO_64|MO_SIGN:

        tcg_gen_ld_i64(VAR_1, cpu_env, VAR_5);

        break;

    default:

        g_assert_not_reached();

    }

}

static void FUNC_0(DisasContext *VAR_0, TCGv_i64 VAR_1, int VAR_2,
int VAR_3, TCGMemOp VAR_4)
{ int VAR_5 = vec_reg_offset(VAR_2, VAR_3, VAR_4 & MO_SIZE); switch (VAR_4) { case MO_8:
tcg_gen_ld8u_i64(VAR_1, cpu_env, VAR_5); break; case MO_16:
tcg_gen_ld16u_i64(VAR_1, cpu_env, VAR_5); break; case MO_32:
tcg_gen_ld32u_i64(VAR_1, cpu_env, VAR_5); break; case MO_8|MO_SIGN:
tcg_gen_ld8s_i64(VAR_1, cpu_env, VAR_5); break; case MO_16|MO_SIGN:
tcg_gen_ld16s_i64(VAR_1, cpu_env, VAR_5); break; case MO_32|MO_SIGN:
tcg_gen_ld32s_i64(VAR_1, cpu_env, VAR_5); break; case MO_64:
case MO_64|MO_SIGN:
tcg_gen_ld_i64(VAR_1, cpu_env, VAR_5); break; default:
g_assert_not_reached(); } }