static int get_mmu_address(CPUState * env, target_ulong * physical,

			   int *prot, target_ulong address,

			   int rw, int access_type)

{

    int use_asid, is_code, n;

    tlb_t *matching = NULL;



    use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;

    is_code = env->pc == address;	/* Hack */



    /* Use a hack to find if this is an instruction or data access */

    if (env->pc == address && !(rw & PAGE_WRITE)) {

	n = find_itlb_entry(env, address, use_asid, 1);

	if (n >= 0) {

	    matching = &env->itlb[n];

	    if ((env->sr & SR_MD) & !(matching->pr & 2))

		n = MMU_ITLB_VIOLATION;

	    else

		*prot = PAGE_READ;

	}

    } else {

	n = find_utlb_entry(env, address, use_asid);

	if (n >= 0) {

	    matching = &env->utlb[n];

	    switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {

	    case 0:		/* 000 */

	    case 2:		/* 010 */

		n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :

		    MMU_DTLB_VIOLATION_READ;

		break;

	    case 1:		/* 001 */

	    case 4:		/* 100 */

	    case 5:		/* 101 */

		if (rw & PAGE_WRITE)

		    n = MMU_DTLB_VIOLATION_WRITE;

		else

		    *prot = PAGE_READ;

		break;

	    case 3:		/* 011 */

	    case 6:		/* 110 */

	    case 7:		/* 111 */

		*prot = rw & (PAGE_READ | PAGE_WRITE);

		break;

	    }

	} else if (n == MMU_DTLB_MISS) {

	    n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :

		MMU_DTLB_MISS_READ;

	}

    }

    if (n >= 0) {

	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |

	    (address & (matching->size - 1));

	if ((rw & PAGE_WRITE) & !matching->d)

	    n = MMU_DTLB_INITIAL_WRITE;

	else

	    n = MMU_OK;

    }

    return n;

}

static int get_mmu_address(CPUState * env, target_ulong * physical,

			   int *prot, target_ulong address,

			   int rw, int access_type)

{

    int use_asid, is_code, n;

    tlb_t *matching = NULL;



    use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;

    is_code = env->pc == address;	



    

    if (env->pc == address && !(rw & PAGE_WRITE)) {

	n = find_itlb_entry(env, address, use_asid, 1);

	if (n >= 0) {

	    matching = &env->itlb[n];

	    if ((env->sr & SR_MD) & !(matching->pr & 2))

		n = MMU_ITLB_VIOLATION;

	    else

		*prot = PAGE_READ;

	}

    } else {

	n = find_utlb_entry(env, address, use_asid);

	if (n >= 0) {

	    matching = &env->utlb[n];

	    switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {

	    case 0:		

	    case 2:		

		n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :

		    MMU_DTLB_VIOLATION_READ;

		break;

	    case 1:		

	    case 4:		

	    case 5:		

		if (rw & PAGE_WRITE)

		    n = MMU_DTLB_VIOLATION_WRITE;

		else

		    *prot = PAGE_READ;

		break;

	    case 3:		

	    case 6:		

	    case 7:		

		*prot = rw & (PAGE_READ | PAGE_WRITE);

		break;

	    }

	} else if (n == MMU_DTLB_MISS) {

	    n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :

		MMU_DTLB_MISS_READ;

	}

    }

    if (n >= 0) {

	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |

	    (address & (matching->size - 1));

	if ((rw & PAGE_WRITE) & !matching->d)

	    n = MMU_DTLB_INITIAL_WRITE;

	else

	    n = MMU_OK;

    }

    return n;

}

    use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;
static int FUNC_0(CPUState * VAR_0, target_ulong * VAR_1,

			   int *VAR_2, target_ulong VAR_3,

			   int VAR_4, int VAR_5)

{

    int VAR_6, VAR_7, VAR_8;

    tlb_t *matching = NULL;



    VAR_6 = (VAR_0->mmucr & MMUCR_SV) == 0 && (VAR_0->sr & SR_MD) == 0;

    VAR_7 = VAR_0->pc == VAR_3;	



    

    if (VAR_0->pc == VAR_3 && !(VAR_4 & PAGE_WRITE)) {

	VAR_8 = find_itlb_entry(VAR_0, VAR_3, VAR_6, 1);

	if (VAR_8 >= 0) {

	    matching = &VAR_0->itlb[VAR_8];

	    if ((VAR_0->sr & SR_MD) & !(matching->pr & 2))

		VAR_8 = MMU_ITLB_VIOLATION;

	    else

		*VAR_2 = PAGE_READ;

	}

    } else {

	VAR_8 = find_utlb_entry(VAR_0, VAR_3, VAR_6);

	if (VAR_8 >= 0) {

	    matching = &VAR_0->utlb[VAR_8];

	    switch ((matching->pr << 1) | ((VAR_0->sr & SR_MD) ? 1 : 0)) {

	    case 0:		

	    case 2:		

		VAR_8 = (VAR_4 & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :

		    MMU_DTLB_VIOLATION_READ;

		break;

	    case 1:		

	    case 4:		

	    case 5:		

		if (VAR_4 & PAGE_WRITE)

		    VAR_8 = MMU_DTLB_VIOLATION_WRITE;

		else

		    *VAR_2 = PAGE_READ;

		break;

	    case 3:		

	    case 6:		

	    case 7:		

		*VAR_2 = VAR_4 & (PAGE_READ | PAGE_WRITE);

		break;

	    }

	} else if (VAR_8 == MMU_DTLB_MISS) {

	    VAR_8 = (VAR_4 & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :

		MMU_DTLB_MISS_READ;

	}

    }

    if (VAR_8 >= 0) {

	*VAR_1 = ((matching->ppn << 10) & ~(matching->size - 1)) |

	    (VAR_3 & (matching->size - 1));

	if ((VAR_4 & PAGE_WRITE) & !matching->d)

	    VAR_8 = MMU_DTLB_INITIAL_WRITE;

	else

	    VAR_8 = MMU_OK;

    }

    return VAR_8;

}

static int FUNC_0(CPUState * VAR_0, target_ulong * VAR_1,
int *VAR_2, target_ulong VAR_3,
int VAR_4, int VAR_5)
{ int VAR_6, VAR_7, VAR_8; tlb_t *matching = NULL; VAR_6 = (VAR_0->mmucr & MMUCR_SV) == 0 && (VAR_0->sr & SR_MD) == 0; VAR_7 = VAR_0->pc == VAR_3; if (VAR_0->pc == VAR_3 && !(VAR_4 & PAGE_WRITE)) { VAR_8 = find_itlb_entry(VAR_0, VAR_3, VAR_6, 1); if (VAR_8 >= 0) { matching = &VAR_0->itlb[VAR_8]; if ((VAR_0->sr & SR_MD) & !(matching->pr & 2))
VAR_8 = MMU_ITLB_VIOLATION; else
*VAR_2 = PAGE_READ; } } else { VAR_8 = find_utlb_entry(VAR_0, VAR_3, VAR_6); if (VAR_8 >= 0) { matching = &VAR_0->utlb[VAR_8]; switch ((matching->pr << 1) | ((VAR_0->sr & SR_MD) ? 1 : 0)) { case 0:
case 2:
VAR_8 = (VAR_4 & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :
MMU_DTLB_VIOLATION_READ; break; case 1:
case 4:
case 5:
if (VAR_4 & PAGE_WRITE)
VAR_8 = MMU_DTLB_VIOLATION_WRITE; else
*VAR_2 = PAGE_READ; break; case 3:
case 6:
case 7:
*VAR_2 = VAR_4 & (PAGE_READ | PAGE_WRITE); break; } } else if (VAR_8 == MMU_DTLB_MISS) { VAR_8 = (VAR_4 & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
MMU_DTLB_MISS_READ; } } if (VAR_8 >= 0) { *VAR_1 = ((matching->ppn << 10) & ~(matching->size - 1)) |
(VAR_3 & (matching->size - 1)); if ((VAR_4 & PAGE_WRITE) & !matching->d)
VAR_8 = MMU_DTLB_INITIAL_WRITE; else
VAR_8 = MMU_OK; } return VAR_8; }