xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,

                 hwaddr cfg_base, uint64_t cfg_size,

                 hwaddr mmio_base, uint64_t mmio_size,

                 qemu_irq irq, bool link_up)

{

    DeviceState *dev;

    MemoryRegion *cfg, *mmio;



    dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST);



    qdev_prop_set_uint32(dev, "bus_nr", bus_nr);

    qdev_prop_set_uint64(dev, "cfg_base", cfg_base);

    qdev_prop_set_uint64(dev, "cfg_size", cfg_size);

    qdev_prop_set_uint64(dev, "mmio_base", mmio_base);

    qdev_prop_set_uint64(dev, "mmio_size", mmio_size);

    qdev_prop_set_bit(dev, "link_up", link_up);



    qdev_init_nofail(dev);



    cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

    memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);



    mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);

    memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);



    qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);



    return XILINX_PCIE_HOST(dev);

}

xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,

                 hwaddr cfg_base, uint64_t cfg_size,

                 hwaddr mmio_base, uint64_t mmio_size,

                 qemu_irq irq, bool link_up)

{

    DeviceState *dev;

    MemoryRegion *cfg, *mmio;



    dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST);



    qdev_prop_set_uint32(dev, "bus_nr", bus_nr);

    qdev_prop_set_uint64(dev, "cfg_base", cfg_base);

    qdev_prop_set_uint64(dev, "cfg_size", cfg_size);

    qdev_prop_set_uint64(dev, "mmio_base", mmio_base);

    qdev_prop_set_uint64(dev, "mmio_size", mmio_size);

    qdev_prop_set_bit(dev, "link_up", link_up);



    qdev_init_nofail(dev);



    cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

    memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);



    mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);

    memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);



    qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);



    return XILINX_PCIE_HOST(dev);

}

xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,                  hwaddr cfg_base, uint64_t cfg_size,                  hwaddr mmio_base, uint64_t mmio_size,                  qemu_irq irq, bool link_up)     DeviceState *dev;     MemoryRegion *cfg, *mmio;     dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST);     qdev_prop_set_uint32(dev, "bus_nr", bus_nr);     qdev_prop_set_uint64(dev, "cfg_base", cfg_base);     qdev_prop_set_uint64(dev, "cfg_size", cfg_size);     qdev_prop_set_uint64(dev, "mmio_base", mmio_base);     qdev_prop_set_uint64(dev, "mmio_size", mmio_size);     qdev_prop_set_bit(dev, "link_up", link_up);     qdev_init_nofail(dev);     cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);     memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);     mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);     memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);     qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);     return XILINX_PCIE_HOST(dev);     DeviceState *dev;     qdev_init_nofail(dev);
FUNC_0(MemoryRegion *VAR_0, uint32_t VAR_1,

                 hwaddr VAR_2, uint64_t VAR_3,

                 hwaddr VAR_4, uint64_t VAR_5,

                 qemu_irq VAR_6, bool VAR_7)

{

    DeviceState *dev;

    MemoryRegion *cfg, *mmio;



    dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST);



    qdev_prop_set_uint32(dev, "VAR_1", VAR_1);

    qdev_prop_set_uint64(dev, "VAR_2", VAR_2);

    qdev_prop_set_uint64(dev, "VAR_3", VAR_3);

    qdev_prop_set_uint64(dev, "VAR_4", VAR_4);

    qdev_prop_set_uint64(dev, "VAR_5", VAR_5);

    qdev_prop_set_bit(dev, "VAR_7", VAR_7);



    qdev_init_nofail(dev);



    cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

    memory_region_add_subregion_overlap(VAR_0, VAR_2, cfg, 0);



    mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);

    memory_region_add_subregion_overlap(VAR_0, 0, mmio, 0);



    qdev_connect_gpio_out_named(dev, "interrupt_out", 0, VAR_6);



    return XILINX_PCIE_HOST(dev);

}

FUNC_0(MemoryRegion *VAR_0, uint32_t VAR_1,
hwaddr VAR_2, uint64_t VAR_3,
hwaddr VAR_4, uint64_t VAR_5,
qemu_irq VAR_6, bool VAR_7)
{ DeviceState *dev; MemoryRegion *cfg, *mmio; dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST); qdev_prop_set_uint32(dev, "VAR_1", VAR_1); qdev_prop_set_uint64(dev, "VAR_2", VAR_2); qdev_prop_set_uint64(dev, "VAR_3", VAR_3); qdev_prop_set_uint64(dev, "VAR_4", VAR_4); qdev_prop_set_uint64(dev, "VAR_5", VAR_5); qdev_prop_set_bit(dev, "VAR_7", VAR_7); qdev_init_nofail(dev); cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); memory_region_add_subregion_overlap(VAR_0, VAR_2, cfg, 0); mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); memory_region_add_subregion_overlap(VAR_0, 0, mmio, 0); qdev_connect_gpio_out_named(dev, "interrupt_out", 0, VAR_6); return XILINX_PCIE_HOST(dev); }