eth_write(void *opaque, target_phys_addr_t addr,

          uint64_t val64, unsigned int size)

{

	struct fs_eth *eth = opaque;

	uint32_t value = val64;



	addr >>= 2;

	switch (addr)

	{

		case RW_MA0_LO:

		case RW_MA0_HI:

			eth->regs[addr] = value;

			eth_update_ma(eth, 0);

			break;

		case RW_MA1_LO:

		case RW_MA1_HI:

			eth->regs[addr] = value;

			eth_update_ma(eth, 1);

			break;



		case RW_MGM_CTRL:

			/* Attach an MDIO/PHY abstraction.  */

			if (value & 2)

				eth->mdio_bus.mdio = value & 1;

			if (eth->mdio_bus.mdc != (value & 4)) {

				mdio_cycle(&eth->mdio_bus);

				eth_validate_duplex(eth);

			}

			eth->mdio_bus.mdc = !!(value & 4);

			eth->regs[addr] = value;

			break;



		case RW_REC_CTRL:

			eth->regs[addr] = value;

			eth_validate_duplex(eth);

			break;



		default:

			eth->regs[addr] = value;

			D(printf ("%s %x %x\n",

				  __func__, addr, value));

			break;

	}

}

eth_write(void *opaque, target_phys_addr_t addr,

          uint64_t val64, unsigned int size)

{

	struct fs_eth *eth = opaque;

	uint32_t value = val64;



	addr >>= 2;

	switch (addr)

	{

		case RW_MA0_LO:

		case RW_MA0_HI:

			eth->regs[addr] = value;

			eth_update_ma(eth, 0);

			break;

		case RW_MA1_LO:

		case RW_MA1_HI:

			eth->regs[addr] = value;

			eth_update_ma(eth, 1);

			break;



		case RW_MGM_CTRL:

			

			if (value & 2)

				eth->mdio_bus.mdio = value & 1;

			if (eth->mdio_bus.mdc != (value & 4)) {

				mdio_cycle(&eth->mdio_bus);

				eth_validate_duplex(eth);

			}

			eth->mdio_bus.mdc = !!(value & 4);

			eth->regs[addr] = value;

			break;



		case RW_REC_CTRL:

			eth->regs[addr] = value;

			eth_validate_duplex(eth);

			break;



		default:

			eth->regs[addr] = value;

			D(printf ("%s %x %x\n",

				  __func__, addr, value));

			break;

	}

}

FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

          uint64_t VAR_2, unsigned int VAR_3)

{

	struct fs_eth *VAR_4 = VAR_0;

	uint32_t value = VAR_2;



	VAR_1 >>= 2;

	switch (VAR_1)

	{

		case RW_MA0_LO:

		case RW_MA0_HI:

			VAR_4->regs[VAR_1] = value;

			eth_update_ma(VAR_4, 0);

			break;

		case RW_MA1_LO:

		case RW_MA1_HI:

			VAR_4->regs[VAR_1] = value;

			eth_update_ma(VAR_4, 1);

			break;



		case RW_MGM_CTRL:

			

			if (value & 2)

				VAR_4->mdio_bus.mdio = value & 1;

			if (VAR_4->mdio_bus.mdc != (value & 4)) {

				mdio_cycle(&VAR_4->mdio_bus);

				eth_validate_duplex(VAR_4);

			}

			VAR_4->mdio_bus.mdc = !!(value & 4);

			VAR_4->regs[VAR_1] = value;

			break;



		case RW_REC_CTRL:

			VAR_4->regs[VAR_1] = value;

			eth_validate_duplex(VAR_4);

			break;



		default:

			VAR_4->regs[VAR_1] = value;

			D(printf ("%s %x %x\n",

				  __func__, VAR_1, value));

			break;

	}

}

FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned int VAR_3)
{ struct fs_eth *VAR_4 = VAR_0; uint32_t value = VAR_2; VAR_1 >>= 2; switch (VAR_1)
{ case RW_MA0_LO:
case RW_MA0_HI:
VAR_4->regs[VAR_1] = value; eth_update_ma(VAR_4, 0); break; case RW_MA1_LO:
case RW_MA1_HI:
VAR_4->regs[VAR_1] = value; eth_update_ma(VAR_4, 1); break; case RW_MGM_CTRL:
if (value & 2)
VAR_4->mdio_bus.mdio = value & 1; if (VAR_4->mdio_bus.mdc != (value & 4)) { mdio_cycle(&VAR_4->mdio_bus); eth_validate_duplex(VAR_4); } VAR_4->mdio_bus.mdc = !!(value & 4); VAR_4->regs[VAR_1] = value; break; case RW_REC_CTRL:
VAR_4->regs[VAR_1] = value; eth_validate_duplex(VAR_4); break; default:
VAR_4->regs[VAR_1] = value; D(printf ("%s %x %x\n",
__func__, VAR_1, value)); break; } }