int spapr_h_cas_compose_response(sPAPRMachineState *spapr,

                                 target_ulong addr, target_ulong size,

                                 bool cpu_update)

{

    void *fdt, *fdt_skel;

    sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };

    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());



    size -= sizeof(hdr);



    /* Create sceleton */

    fdt_skel = g_malloc0(size);

    _FDT((fdt_create(fdt_skel, size)));

    _FDT((fdt_begin_node(fdt_skel, "")));

    _FDT((fdt_end_node(fdt_skel)));

    _FDT((fdt_finish(fdt_skel)));

    fdt = g_malloc0(size);

    _FDT((fdt_open_into(fdt_skel, fdt, size)));

    g_free(fdt_skel);



    /* Fixup cpu nodes */

    if (cpu_update) {

        _FDT((spapr_fixup_cpu_dt(fdt, spapr)));

    }



    /* Generate ibm,dynamic-reconfiguration-memory node if required */

    if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) {

        g_assert(smc->dr_lmb_enabled);

        _FDT((spapr_populate_drconf_memory(spapr, fdt)));

    }



    /* Pack resulting tree */

    _FDT((fdt_pack(fdt)));



    if (fdt_totalsize(fdt) + sizeof(hdr) > size) {

        trace_spapr_cas_failed(size);

        return -1;

    }



    cpu_physical_memory_write(addr, &hdr, sizeof(hdr));

    cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));

    trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));

    g_free(fdt);



    return 0;

}

int spapr_h_cas_compose_response(sPAPRMachineState *spapr,

                                 target_ulong addr, target_ulong size,

                                 bool cpu_update)

{

    void *fdt, *fdt_skel;

    sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };

    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());



    size -= sizeof(hdr);



    

    fdt_skel = g_malloc0(size);

    _FDT((fdt_create(fdt_skel, size)));

    _FDT((fdt_begin_node(fdt_skel, "")));

    _FDT((fdt_end_node(fdt_skel)));

    _FDT((fdt_finish(fdt_skel)));

    fdt = g_malloc0(size);

    _FDT((fdt_open_into(fdt_skel, fdt, size)));

    g_free(fdt_skel);



    

    if (cpu_update) {

        _FDT((spapr_fixup_cpu_dt(fdt, spapr)));

    }



    

    if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) {

        g_assert(smc->dr_lmb_enabled);

        _FDT((spapr_populate_drconf_memory(spapr, fdt)));

    }



    

    _FDT((fdt_pack(fdt)));



    if (fdt_totalsize(fdt) + sizeof(hdr) > size) {

        trace_spapr_cas_failed(size);

        return -1;

    }



    cpu_physical_memory_write(addr, &hdr, sizeof(hdr));

    cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));

    trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));

    g_free(fdt);



    return 0;

}

                                 bool cpu_update)     sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());     if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) {         g_assert(smc->dr_lmb_enabled);         _FDT((spapr_populate_drconf_memory(spapr, fdt)));
int FUNC_0(sPAPRMachineState *VAR_0,

                                 target_ulong VAR_1, target_ulong VAR_2,

                                 bool VAR_3)

{

    void *VAR_4, *VAR_5;

    sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };

    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());



    VAR_2 -= sizeof(hdr);



    

    VAR_5 = g_malloc0(VAR_2);

    _FDT((fdt_create(VAR_5, VAR_2)));

    _FDT((fdt_begin_node(VAR_5, "")));

    _FDT((fdt_end_node(VAR_5)));

    _FDT((fdt_finish(VAR_5)));

    VAR_4 = g_malloc0(VAR_2);

    _FDT((fdt_open_into(VAR_5, VAR_4, VAR_2)));

    g_free(VAR_5);



    

    if (VAR_3) {

        _FDT((spapr_fixup_cpu_dt(VAR_4, VAR_0)));

    }



    

    if (spapr_ovec_test(VAR_0->ov5_cas, OV5_DRCONF_MEMORY)) {

        g_assert(smc->dr_lmb_enabled);

        _FDT((spapr_populate_drconf_memory(VAR_0, VAR_4)));

    }



    

    _FDT((fdt_pack(VAR_4)));



    if (fdt_totalsize(VAR_4) + sizeof(hdr) > VAR_2) {

        trace_spapr_cas_failed(VAR_2);

        return -1;

    }



    cpu_physical_memory_write(VAR_1, &hdr, sizeof(hdr));

    cpu_physical_memory_write(VAR_1 + sizeof(hdr), VAR_4, fdt_totalsize(VAR_4));

    trace_spapr_cas_continue(fdt_totalsize(VAR_4) + sizeof(hdr));

    g_free(VAR_4);



    return 0;

}

int FUNC_0(sPAPRMachineState *VAR_0,
target_ulong VAR_1, target_ulong VAR_2,
bool VAR_3)
{ void *VAR_4, *VAR_5; sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); VAR_2 -= sizeof(hdr); VAR_5 = g_malloc0(VAR_2); _FDT((fdt_create(VAR_5, VAR_2))); _FDT((fdt_begin_node(VAR_5, ""))); _FDT((fdt_end_node(VAR_5))); _FDT((fdt_finish(VAR_5))); VAR_4 = g_malloc0(VAR_2); _FDT((fdt_open_into(VAR_5, VAR_4, VAR_2))); g_free(VAR_5); if (VAR_3) { _FDT((spapr_fixup_cpu_dt(VAR_4, VAR_0))); } if (spapr_ovec_test(VAR_0->ov5_cas, OV5_DRCONF_MEMORY)) { g_assert(smc->dr_lmb_enabled); _FDT((spapr_populate_drconf_memory(VAR_0, VAR_4))); } _FDT((fdt_pack(VAR_4))); if (fdt_totalsize(VAR_4) + sizeof(hdr) > VAR_2) { trace_spapr_cas_failed(VAR_2); return -1; } cpu_physical_memory_write(VAR_1, &hdr, sizeof(hdr)); cpu_physical_memory_write(VAR_1 + sizeof(hdr), VAR_4, fdt_totalsize(VAR_4)); trace_spapr_cas_continue(fdt_totalsize(VAR_4) + sizeof(hdr)); g_free(VAR_4); return 0; }