static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,

                                 uint64_t asc, uint64_t st_entry,

                                 target_ulong *raddr, int *flags, int rw)

{

    CPUState *cs = CPU(s390_env_get_cpu(env));

    uint64_t origin, offs, pt_entry;



    if (st_entry & _SEGMENT_ENTRY_RO) {

        *flags &= ~PAGE_WRITE;

    }



    if ((st_entry & _SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {

        /* Decode EDAT1 segment frame absolute address (1MB page) */

        *raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff);

        PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry);

        return 0;

    }



    /* Look up 4KB page entry */

    origin = st_entry & _SEGMENT_ENTRY_ORIGIN;

    offs  = (vaddr & VADDR_PX) >> 9;

    pt_entry = ldq_phys(cs->as, origin + offs);

    PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",

                __func__, origin, offs, pt_entry);

    return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw);

}

static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,

                                 uint64_t asc, uint64_t st_entry,

                                 target_ulong *raddr, int *flags, int rw)

{

    CPUState *cs = CPU(s390_env_get_cpu(env));

    uint64_t origin, offs, pt_entry;



    if (st_entry & _SEGMENT_ENTRY_RO) {

        *flags &= ~PAGE_WRITE;

    }



    if ((st_entry & _SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {

        

        *raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff);

        PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry);

        return 0;

    }



    

    origin = st_entry & _SEGMENT_ENTRY_ORIGIN;

    offs  = (vaddr & VADDR_PX) >> 9;

    pt_entry = ldq_phys(cs->as, origin + offs);

    PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",

                __func__, origin, offs, pt_entry);

    return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw);

}

static int FUNC_0(CPUS390XState *VAR_0, target_ulong VAR_1,

                                 uint64_t VAR_2, uint64_t VAR_3,

                                 target_ulong *VAR_4, int *VAR_5, int VAR_6)

{

    CPUState *cs = CPU(s390_env_get_cpu(VAR_0));

    uint64_t origin, offs, pt_entry;



    if (VAR_3 & _SEGMENT_ENTRY_RO) {

        *VAR_5 &= ~PAGE_WRITE;

    }



    if ((VAR_3 & _SEGMENT_ENTRY_FC) && (VAR_0->cregs[0] & CR0_EDAT)) {

        

        *VAR_4 = (VAR_3 & 0xfffffffffff00000ULL) | (VAR_1 & 0xfffff);

        PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, VAR_3);

        return 0;

    }



    

    origin = VAR_3 & _SEGMENT_ENTRY_ORIGIN;

    offs  = (VAR_1 & VADDR_PX) >> 9;

    pt_entry = ldq_phys(cs->as, origin + offs);

    PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",

                __func__, origin, offs, pt_entry);

    return mmu_translate_pte(VAR_0, VAR_1, VAR_2, pt_entry, VAR_4, VAR_5, VAR_6);

}

static int FUNC_0(CPUS390XState *VAR_0, target_ulong VAR_1,
uint64_t VAR_2, uint64_t VAR_3,
target_ulong *VAR_4, int *VAR_5, int VAR_6)
{ CPUState *cs = CPU(s390_env_get_cpu(VAR_0)); uint64_t origin, offs, pt_entry; if (VAR_3 & _SEGMENT_ENTRY_RO) { *VAR_5 &= ~PAGE_WRITE; } if ((VAR_3 & _SEGMENT_ENTRY_FC) && (VAR_0->cregs[0] & CR0_EDAT)) { *VAR_4 = (VAR_3 & 0xfffffffffff00000ULL) | (VAR_1 & 0xfffff); PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, VAR_3); return 0; } origin = VAR_3 & _SEGMENT_ENTRY_ORIGIN; offs  = (VAR_1 & VADDR_PX) >> 9; pt_entry = ldq_phys(cs->as, origin + offs); PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
__func__, origin, offs, pt_entry); return mmu_translate_pte(VAR_0, VAR_1, VAR_2, pt_entry, VAR_4, VAR_5, VAR_6); }