DISAS_INSN(shift_im)

{

    TCGv reg;

    int tmp;

    TCGv shift;



    set_cc_op(s, CC_OP_FLAGS);



    reg = DREG(insn, 0);

    tmp = (insn >> 9) & 7;

    if (tmp == 0)

        tmp = 8;

    shift = tcg_const_i32(tmp);

    /* No need to flush flags becuse we know we will set C flag.  */

    if (insn & 0x100) {

        gen_helper_shl_cc(reg, cpu_env, reg, shift);

    } else {

        if (insn & 8) {

            gen_helper_shr_cc(reg, cpu_env, reg, shift);

        } else {

            gen_helper_sar_cc(reg, cpu_env, reg, shift);

        }

    }

}

DISAS_INSN(shift_im)

{

    TCGv reg;

    int tmp;

    TCGv shift;



    set_cc_op(s, CC_OP_FLAGS);



    reg = DREG(insn, 0);

    tmp = (insn >> 9) & 7;

    if (tmp == 0)

        tmp = 8;

    shift = tcg_const_i32(tmp);

    

    if (insn & 0x100) {

        gen_helper_shl_cc(reg, cpu_env, reg, shift);

    } else {

        if (insn & 8) {

            gen_helper_shr_cc(reg, cpu_env, reg, shift);

        } else {

            gen_helper_sar_cc(reg, cpu_env, reg, shift);

        }

    }

}

DISAS_INSN(shift_im)     TCGv reg;     int tmp;     TCGv shift;     reg = DREG(insn, 0);     tmp = (insn >> 9) & 7;     if (tmp == 0)         tmp = 8;     shift = tcg_const_i32(tmp);     if (insn & 0x100) {         gen_helper_shl_cc(reg, cpu_env, reg, shift);         if (insn & 8) {             gen_helper_shr_cc(reg, cpu_env, reg, shift);             gen_helper_sar_cc(reg, cpu_env, reg, shift);     TCGv reg;     TCGv shift;     reg = DREG(insn, 0);     if (insn & 0x100) {         gen_helper_shl_cc(reg, cpu_env, reg, shift);         if (insn & 8) {             gen_helper_shr_cc(reg, cpu_env, reg, shift);             gen_helper_sar_cc(reg, cpu_env, reg, shift);
FUNC_0(VAR_0)

{

    TCGv reg;

    int VAR_1;

    TCGv shift;



    set_cc_op(s, CC_OP_FLAGS);



    reg = DREG(insn, 0);

    VAR_1 = (insn >> 9) & 7;

    if (VAR_1 == 0)

        VAR_1 = 8;

    shift = tcg_const_i32(VAR_1);

    

    if (insn & 0x100) {

        gen_helper_shl_cc(reg, cpu_env, reg, shift);

    } else {

        if (insn & 8) {

            gen_helper_shr_cc(reg, cpu_env, reg, shift);

        } else {

            gen_helper_sar_cc(reg, cpu_env, reg, shift);

        }

    }

}

FUNC_0(VAR_0)
{ TCGv reg; int VAR_1; TCGv shift; set_cc_op(s, CC_OP_FLAGS); reg = DREG(insn, 0); VAR_1 = (insn >> 9) & 7; if (VAR_1 == 0)
VAR_1 = 8; shift = tcg_const_i32(VAR_1); if (insn & 0x100) { gen_helper_shl_cc(reg, cpu_env, reg, shift); } else { if (insn & 8) { gen_helper_shr_cc(reg, cpu_env, reg, shift); } else { gen_helper_sar_cc(reg, cpu_env, reg, shift); } } }