static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,

                           Error **errp)

{

    CPUPPCState *env = &cpu->env;

    CPUState *cs = CPU(cpu);

    int i;



    /* Set time-base frequency to 512 MHz */

    cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);



    /* Enable PAPR mode in TCG or KVM */


    cpu_ppc_set_papr(cpu);



    if (cpu->max_compat) {

        Error *local_err = NULL;



        ppc_set_compat(cpu, cpu->max_compat, &local_err);

        if (local_err) {

            error_propagate(errp, local_err);

            return;

        }

    }



    /* Set NUMA node for the added CPUs  */

    i = numa_get_node_for_cpu(cs->cpu_index);

    if (i < nb_numa_nodes) {

            cs->numa_node = i;

    }



    xics_cpu_setup(spapr->xics, cpu);



    qemu_register_reset(spapr_cpu_reset, cpu);

    spapr_cpu_reset(cpu);

}
static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,

                           Error **errp)

{

    CPUPPCState *env = &cpu->env;

    CPUState *cs = CPU(cpu);

    int i;



    

    cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);



    


    cpu_ppc_set_papr(cpu);



    if (cpu->max_compat) {

        Error *local_err = NULL;



        ppc_set_compat(cpu, cpu->max_compat, &local_err);

        if (local_err) {

            error_propagate(errp, local_err);

            return;

        }

    }



    

    i = numa_get_node_for_cpu(cs->cpu_index);

    if (i < nb_numa_nodes) {

            cs->numa_node = i;

    }



    xics_cpu_setup(spapr->xics, cpu);



    qemu_register_reset(spapr_cpu_reset, cpu);

    spapr_cpu_reset(cpu);

}
static void FUNC_0(sPAPRMachineState *VAR_0, PowerPCCPU *VAR_1,

                           Error **VAR_2)

{

    CPUPPCState *env = &VAR_1->env;

    CPUState *cs = CPU(VAR_1);

    int VAR_3;



    

    cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);



    


    cpu_ppc_set_papr(VAR_1);



    if (VAR_1->max_compat) {

        Error *local_err = NULL;



        ppc_set_compat(VAR_1, VAR_1->max_compat, &local_err);

        if (local_err) {

            error_propagate(VAR_2, local_err);

            return;

        }

    }



    

    VAR_3 = numa_get_node_for_cpu(cs->cpu_index);

    if (VAR_3 < nb_numa_nodes) {

            cs->numa_node = VAR_3;

    }



    xics_cpu_setup(VAR_0->xics, VAR_1);



    qemu_register_reset(spapr_cpu_reset, VAR_1);

    spapr_cpu_reset(VAR_1);

}
static void FUNC_0(sPAPRMachineState *VAR_0, PowerPCCPU *VAR_1,
Error **VAR_2)
{ CPUPPCState *env = &VAR_1->env; CPUState *cs = CPU(VAR_1); int VAR_3; cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); cpu_ppc_set_papr(VAR_1); if (VAR_1->max_compat) { Error *local_err = NULL; ppc_set_compat(VAR_1, VAR_1->max_compat, &local_err); if (local_err) { error_propagate(VAR_2, local_err); return; } } VAR_3 = numa_get_node_for_cpu(cs->cpu_index); if (VAR_3 < nb_numa_nodes) { cs->numa_node = VAR_3; } xics_cpu_setup(VAR_0->xics, VAR_1); qemu_register_reset(spapr_cpu_reset, VAR_1); spapr_cpu_reset(VAR_1); }