static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)

{

    ECCState *s = opaque;



    switch (addr & ECC_ADDR_MASK) {

    case ECC_MER:

        s->regs[0] = (s->regs[0] & (ECC_MER_VER | ECC_MER_IMPL)) |

                     (val & ~(ECC_MER_VER | ECC_MER_IMPL));

        DPRINTF("Write memory enable %08x\n", val);

        break;

    case ECC_MDR:

        s->regs[1] =  val & ECC_MDR_MASK;

        DPRINTF("Write memory delay %08x\n", val);

        break;

    case ECC_MFSR:

        s->regs[2] =  val;

        DPRINTF("Write memory fault status %08x\n", val);

        break;

    case ECC_VCR:

        s->regs[3] =  val;

        DPRINTF("Write slot configuration %08x\n", val);

        break;

    case ECC_DR:

        s->regs[6] =  val;

        DPRINTF("Write diagnosiic %08x\n", val);

        break;

    case ECC_ECR0:

        s->regs[7] =  val;

        DPRINTF("Write event count 1 %08x\n", val);

        break;

    case ECC_ECR1:

        s->regs[7] =  val;

        DPRINTF("Write event count 2 %08x\n", val);

        break;

    }

}

static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)

{

    ECCState *s = opaque;



    switch (addr & ECC_ADDR_MASK) {

    case ECC_MER:

        s->regs[0] = (s->regs[0] & (ECC_MER_VER | ECC_MER_IMPL)) |

                     (val & ~(ECC_MER_VER | ECC_MER_IMPL));

        DPRINTF("Write memory enable %08x\n", val);

        break;

    case ECC_MDR:

        s->regs[1] =  val & ECC_MDR_MASK;

        DPRINTF("Write memory delay %08x\n", val);

        break;

    case ECC_MFSR:

        s->regs[2] =  val;

        DPRINTF("Write memory fault status %08x\n", val);

        break;

    case ECC_VCR:

        s->regs[3] =  val;

        DPRINTF("Write slot configuration %08x\n", val);

        break;

    case ECC_DR:

        s->regs[6] =  val;

        DPRINTF("Write diagnosiic %08x\n", val);

        break;

    case ECC_ECR0:

        s->regs[7] =  val;

        DPRINTF("Write event count 1 %08x\n", val);

        break;

    case ECC_ECR1:

        s->regs[7] =  val;

        DPRINTF("Write event count 2 %08x\n", val);

        break;

    }

}

    switch (addr & ECC_ADDR_MASK) {         s->regs[0] = (s->regs[0] & (ECC_MER_VER | ECC_MER_IMPL)) |                      (val & ~(ECC_MER_VER | ECC_MER_IMPL));         s->regs[1] =  val & ECC_MDR_MASK;         s->regs[2] =  val;         s->regs[3] =  val;         s->regs[6] =  val;         s->regs[7] =  val;         s->regs[7] =  val;     switch (addr & ECC_ADDR_MASK) {
static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint32_t VAR_2)

{

    ECCState *s = VAR_0;



    switch (VAR_1 & ECC_ADDR_MASK) {

    case ECC_MER:

        s->regs[0] = (s->regs[0] & (ECC_MER_VER | ECC_MER_IMPL)) |

                     (VAR_2 & ~(ECC_MER_VER | ECC_MER_IMPL));

        DPRINTF("Write memory enable %08x\n", VAR_2);

        break;

    case ECC_MDR:

        s->regs[1] =  VAR_2 & ECC_MDR_MASK;

        DPRINTF("Write memory delay %08x\n", VAR_2);

        break;

    case ECC_MFSR:

        s->regs[2] =  VAR_2;

        DPRINTF("Write memory fault status %08x\n", VAR_2);

        break;

    case ECC_VCR:

        s->regs[3] =  VAR_2;

        DPRINTF("Write slot configuration %08x\n", VAR_2);

        break;

    case ECC_DR:

        s->regs[6] =  VAR_2;

        DPRINTF("Write diagnosiic %08x\n", VAR_2);

        break;

    case ECC_ECR0:

        s->regs[7] =  VAR_2;

        DPRINTF("Write event count 1 %08x\n", VAR_2);

        break;

    case ECC_ECR1:

        s->regs[7] =  VAR_2;

        DPRINTF("Write event count 2 %08x\n", VAR_2);

        break;

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint32_t VAR_2)
{ ECCState *s = VAR_0; switch (VAR_1 & ECC_ADDR_MASK) { case ECC_MER:
s->regs[0] = (s->regs[0] & (ECC_MER_VER | ECC_MER_IMPL)) |
(VAR_2 & ~(ECC_MER_VER | ECC_MER_IMPL)); DPRINTF("Write memory enable %08x\n", VAR_2); break; case ECC_MDR:
s->regs[1] =  VAR_2 & ECC_MDR_MASK; DPRINTF("Write memory delay %08x\n", VAR_2); break; case ECC_MFSR:
s->regs[2] =  VAR_2; DPRINTF("Write memory fault status %08x\n", VAR_2); break; case ECC_VCR:
s->regs[3] =  VAR_2; DPRINTF("Write slot configuration %08x\n", VAR_2); break; case ECC_DR:
s->regs[6] =  VAR_2; DPRINTF("Write diagnosiic %08x\n", VAR_2); break; case ECC_ECR0:
s->regs[7] =  VAR_2; DPRINTF("Write event count 1 %08x\n", VAR_2); break; case ECC_ECR1:
s->regs[7] =  VAR_2; DPRINTF("Write event count 2 %08x\n", VAR_2); break; } }