static void imx_enet_do_tx(IMXFECState *s)

{

    int frame_size = 0;

    uint8_t frame[ENET_MAX_FRAME_SIZE];

    uint8_t *ptr = frame;

    uint32_t addr = s->tx_descriptor;



    while (1) {

        IMXENETBufDesc bd;

        int len;



        imx_enet_read_bd(&bd, addr);

        FEC_PRINTF("tx_bd %x flags %04x len %d data %08x option %04x "

                   "status %04x\n", addr, bd.flags, bd.length, bd.data,

                   bd.option, bd.status);

        if ((bd.flags & ENET_BD_R) == 0) {

            /* Run out of descriptors to transmit.  */

            break;

        }

        len = bd.length;

        if (frame_size + len > ENET_MAX_FRAME_SIZE) {

            len = ENET_MAX_FRAME_SIZE - frame_size;

            s->regs[ENET_EIR] |= ENET_INT_BABT;

        }

        dma_memory_read(&address_space_memory, bd.data, ptr, len);

        ptr += len;

        frame_size += len;

        if (bd.flags & ENET_BD_L) {

            if (bd.option & ENET_BD_PINS) {

                struct ip_header *ip_hd = PKT_GET_IP_HDR(frame);

                if (IP_HEADER_VERSION(ip_hd) == 4) {

                    net_checksum_calculate(frame, frame_size);

                }

            }

            if (bd.option & ENET_BD_IINS) {

                struct ip_header *ip_hd = PKT_GET_IP_HDR(frame);

                /* We compute checksum only for IPv4 frames */

                if (IP_HEADER_VERSION(ip_hd) == 4) {

                    uint16_t csum;

                    ip_hd->ip_sum = 0;

                    csum = net_raw_checksum((uint8_t *)ip_hd, sizeof(*ip_hd));

                    ip_hd->ip_sum = cpu_to_be16(csum);

                }

            }

            /* Last buffer in frame.  */

            qemu_send_packet(qemu_get_queue(s->nic), frame, len);

            ptr = frame;

            frame_size = 0;

            if (bd.option & ENET_BD_TX_INT) {

                s->regs[ENET_EIR] |= ENET_INT_TXF;

            }

        }

        if (bd.option & ENET_BD_TX_INT) {

            s->regs[ENET_EIR] |= ENET_INT_TXB;

        }

        bd.flags &= ~ENET_BD_R;

        /* Write back the modified descriptor.  */

        imx_enet_write_bd(&bd, addr);

        /* Advance to the next descriptor.  */

        if ((bd.flags & ENET_BD_W) != 0) {

            addr = s->regs[ENET_TDSR];

        } else {

            addr += sizeof(bd);

        }

    }



    s->tx_descriptor = addr;



    imx_eth_update(s);

}

static void imx_enet_do_tx(IMXFECState *s)

{

    int frame_size = 0;

    uint8_t frame[ENET_MAX_FRAME_SIZE];

    uint8_t *ptr = frame;

    uint32_t addr = s->tx_descriptor;



    while (1) {

        IMXENETBufDesc bd;

        int len;



        imx_enet_read_bd(&bd, addr);

        FEC_PRINTF("tx_bd %x flags %04x len %d data %08x option %04x "

                   "status %04x\n", addr, bd.flags, bd.length, bd.data,

                   bd.option, bd.status);

        if ((bd.flags & ENET_BD_R) == 0) {

            

            break;

        }

        len = bd.length;

        if (frame_size + len > ENET_MAX_FRAME_SIZE) {

            len = ENET_MAX_FRAME_SIZE - frame_size;

            s->regs[ENET_EIR] |= ENET_INT_BABT;

        }

        dma_memory_read(&address_space_memory, bd.data, ptr, len);

        ptr += len;

        frame_size += len;

        if (bd.flags & ENET_BD_L) {

            if (bd.option & ENET_BD_PINS) {

                struct ip_header *ip_hd = PKT_GET_IP_HDR(frame);

                if (IP_HEADER_VERSION(ip_hd) == 4) {

                    net_checksum_calculate(frame, frame_size);

                }

            }

            if (bd.option & ENET_BD_IINS) {

                struct ip_header *ip_hd = PKT_GET_IP_HDR(frame);

                

                if (IP_HEADER_VERSION(ip_hd) == 4) {

                    uint16_t csum;

                    ip_hd->ip_sum = 0;

                    csum = net_raw_checksum((uint8_t *)ip_hd, sizeof(*ip_hd));

                    ip_hd->ip_sum = cpu_to_be16(csum);

                }

            }

            

            qemu_send_packet(qemu_get_queue(s->nic), frame, len);

            ptr = frame;

            frame_size = 0;

            if (bd.option & ENET_BD_TX_INT) {

                s->regs[ENET_EIR] |= ENET_INT_TXF;

            }

        }

        if (bd.option & ENET_BD_TX_INT) {

            s->regs[ENET_EIR] |= ENET_INT_TXB;

        }

        bd.flags &= ~ENET_BD_R;

        

        imx_enet_write_bd(&bd, addr);

        

        if ((bd.flags & ENET_BD_W) != 0) {

            addr = s->regs[ENET_TDSR];

        } else {

            addr += sizeof(bd);

        }

    }



    s->tx_descriptor = addr;



    imx_eth_update(s);

}

static void FUNC_0(IMXFECState *VAR_0)

{

    int VAR_1 = 0;

    uint8_t frame[ENET_MAX_FRAME_SIZE];

    uint8_t *ptr = frame;

    uint32_t addr = VAR_0->tx_descriptor;



    while (1) {

        IMXENETBufDesc bd;

        int VAR_2;



        imx_enet_read_bd(&bd, addr);

        FEC_PRINTF("tx_bd %x flags %04x VAR_2 %d data %08x option %04x "

                   "status %04x\n", addr, bd.flags, bd.length, bd.data,

                   bd.option, bd.status);

        if ((bd.flags & ENET_BD_R) == 0) {

            

            break;

        }

        VAR_2 = bd.length;

        if (VAR_1 + VAR_2 > ENET_MAX_FRAME_SIZE) {

            VAR_2 = ENET_MAX_FRAME_SIZE - VAR_1;

            VAR_0->regs[ENET_EIR] |= ENET_INT_BABT;

        }

        dma_memory_read(&address_space_memory, bd.data, ptr, VAR_2);

        ptr += VAR_2;

        VAR_1 += VAR_2;

        if (bd.flags & ENET_BD_L) {

            if (bd.option & ENET_BD_PINS) {

                struct ip_header *VAR_4 = PKT_GET_IP_HDR(frame);

                if (IP_HEADER_VERSION(VAR_4) == 4) {

                    net_checksum_calculate(frame, VAR_1);

                }

            }

            if (bd.option & ENET_BD_IINS) {

                struct ip_header *VAR_4 = PKT_GET_IP_HDR(frame);

                

                if (IP_HEADER_VERSION(VAR_4) == 4) {

                    uint16_t csum;

                    VAR_4->ip_sum = 0;

                    csum = net_raw_checksum((uint8_t *)VAR_4, sizeof(*VAR_4));

                    VAR_4->ip_sum = cpu_to_be16(csum);

                }

            }

            

            qemu_send_packet(qemu_get_queue(VAR_0->nic), frame, VAR_2);

            ptr = frame;

            VAR_1 = 0;

            if (bd.option & ENET_BD_TX_INT) {

                VAR_0->regs[ENET_EIR] |= ENET_INT_TXF;

            }

        }

        if (bd.option & ENET_BD_TX_INT) {

            VAR_0->regs[ENET_EIR] |= ENET_INT_TXB;

        }

        bd.flags &= ~ENET_BD_R;

        

        imx_enet_write_bd(&bd, addr);

        

        if ((bd.flags & ENET_BD_W) != 0) {

            addr = VAR_0->regs[ENET_TDSR];

        } else {

            addr += sizeof(bd);

        }

    }



    VAR_0->tx_descriptor = addr;



    imx_eth_update(VAR_0);

}

static void FUNC_0(IMXFECState *VAR_0)
{ int VAR_1 = 0; uint8_t frame[ENET_MAX_FRAME_SIZE]; uint8_t *ptr = frame; uint32_t addr = VAR_0->tx_descriptor; while (1) { IMXENETBufDesc bd; int VAR_2; imx_enet_read_bd(&bd, addr); FEC_PRINTF("tx_bd %x flags %04x VAR_2 %d data %08x option %04x "
"status %04x\n", addr, bd.flags, bd.length, bd.data,
bd.option, bd.status); if ((bd.flags & ENET_BD_R) == 0) { break; } VAR_2 = bd.length; if (VAR_1 + VAR_2 > ENET_MAX_FRAME_SIZE) { VAR_2 = ENET_MAX_FRAME_SIZE - VAR_1; VAR_0->regs[ENET_EIR] |= ENET_INT_BABT; } dma_memory_read(&address_space_memory, bd.data, ptr, VAR_2); ptr += VAR_2; VAR_1 += VAR_2; if (bd.flags & ENET_BD_L) { if (bd.option & ENET_BD_PINS) { struct ip_header *VAR_4 = PKT_GET_IP_HDR(frame); if (IP_HEADER_VERSION(VAR_4) == 4) { net_checksum_calculate(frame, VAR_1); } } if (bd.option & ENET_BD_IINS) { struct ip_header *VAR_4 = PKT_GET_IP_HDR(frame); if (IP_HEADER_VERSION(VAR_4) == 4) { uint16_t csum; VAR_4->ip_sum = 0; csum = net_raw_checksum((uint8_t *)VAR_4, sizeof(*VAR_4)); VAR_4->ip_sum = cpu_to_be16(csum); } } qemu_send_packet(qemu_get_queue(VAR_0->nic), frame, VAR_2); ptr = frame; VAR_1 = 0; if (bd.option & ENET_BD_TX_INT) { VAR_0->regs[ENET_EIR] |= ENET_INT_TXF; } } if (bd.option & ENET_BD_TX_INT) { VAR_0->regs[ENET_EIR] |= ENET_INT_TXB; } bd.flags &= ~ENET_BD_R; imx_enet_write_bd(&bd, addr); if ((bd.flags & ENET_BD_W) != 0) { addr = VAR_0->regs[ENET_TDSR]; } else { addr += sizeof(bd); } } VAR_0->tx_descriptor = addr; imx_eth_update(VAR_0); }