static int get_physical_address_data(CPUState *env,

                                     target_phys_addr_t *physical, int *prot,

                                     target_ulong address, int rw, int is_user)

{

    target_ulong mask;

    unsigned int i;



    if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */

        *physical = address;

        *prot = PAGE_READ | PAGE_WRITE;

        return 0;

    }



    for (i = 0; i < 64; i++) {

        switch ((env->dtlb_tte[i] >> 61) & 3) {

        default:

        case 0x0: // 8k

            mask = 0xffffffffffffe000ULL;

            break;

        case 0x1: // 64k

            mask = 0xffffffffffff0000ULL;

            break;

        case 0x2: // 512k

            mask = 0xfffffffffff80000ULL;

            break;

        case 0x3: // 4M

            mask = 0xffffffffffc00000ULL;

            break;

        }

        // ctx match, vaddr match, valid?

        if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&

            (address & mask) == (env->dtlb_tag[i] & mask) &&

            (env->dtlb_tte[i] & 0x8000000000000000ULL)) {

            // access ok?

            if (((env->dtlb_tte[i] & 0x4) && is_user) ||

                (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {

                if (env->dmmuregs[3]) /* Fault status register */

                    env->dmmuregs[3] = 2; /* overflow (not read before

                                             another fault) */

                env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;

                env->dmmuregs[4] = address; /* Fault address register */

                env->exception_index = TT_DFAULT;

#ifdef DEBUG_MMU

                printf("DFAULT at 0x%" PRIx64 "\n", address);

#endif

                return 1;

            }

            *physical = ((env->dtlb_tte[i] & mask) | (address & ~mask)) &

                        0x1ffffffe000ULL;

            *prot = PAGE_READ;

            if (env->dtlb_tte[i] & 0x2)

                *prot |= PAGE_WRITE;

            return 0;

        }

    }

#ifdef DEBUG_MMU

    printf("DMISS at 0x%" PRIx64 "\n", address);

#endif

    env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);

    env->exception_index = TT_DMISS;

    return 1;

}

static int get_physical_address_data(CPUState *env,

                                     target_phys_addr_t *physical, int *prot,

                                     target_ulong address, int rw, int is_user)

{

    target_ulong mask;

    unsigned int i;



    if ((env->lsu & DMMU_E) == 0) { 

        *physical = address;

        *prot = PAGE_READ | PAGE_WRITE;

        return 0;

    }



    for (i = 0; i < 64; i++) {

        switch ((env->dtlb_tte[i] >> 61) & 3) {

        default:

        case 0x0: 

            mask = 0xffffffffffffe000ULL;

            break;

        case 0x1: 

            mask = 0xffffffffffff0000ULL;

            break;

        case 0x2: 

            mask = 0xfffffffffff80000ULL;

            break;

        case 0x3: 

            mask = 0xffffffffffc00000ULL;

            break;

        }

        

        if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&

            (address & mask) == (env->dtlb_tag[i] & mask) &&

            (env->dtlb_tte[i] & 0x8000000000000000ULL)) {

            

            if (((env->dtlb_tte[i] & 0x4) && is_user) ||

                (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {

                if (env->dmmuregs[3]) 

                    env->dmmuregs[3] = 2; 



                env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;

                env->dmmuregs[4] = address; 

                env->exception_index = TT_DFAULT;

#ifdef DEBUG_MMU

                printf("DFAULT at 0x%" PRIx64 "\n", address);

#endif

                return 1;

            }

            *physical = ((env->dtlb_tte[i] & mask) | (address & ~mask)) &

                        0x1ffffffe000ULL;

            *prot = PAGE_READ;

            if (env->dtlb_tte[i] & 0x2)

                *prot |= PAGE_WRITE;

            return 0;

        }

    }

#ifdef DEBUG_MMU

    printf("DMISS at 0x%" PRIx64 "\n", address);

#endif

    env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);

    env->exception_index = TT_DMISS;

    return 1;

}

static int FUNC_0(CPUState *VAR_0,

                                     target_phys_addr_t *VAR_1, int *VAR_2,

                                     target_ulong VAR_3, int VAR_4, int VAR_5)

{

    target_ulong mask;

    unsigned int VAR_6;



    if ((VAR_0->lsu & DMMU_E) == 0) { 

        *VAR_1 = VAR_3;

        *VAR_2 = PAGE_READ | PAGE_WRITE;

        return 0;

    }



    for (VAR_6 = 0; VAR_6 < 64; VAR_6++) {

        switch ((VAR_0->dtlb_tte[VAR_6] >> 61) & 3) {

        default:

        case 0x0: 

            mask = 0xffffffffffffe000ULL;

            break;

        case 0x1: 

            mask = 0xffffffffffff0000ULL;

            break;

        case 0x2: 

            mask = 0xfffffffffff80000ULL;

            break;

        case 0x3: 

            mask = 0xffffffffffc00000ULL;

            break;

        }

        

        if (VAR_0->dmmuregs[1] == (VAR_0->dtlb_tag[VAR_6] & 0x1fff) &&

            (VAR_3 & mask) == (VAR_0->dtlb_tag[VAR_6] & mask) &&

            (VAR_0->dtlb_tte[VAR_6] & 0x8000000000000000ULL)) {

            

            if (((VAR_0->dtlb_tte[VAR_6] & 0x4) && VAR_5) ||

                (!(VAR_0->dtlb_tte[VAR_6] & 0x2) && (VAR_4 == 1))) {

                if (VAR_0->dmmuregs[3]) 

                    VAR_0->dmmuregs[3] = 2; 



                VAR_0->dmmuregs[3] |= (VAR_5 << 3) | ((VAR_4 == 1) << 2) | 1;

                VAR_0->dmmuregs[4] = VAR_3; 

                VAR_0->exception_index = TT_DFAULT;

#ifdef DEBUG_MMU

                printf("DFAULT at 0x%" PRIx64 "\n", VAR_3);

#endif

                return 1;

            }

            *VAR_1 = ((VAR_0->dtlb_tte[VAR_6] & mask) | (VAR_3 & ~mask)) &

                        0x1ffffffe000ULL;

            *VAR_2 = PAGE_READ;

            if (VAR_0->dtlb_tte[VAR_6] & 0x2)

                *VAR_2 |= PAGE_WRITE;

            return 0;

        }

    }

#ifdef DEBUG_MMU

    printf("DMISS at 0x%" PRIx64 "\n", VAR_3);

#endif

    VAR_0->dmmuregs[6] = (VAR_3 & ~0x1fffULL) | (VAR_0->dmmuregs[1] & 0x1fff);

    VAR_0->exception_index = TT_DMISS;

    return 1;

}

static int FUNC_0(CPUState *VAR_0,
target_phys_addr_t *VAR_1, int *VAR_2,
target_ulong VAR_3, int VAR_4, int VAR_5)
{ target_ulong mask; unsigned int VAR_6; if ((VAR_0->lsu & DMMU_E) == 0) { *VAR_1 = VAR_3; *VAR_2 = PAGE_READ | PAGE_WRITE; return 0; } for (VAR_6 = 0; VAR_6 < 64; VAR_6++) { switch ((VAR_0->dtlb_tte[VAR_6] >> 61) & 3) { default:
case 0x0:
mask = 0xffffffffffffe000ULL; break; case 0x1:
mask = 0xffffffffffff0000ULL; break; case 0x2:
mask = 0xfffffffffff80000ULL; break; case 0x3:
mask = 0xffffffffffc00000ULL; break; } if (VAR_0->dmmuregs[1] == (VAR_0->dtlb_tag[VAR_6] & 0x1fff) &&
(VAR_3 & mask) == (VAR_0->dtlb_tag[VAR_6] & mask) &&
(VAR_0->dtlb_tte[VAR_6] & 0x8000000000000000ULL)) { if (((VAR_0->dtlb_tte[VAR_6] & 0x4) && VAR_5) ||
(!(VAR_0->dtlb_tte[VAR_6] & 0x2) && (VAR_4 == 1))) { if (VAR_0->dmmuregs[3])
VAR_0->dmmuregs[3] = 2; VAR_0->dmmuregs[3] |= (VAR_5 << 3) | ((VAR_4 == 1) << 2) | 1; VAR_0->dmmuregs[4] = VAR_3; VAR_0->exception_index = TT_DFAULT; #ifdef DEBUG_MMU
printf("DFAULT at 0x%" PRIx64 "\n", VAR_3); #endif
return 1; } *VAR_1 = ((VAR_0->dtlb_tte[VAR_6] & mask) | (VAR_3 & ~mask)) &
0x1ffffffe000ULL; *VAR_2 = PAGE_READ; if (VAR_0->dtlb_tte[VAR_6] & 0x2)
*VAR_2 |= PAGE_WRITE; return 0; } } #ifdef DEBUG_MMU
printf("DMISS at 0x%" PRIx64 "\n", VAR_3); #endif
VAR_0->dmmuregs[6] = (VAR_3 & ~0x1fffULL) | (VAR_0->dmmuregs[1] & 0x1fff); VAR_0->exception_index = TT_DMISS; return 1; }