static void qxl_dirty_surfaces(PCIQXLDevice *qxl)

{

    uintptr_t vram_start;

    int i;



    if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {

        return;

    }



    /* dirty the primary surface */

    qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,

                  qxl->shadow_rom.surface0_area_size);



    vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);



    /* dirty the off-screen surfaces */

    for (i = 0; i < qxl->ssd.num_surfaces; i++) {

        QXLSurfaceCmd *cmd;

        intptr_t surface_offset;

        int surface_size;



        if (qxl->guest_surfaces.cmds[i] == 0) {

            continue;

        }



        cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],

                            MEMSLOT_GROUP_GUEST);

        assert(cmd);

        assert(cmd->type == QXL_SURFACE_CMD_CREATE);

        surface_offset = (intptr_t)qxl_phys2virt(qxl,

                                                 cmd->u.surface_create.data,

                                                 MEMSLOT_GROUP_GUEST);

        assert(surface_offset);

        surface_offset -= vram_start;

        surface_size = cmd->u.surface_create.height *

                       abs(cmd->u.surface_create.stride);

        trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);

        qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);

    }

}

static void qxl_dirty_surfaces(PCIQXLDevice *qxl)

{

    uintptr_t vram_start;

    int i;



    if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {

        return;

    }



    

    qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,

                  qxl->shadow_rom.surface0_area_size);



    vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);



    

    for (i = 0; i < qxl->ssd.num_surfaces; i++) {

        QXLSurfaceCmd *cmd;

        intptr_t surface_offset;

        int surface_size;



        if (qxl->guest_surfaces.cmds[i] == 0) {

            continue;

        }



        cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],

                            MEMSLOT_GROUP_GUEST);

        assert(cmd);

        assert(cmd->type == QXL_SURFACE_CMD_CREATE);

        surface_offset = (intptr_t)qxl_phys2virt(qxl,

                                                 cmd->u.surface_create.data,

                                                 MEMSLOT_GROUP_GUEST);

        assert(surface_offset);

        surface_offset -= vram_start;

        surface_size = cmd->u.surface_create.height *

                       abs(cmd->u.surface_create.stride);

        trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);

        qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);

    }

}

static void FUNC_0(PCIQXLDevice *VAR_0)

{

    uintptr_t vram_start;

    int VAR_1;



    if (VAR_0->mode != QXL_MODE_NATIVE && VAR_0->mode != QXL_MODE_COMPAT) {

        return;

    }



    

    qxl_set_dirty(&VAR_0->vga.vram, VAR_0->shadow_rom.draw_area_offset,

                  VAR_0->shadow_rom.surface0_area_size);



    vram_start = (uintptr_t)memory_region_get_ram_ptr(&VAR_0->vram_bar);



    

    for (VAR_1 = 0; VAR_1 < VAR_0->ssd.num_surfaces; VAR_1++) {

        QXLSurfaceCmd *cmd;

        intptr_t surface_offset;

        int surface_size;



        if (VAR_0->guest_surfaces.cmds[VAR_1] == 0) {

            continue;

        }



        cmd = qxl_phys2virt(VAR_0, VAR_0->guest_surfaces.cmds[VAR_1],

                            MEMSLOT_GROUP_GUEST);

        assert(cmd);

        assert(cmd->type == QXL_SURFACE_CMD_CREATE);

        surface_offset = (intptr_t)qxl_phys2virt(VAR_0,

                                                 cmd->u.surface_create.data,

                                                 MEMSLOT_GROUP_GUEST);

        assert(surface_offset);

        surface_offset -= vram_start;

        surface_size = cmd->u.surface_create.height *

                       abs(cmd->u.surface_create.stride);

        trace_qxl_surfaces_dirty(VAR_0->id, VAR_1, (int)surface_offset, surface_size);

        qxl_set_dirty(&VAR_0->vram_bar, surface_offset, surface_size);

    }

}

static void FUNC_0(PCIQXLDevice *VAR_0)
{ uintptr_t vram_start; int VAR_1; if (VAR_0->mode != QXL_MODE_NATIVE && VAR_0->mode != QXL_MODE_COMPAT) { return; } qxl_set_dirty(&VAR_0->vga.vram, VAR_0->shadow_rom.draw_area_offset,
VAR_0->shadow_rom.surface0_area_size); vram_start = (uintptr_t)memory_region_get_ram_ptr(&VAR_0->vram_bar); for (VAR_1 = 0; VAR_1 < VAR_0->ssd.num_surfaces; VAR_1++) { QXLSurfaceCmd *cmd; intptr_t surface_offset; int surface_size; if (VAR_0->guest_surfaces.cmds[VAR_1] == 0) { continue; } cmd = qxl_phys2virt(VAR_0, VAR_0->guest_surfaces.cmds[VAR_1],
MEMSLOT_GROUP_GUEST); assert(cmd); assert(cmd->type == QXL_SURFACE_CMD_CREATE); surface_offset = (intptr_t)qxl_phys2virt(VAR_0,
cmd->u.surface_create.data,
MEMSLOT_GROUP_GUEST); assert(surface_offset); surface_offset -= vram_start; surface_size = cmd->u.surface_create.height *
abs(cmd->u.surface_create.stride); trace_qxl_surfaces_dirty(VAR_0->id, VAR_1, (int)surface_offset, surface_size); qxl_set_dirty(&VAR_0->vram_bar, surface_offset, surface_size); } }