void do_interrupt(CPUState *env)

{

	int ex_vec = -1;



	D(fprintf (stderr, "exception index=%d interrupt_req=%d\n",

		   env->exception_index,

		   env->interrupt_request));



	switch (env->exception_index)

	{

		case EXCP_BREAK:

			/* These exceptions are genereated by the core itself.

			   ERP should point to the insn following the brk.  */

			ex_vec = env->trap_vector;

			env->pregs[PR_ERP] = env->pc + 2;

			break;



		case EXCP_MMU_FAULT:

			ex_vec = env->fault_vector;

			env->pregs[PR_ERP] = env->pc;

			break;



		default:

			/* Is the core accepting interrupts?  */

			if (!(env->pregs[PR_CCS] & I_FLAG))

				return;

			/* The interrupt controller gives us the

			   vector.  */

			ex_vec = env->interrupt_vector;

			/* Normal interrupts are taken between

			   TB's.  env->pc is valid here.  */

			env->pregs[PR_ERP] = env->pc;

			break;

	}



	if ((env->pregs[PR_CCS] & U_FLAG)) {

		D(fprintf(logfile, "excp isr=%x PC=%x ERP=%x pid=%x ccs=%x cc=%d %x\n",

			  ex_vec, env->pc,

			  env->pregs[PR_ERP], env->pregs[PR_PID],

			  env->pregs[PR_CCS],

			  env->cc_op, env->cc_mask));

	}

	

	env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);



	if (env->pregs[PR_CCS] & U_FLAG) {

		/* Swap stack pointers.  */

		env->pregs[PR_USP] = env->regs[R_SP];

		env->regs[R_SP] = env->ksp;

	}



	/* Apply the CRIS CCS shift. Clears U if set.  */

	cris_shift_ccs(env);

	D(fprintf (logfile, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", 

		   __func__, env->pc, ex_vec, 

		   env->pregs[PR_CCS],

		   env->pregs[PR_PID], 

		   env->pregs[PR_ERP]));

}

void do_interrupt(CPUState *env)

{

	int ex_vec = -1;



	D(fprintf (stderr, "exception index=%d interrupt_req=%d\n",

		   env->exception_index,

		   env->interrupt_request));



	switch (env->exception_index)

	{

		case EXCP_BREAK:

			



			ex_vec = env->trap_vector;

			env->pregs[PR_ERP] = env->pc + 2;

			break;



		case EXCP_MMU_FAULT:

			ex_vec = env->fault_vector;

			env->pregs[PR_ERP] = env->pc;

			break;



		default:

			

			if (!(env->pregs[PR_CCS] & I_FLAG))

				return;

			



			ex_vec = env->interrupt_vector;

			



			env->pregs[PR_ERP] = env->pc;

			break;

	}



	if ((env->pregs[PR_CCS] & U_FLAG)) {

		D(fprintf(logfile, "excp isr=%x PC=%x ERP=%x pid=%x ccs=%x cc=%d %x\n",

			  ex_vec, env->pc,

			  env->pregs[PR_ERP], env->pregs[PR_PID],

			  env->pregs[PR_CCS],

			  env->cc_op, env->cc_mask));

	}

	

	env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);



	if (env->pregs[PR_CCS] & U_FLAG) {

		

		env->pregs[PR_USP] = env->regs[R_SP];

		env->regs[R_SP] = env->ksp;

	}



	

	cris_shift_ccs(env);

	D(fprintf (logfile, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", 

		   __func__, env->pc, ex_vec, 

		   env->pregs[PR_CCS],

		   env->pregs[PR_PID], 

		   env->pregs[PR_ERP]));

}

void FUNC_0(CPUState *VAR_0)

{

	int VAR_1 = -1;



	D(fprintf (stderr, "exception index=%d interrupt_req=%d\n",

		   VAR_0->exception_index,

		   VAR_0->interrupt_request));



	switch (VAR_0->exception_index)

	{

		case EXCP_BREAK:

			



			VAR_1 = VAR_0->trap_vector;

			VAR_0->pregs[PR_ERP] = VAR_0->pc + 2;

			break;



		case EXCP_MMU_FAULT:

			VAR_1 = VAR_0->fault_vector;

			VAR_0->pregs[PR_ERP] = VAR_0->pc;

			break;



		default:

			

			if (!(VAR_0->pregs[PR_CCS] & I_FLAG))

				return;

			



			VAR_1 = VAR_0->interrupt_vector;

			



			VAR_0->pregs[PR_ERP] = VAR_0->pc;

			break;

	}



	if ((VAR_0->pregs[PR_CCS] & U_FLAG)) {

		D(fprintf(logfile, "excp isr=%x PC=%x ERP=%x pid=%x ccs=%x cc=%d %x\n",

			  VAR_1, VAR_0->pc,

			  VAR_0->pregs[PR_ERP], VAR_0->pregs[PR_PID],

			  VAR_0->pregs[PR_CCS],

			  VAR_0->cc_op, VAR_0->cc_mask));

	}

	

	VAR_0->pc = ldl_code(VAR_0->pregs[PR_EBP] + VAR_1 * 4);



	if (VAR_0->pregs[PR_CCS] & U_FLAG) {

		

		VAR_0->pregs[PR_USP] = VAR_0->regs[R_SP];

		VAR_0->regs[R_SP] = VAR_0->ksp;

	}



	

	cris_shift_ccs(VAR_0);

	D(fprintf (logfile, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", 

		   __func__, VAR_0->pc, VAR_1, 

		   VAR_0->pregs[PR_CCS],

		   VAR_0->pregs[PR_PID], 

		   VAR_0->pregs[PR_ERP]));

}

void FUNC_0(CPUState *VAR_0)
{ int VAR_1 = -1; D(fprintf (stderr, "exception index=%d interrupt_req=%d\n",
VAR_0->exception_index,
VAR_0->interrupt_request)); switch (VAR_0->exception_index)
{ case EXCP_BREAK:
VAR_1 = VAR_0->trap_vector; VAR_0->pregs[PR_ERP] = VAR_0->pc + 2; break; case EXCP_MMU_FAULT:
VAR_1 = VAR_0->fault_vector; VAR_0->pregs[PR_ERP] = VAR_0->pc; break; default:
if (!(VAR_0->pregs[PR_CCS] & I_FLAG))
return; VAR_1 = VAR_0->interrupt_vector; VAR_0->pregs[PR_ERP] = VAR_0->pc; break; } if ((VAR_0->pregs[PR_CCS] & U_FLAG)) { D(fprintf(logfile, "excp isr=%x PC=%x ERP=%x pid=%x ccs=%x cc=%d %x\n",
VAR_1, VAR_0->pc,
VAR_0->pregs[PR_ERP], VAR_0->pregs[PR_PID],
VAR_0->pregs[PR_CCS],
VAR_0->cc_op, VAR_0->cc_mask)); } VAR_0->pc = ldl_code(VAR_0->pregs[PR_EBP] + VAR_1 * 4); if (VAR_0->pregs[PR_CCS] & U_FLAG) { VAR_0->pregs[PR_USP] = VAR_0->regs[R_SP]; VAR_0->regs[R_SP] = VAR_0->ksp; } cris_shift_ccs(VAR_0); D(fprintf (logfile, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
__func__, VAR_0->pc, VAR_1,
VAR_0->pregs[PR_CCS],
VAR_0->pregs[PR_PID],
VAR_0->pregs[PR_ERP])); }