void msix_write_config(PCIDevice *dev, uint32_t addr,

                       uint32_t val, int len)

{

    unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;

    if (addr + len <= enable_pos || addr > enable_pos)

        return;



    if (msix_enabled(dev))

        qemu_set_irq(dev->irq[0], 0);

}

void msix_write_config(PCIDevice *dev, uint32_t addr,

                       uint32_t val, int len)

{

    unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;

    if (addr + len <= enable_pos || addr > enable_pos)

        return;



    if (msix_enabled(dev))

        qemu_set_irq(dev->irq[0], 0);

}

void FUNC_0(PCIDevice *VAR_0, uint32_t VAR_1,

                       uint32_t VAR_2, int VAR_3)

{

    unsigned VAR_4 = VAR_0->msix_cap + MSIX_CONTROL_OFFSET;

    if (VAR_1 + VAR_3 <= VAR_4 || VAR_1 > VAR_4)

        return;



    if (msix_enabled(VAR_0))

        qemu_set_irq(VAR_0->irq[0], 0);

}

void FUNC_0(PCIDevice *VAR_0, uint32_t VAR_1,
uint32_t VAR_2, int VAR_3)
{ unsigned VAR_4 = VAR_0->msix_cap + MSIX_CONTROL_OFFSET; if (VAR_1 + VAR_3 <= VAR_4 || VAR_1 > VAR_4)
return; if (msix_enabled(VAR_0))
qemu_set_irq(VAR_0->irq[0], 0); }