static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)

{

    int sx = 0, sy = 0;

    int dx = 0, dy = 0;

    int depth = 0;

    int notify = 0;



    /* make sure to only copy if it's a plain copy ROP */

    if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||

        *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {



        int width, height;



        depth = s->vga.get_bpp(&s->vga) / 8;

        s->vga.get_resolution(&s->vga, &width, &height);



        /* extra x, y */

        sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;

        sy = (src / ABS(s->cirrus_blt_srcpitch));

        dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;

        dy = (dst / ABS(s->cirrus_blt_dstpitch));



        /* normalize width */

        w /= depth;



        /* if we're doing a backward copy, we have to adjust

           our x/y to be the upper left corner (instead of the lower

           right corner) */

        if (s->cirrus_blt_dstpitch < 0) {

            sx -= (s->cirrus_blt_width / depth) - 1;

            dx -= (s->cirrus_blt_width / depth) - 1;

            sy -= s->cirrus_blt_height - 1;

            dy -= s->cirrus_blt_height - 1;

        }



        /* are we in the visible portion of memory? */

        if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&

            (sx + w) <= width && (sy + h) <= height &&

            (dx + w) <= width && (dy + h) <= height) {

            notify = 1;

        }

    }



    /* we have to flush all pending changes so that the copy

       is generated at the appropriate moment in time */

    if (notify)

        graphic_hw_update(s->vga.con);



    (*s->cirrus_rop) (s, s->vga.vram_ptr +

		      (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),

		      s->vga.vram_ptr +

		      (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),

		      s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,

		      s->cirrus_blt_width, s->cirrus_blt_height);



    if (notify) {

        qemu_console_copy(s->vga.con,

			  sx, sy, dx, dy,

			  s->cirrus_blt_width / depth,

			  s->cirrus_blt_height);

    }



    /* we don't have to notify the display that this portion has

       changed since qemu_console_copy implies this */



    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,

				s->cirrus_blt_dstpitch, s->cirrus_blt_width,

				s->cirrus_blt_height);

}

static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)

{

    int sx = 0, sy = 0;

    int dx = 0, dy = 0;

    int depth = 0;

    int notify = 0;



    

    if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||

        *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {



        int width, height;



        depth = s->vga.get_bpp(&s->vga) / 8;

        s->vga.get_resolution(&s->vga, &width, &height);



        

        sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;

        sy = (src / ABS(s->cirrus_blt_srcpitch));

        dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;

        dy = (dst / ABS(s->cirrus_blt_dstpitch));



        

        w /= depth;



        





        if (s->cirrus_blt_dstpitch < 0) {

            sx -= (s->cirrus_blt_width / depth) - 1;

            dx -= (s->cirrus_blt_width / depth) - 1;

            sy -= s->cirrus_blt_height - 1;

            dy -= s->cirrus_blt_height - 1;

        }



        

        if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&

            (sx + w) <= width && (sy + h) <= height &&

            (dx + w) <= width && (dy + h) <= height) {

            notify = 1;

        }

    }



    



    if (notify)

        graphic_hw_update(s->vga.con);



    (*s->cirrus_rop) (s, s->vga.vram_ptr +

		      (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),

		      s->vga.vram_ptr +

		      (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),

		      s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,

		      s->cirrus_blt_width, s->cirrus_blt_height);



    if (notify) {

        qemu_console_copy(s->vga.con,

			  sx, sy, dx, dy,

			  s->cirrus_blt_width / depth,

			  s->cirrus_blt_height);

    }



    





    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,

				s->cirrus_blt_dstpitch, s->cirrus_blt_width,

				s->cirrus_blt_height);

}

static void FUNC_0(CirrusVGAState *VAR_0, int VAR_1, int VAR_2, int VAR_3, int VAR_4)

{

    int VAR_5 = 0, VAR_6 = 0;

    int VAR_7 = 0, VAR_8 = 0;

    int VAR_9 = 0;

    int VAR_10 = 0;



    

    if (*VAR_0->cirrus_rop == cirrus_bitblt_rop_fwd_src ||

        *VAR_0->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {



        int VAR_11, VAR_12;



        VAR_9 = VAR_0->vga.get_bpp(&VAR_0->vga) / 8;

        VAR_0->vga.get_resolution(&VAR_0->vga, &VAR_11, &VAR_12);



        

        VAR_5 = (VAR_2 % ABS(VAR_0->cirrus_blt_srcpitch)) / VAR_9;

        VAR_6 = (VAR_2 / ABS(VAR_0->cirrus_blt_srcpitch));

        VAR_7 = (VAR_1 % ABS(VAR_0->cirrus_blt_dstpitch)) / VAR_9;

        VAR_8 = (VAR_1 / ABS(VAR_0->cirrus_blt_dstpitch));



        

        VAR_3 /= VAR_9;



        





        if (VAR_0->cirrus_blt_dstpitch < 0) {

            VAR_5 -= (VAR_0->cirrus_blt_width / VAR_9) - 1;

            VAR_7 -= (VAR_0->cirrus_blt_width / VAR_9) - 1;

            VAR_6 -= VAR_0->cirrus_blt_height - 1;

            VAR_8 -= VAR_0->cirrus_blt_height - 1;

        }



        

        if (VAR_5 >= 0 && VAR_6 >= 0 && VAR_7 >= 0 && VAR_8 >= 0 &&

            (VAR_5 + VAR_3) <= VAR_11 && (VAR_6 + VAR_4) <= VAR_12 &&

            (VAR_7 + VAR_3) <= VAR_11 && (VAR_8 + VAR_4) <= VAR_12) {

            VAR_10 = 1;

        }

    }



    



    if (VAR_10)

        graphic_hw_update(VAR_0->vga.con);



    (*VAR_0->cirrus_rop) (VAR_0, VAR_0->vga.vram_ptr +

		      (VAR_0->cirrus_blt_dstaddr & VAR_0->cirrus_addr_mask),

		      VAR_0->vga.vram_ptr +

		      (VAR_0->cirrus_blt_srcaddr & VAR_0->cirrus_addr_mask),

		      VAR_0->cirrus_blt_dstpitch, VAR_0->cirrus_blt_srcpitch,

		      VAR_0->cirrus_blt_width, VAR_0->cirrus_blt_height);



    if (VAR_10) {

        qemu_console_copy(VAR_0->vga.con,

			  VAR_5, VAR_6, VAR_7, VAR_8,

			  VAR_0->cirrus_blt_width / VAR_9,

			  VAR_0->cirrus_blt_height);

    }



    





    cirrus_invalidate_region(VAR_0, VAR_0->cirrus_blt_dstaddr,

				VAR_0->cirrus_blt_dstpitch, VAR_0->cirrus_blt_width,

				VAR_0->cirrus_blt_height);

}

static void FUNC_0(CirrusVGAState *VAR_0, int VAR_1, int VAR_2, int VAR_3, int VAR_4)
{ int VAR_5 = 0, VAR_6 = 0; int VAR_7 = 0, VAR_8 = 0; int VAR_9 = 0; int VAR_10 = 0; if (*VAR_0->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
*VAR_0->cirrus_rop == cirrus_bitblt_rop_bkwd_src) { int VAR_11, VAR_12; VAR_9 = VAR_0->vga.get_bpp(&VAR_0->vga) / 8; VAR_0->vga.get_resolution(&VAR_0->vga, &VAR_11, &VAR_12); VAR_5 = (VAR_2 % ABS(VAR_0->cirrus_blt_srcpitch)) / VAR_9; VAR_6 = (VAR_2 / ABS(VAR_0->cirrus_blt_srcpitch)); VAR_7 = (VAR_1 % ABS(VAR_0->cirrus_blt_dstpitch)) / VAR_9; VAR_8 = (VAR_1 / ABS(VAR_0->cirrus_blt_dstpitch)); VAR_3 /= VAR_9; if (VAR_0->cirrus_blt_dstpitch < 0) { VAR_5 -= (VAR_0->cirrus_blt_width / VAR_9) - 1; VAR_7 -= (VAR_0->cirrus_blt_width / VAR_9) - 1; VAR_6 -= VAR_0->cirrus_blt_height - 1; VAR_8 -= VAR_0->cirrus_blt_height - 1; } if (VAR_5 >= 0 && VAR_6 >= 0 && VAR_7 >= 0 && VAR_8 >= 0 &&
(VAR_5 + VAR_3) <= VAR_11 && (VAR_6 + VAR_4) <= VAR_12 &&
(VAR_7 + VAR_3) <= VAR_11 && (VAR_8 + VAR_4) <= VAR_12) { VAR_10 = 1; } } if (VAR_10)
graphic_hw_update(VAR_0->vga.con); (*VAR_0->cirrus_rop) (VAR_0, VAR_0->vga.vram_ptr +
(VAR_0->cirrus_blt_dstaddr & VAR_0->cirrus_addr_mask),
VAR_0->vga.vram_ptr +
(VAR_0->cirrus_blt_srcaddr & VAR_0->cirrus_addr_mask),
VAR_0->cirrus_blt_dstpitch, VAR_0->cirrus_blt_srcpitch,
VAR_0->cirrus_blt_width, VAR_0->cirrus_blt_height); if (VAR_10) { qemu_console_copy(VAR_0->vga.con,
VAR_5, VAR_6, VAR_7, VAR_8,
VAR_0->cirrus_blt_width / VAR_9,
VAR_0->cirrus_blt_height); } cirrus_invalidate_region(VAR_0, VAR_0->cirrus_blt_dstaddr,
VAR_0->cirrus_blt_dstpitch, VAR_0->cirrus_blt_width,
VAR_0->cirrus_blt_height); }