static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)

{

    RTL8139State *s = opaque;



    addr &= 0xfc;



    switch (addr)

    {

        case RxMissed:

            DPRINTF("RxMissed clearing on write\n");

            s->RxMissed = 0;

            break;



        case TxConfig:

            rtl8139_TxConfig_write(s, val);

            break;



        case RxConfig:

            rtl8139_RxConfig_write(s, val);

            break;



        case TxStatus0 ... TxStatus0+4*4-1:

            rtl8139_TxStatus_write(s, addr-TxStatus0, val);

            break;



        case TxAddr0 ... TxAddr0+4*4-1:

            rtl8139_TxAddr_write(s, addr-TxAddr0, val);

            break;



        case RxBuf:

            rtl8139_RxBuf_write(s, val);

            break;



        case RxRingAddrLO:

            DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);

            s->RxRingAddrLO = val;

            break;



        case RxRingAddrHI:

            DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);

            s->RxRingAddrHI = val;

            break;



        case Timer:

            DPRINTF("TCTR Timer reset on write\n");

            s->TCTR_base = qemu_get_clock_ns(vm_clock);

            rtl8139_set_next_tctr_time(s, s->TCTR_base);

            break;



        case FlashReg:

            DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);

            if (s->TimerInt != val) {

                s->TimerInt = val;

                rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));

            }

            break;



        default:

            DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",

                addr, val);

            rtl8139_io_writeb(opaque, addr, val & 0xff);

            rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);

            rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);

            rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);

            break;

    }

}

static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)

{

    RTL8139State *s = opaque;



    addr &= 0xfc;



    switch (addr)

    {

        case RxMissed:

            DPRINTF("RxMissed clearing on write\n");

            s->RxMissed = 0;

            break;



        case TxConfig:

            rtl8139_TxConfig_write(s, val);

            break;



        case RxConfig:

            rtl8139_RxConfig_write(s, val);

            break;



        case TxStatus0 ... TxStatus0+4*4-1:

            rtl8139_TxStatus_write(s, addr-TxStatus0, val);

            break;



        case TxAddr0 ... TxAddr0+4*4-1:

            rtl8139_TxAddr_write(s, addr-TxAddr0, val);

            break;



        case RxBuf:

            rtl8139_RxBuf_write(s, val);

            break;



        case RxRingAddrLO:

            DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);

            s->RxRingAddrLO = val;

            break;



        case RxRingAddrHI:

            DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);

            s->RxRingAddrHI = val;

            break;



        case Timer:

            DPRINTF("TCTR Timer reset on write\n");

            s->TCTR_base = qemu_get_clock_ns(vm_clock);

            rtl8139_set_next_tctr_time(s, s->TCTR_base);

            break;



        case FlashReg:

            DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);

            if (s->TimerInt != val) {

                s->TimerInt = val;

                rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));

            }

            break;



        default:

            DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",

                addr, val);

            rtl8139_io_writeb(opaque, addr, val & 0xff);

            rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);

            rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);

            rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);

            break;

    }

}

    addr &= 0xfc;
static void FUNC_0(void *VAR_0, uint8_t VAR_1, uint32_t VAR_2)

{

    RTL8139State *s = VAR_0;



    VAR_1 &= 0xfc;



    switch (VAR_1)

    {

        case RxMissed:

            DPRINTF("RxMissed clearing on write\n");

            s->RxMissed = 0;

            break;



        case TxConfig:

            rtl8139_TxConfig_write(s, VAR_2);

            break;



        case RxConfig:

            rtl8139_RxConfig_write(s, VAR_2);

            break;



        case TxStatus0 ... TxStatus0+4*4-1:

            rtl8139_TxStatus_write(s, VAR_1-TxStatus0, VAR_2);

            break;



        case TxAddr0 ... TxAddr0+4*4-1:

            rtl8139_TxAddr_write(s, VAR_1-TxAddr0, VAR_2);

            break;



        case RxBuf:

            rtl8139_RxBuf_write(s, VAR_2);

            break;



        case RxRingAddrLO:

            DPRINTF("C+ RxRing low bits write VAR_2=0x%08x\n", VAR_2);

            s->RxRingAddrLO = VAR_2;

            break;



        case RxRingAddrHI:

            DPRINTF("C+ RxRing high bits write VAR_2=0x%08x\n", VAR_2);

            s->RxRingAddrHI = VAR_2;

            break;



        case Timer:

            DPRINTF("TCTR Timer reset on write\n");

            s->TCTR_base = qemu_get_clock_ns(vm_clock);

            rtl8139_set_next_tctr_time(s, s->TCTR_base);

            break;



        case FlashReg:

            DPRINTF("FlashReg TimerInt write VAR_2=0x%08x\n", VAR_2);

            if (s->TimerInt != VAR_2) {

                s->TimerInt = VAR_2;

                rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));

            }

            break;



        default:

            DPRINTF("ioport write(l) VAR_1=0x%x VAR_2=0x%08x via write(b)\n",

                VAR_1, VAR_2);

            rtl8139_io_writeb(VAR_0, VAR_1, VAR_2 & 0xff);

            rtl8139_io_writeb(VAR_0, VAR_1 + 1, (VAR_2 >> 8) & 0xff);

            rtl8139_io_writeb(VAR_0, VAR_1 + 2, (VAR_2 >> 16) & 0xff);

            rtl8139_io_writeb(VAR_0, VAR_1 + 3, (VAR_2 >> 24) & 0xff);

            break;

    }

}

static void FUNC_0(void *VAR_0, uint8_t VAR_1, uint32_t VAR_2)
{ RTL8139State *s = VAR_0; VAR_1 &= 0xfc; switch (VAR_1)
{ case RxMissed:
DPRINTF("RxMissed clearing on write\n"); s->RxMissed = 0; break; case TxConfig:
rtl8139_TxConfig_write(s, VAR_2); break; case RxConfig:
rtl8139_RxConfig_write(s, VAR_2); break; case TxStatus0 ... TxStatus0+4*4-1:
rtl8139_TxStatus_write(s, VAR_1-TxStatus0, VAR_2); break; case TxAddr0 ... TxAddr0+4*4-1:
rtl8139_TxAddr_write(s, VAR_1-TxAddr0, VAR_2); break; case RxBuf:
rtl8139_RxBuf_write(s, VAR_2); break; case RxRingAddrLO:
DPRINTF("C+ RxRing low bits write VAR_2=0x%08x\n", VAR_2); s->RxRingAddrLO = VAR_2; break; case RxRingAddrHI:
DPRINTF("C+ RxRing high bits write VAR_2=0x%08x\n", VAR_2); s->RxRingAddrHI = VAR_2; break; case Timer:
DPRINTF("TCTR Timer reset on write\n"); s->TCTR_base = qemu_get_clock_ns(vm_clock); rtl8139_set_next_tctr_time(s, s->TCTR_base); break; case FlashReg:
DPRINTF("FlashReg TimerInt write VAR_2=0x%08x\n", VAR_2); if (s->TimerInt != VAR_2) { s->TimerInt = VAR_2; rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); } break; default:
DPRINTF("ioport write(l) VAR_1=0x%x VAR_2=0x%08x via write(b)\n",
VAR_1, VAR_2); rtl8139_io_writeb(VAR_0, VAR_1, VAR_2 & 0xff); rtl8139_io_writeb(VAR_0, VAR_1 + 1, (VAR_2 >> 8) & 0xff); rtl8139_io_writeb(VAR_0, VAR_1 + 2, (VAR_2 >> 16) & 0xff); rtl8139_io_writeb(VAR_0, VAR_1 + 3, (VAR_2 >> 24) & 0xff); break; } }