static void gic_reset(gic_state *s)

{

    int i;

    memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));

    for (i = 0 ; i < NUM_CPU(s); i++) {

        s->priority_mask[i] = 0xf0;

        s->current_pending[i] = 1023;

        s->running_irq[i] = 1023;

        s->running_priority[i] = 0x100;

#ifdef NVIC

        /* The NVIC doesn't have per-cpu interfaces, so enable by default.  */

        s->cpu_enabled[i] = 1;

#else

        s->cpu_enabled[i] = 0;

#endif

    }

    for (i = 0; i < 16; i++) {

        GIC_SET_ENABLED(i);

        GIC_SET_TRIGGER(i);

    }

#ifdef NVIC

    /* The NVIC is always enabled.  */

    s->enabled = 1;

#else

    s->enabled = 0;

#endif

}

static void gic_reset(gic_state *s)

{

    int i;

    memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));

    for (i = 0 ; i < NUM_CPU(s); i++) {

        s->priority_mask[i] = 0xf0;

        s->current_pending[i] = 1023;

        s->running_irq[i] = 1023;

        s->running_priority[i] = 0x100;

#ifdef NVIC

        

        s->cpu_enabled[i] = 1;

#else

        s->cpu_enabled[i] = 0;

#endif

    }

    for (i = 0; i < 16; i++) {

        GIC_SET_ENABLED(i);

        GIC_SET_TRIGGER(i);

    }

#ifdef NVIC

    

    s->enabled = 1;

#else

    s->enabled = 0;

#endif

}

static void FUNC_0(gic_state *VAR_0)

{

    int VAR_1;

    memset(VAR_0->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));

    for (VAR_1 = 0 ; VAR_1 < NUM_CPU(VAR_0); VAR_1++) {

        VAR_0->priority_mask[VAR_1] = 0xf0;

        VAR_0->current_pending[VAR_1] = 1023;

        VAR_0->running_irq[VAR_1] = 1023;

        VAR_0->running_priority[VAR_1] = 0x100;

#ifdef NVIC

        

        VAR_0->cpu_enabled[VAR_1] = 1;

#else

        VAR_0->cpu_enabled[VAR_1] = 0;

#endif

    }

    for (VAR_1 = 0; VAR_1 < 16; VAR_1++) {

        GIC_SET_ENABLED(VAR_1);

        GIC_SET_TRIGGER(VAR_1);

    }

#ifdef NVIC

    

    VAR_0->enabled = 1;

#else

    VAR_0->enabled = 0;

#endif

}

static void FUNC_0(gic_state *VAR_0)
{ int VAR_1; memset(VAR_0->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state)); for (VAR_1 = 0 ; VAR_1 < NUM_CPU(VAR_0); VAR_1++) { VAR_0->priority_mask[VAR_1] = 0xf0; VAR_0->current_pending[VAR_1] = 1023; VAR_0->running_irq[VAR_1] = 1023; VAR_0->running_priority[VAR_1] = 0x100; #ifdef NVIC
VAR_0->cpu_enabled[VAR_1] = 1; #else
VAR_0->cpu_enabled[VAR_1] = 0; #endif
} for (VAR_1 = 0; VAR_1 < 16; VAR_1++) { GIC_SET_ENABLED(VAR_1); GIC_SET_TRIGGER(VAR_1); } #ifdef NVIC
VAR_0->enabled = 1; #else
VAR_0->enabled = 0; #endif
}