void armv7m_nvic_acknowledge_irq(void *opaque)

{

    NVICState *s = (NVICState *)opaque;

    CPUARMState *env = &s->cpu->env;

    const int pending = s->vectpending;

    const int running = nvic_exec_prio(s);

    int pendgroupprio;

    VecInfo *vec;



    assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);



    vec = &s->vectors[pending];



    assert(vec->enabled);

    assert(vec->pending);



    pendgroupprio = vec->prio;

    if (pendgroupprio > 0) {

        pendgroupprio &= nvic_gprio_mask(s);

    }

    assert(pendgroupprio < running);



    trace_nvic_acknowledge_irq(pending, vec->prio);



    vec->active = 1;

    vec->pending = 0;



    env->v7m.exception = s->vectpending;



    nvic_irq_update(s);

}

void armv7m_nvic_acknowledge_irq(void *opaque)

{

    NVICState *s = (NVICState *)opaque;

    CPUARMState *env = &s->cpu->env;

    const int pending = s->vectpending;

    const int running = nvic_exec_prio(s);

    int pendgroupprio;

    VecInfo *vec;



    assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);



    vec = &s->vectors[pending];



    assert(vec->enabled);

    assert(vec->pending);



    pendgroupprio = vec->prio;

    if (pendgroupprio > 0) {

        pendgroupprio &= nvic_gprio_mask(s);

    }

    assert(pendgroupprio < running);



    trace_nvic_acknowledge_irq(pending, vec->prio);



    vec->active = 1;

    vec->pending = 0;



    env->v7m.exception = s->vectpending;



    nvic_irq_update(s);

}

void FUNC_0(void *VAR_0)

{

    NVICState *s = (NVICState *)VAR_0;

    CPUARMState *env = &s->cpu->env;

    const int VAR_1 = s->vectpending;

    const int VAR_2 = nvic_exec_prio(s);

    int VAR_3;

    VecInfo *vec;



    assert(VAR_1 > ARMV7M_EXCP_RESET && VAR_1 < s->num_irq);



    vec = &s->vectors[VAR_1];



    assert(vec->enabled);

    assert(vec->VAR_1);



    VAR_3 = vec->prio;

    if (VAR_3 > 0) {

        VAR_3 &= nvic_gprio_mask(s);

    }

    assert(VAR_3 < VAR_2);



    trace_nvic_acknowledge_irq(VAR_1, vec->prio);



    vec->active = 1;

    vec->VAR_1 = 0;



    env->v7m.exception = s->vectpending;



    nvic_irq_update(s);

}

void FUNC_0(void *VAR_0)
{ NVICState *s = (NVICState *)VAR_0; CPUARMState *env = &s->cpu->env; const int VAR_1 = s->vectpending; const int VAR_2 = nvic_exec_prio(s); int VAR_3; VecInfo *vec; assert(VAR_1 > ARMV7M_EXCP_RESET && VAR_1 < s->num_irq); vec = &s->vectors[VAR_1]; assert(vec->enabled); assert(vec->VAR_1); VAR_3 = vec->prio; if (VAR_3 > 0) { VAR_3 &= nvic_gprio_mask(s); } assert(VAR_3 < VAR_2); trace_nvic_acknowledge_irq(VAR_1, vec->prio); vec->active = 1; vec->VAR_1 = 0; env->v7m.exception = s->vectpending; nvic_irq_update(s); }