static void imx_serial_write(void *opaque, hwaddr offset,

                             uint64_t value, unsigned size)

{

    IMXSerialState *s = (IMXSerialState *)opaque;

    unsigned char ch;



    DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",

            offset, (unsigned int)value, s->chr ? s->chr->label : "NODEV");



    switch (offset >> 2) {

    case 0x10: /* UTXD */

        ch = value;

        if (s->ucr2 & UCR2_TXEN) {

            if (s->chr) {

                qemu_chr_fe_write(s->chr, &ch, 1);

            }

            s->usr1 &= ~USR1_TRDY;

            imx_update(s);

            s->usr1 |= USR1_TRDY;

            imx_update(s);

        }

        break;



    case 0x20: /* UCR1 */

        s->ucr1 = value & 0xffff;



        DPRINTF("write(ucr1=%x)\n", (unsigned int)value);



        imx_update(s);

        break;



    case 0x21: /* UCR2 */

        /*

         * Only a few bits in control register 2 are implemented as yet.

         * If it's intended to use a real serial device as a back-end, this

         * register will have to be implemented more fully.

         */

        if (!(value & UCR2_SRST)) {

            imx_serial_reset(s);

            imx_update(s);

            value |= UCR2_SRST;

        }

        if (value & UCR2_RXEN) {

            if (!(s->ucr2 & UCR2_RXEN)) {

                if (s->chr) {

                    qemu_chr_accept_input(s->chr);

                }

            }

        }

        s->ucr2 = value & 0xffff;

        break;



    case 0x25: /* USR1 */

        value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |

                 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;

        s->usr1 &= ~value;

        break;



    case 0x26: /* USR2 */

        /*

         * Writing 1 to some bits clears them; all other

         * values are ignored

         */

        value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |

                 USR2_RIDELT | USR2_IRINT | USR2_WAKE |

                 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;

        s->usr2 &= ~value;

        break;



    /*

     * Linux expects to see what it writes to these registers

     * We don't currently alter the baud rate

     */

    case 0x29: /* UBIR */

        s->ubrc = value & 0xffff;

        break;



    case 0x2a: /* UBMR */

        s->ubmr = value & 0xffff;

        break;



    case 0x2c: /* One ms reg */

        s->onems = value & 0xffff;

        break;



    case 0x24: /* FIFO control register */

        s->ufcr = value & 0xffff;

        break;



    case 0x22: /* UCR3 */

        s->ucr3 = value & 0xffff;

        break;



    case 0x2d: /* UTS1 */

    case 0x23: /* UCR4 */

        qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"

                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);

        /* TODO */

        break;



    default:

        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"

                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);

    }

}

static void imx_serial_write(void *opaque, hwaddr offset,

                             uint64_t value, unsigned size)

{

    IMXSerialState *s = (IMXSerialState *)opaque;

    unsigned char ch;



    DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",

            offset, (unsigned int)value, s->chr ? s->chr->label : "NODEV");



    switch (offset >> 2) {

    case 0x10: 

        ch = value;

        if (s->ucr2 & UCR2_TXEN) {

            if (s->chr) {

                qemu_chr_fe_write(s->chr, &ch, 1);

            }

            s->usr1 &= ~USR1_TRDY;

            imx_update(s);

            s->usr1 |= USR1_TRDY;

            imx_update(s);

        }

        break;



    case 0x20: 

        s->ucr1 = value & 0xffff;



        DPRINTF("write(ucr1=%x)\n", (unsigned int)value);



        imx_update(s);

        break;



    case 0x21: 

        









        if (!(value & UCR2_SRST)) {

            imx_serial_reset(s);

            imx_update(s);

            value |= UCR2_SRST;

        }

        if (value & UCR2_RXEN) {

            if (!(s->ucr2 & UCR2_RXEN)) {

                if (s->chr) {

                    qemu_chr_accept_input(s->chr);

                }

            }

        }

        s->ucr2 = value & 0xffff;

        break;



    case 0x25: 

        value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |

                 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;

        s->usr1 &= ~value;

        break;



    case 0x26: 

        







        value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |

                 USR2_RIDELT | USR2_IRINT | USR2_WAKE |

                 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;

        s->usr2 &= ~value;

        break;



    







    case 0x29: 

        s->ubrc = value & 0xffff;

        break;



    case 0x2a: 

        s->ubmr = value & 0xffff;

        break;



    case 0x2c: 

        s->onems = value & 0xffff;

        break;



    case 0x24: 

        s->ufcr = value & 0xffff;

        break;



    case 0x22: 

        s->ucr3 = value & 0xffff;

        break;



    case 0x2d: 

    case 0x23: 

        qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"

                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);

        

        break;



    default:

        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"

                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);

    }

}

                qemu_chr_fe_write(s->chr, &ch, 1);                 qemu_chr_fe_write(s->chr, &ch, 1);
static void FUNC_0(void *VAR_0, hwaddr VAR_1,

                             uint64_t VAR_2, unsigned VAR_3)

{

    IMXSerialState *s = (IMXSerialState *)VAR_0;

    unsigned char VAR_4;



    DPRINTF("write(VAR_1=0x%" HWADDR_PRIx ", VAR_2 = 0x%x) to %s\n",

            VAR_1, (unsigned int)VAR_2, s->chr ? s->chr->label : "NODEV");



    switch (VAR_1 >> 2) {

    case 0x10: 

        VAR_4 = VAR_2;

        if (s->ucr2 & UCR2_TXEN) {

            if (s->chr) {

                qemu_chr_fe_write(s->chr, &VAR_4, 1);

            }

            s->usr1 &= ~USR1_TRDY;

            imx_update(s);

            s->usr1 |= USR1_TRDY;

            imx_update(s);

        }

        break;



    case 0x20: 

        s->ucr1 = VAR_2 & 0xffff;



        DPRINTF("write(ucr1=%x)\n", (unsigned int)VAR_2);



        imx_update(s);

        break;



    case 0x21: 

        









        if (!(VAR_2 & UCR2_SRST)) {

            imx_serial_reset(s);

            imx_update(s);

            VAR_2 |= UCR2_SRST;

        }

        if (VAR_2 & UCR2_RXEN) {

            if (!(s->ucr2 & UCR2_RXEN)) {

                if (s->chr) {

                    qemu_chr_accept_input(s->chr);

                }

            }

        }

        s->ucr2 = VAR_2 & 0xffff;

        break;



    case 0x25: 

        VAR_2 &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |

                 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;

        s->usr1 &= ~VAR_2;

        break;



    case 0x26: 

        







        VAR_2 &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |

                 USR2_RIDELT | USR2_IRINT | USR2_WAKE |

                 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;

        s->usr2 &= ~VAR_2;

        break;



    







    case 0x29: 

        s->ubrc = VAR_2 & 0xffff;

        break;



    case 0x2a: 

        s->ubmr = VAR_2 & 0xffff;

        break;



    case 0x2c: 

        s->onems = VAR_2 & 0xffff;

        break;



    case 0x24: 

        s->ufcr = VAR_2 & 0xffff;

        break;



    case 0x22: 

        s->ucr3 = VAR_2 & 0xffff;

        break;



    case 0x2d: 

    case 0x23: 

        qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"

                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, VAR_1);

        

        break;



    default:

        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at VAR_1 0x%"

                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, VAR_1);

    }

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ IMXSerialState *s = (IMXSerialState *)VAR_0; unsigned char VAR_4; DPRINTF("write(VAR_1=0x%" HWADDR_PRIx ", VAR_2 = 0x%x) to %s\n",
VAR_1, (unsigned int)VAR_2, s->chr ? s->chr->label : "NODEV"); switch (VAR_1 >> 2) { case 0x10:
VAR_4 = VAR_2; if (s->ucr2 & UCR2_TXEN) { if (s->chr) { qemu_chr_fe_write(s->chr, &VAR_4, 1); } s->usr1 &= ~USR1_TRDY; imx_update(s); s->usr1 |= USR1_TRDY; imx_update(s); } break; case 0x20:
s->ucr1 = VAR_2 & 0xffff; DPRINTF("write(ucr1=%x)\n", (unsigned int)VAR_2); imx_update(s); break; case 0x21:
if (!(VAR_2 & UCR2_SRST)) { imx_serial_reset(s); imx_update(s); VAR_2 |= UCR2_SRST; } if (VAR_2 & UCR2_RXEN) { if (!(s->ucr2 & UCR2_RXEN)) { if (s->chr) { qemu_chr_accept_input(s->chr); } } } s->ucr2 = VAR_2 & 0xffff; break; case 0x25:
VAR_2 &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |
USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; s->usr1 &= ~VAR_2; break; case 0x26:
VAR_2 &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |
USR2_RIDELT | USR2_IRINT | USR2_WAKE |
USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; s->usr2 &= ~VAR_2; break; case 0x29:
s->ubrc = VAR_2 & 0xffff; break; case 0x2a:
s->ubmr = VAR_2 & 0xffff; break; case 0x2c:
s->onems = VAR_2 & 0xffff; break; case 0x24:
s->ufcr = VAR_2 & 0xffff; break; case 0x22:
s->ucr3 = VAR_2 & 0xffff; break; case 0x2d:
case 0x23:
qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, VAR_1); break; default:
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at VAR_1 0x%"
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, VAR_1); } }