static void mem_info_32(Monitor *mon, CPUState *env)

{

    int l1, l2, prot, last_prot;

    uint32_t pgd, pde, pte;

    target_phys_addr_t start, end;



    pgd = env->cr[3] & ~0xfff;

    last_prot = 0;

    start = -1;

    for(l1 = 0; l1 < 1024; l1++) {

        cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);

        pde = le32_to_cpu(pde);

        end = l1 << 22;

        if (pde & PG_PRESENT_MASK) {

            if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {

                prot = pde & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);

                mem_print(mon, &start, &last_prot, end, prot);

            } else {

                for(l2 = 0; l2 < 1024; l2++) {

                    cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);

                    pte = le32_to_cpu(pte);

                    end = (l1 << 22) + (l2 << 12);

                    if (pte & PG_PRESENT_MASK) {

                        prot = pte & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);

                    } else {

                        prot = 0;

                    }

                    mem_print(mon, &start, &last_prot, end, prot);

                }

            }

        } else {

            prot = 0;

            mem_print(mon, &start, &last_prot, end, prot);

        }

    }

}

static void mem_info_32(Monitor *mon, CPUState *env)

{

    int l1, l2, prot, last_prot;

    uint32_t pgd, pde, pte;

    target_phys_addr_t start, end;



    pgd = env->cr[3] & ~0xfff;

    last_prot = 0;

    start = -1;

    for(l1 = 0; l1 < 1024; l1++) {

        cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);

        pde = le32_to_cpu(pde);

        end = l1 << 22;

        if (pde & PG_PRESENT_MASK) {

            if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {

                prot = pde & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);

                mem_print(mon, &start, &last_prot, end, prot);

            } else {

                for(l2 = 0; l2 < 1024; l2++) {

                    cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);

                    pte = le32_to_cpu(pte);

                    end = (l1 << 22) + (l2 << 12);

                    if (pte & PG_PRESENT_MASK) {

                        prot = pte & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);

                    } else {

                        prot = 0;

                    }

                    mem_print(mon, &start, &last_prot, end, prot);

                }

            }

        } else {

            prot = 0;

            mem_print(mon, &start, &last_prot, end, prot);

        }

    }

}

static void FUNC_0(Monitor *VAR_0, CPUState *VAR_1)

{

    int VAR_2, VAR_3, VAR_4, VAR_5;

    uint32_t pgd, pde, pte;

    target_phys_addr_t start, end;



    pgd = VAR_1->cr[3] & ~0xfff;

    VAR_5 = 0;

    start = -1;

    for(VAR_2 = 0; VAR_2 < 1024; VAR_2++) {

        cpu_physical_memory_read(pgd + VAR_2 * 4, &pde, 4);

        pde = le32_to_cpu(pde);

        end = VAR_2 << 22;

        if (pde & PG_PRESENT_MASK) {

            if ((pde & PG_PSE_MASK) && (VAR_1->cr[4] & CR4_PSE_MASK)) {

                VAR_4 = pde & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);

                mem_print(VAR_0, &start, &VAR_5, end, VAR_4);

            } else {

                for(VAR_3 = 0; VAR_3 < 1024; VAR_3++) {

                    cpu_physical_memory_read((pde & ~0xfff) + VAR_3 * 4, &pte, 4);

                    pte = le32_to_cpu(pte);

                    end = (VAR_2 << 22) + (VAR_3 << 12);

                    if (pte & PG_PRESENT_MASK) {

                        VAR_4 = pte & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);

                    } else {

                        VAR_4 = 0;

                    }

                    mem_print(VAR_0, &start, &VAR_5, end, VAR_4);

                }

            }

        } else {

            VAR_4 = 0;

            mem_print(VAR_0, &start, &VAR_5, end, VAR_4);

        }

    }

}

static void FUNC_0(Monitor *VAR_0, CPUState *VAR_1)
{ int VAR_2, VAR_3, VAR_4, VAR_5; uint32_t pgd, pde, pte; target_phys_addr_t start, end; pgd = VAR_1->cr[3] & ~0xfff; VAR_5 = 0; start = -1; for(VAR_2 = 0; VAR_2 < 1024; VAR_2++) { cpu_physical_memory_read(pgd + VAR_2 * 4, &pde, 4); pde = le32_to_cpu(pde); end = VAR_2 << 22; if (pde & PG_PRESENT_MASK) { if ((pde & PG_PSE_MASK) && (VAR_1->cr[4] & CR4_PSE_MASK)) { VAR_4 = pde & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK); mem_print(VAR_0, &start, &VAR_5, end, VAR_4); } else { for(VAR_3 = 0; VAR_3 < 1024; VAR_3++) { cpu_physical_memory_read((pde & ~0xfff) + VAR_3 * 4, &pte, 4); pte = le32_to_cpu(pte); end = (VAR_2 << 22) + (VAR_3 << 12); if (pte & PG_PRESENT_MASK) { VAR_4 = pte & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK); } else { VAR_4 = 0; } mem_print(VAR_0, &start, &VAR_5, end, VAR_4); } } } else { VAR_4 = 0; mem_print(VAR_0, &start, &VAR_5, end, VAR_4); } } }