void *etraxfs_dmac_init(CPUState *env, 

			target_phys_addr_t base, int nr_channels)

{

	struct fs_dma_ctrl *ctrl = NULL;

	int i;



	ctrl = qemu_mallocz(sizeof *ctrl);

	if (!ctrl)

		return NULL;



	ctrl->base = base;

	ctrl->env = env;

	ctrl->nr_channels = nr_channels;

	ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);

	if (!ctrl->channels)

		goto err;



	for (i = 0; i < nr_channels; i++)

	{

		ctrl->channels[i].regmap = cpu_register_io_memory(0,

								  dma_read, 

								  dma_write, 

								  ctrl);

		cpu_register_physical_memory (base + i * 0x2000,

					      sizeof ctrl->channels[i].regs, 

					      ctrl->channels[i].regmap);

	}



	/* Hax, we only support one DMA controller at a time.  */

	etraxfs_dmac = ctrl;

	return ctrl;

  err:

	qemu_free(ctrl->channels);

	qemu_free(ctrl);

	return NULL;

}

void *etraxfs_dmac_init(CPUState *env, 

			target_phys_addr_t base, int nr_channels)

{

	struct fs_dma_ctrl *ctrl = NULL;

	int i;



	ctrl = qemu_mallocz(sizeof *ctrl);

	if (!ctrl)

		return NULL;



	ctrl->base = base;

	ctrl->env = env;

	ctrl->nr_channels = nr_channels;

	ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);

	if (!ctrl->channels)

		goto err;



	for (i = 0; i < nr_channels; i++)

	{

		ctrl->channels[i].regmap = cpu_register_io_memory(0,

								  dma_read, 

								  dma_write, 

								  ctrl);

		cpu_register_physical_memory (base + i * 0x2000,

					      sizeof ctrl->channels[i].regs, 

					      ctrl->channels[i].regmap);

	}



	

	etraxfs_dmac = ctrl;

	return ctrl;

  err:

	qemu_free(ctrl->channels);

	qemu_free(ctrl);

	return NULL;

}

void *FUNC_0(CPUState *VAR_0, 

			target_phys_addr_t VAR_1, int VAR_2)

{

	struct fs_dma_ctrl *VAR_3 = NULL;

	int VAR_4;



	VAR_3 = qemu_mallocz(sizeof *VAR_3);

	if (!VAR_3)

		return NULL;



	VAR_3->VAR_1 = VAR_1;

	VAR_3->VAR_0 = VAR_0;

	VAR_3->VAR_2 = VAR_2;

	VAR_3->channels = qemu_mallocz(sizeof VAR_3->channels[0] * VAR_2);

	if (!VAR_3->channels)

		goto err;



	for (VAR_4 = 0; VAR_4 < VAR_2; VAR_4++)

	{

		VAR_3->channels[VAR_4].regmap = cpu_register_io_memory(0,

								  dma_read, 

								  dma_write, 

								  VAR_3);

		cpu_register_physical_memory (VAR_1 + VAR_4 * 0x2000,

					      sizeof VAR_3->channels[VAR_4].regs, 

					      VAR_3->channels[VAR_4].regmap);

	}



	

	etraxfs_dmac = VAR_3;

	return VAR_3;

  err:

	qemu_free(VAR_3->channels);

	qemu_free(VAR_3);

	return NULL;

}

void *FUNC_0(CPUState *VAR_0,
target_phys_addr_t VAR_1, int VAR_2)
{ struct fs_dma_ctrl *VAR_3 = NULL; int VAR_4; VAR_3 = qemu_mallocz(sizeof *VAR_3); if (!VAR_3)
return NULL; VAR_3->VAR_1 = VAR_1; VAR_3->VAR_0 = VAR_0; VAR_3->VAR_2 = VAR_2; VAR_3->channels = qemu_mallocz(sizeof VAR_3->channels[0] * VAR_2); if (!VAR_3->channels)
goto err; for (VAR_4 = 0; VAR_4 < VAR_2; VAR_4++) { VAR_3->channels[VAR_4].regmap = cpu_register_io_memory(0,
dma_read,
dma_write,
VAR_3); cpu_register_physical_memory (VAR_1 + VAR_4 * 0x2000,
sizeof VAR_3->channels[VAR_4].regs,
VAR_3->channels[VAR_4].regmap); } etraxfs_dmac = VAR_3; return VAR_3; err:
qemu_free(VAR_3->channels); qemu_free(VAR_3); return NULL; }