int ff_get_cpu_flags_x86(void)

{

    int rval = 0;

    int eax, ebx, ecx, edx;

    int max_std_level, max_ext_level, std_caps=0, ext_caps=0;

    int family=0, model=0;

    union { int i[3]; char c[12]; } vendor;



#if ARCH_X86_32

    x86_reg a, c;

    __asm__ volatile (

        /* See if CPUID instruction is supported ... */

        /* ... Get copies of EFLAGS into eax and ecx */

        "pushfl\n\t"

        "pop %0\n\t"

        "mov %0, %1\n\t"



        /* ... Toggle the ID bit in one copy and store */

        /*     to the EFLAGS reg */

        "xor $0x200000, %0\n\t"

        "push %0\n\t"

        "popfl\n\t"



        /* ... Get the (hopefully modified) EFLAGS */

        "pushfl\n\t"

        "pop %0\n\t"

        : "=a" (a), "=c" (c)

        :

        : "cc"

        );



    if (a == c)

        return 0; /* CPUID not supported */

#endif



    cpuid(0, max_std_level, vendor.i[0], vendor.i[2], vendor.i[1]);



    if(max_std_level >= 1){

        cpuid(1, eax, ebx, ecx, std_caps);

        family = ((eax>>8)&0xf) + ((eax>>20)&0xff);

        model  = ((eax>>4)&0xf) + ((eax>>12)&0xf0);

        if (std_caps & (1<<23))

            rval |= AV_CPU_FLAG_MMX;

        if (std_caps & (1<<25))

            rval |= AV_CPU_FLAG_MMX2

#if HAVE_SSE

                  | AV_CPU_FLAG_SSE;

        if (std_caps & (1<<26))

            rval |= AV_CPU_FLAG_SSE2;

        if (ecx & 1)

            rval |= AV_CPU_FLAG_SSE3;

        if (ecx & 0x00000200 )

            rval |= AV_CPU_FLAG_SSSE3;

        if (ecx & 0x00080000 )

            rval |= AV_CPU_FLAG_SSE4;

        if (ecx & 0x00100000 )

            rval |= AV_CPU_FLAG_SSE42;

#if HAVE_AVX

        /* Check OXSAVE and AVX bits */

        if ((ecx & 0x18000000) == 0x18000000) {

            /* Check for OS support */

            xgetbv(0, eax, edx);

            if ((eax & 0x6) == 0x6)

                rval |= AV_CPU_FLAG_AVX;

        }

#endif

#endif

                  ;

    }



    cpuid(0x80000000, max_ext_level, ebx, ecx, edx);



    if(max_ext_level >= 0x80000001){

        cpuid(0x80000001, eax, ebx, ecx, ext_caps);

        if (ext_caps & (1<<31))

            rval |= AV_CPU_FLAG_3DNOW;

        if (ext_caps & (1<<30))

            rval |= AV_CPU_FLAG_3DNOWEXT;

        if (ext_caps & (1<<23))

            rval |= AV_CPU_FLAG_MMX;

        if (ext_caps & (1<<22))

            rval |= AV_CPU_FLAG_MMX2;



        /* Allow for selectively disabling SSE2 functions on AMD processors

           with SSE2 support but not SSE4a. This includes Athlon64, some

           Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster

           than SSE2 often enough to utilize this special-case flag.

           AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case

           so that SSE2 is used unless explicitly disabled by checking

           AV_CPU_FLAG_SSE2SLOW. */

        if (!strncmp(vendor.c, "AuthenticAMD", 12) &&

            rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) {

            rval |= AV_CPU_FLAG_SSE2SLOW;

        }

    }



    if (!strncmp(vendor.c, "GenuineIntel", 12)) {

        if (family == 6 && (model == 9 || model == 13 || model == 14)) {

            /* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and 6/14 (core1 "yonah")

            * theoretically support sse2, but it's usually slower than mmx,

            * so let's just pretend they don't. AV_CPU_FLAG_SSE2 is disabled and

            * AV_CPU_FLAG_SSE2SLOW is enabled so that SSE2 is not used unless

            * explicitly enabled by checking AV_CPU_FLAG_SSE2SLOW. The same

            * situation applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */

            if (rval & AV_CPU_FLAG_SSE2) rval ^= AV_CPU_FLAG_SSE2SLOW|AV_CPU_FLAG_SSE2;

            if (rval & AV_CPU_FLAG_SSE3) rval ^= AV_CPU_FLAG_SSE3SLOW|AV_CPU_FLAG_SSE3;

        }

        /* The Atom processor has SSSE3 support, which is useful in many cases,

         * but sometimes the SSSE3 version is slower than the SSE2 equivalent

         * on the Atom, but is generally faster on other processors supporting

         * SSSE3. This flag allows for selectively disabling certain SSSE3

         * functions on the Atom. */

        if (family == 6 && model == 28)

            rval |= AV_CPU_FLAG_ATOM;

    }



    return rval;

}

int ff_get_cpu_flags_x86(void)

{

    int rval = 0;

    int eax, ebx, ecx, edx;

    int max_std_level, max_ext_level, std_caps=0, ext_caps=0;

    int family=0, model=0;

    union { int i[3]; char c[12]; } vendor;



#if ARCH_X86_32

    x86_reg a, c;

    __asm__ volatile (

        

        

        "pushfl\n\t"

        "pop %0\n\t"

        "mov %0, %1\n\t"



        

        

        "xor $0x200000, %0\n\t"

        "push %0\n\t"

        "popfl\n\t"



        

        "pushfl\n\t"

        "pop %0\n\t"

        : "=a" (a), "=c" (c)

        :

        : "cc"

        );



    if (a == c)

        return 0; 

#endif



    cpuid(0, max_std_level, vendor.i[0], vendor.i[2], vendor.i[1]);



    if(max_std_level >= 1){

        cpuid(1, eax, ebx, ecx, std_caps);

        family = ((eax>>8)&0xf) + ((eax>>20)&0xff);

        model  = ((eax>>4)&0xf) + ((eax>>12)&0xf0);

        if (std_caps & (1<<23))

            rval |= AV_CPU_FLAG_MMX;

        if (std_caps & (1<<25))

            rval |= AV_CPU_FLAG_MMX2

#if HAVE_SSE

                  | AV_CPU_FLAG_SSE;

        if (std_caps & (1<<26))

            rval |= AV_CPU_FLAG_SSE2;

        if (ecx & 1)

            rval |= AV_CPU_FLAG_SSE3;

        if (ecx & 0x00000200 )

            rval |= AV_CPU_FLAG_SSSE3;

        if (ecx & 0x00080000 )

            rval |= AV_CPU_FLAG_SSE4;

        if (ecx & 0x00100000 )

            rval |= AV_CPU_FLAG_SSE42;

#if HAVE_AVX

        

        if ((ecx & 0x18000000) == 0x18000000) {

            

            xgetbv(0, eax, edx);

            if ((eax & 0x6) == 0x6)

                rval |= AV_CPU_FLAG_AVX;

        }

#endif

#endif

                  ;

    }



    cpuid(0x80000000, max_ext_level, ebx, ecx, edx);



    if(max_ext_level >= 0x80000001){

        cpuid(0x80000001, eax, ebx, ecx, ext_caps);

        if (ext_caps & (1<<31))

            rval |= AV_CPU_FLAG_3DNOW;

        if (ext_caps & (1<<30))

            rval |= AV_CPU_FLAG_3DNOWEXT;

        if (ext_caps & (1<<23))

            rval |= AV_CPU_FLAG_MMX;

        if (ext_caps & (1<<22))

            rval |= AV_CPU_FLAG_MMX2;



        













        if (!strncmp(vendor.c, "AuthenticAMD", 12) &&

            rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) {

            rval |= AV_CPU_FLAG_SSE2SLOW;

        }

    }



    if (!strncmp(vendor.c, "GenuineIntel", 12)) {

        if (family == 6 && (model == 9 || model == 13 || model == 14)) {

            











            if (rval & AV_CPU_FLAG_SSE2) rval ^= AV_CPU_FLAG_SSE2SLOW|AV_CPU_FLAG_SSE2;

            if (rval & AV_CPU_FLAG_SSE3) rval ^= AV_CPU_FLAG_SSE3SLOW|AV_CPU_FLAG_SSE3;

        }

        









        if (family == 6 && model == 28)

            rval |= AV_CPU_FLAG_ATOM;

    }



    return rval;

}

        if (ext_caps & (1<<31))
int FUNC_0(void)

{

    int VAR_0 = 0;

    int VAR_1, VAR_2, VAR_3, VAR_4;

    int VAR_5, VAR_6, VAR_7=0, VAR_8=0;

    int VAR_9=0, VAR_10=0;

    union { int i[3]; char c[12]; } VAR_11;



#if ARCH_X86_32

    x86_reg a, c;

    __asm__ volatile (

        

        

        "pushfl\n\t"

        "pop %0\n\t"

        "mov %0, %1\n\t"



        

        

        "xor $0x200000, %0\n\t"

        "push %0\n\t"

        "popfl\n\t"



        

        "pushfl\n\t"

        "pop %0\n\t"

        : "=a" (a), "=c" (c)

        :

        : "cc"

        );



    if (a == c)

        return 0; 

#endif



    cpuid(0, VAR_5, VAR_11.i[0], VAR_11.i[2], VAR_11.i[1]);



    if(VAR_5 >= 1){

        cpuid(1, VAR_1, VAR_2, VAR_3, VAR_7);

        VAR_9 = ((VAR_1>>8)&0xf) + ((VAR_1>>20)&0xff);

        VAR_10  = ((VAR_1>>4)&0xf) + ((VAR_1>>12)&0xf0);

        if (VAR_7 & (1<<23))

            VAR_0 |= AV_CPU_FLAG_MMX;

        if (VAR_7 & (1<<25))

            VAR_0 |= AV_CPU_FLAG_MMX2

#if HAVE_SSE

                  | AV_CPU_FLAG_SSE;

        if (VAR_7 & (1<<26))

            VAR_0 |= AV_CPU_FLAG_SSE2;

        if (VAR_3 & 1)

            VAR_0 |= AV_CPU_FLAG_SSE3;

        if (VAR_3 & 0x00000200 )

            VAR_0 |= AV_CPU_FLAG_SSSE3;

        if (VAR_3 & 0x00080000 )

            VAR_0 |= AV_CPU_FLAG_SSE4;

        if (VAR_3 & 0x00100000 )

            VAR_0 |= AV_CPU_FLAG_SSE42;

#if HAVE_AVX

        

        if ((VAR_3 & 0x18000000) == 0x18000000) {

            

            xgetbv(0, VAR_1, VAR_4);

            if ((VAR_1 & 0x6) == 0x6)

                VAR_0 |= AV_CPU_FLAG_AVX;

        }

#endif

#endif

                  ;

    }



    cpuid(0x80000000, VAR_6, VAR_2, VAR_3, VAR_4);



    if(VAR_6 >= 0x80000001){

        cpuid(0x80000001, VAR_1, VAR_2, VAR_3, VAR_8);

        if (VAR_8 & (1<<31))

            VAR_0 |= AV_CPU_FLAG_3DNOW;

        if (VAR_8 & (1<<30))

            VAR_0 |= AV_CPU_FLAG_3DNOWEXT;

        if (VAR_8 & (1<<23))

            VAR_0 |= AV_CPU_FLAG_MMX;

        if (VAR_8 & (1<<22))

            VAR_0 |= AV_CPU_FLAG_MMX2;



        













        if (!strncmp(VAR_11.c, "AuthenticAMD", 12) &&

            VAR_0 & AV_CPU_FLAG_SSE2 && !(VAR_3 & 0x00000040)) {

            VAR_0 |= AV_CPU_FLAG_SSE2SLOW;

        }

    }



    if (!strncmp(VAR_11.c, "GenuineIntel", 12)) {

        if (VAR_9 == 6 && (VAR_10 == 9 || VAR_10 == 13 || VAR_10 == 14)) {

            











            if (VAR_0 & AV_CPU_FLAG_SSE2) VAR_0 ^= AV_CPU_FLAG_SSE2SLOW|AV_CPU_FLAG_SSE2;

            if (VAR_0 & AV_CPU_FLAG_SSE3) VAR_0 ^= AV_CPU_FLAG_SSE3SLOW|AV_CPU_FLAG_SSE3;

        }

        









        if (VAR_9 == 6 && VAR_10 == 28)

            VAR_0 |= AV_CPU_FLAG_ATOM;

    }



    return VAR_0;

}

int FUNC_0(void)
{ int VAR_0 = 0; int VAR_1, VAR_2, VAR_3, VAR_4; int VAR_5, VAR_6, VAR_7=0, VAR_8=0; int VAR_9=0, VAR_10=0; union { int i[3]; char c[12]; } VAR_11; #if ARCH_X86_32
x86_reg a, c; __asm__ volatile (
"pushfl\n\t"
"pop %0\n\t"
"mov %0, %1\n\t"
"xor $0x200000, %0\n\t"
"push %0\n\t"
"popfl\n\t"
"pushfl\n\t"
"pop %0\n\t"
: "=a" (a), "=c" (c)
:
: "cc"
); if (a == c)
return 0; #endif
cpuid(0, VAR_5, VAR_11.i[0], VAR_11.i[2], VAR_11.i[1]); if(VAR_5 >= 1){ cpuid(1, VAR_1, VAR_2, VAR_3, VAR_7); VAR_9 = ((VAR_1>>8)&0xf) + ((VAR_1>>20)&0xff); VAR_10  = ((VAR_1>>4)&0xf) + ((VAR_1>>12)&0xf0); if (VAR_7 & (1<<23))
VAR_0 |= AV_CPU_FLAG_MMX; if (VAR_7 & (1<<25))
VAR_0 |= AV_CPU_FLAG_MMX2
#if HAVE_SSE
| AV_CPU_FLAG_SSE; if (VAR_7 & (1<<26))
VAR_0 |= AV_CPU_FLAG_SSE2; if (VAR_3 & 1)
VAR_0 |= AV_CPU_FLAG_SSE3; if (VAR_3 & 0x00000200 )
VAR_0 |= AV_CPU_FLAG_SSSE3; if (VAR_3 & 0x00080000 )
VAR_0 |= AV_CPU_FLAG_SSE4; if (VAR_3 & 0x00100000 )
VAR_0 |= AV_CPU_FLAG_SSE42; #if HAVE_AVX
if ((VAR_3 & 0x18000000) == 0x18000000) { xgetbv(0, VAR_1, VAR_4); if ((VAR_1 & 0x6) == 0x6)
VAR_0 |= AV_CPU_FLAG_AVX; } #endif
#endif
; } cpuid(0x80000000, VAR_6, VAR_2, VAR_3, VAR_4); if(VAR_6 >= 0x80000001){ cpuid(0x80000001, VAR_1, VAR_2, VAR_3, VAR_8); if (VAR_8 & (1<<31))
VAR_0 |= AV_CPU_FLAG_3DNOW; if (VAR_8 & (1<<30))
VAR_0 |= AV_CPU_FLAG_3DNOWEXT; if (VAR_8 & (1<<23))
VAR_0 |= AV_CPU_FLAG_MMX; if (VAR_8 & (1<<22))
VAR_0 |= AV_CPU_FLAG_MMX2; if (!strncmp(VAR_11.c, "AuthenticAMD", 12) &&
VAR_0 & AV_CPU_FLAG_SSE2 && !(VAR_3 & 0x00000040)) { VAR_0 |= AV_CPU_FLAG_SSE2SLOW; } } if (!strncmp(VAR_11.c, "GenuineIntel", 12)) { if (VAR_9 == 6 && (VAR_10 == 9 || VAR_10 == 13 || VAR_10 == 14)) { if (VAR_0 & AV_CPU_FLAG_SSE2) VAR_0 ^= AV_CPU_FLAG_SSE2SLOW|AV_CPU_FLAG_SSE2; if (VAR_0 & AV_CPU_FLAG_SSE3) VAR_0 ^= AV_CPU_FLAG_SSE3SLOW|AV_CPU_FLAG_SSE3; } if (VAR_9 == 6 && VAR_10 == 28)
VAR_0 |= AV_CPU_FLAG_ATOM; } return VAR_0; }