static int kvm_put_sregs(CPUState *env)

{

    struct kvm_sregs sregs;



    memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));

    if (env->interrupt_injected >= 0) {

        sregs.interrupt_bitmap[env->interrupt_injected / 64] |=

                (uint64_t)1 << (env->interrupt_injected % 64);

    }



    if ((env->eflags & VM_MASK)) {

	    set_v8086_seg(&sregs.cs, &env->segs[R_CS]);

	    set_v8086_seg(&sregs.ds, &env->segs[R_DS]);

	    set_v8086_seg(&sregs.es, &env->segs[R_ES]);

	    set_v8086_seg(&sregs.fs, &env->segs[R_FS]);

	    set_v8086_seg(&sregs.gs, &env->segs[R_GS]);

	    set_v8086_seg(&sregs.ss, &env->segs[R_SS]);

    } else {

	    set_seg(&sregs.cs, &env->segs[R_CS]);

	    set_seg(&sregs.ds, &env->segs[R_DS]);

	    set_seg(&sregs.es, &env->segs[R_ES]);

	    set_seg(&sregs.fs, &env->segs[R_FS]);

	    set_seg(&sregs.gs, &env->segs[R_GS]);

	    set_seg(&sregs.ss, &env->segs[R_SS]);

    }



    set_seg(&sregs.tr, &env->tr);

    set_seg(&sregs.ldt, &env->ldt);



    sregs.idt.limit = env->idt.limit;

    sregs.idt.base = env->idt.base;

    sregs.gdt.limit = env->gdt.limit;

    sregs.gdt.base = env->gdt.base;



    sregs.cr0 = env->cr[0];

    sregs.cr2 = env->cr[2];

    sregs.cr3 = env->cr[3];

    sregs.cr4 = env->cr[4];



    sregs.cr8 = cpu_get_apic_tpr(env->apic_state);

    sregs.apic_base = cpu_get_apic_base(env->apic_state);



    sregs.efer = env->efer;



    return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);

}

static int kvm_put_sregs(CPUState *env)

{

    struct kvm_sregs sregs;



    memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));

    if (env->interrupt_injected >= 0) {

        sregs.interrupt_bitmap[env->interrupt_injected / 64] |=

                (uint64_t)1 << (env->interrupt_injected % 64);

    }



    if ((env->eflags & VM_MASK)) {

	    set_v8086_seg(&sregs.cs, &env->segs[R_CS]);

	    set_v8086_seg(&sregs.ds, &env->segs[R_DS]);

	    set_v8086_seg(&sregs.es, &env->segs[R_ES]);

	    set_v8086_seg(&sregs.fs, &env->segs[R_FS]);

	    set_v8086_seg(&sregs.gs, &env->segs[R_GS]);

	    set_v8086_seg(&sregs.ss, &env->segs[R_SS]);

    } else {

	    set_seg(&sregs.cs, &env->segs[R_CS]);

	    set_seg(&sregs.ds, &env->segs[R_DS]);

	    set_seg(&sregs.es, &env->segs[R_ES]);

	    set_seg(&sregs.fs, &env->segs[R_FS]);

	    set_seg(&sregs.gs, &env->segs[R_GS]);

	    set_seg(&sregs.ss, &env->segs[R_SS]);

    }



    set_seg(&sregs.tr, &env->tr);

    set_seg(&sregs.ldt, &env->ldt);



    sregs.idt.limit = env->idt.limit;

    sregs.idt.base = env->idt.base;

    sregs.gdt.limit = env->gdt.limit;

    sregs.gdt.base = env->gdt.base;



    sregs.cr0 = env->cr[0];

    sregs.cr2 = env->cr[2];

    sregs.cr3 = env->cr[3];

    sregs.cr4 = env->cr[4];



    sregs.cr8 = cpu_get_apic_tpr(env->apic_state);

    sregs.apic_base = cpu_get_apic_base(env->apic_state);



    sregs.efer = env->efer;



    return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);

}

static int FUNC_0(CPUState *VAR_0)

{

    struct kvm_sregs VAR_1;



    memset(VAR_1.interrupt_bitmap, 0, sizeof(VAR_1.interrupt_bitmap));

    if (VAR_0->interrupt_injected >= 0) {

        VAR_1.interrupt_bitmap[VAR_0->interrupt_injected / 64] |=

                (uint64_t)1 << (VAR_0->interrupt_injected % 64);

    }



    if ((VAR_0->eflags & VM_MASK)) {

	    set_v8086_seg(&VAR_1.cs, &VAR_0->segs[R_CS]);

	    set_v8086_seg(&VAR_1.ds, &VAR_0->segs[R_DS]);

	    set_v8086_seg(&VAR_1.es, &VAR_0->segs[R_ES]);

	    set_v8086_seg(&VAR_1.fs, &VAR_0->segs[R_FS]);

	    set_v8086_seg(&VAR_1.gs, &VAR_0->segs[R_GS]);

	    set_v8086_seg(&VAR_1.ss, &VAR_0->segs[R_SS]);

    } else {

	    set_seg(&VAR_1.cs, &VAR_0->segs[R_CS]);

	    set_seg(&VAR_1.ds, &VAR_0->segs[R_DS]);

	    set_seg(&VAR_1.es, &VAR_0->segs[R_ES]);

	    set_seg(&VAR_1.fs, &VAR_0->segs[R_FS]);

	    set_seg(&VAR_1.gs, &VAR_0->segs[R_GS]);

	    set_seg(&VAR_1.ss, &VAR_0->segs[R_SS]);

    }



    set_seg(&VAR_1.tr, &VAR_0->tr);

    set_seg(&VAR_1.ldt, &VAR_0->ldt);



    VAR_1.idt.limit = VAR_0->idt.limit;

    VAR_1.idt.base = VAR_0->idt.base;

    VAR_1.gdt.limit = VAR_0->gdt.limit;

    VAR_1.gdt.base = VAR_0->gdt.base;



    VAR_1.cr0 = VAR_0->cr[0];

    VAR_1.cr2 = VAR_0->cr[2];

    VAR_1.cr3 = VAR_0->cr[3];

    VAR_1.cr4 = VAR_0->cr[4];



    VAR_1.cr8 = cpu_get_apic_tpr(VAR_0->apic_state);

    VAR_1.apic_base = cpu_get_apic_base(VAR_0->apic_state);



    VAR_1.efer = VAR_0->efer;



    return kvm_vcpu_ioctl(VAR_0, KVM_SET_SREGS, &VAR_1);

}

static int FUNC_0(CPUState *VAR_0)
{ struct kvm_sregs VAR_1; memset(VAR_1.interrupt_bitmap, 0, sizeof(VAR_1.interrupt_bitmap)); if (VAR_0->interrupt_injected >= 0) { VAR_1.interrupt_bitmap[VAR_0->interrupt_injected / 64] |=
(uint64_t)1 << (VAR_0->interrupt_injected % 64); } if ((VAR_0->eflags & VM_MASK)) { set_v8086_seg(&VAR_1.cs, &VAR_0->segs[R_CS]); set_v8086_seg(&VAR_1.ds, &VAR_0->segs[R_DS]); set_v8086_seg(&VAR_1.es, &VAR_0->segs[R_ES]); set_v8086_seg(&VAR_1.fs, &VAR_0->segs[R_FS]); set_v8086_seg(&VAR_1.gs, &VAR_0->segs[R_GS]); set_v8086_seg(&VAR_1.ss, &VAR_0->segs[R_SS]); } else { set_seg(&VAR_1.cs, &VAR_0->segs[R_CS]); set_seg(&VAR_1.ds, &VAR_0->segs[R_DS]); set_seg(&VAR_1.es, &VAR_0->segs[R_ES]); set_seg(&VAR_1.fs, &VAR_0->segs[R_FS]); set_seg(&VAR_1.gs, &VAR_0->segs[R_GS]); set_seg(&VAR_1.ss, &VAR_0->segs[R_SS]); } set_seg(&VAR_1.tr, &VAR_0->tr); set_seg(&VAR_1.ldt, &VAR_0->ldt); VAR_1.idt.limit = VAR_0->idt.limit; VAR_1.idt.base = VAR_0->idt.base; VAR_1.gdt.limit = VAR_0->gdt.limit; VAR_1.gdt.base = VAR_0->gdt.base; VAR_1.cr0 = VAR_0->cr[0]; VAR_1.cr2 = VAR_0->cr[2]; VAR_1.cr3 = VAR_0->cr[3]; VAR_1.cr4 = VAR_0->cr[4]; VAR_1.cr8 = cpu_get_apic_tpr(VAR_0->apic_state); VAR_1.apic_base = cpu_get_apic_base(VAR_0->apic_state); VAR_1.efer = VAR_0->efer; return kvm_vcpu_ioctl(VAR_0, KVM_SET_SREGS, &VAR_1); }