static uint32_t vmsvga_value_read(void *opaque, uint32_t address)

{

    uint32_t caps;

    struct vmsvga_state_s *s = opaque;

    switch (s->index) {

    case SVGA_REG_ID:

        return s->svgaid;



    case SVGA_REG_ENABLE:

        return s->enable;



    case SVGA_REG_WIDTH:

        return s->width;



    case SVGA_REG_HEIGHT:

        return s->height;



    case SVGA_REG_MAX_WIDTH:

        return SVGA_MAX_WIDTH;



    case SVGA_REG_MAX_HEIGHT:

        return SVGA_MAX_HEIGHT;



    case SVGA_REG_DEPTH:

        return s->depth;



    case SVGA_REG_BITS_PER_PIXEL:

        return (s->depth + 7) & ~7;



    case SVGA_REG_PSEUDOCOLOR:

        return 0x0;



    case SVGA_REG_RED_MASK:

        return s->wred;

    case SVGA_REG_GREEN_MASK:

        return s->wgreen;

    case SVGA_REG_BLUE_MASK:

        return s->wblue;



    case SVGA_REG_BYTES_PER_LINE:

        return ((s->depth + 7) >> 3) * s->new_width;



    case SVGA_REG_FB_START: {

        struct pci_vmsvga_state_s *pci_vmsvga

            = container_of(s, struct pci_vmsvga_state_s, chip);

        return pci_get_bar_addr(&pci_vmsvga->card, 1);

    }



    case SVGA_REG_FB_OFFSET:

        return 0x0;



    case SVGA_REG_VRAM_SIZE:

        return s->vga.vram_size;



    case SVGA_REG_FB_SIZE:

        return s->fb_size;



    case SVGA_REG_CAPABILITIES:

        caps = SVGA_CAP_NONE;

#ifdef HW_RECT_ACCEL

        caps |= SVGA_CAP_RECT_COPY;

#endif

#ifdef HW_FILL_ACCEL

        caps |= SVGA_CAP_RECT_FILL;

#endif

#ifdef HW_MOUSE_ACCEL

        if (dpy_cursor_define_supported(s->vga.ds)) {

            caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |

                    SVGA_CAP_CURSOR_BYPASS;

        }

#endif

        return caps;



    case SVGA_REG_MEM_START: {

        struct pci_vmsvga_state_s *pci_vmsvga

            = container_of(s, struct pci_vmsvga_state_s, chip);

        return pci_get_bar_addr(&pci_vmsvga->card, 2);

    }



    case SVGA_REG_MEM_SIZE:

        return s->fifo_size;



    case SVGA_REG_CONFIG_DONE:

        return s->config;



    case SVGA_REG_SYNC:

    case SVGA_REG_BUSY:

        return s->syncing;



    case SVGA_REG_GUEST_ID:

        return s->guest;



    case SVGA_REG_CURSOR_ID:

        return s->cursor.id;



    case SVGA_REG_CURSOR_X:

        return s->cursor.x;



    case SVGA_REG_CURSOR_Y:

        return s->cursor.x;



    case SVGA_REG_CURSOR_ON:

        return s->cursor.on;



    case SVGA_REG_HOST_BITS_PER_PIXEL:

        return (s->depth + 7) & ~7;



    case SVGA_REG_SCRATCH_SIZE:

        return s->scratch_size;



    case SVGA_REG_MEM_REGS:

    case SVGA_REG_NUM_DISPLAYS:

    case SVGA_REG_PITCHLOCK:

    case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:

        return 0;



    default:

        if (s->index >= SVGA_SCRATCH_BASE &&

                s->index < SVGA_SCRATCH_BASE + s->scratch_size)

            return s->scratch[s->index - SVGA_SCRATCH_BASE];

        printf("%s: Bad register %02x\n", __FUNCTION__, s->index);

    }



    return 0;

}

static uint32_t vmsvga_value_read(void *opaque, uint32_t address)

{

    uint32_t caps;

    struct vmsvga_state_s *s = opaque;

    switch (s->index) {

    case SVGA_REG_ID:

        return s->svgaid;



    case SVGA_REG_ENABLE:

        return s->enable;



    case SVGA_REG_WIDTH:

        return s->width;



    case SVGA_REG_HEIGHT:

        return s->height;



    case SVGA_REG_MAX_WIDTH:

        return SVGA_MAX_WIDTH;



    case SVGA_REG_MAX_HEIGHT:

        return SVGA_MAX_HEIGHT;



    case SVGA_REG_DEPTH:

        return s->depth;



    case SVGA_REG_BITS_PER_PIXEL:

        return (s->depth + 7) & ~7;



    case SVGA_REG_PSEUDOCOLOR:

        return 0x0;



    case SVGA_REG_RED_MASK:

        return s->wred;

    case SVGA_REG_GREEN_MASK:

        return s->wgreen;

    case SVGA_REG_BLUE_MASK:

        return s->wblue;



    case SVGA_REG_BYTES_PER_LINE:

        return ((s->depth + 7) >> 3) * s->new_width;



    case SVGA_REG_FB_START: {

        struct pci_vmsvga_state_s *pci_vmsvga

            = container_of(s, struct pci_vmsvga_state_s, chip);

        return pci_get_bar_addr(&pci_vmsvga->card, 1);

    }



    case SVGA_REG_FB_OFFSET:

        return 0x0;



    case SVGA_REG_VRAM_SIZE:

        return s->vga.vram_size;



    case SVGA_REG_FB_SIZE:

        return s->fb_size;



    case SVGA_REG_CAPABILITIES:

        caps = SVGA_CAP_NONE;

#ifdef HW_RECT_ACCEL

        caps |= SVGA_CAP_RECT_COPY;

#endif

#ifdef HW_FILL_ACCEL

        caps |= SVGA_CAP_RECT_FILL;

#endif

#ifdef HW_MOUSE_ACCEL

        if (dpy_cursor_define_supported(s->vga.ds)) {

            caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |

                    SVGA_CAP_CURSOR_BYPASS;

        }

#endif

        return caps;



    case SVGA_REG_MEM_START: {

        struct pci_vmsvga_state_s *pci_vmsvga

            = container_of(s, struct pci_vmsvga_state_s, chip);

        return pci_get_bar_addr(&pci_vmsvga->card, 2);

    }



    case SVGA_REG_MEM_SIZE:

        return s->fifo_size;



    case SVGA_REG_CONFIG_DONE:

        return s->config;



    case SVGA_REG_SYNC:

    case SVGA_REG_BUSY:

        return s->syncing;



    case SVGA_REG_GUEST_ID:

        return s->guest;



    case SVGA_REG_CURSOR_ID:

        return s->cursor.id;



    case SVGA_REG_CURSOR_X:

        return s->cursor.x;



    case SVGA_REG_CURSOR_Y:

        return s->cursor.x;



    case SVGA_REG_CURSOR_ON:

        return s->cursor.on;



    case SVGA_REG_HOST_BITS_PER_PIXEL:

        return (s->depth + 7) & ~7;



    case SVGA_REG_SCRATCH_SIZE:

        return s->scratch_size;



    case SVGA_REG_MEM_REGS:

    case SVGA_REG_NUM_DISPLAYS:

    case SVGA_REG_PITCHLOCK:

    case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:

        return 0;



    default:

        if (s->index >= SVGA_SCRATCH_BASE &&

                s->index < SVGA_SCRATCH_BASE + s->scratch_size)

            return s->scratch[s->index - SVGA_SCRATCH_BASE];

        printf("%s: Bad register %02x\n", __FUNCTION__, s->index);

    }



    return 0;

}

static uint32_t FUNC_0(void *opaque, uint32_t address)

{

    uint32_t caps;

    struct vmsvga_state_s *VAR_0 = opaque;

    switch (VAR_0->index) {

    case SVGA_REG_ID:

        return VAR_0->svgaid;



    case SVGA_REG_ENABLE:

        return VAR_0->enable;



    case SVGA_REG_WIDTH:

        return VAR_0->width;



    case SVGA_REG_HEIGHT:

        return VAR_0->height;



    case SVGA_REG_MAX_WIDTH:

        return SVGA_MAX_WIDTH;



    case SVGA_REG_MAX_HEIGHT:

        return SVGA_MAX_HEIGHT;



    case SVGA_REG_DEPTH:

        return VAR_0->depth;



    case SVGA_REG_BITS_PER_PIXEL:

        return (VAR_0->depth + 7) & ~7;



    case SVGA_REG_PSEUDOCOLOR:

        return 0x0;



    case SVGA_REG_RED_MASK:

        return VAR_0->wred;

    case SVGA_REG_GREEN_MASK:

        return VAR_0->wgreen;

    case SVGA_REG_BLUE_MASK:

        return VAR_0->wblue;



    case SVGA_REG_BYTES_PER_LINE:

        return ((VAR_0->depth + 7) >> 3) * VAR_0->new_width;



    case SVGA_REG_FB_START: {

        struct pci_vmsvga_state_s *VAR_2

            = container_of(VAR_0, struct pci_vmsvga_state_s, chip);

        return pci_get_bar_addr(&VAR_2->card, 1);

    }



    case SVGA_REG_FB_OFFSET:

        return 0x0;



    case SVGA_REG_VRAM_SIZE:

        return VAR_0->vga.vram_size;



    case SVGA_REG_FB_SIZE:

        return VAR_0->fb_size;



    case SVGA_REG_CAPABILITIES:

        caps = SVGA_CAP_NONE;

#ifdef HW_RECT_ACCEL

        caps |= SVGA_CAP_RECT_COPY;

#endif

#ifdef HW_FILL_ACCEL

        caps |= SVGA_CAP_RECT_FILL;

#endif

#ifdef HW_MOUSE_ACCEL

        if (dpy_cursor_define_supported(VAR_0->vga.ds)) {

            caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |

                    SVGA_CAP_CURSOR_BYPASS;

        }

#endif

        return caps;



    case SVGA_REG_MEM_START: {

        struct pci_vmsvga_state_s *VAR_2

            = container_of(VAR_0, struct pci_vmsvga_state_s, chip);

        return pci_get_bar_addr(&VAR_2->card, 2);

    }



    case SVGA_REG_MEM_SIZE:

        return VAR_0->fifo_size;



    case SVGA_REG_CONFIG_DONE:

        return VAR_0->config;



    case SVGA_REG_SYNC:

    case SVGA_REG_BUSY:

        return VAR_0->syncing;



    case SVGA_REG_GUEST_ID:

        return VAR_0->guest;



    case SVGA_REG_CURSOR_ID:

        return VAR_0->cursor.id;



    case SVGA_REG_CURSOR_X:

        return VAR_0->cursor.x;



    case SVGA_REG_CURSOR_Y:

        return VAR_0->cursor.x;



    case SVGA_REG_CURSOR_ON:

        return VAR_0->cursor.on;



    case SVGA_REG_HOST_BITS_PER_PIXEL:

        return (VAR_0->depth + 7) & ~7;



    case SVGA_REG_SCRATCH_SIZE:

        return VAR_0->scratch_size;



    case SVGA_REG_MEM_REGS:

    case SVGA_REG_NUM_DISPLAYS:

    case SVGA_REG_PITCHLOCK:

    case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:

        return 0;



    default:

        if (VAR_0->index >= SVGA_SCRATCH_BASE &&

                VAR_0->index < SVGA_SCRATCH_BASE + VAR_0->scratch_size)

            return VAR_0->scratch[VAR_0->index - SVGA_SCRATCH_BASE];

        printf("%VAR_0: Bad register %02x\n", __FUNCTION__, VAR_0->index);

    }



    return 0;

}

static uint32_t FUNC_0(void *opaque, uint32_t address)
{ uint32_t caps; struct vmsvga_state_s *VAR_0 = opaque; switch (VAR_0->index) { case SVGA_REG_ID:
return VAR_0->svgaid; case SVGA_REG_ENABLE:
return VAR_0->enable; case SVGA_REG_WIDTH:
return VAR_0->width; case SVGA_REG_HEIGHT:
return VAR_0->height; case SVGA_REG_MAX_WIDTH:
return SVGA_MAX_WIDTH; case SVGA_REG_MAX_HEIGHT:
return SVGA_MAX_HEIGHT; case SVGA_REG_DEPTH:
return VAR_0->depth; case SVGA_REG_BITS_PER_PIXEL:
return (VAR_0->depth + 7) & ~7; case SVGA_REG_PSEUDOCOLOR:
return 0x0; case SVGA_REG_RED_MASK:
return VAR_0->wred; case SVGA_REG_GREEN_MASK:
return VAR_0->wgreen; case SVGA_REG_BLUE_MASK:
return VAR_0->wblue; case SVGA_REG_BYTES_PER_LINE:
return ((VAR_0->depth + 7) >> 3) * VAR_0->new_width; case SVGA_REG_FB_START: { struct pci_vmsvga_state_s *VAR_2
= container_of(VAR_0, struct pci_vmsvga_state_s, chip); return pci_get_bar_addr(&VAR_2->card, 1); } case SVGA_REG_FB_OFFSET:
return 0x0; case SVGA_REG_VRAM_SIZE:
return VAR_0->vga.vram_size; case SVGA_REG_FB_SIZE:
return VAR_0->fb_size; case SVGA_REG_CAPABILITIES:
caps = SVGA_CAP_NONE; #ifdef HW_RECT_ACCEL
caps |= SVGA_CAP_RECT_COPY; #endif
#ifdef HW_FILL_ACCEL
caps |= SVGA_CAP_RECT_FILL; #endif
#ifdef HW_MOUSE_ACCEL
if (dpy_cursor_define_supported(VAR_0->vga.ds)) { caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
SVGA_CAP_CURSOR_BYPASS; } #endif
return caps; case SVGA_REG_MEM_START: { struct pci_vmsvga_state_s *VAR_2
= container_of(VAR_0, struct pci_vmsvga_state_s, chip); return pci_get_bar_addr(&VAR_2->card, 2); } case SVGA_REG_MEM_SIZE:
return VAR_0->fifo_size; case SVGA_REG_CONFIG_DONE:
return VAR_0->config; case SVGA_REG_SYNC:
case SVGA_REG_BUSY:
return VAR_0->syncing; case SVGA_REG_GUEST_ID:
return VAR_0->guest; case SVGA_REG_CURSOR_ID:
return VAR_0->cursor.id; case SVGA_REG_CURSOR_X:
return VAR_0->cursor.x; case SVGA_REG_CURSOR_Y:
return VAR_0->cursor.x; case SVGA_REG_CURSOR_ON:
return VAR_0->cursor.on; case SVGA_REG_HOST_BITS_PER_PIXEL:
return (VAR_0->depth + 7) & ~7; case SVGA_REG_SCRATCH_SIZE:
return VAR_0->scratch_size; case SVGA_REG_MEM_REGS:
case SVGA_REG_NUM_DISPLAYS:
case SVGA_REG_PITCHLOCK:
case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
return 0; default:
if (VAR_0->index >= SVGA_SCRATCH_BASE &&
VAR_0->index < SVGA_SCRATCH_BASE + VAR_0->scratch_size)
return VAR_0->scratch[VAR_0->index - SVGA_SCRATCH_BASE]; printf("%VAR_0: Bad register %02x\n", __FUNCTION__, VAR_0->index); } return 0; }