static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,

                                uint64_t value, unsigned size)

{

    struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;



    if (size != 2) {

        return omap_badwidth_write16(opaque, addr, value);

    }



    switch (addr) {

    case 0x00:	/* CNTL_TIMER */

        omap_timer_sync(&s->timer);

        s->timer.ptv = (value >> 9) & 7;

        s->timer.ar = (value >> 8) & 1;

        s->timer.st = (value >> 7) & 1;

        s->free = (value >> 1) & 1;

        omap_timer_update(&s->timer);

        break;



    case 0x04:	/* LOAD_TIMER */

        s->timer.reset_val = value & 0xffff;

        break;



    case 0x08:	/* TIMER_MODE */

        if (!s->mode && ((value >> 15) & 1))

            omap_clk_get(s->timer.clk);

        s->mode |= (value >> 15) & 1;

        if (s->last_wr == 0xf5) {

            if ((value & 0xff) == 0xa0) {

                if (s->mode) {

                    s->mode = 0;

                    omap_clk_put(s->timer.clk);

                }

            } else {

                /* XXX: on T|E hardware somehow this has no effect,

                 * on Zire 71 it works as specified.  */

                s->reset = 1;

                qemu_system_reset_request();

            }

        }

        s->last_wr = value & 0xff;

        break;



    default:

        OMAP_BAD_REG(addr);

    }

}

static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,

                                uint64_t value, unsigned size)

{

    struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;



    if (size != 2) {

        return omap_badwidth_write16(opaque, addr, value);

    }



    switch (addr) {

    case 0x00:	

        omap_timer_sync(&s->timer);

        s->timer.ptv = (value >> 9) & 7;

        s->timer.ar = (value >> 8) & 1;

        s->timer.st = (value >> 7) & 1;

        s->free = (value >> 1) & 1;

        omap_timer_update(&s->timer);

        break;



    case 0x04:	

        s->timer.reset_val = value & 0xffff;

        break;



    case 0x08:	

        if (!s->mode && ((value >> 15) & 1))

            omap_clk_get(s->timer.clk);

        s->mode |= (value >> 15) & 1;

        if (s->last_wr == 0xf5) {

            if ((value & 0xff) == 0xa0) {

                if (s->mode) {

                    s->mode = 0;

                    omap_clk_put(s->timer.clk);

                }

            } else {

                



                s->reset = 1;

                qemu_system_reset_request();

            }

        }

        s->last_wr = value & 0xff;

        break;



    default:

        OMAP_BAD_REG(addr);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                                uint64_t VAR_2, unsigned VAR_3)

{

    struct omap_watchdog_timer_s *VAR_4 = (struct omap_watchdog_timer_s *) VAR_0;



    if (VAR_3 != 2) {

        return omap_badwidth_write16(VAR_0, VAR_1, VAR_2);

    }



    switch (VAR_1) {

    case 0x00:	

        omap_timer_sync(&VAR_4->timer);

        VAR_4->timer.ptv = (VAR_2 >> 9) & 7;

        VAR_4->timer.ar = (VAR_2 >> 8) & 1;

        VAR_4->timer.st = (VAR_2 >> 7) & 1;

        VAR_4->free = (VAR_2 >> 1) & 1;

        omap_timer_update(&VAR_4->timer);

        break;



    case 0x04:	

        VAR_4->timer.reset_val = VAR_2 & 0xffff;

        break;



    case 0x08:	

        if (!VAR_4->mode && ((VAR_2 >> 15) & 1))

            omap_clk_get(VAR_4->timer.clk);

        VAR_4->mode |= (VAR_2 >> 15) & 1;

        if (VAR_4->last_wr == 0xf5) {

            if ((VAR_2 & 0xff) == 0xa0) {

                if (VAR_4->mode) {

                    VAR_4->mode = 0;

                    omap_clk_put(VAR_4->timer.clk);

                }

            } else {

                



                VAR_4->reset = 1;

                qemu_system_reset_request();

            }

        }

        VAR_4->last_wr = VAR_2 & 0xff;

        break;



    default:

        OMAP_BAD_REG(VAR_1);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ struct omap_watchdog_timer_s *VAR_4 = (struct omap_watchdog_timer_s *) VAR_0; if (VAR_3 != 2) { return omap_badwidth_write16(VAR_0, VAR_1, VAR_2); } switch (VAR_1) { case 0x00:
omap_timer_sync(&VAR_4->timer); VAR_4->timer.ptv = (VAR_2 >> 9) & 7; VAR_4->timer.ar = (VAR_2 >> 8) & 1; VAR_4->timer.st = (VAR_2 >> 7) & 1; VAR_4->free = (VAR_2 >> 1) & 1; omap_timer_update(&VAR_4->timer); break; case 0x04:
VAR_4->timer.reset_val = VAR_2 & 0xffff; break; case 0x08:
if (!VAR_4->mode && ((VAR_2 >> 15) & 1))
omap_clk_get(VAR_4->timer.clk); VAR_4->mode |= (VAR_2 >> 15) & 1; if (VAR_4->last_wr == 0xf5) { if ((VAR_2 & 0xff) == 0xa0) { if (VAR_4->mode) { VAR_4->mode = 0; omap_clk_put(VAR_4->timer.clk); } } else { VAR_4->reset = 1; qemu_system_reset_request(); } } VAR_4->last_wr = VAR_2 & 0xff; break; default:
OMAP_BAD_REG(VAR_1); } }