static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)

{

    bool output = reg->stream >= 4;

    IntelHDAStream *st = d->st + reg->stream;



    if (st->ctl & 0x01) {

        /* reset */

        dprint(d, 1, "st #%d: reset\n", reg->stream);

        st->ctl = 0;

    }

    if ((st->ctl & 0x02) != (old & 0x02)) {

        uint32_t stnr = (st->ctl >> 20) & 0x0f;

        /* run bit flipped */

        if (st->ctl & 0x02) {

            /* start */

            dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",

                   reg->stream, stnr, st->cbl);

            intel_hda_parse_bdl(d, st);

            intel_hda_notify_codecs(d, stnr, true, output);

        } else {

            /* stop */

            dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);

            intel_hda_notify_codecs(d, stnr, false, output);

        }

    }

    intel_hda_update_irq(d);

}

static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)

{

    bool output = reg->stream >= 4;

    IntelHDAStream *st = d->st + reg->stream;



    if (st->ctl & 0x01) {

        

        dprint(d, 1, "st #%d: reset\n", reg->stream);

        st->ctl = 0;

    }

    if ((st->ctl & 0x02) != (old & 0x02)) {

        uint32_t stnr = (st->ctl >> 20) & 0x0f;

        

        if (st->ctl & 0x02) {

            

            dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",

                   reg->stream, stnr, st->cbl);

            intel_hda_parse_bdl(d, st);

            intel_hda_notify_codecs(d, stnr, true, output);

        } else {

            

            dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);

            intel_hda_notify_codecs(d, stnr, false, output);

        }

    }

    intel_hda_update_irq(d);

}

static void FUNC_0(IntelHDAState *VAR_0, const IntelHDAReg *VAR_1, uint32_t VAR_2)

{

    bool output = VAR_1->stream >= 4;

    IntelHDAStream *st = VAR_0->st + VAR_1->stream;



    if (st->ctl & 0x01) {

        

        dprint(VAR_0, 1, "st #%VAR_0: reset\n", VAR_1->stream);

        st->ctl = 0;

    }

    if ((st->ctl & 0x02) != (VAR_2 & 0x02)) {

        uint32_t stnr = (st->ctl >> 20) & 0x0f;

        

        if (st->ctl & 0x02) {

            

            dprint(VAR_0, 1, "st #%VAR_0: start %VAR_0 (ring buf %VAR_0 bytes)\n",

                   VAR_1->stream, stnr, st->cbl);

            intel_hda_parse_bdl(VAR_0, st);

            intel_hda_notify_codecs(VAR_0, stnr, true, output);

        } else {

            

            dprint(VAR_0, 1, "st #%VAR_0: stop %VAR_0\n", VAR_1->stream, stnr);

            intel_hda_notify_codecs(VAR_0, stnr, false, output);

        }

    }

    intel_hda_update_irq(VAR_0);

}

static void FUNC_0(IntelHDAState *VAR_0, const IntelHDAReg *VAR_1, uint32_t VAR_2)
{ bool output = VAR_1->stream >= 4; IntelHDAStream *st = VAR_0->st + VAR_1->stream; if (st->ctl & 0x01) { dprint(VAR_0, 1, "st #%VAR_0: reset\n", VAR_1->stream); st->ctl = 0; } if ((st->ctl & 0x02) != (VAR_2 & 0x02)) { uint32_t stnr = (st->ctl >> 20) & 0x0f; if (st->ctl & 0x02) { dprint(VAR_0, 1, "st #%VAR_0: start %VAR_0 (ring buf %VAR_0 bytes)\n",
VAR_1->stream, stnr, st->cbl); intel_hda_parse_bdl(VAR_0, st); intel_hda_notify_codecs(VAR_0, stnr, true, output); } else { dprint(VAR_0, 1, "st #%VAR_0: stop %VAR_0\n", VAR_1->stream, stnr); intel_hda_notify_codecs(VAR_0, stnr, false, output); } } intel_hda_update_irq(VAR_0); }