struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,

                int size, int nbanks, qemu_irq **pins,

                qemu_irq parent_irq, qemu_irq parent_fiq,

                omap_clk fclk, omap_clk iclk)

{

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)

            g_malloc0(sizeof(struct omap_intr_handler_s) +

                            sizeof(struct omap_intr_handler_bank_s) * nbanks);



    s->parent_intr[0] = parent_irq;

    s->parent_intr[1] = parent_fiq;

    s->nbanks = nbanks;

    s->level_only = 1;

    s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);

    if (pins)

        *pins = s->pins;



    memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s, "omap2-intc", size);

    memory_region_add_subregion(get_system_memory(), base, &s->mmio);



    omap_inth_reset(s);



    return s;

}

struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,

                int size, int nbanks, qemu_irq **pins,

                qemu_irq parent_irq, qemu_irq parent_fiq,

                omap_clk fclk, omap_clk iclk)

{

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)

            g_malloc0(sizeof(struct omap_intr_handler_s) +

                            sizeof(struct omap_intr_handler_bank_s) * nbanks);



    s->parent_intr[0] = parent_irq;

    s->parent_intr[1] = parent_fiq;

    s->nbanks = nbanks;

    s->level_only = 1;

    s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);

    if (pins)

        *pins = s->pins;



    memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s, "omap2-intc", size);

    memory_region_add_subregion(get_system_memory(), base, &s->mmio);



    omap_inth_reset(s);



    return s;

}

struct omap_intr_handler_s *FUNC_0(target_phys_addr_t VAR_0,

                int VAR_1, int VAR_2, qemu_irq **VAR_3,

                qemu_irq VAR_4, qemu_irq VAR_5,

                omap_clk VAR_6, omap_clk VAR_7)

{

    struct omap_intr_handler_s *VAR_8 = (struct omap_intr_handler_s *)

            g_malloc0(sizeof(struct omap_intr_handler_s) +

                            sizeof(struct omap_intr_handler_bank_s) * VAR_2);



    VAR_8->parent_intr[0] = VAR_4;

    VAR_8->parent_intr[1] = VAR_5;

    VAR_8->VAR_2 = VAR_2;

    VAR_8->level_only = 1;

    VAR_8->VAR_3 = qemu_allocate_irqs(omap_set_intr_noedge, VAR_8, VAR_2 * 32);

    if (VAR_3)

        *VAR_3 = VAR_8->VAR_3;



    memory_region_init_io(&VAR_8->mmio, &omap2_inth_mem_ops, VAR_8, "omap2-intc", VAR_1);

    memory_region_add_subregion(get_system_memory(), VAR_0, &VAR_8->mmio);



    omap_inth_reset(VAR_8);



    return VAR_8;

}

struct omap_intr_handler_s *FUNC_0(target_phys_addr_t VAR_0,
int VAR_1, int VAR_2, qemu_irq **VAR_3,
qemu_irq VAR_4, qemu_irq VAR_5,
omap_clk VAR_6, omap_clk VAR_7)
{ struct omap_intr_handler_s *VAR_8 = (struct omap_intr_handler_s *)
g_malloc0(sizeof(struct omap_intr_handler_s) +
sizeof(struct omap_intr_handler_bank_s) * VAR_2); VAR_8->parent_intr[0] = VAR_4; VAR_8->parent_intr[1] = VAR_5; VAR_8->VAR_2 = VAR_2; VAR_8->level_only = 1; VAR_8->VAR_3 = qemu_allocate_irqs(omap_set_intr_noedge, VAR_8, VAR_2 * 32); if (VAR_3)
*VAR_3 = VAR_8->VAR_3; memory_region_init_io(&VAR_8->mmio, &omap2_inth_mem_ops, VAR_8, "omap2-intc", VAR_1); memory_region_add_subregion(get_system_memory(), VAR_0, &VAR_8->mmio); omap_inth_reset(VAR_8); return VAR_8; }