void omap_inth_reset(struct omap_intr_handler_s *s)

{

    int i;



    for (i = 0; i < s->nbanks; ++i){

        s->bank[i].irqs = 0x00000000;

        s->bank[i].mask = 0xffffffff;

        s->bank[i].sens_edge = 0x00000000;

        s->bank[i].fiq = 0x00000000;

        s->bank[i].inputs = 0x00000000;

        s->bank[i].swi = 0x00000000;

        memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));



        if (s->level_only)

            s->bank[i].sens_edge = 0xffffffff;

    }



    s->new_agr[0] = ~0;

    s->new_agr[1] = ~0;

    s->sir_intr[0] = 0;

    s->sir_intr[1] = 0;

    s->autoidle = 0;

    s->mask = ~0;



    qemu_set_irq(s->parent_intr[0], 0);

    qemu_set_irq(s->parent_intr[1], 0);

}

void omap_inth_reset(struct omap_intr_handler_s *s)

{

    int i;



    for (i = 0; i < s->nbanks; ++i){

        s->bank[i].irqs = 0x00000000;

        s->bank[i].mask = 0xffffffff;

        s->bank[i].sens_edge = 0x00000000;

        s->bank[i].fiq = 0x00000000;

        s->bank[i].inputs = 0x00000000;

        s->bank[i].swi = 0x00000000;

        memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));



        if (s->level_only)

            s->bank[i].sens_edge = 0xffffffff;

    }



    s->new_agr[0] = ~0;

    s->new_agr[1] = ~0;

    s->sir_intr[0] = 0;

    s->sir_intr[1] = 0;

    s->autoidle = 0;

    s->mask = ~0;



    qemu_set_irq(s->parent_intr[0], 0);

    qemu_set_irq(s->parent_intr[1], 0);

}

void FUNC_0(struct omap_intr_handler_s *VAR_0)

{

    int VAR_1;



    for (VAR_1 = 0; VAR_1 < VAR_0->nbanks; ++VAR_1){

        VAR_0->bank[VAR_1].irqs = 0x00000000;

        VAR_0->bank[VAR_1].mask = 0xffffffff;

        VAR_0->bank[VAR_1].sens_edge = 0x00000000;

        VAR_0->bank[VAR_1].fiq = 0x00000000;

        VAR_0->bank[VAR_1].inputs = 0x00000000;

        VAR_0->bank[VAR_1].swi = 0x00000000;

        memset(VAR_0->bank[VAR_1].priority, 0, sizeof(VAR_0->bank[VAR_1].priority));



        if (VAR_0->level_only)

            VAR_0->bank[VAR_1].sens_edge = 0xffffffff;

    }



    VAR_0->new_agr[0] = ~0;

    VAR_0->new_agr[1] = ~0;

    VAR_0->sir_intr[0] = 0;

    VAR_0->sir_intr[1] = 0;

    VAR_0->autoidle = 0;

    VAR_0->mask = ~0;



    qemu_set_irq(VAR_0->parent_intr[0], 0);

    qemu_set_irq(VAR_0->parent_intr[1], 0);

}

void FUNC_0(struct omap_intr_handler_s *VAR_0)
{ int VAR_1; for (VAR_1 = 0; VAR_1 < VAR_0->nbanks; ++VAR_1){ VAR_0->bank[VAR_1].irqs = 0x00000000; VAR_0->bank[VAR_1].mask = 0xffffffff; VAR_0->bank[VAR_1].sens_edge = 0x00000000; VAR_0->bank[VAR_1].fiq = 0x00000000; VAR_0->bank[VAR_1].inputs = 0x00000000; VAR_0->bank[VAR_1].swi = 0x00000000; memset(VAR_0->bank[VAR_1].priority, 0, sizeof(VAR_0->bank[VAR_1].priority)); if (VAR_0->level_only)
VAR_0->bank[VAR_1].sens_edge = 0xffffffff; } VAR_0->new_agr[0] = ~0; VAR_0->new_agr[1] = ~0; VAR_0->sir_intr[0] = 0; VAR_0->sir_intr[1] = 0; VAR_0->autoidle = 0; VAR_0->mask = ~0; qemu_set_irq(VAR_0->parent_intr[0], 0); qemu_set_irq(VAR_0->parent_intr[1], 0); }