static void memory_region_dispatch_write(MemoryRegion *mr,

                                         hwaddr addr,

                                         uint64_t data,

                                         unsigned size)

{

    if (!memory_region_access_valid(mr, addr, size, true)) {

        return; /* FIXME: better signalling */

    }



    adjust_endianness(mr, &data, size);



    if (!mr->ops->write) {

        mr->ops->old_mmio.write[bitops_ctzl(size)](mr->opaque, addr, data);

        return;

    }



    /* FIXME: support unaligned access */

    access_with_adjusted_size(addr, &data, size,

                              mr->ops->impl.min_access_size,

                              mr->ops->impl.max_access_size,

                              memory_region_write_accessor, mr);

}

static void memory_region_dispatch_write(MemoryRegion *mr,

                                         hwaddr addr,

                                         uint64_t data,

                                         unsigned size)

{

    if (!memory_region_access_valid(mr, addr, size, true)) {

        return; 

    }



    adjust_endianness(mr, &data, size);



    if (!mr->ops->write) {

        mr->ops->old_mmio.write[bitops_ctzl(size)](mr->opaque, addr, data);

        return;

    }



    

    access_with_adjusted_size(addr, &data, size,

                              mr->ops->impl.min_access_size,

                              mr->ops->impl.max_access_size,

                              memory_region_write_accessor, mr);

}

static void FUNC_0(MemoryRegion *VAR_0,

                                         hwaddr VAR_1,

                                         uint64_t VAR_2,

                                         unsigned VAR_3)

{

    if (!memory_region_access_valid(VAR_0, VAR_1, VAR_3, true)) {

        return; 

    }



    adjust_endianness(VAR_0, &VAR_2, VAR_3);



    if (!VAR_0->ops->write) {

        VAR_0->ops->old_mmio.write[bitops_ctzl(VAR_3)](VAR_0->opaque, VAR_1, VAR_2);

        return;

    }



    

    access_with_adjusted_size(VAR_1, &VAR_2, VAR_3,

                              VAR_0->ops->impl.min_access_size,

                              VAR_0->ops->impl.max_access_size,

                              memory_region_write_accessor, VAR_0);

}

static void FUNC_0(MemoryRegion *VAR_0,
hwaddr VAR_1,
uint64_t VAR_2,
unsigned VAR_3)
{ if (!memory_region_access_valid(VAR_0, VAR_1, VAR_3, true)) { return; } adjust_endianness(VAR_0, &VAR_2, VAR_3); if (!VAR_0->ops->write) { VAR_0->ops->old_mmio.write[bitops_ctzl(VAR_3)](VAR_0->opaque, VAR_1, VAR_2); return; } access_with_adjusted_size(VAR_1, &VAR_2, VAR_3,
VAR_0->ops->impl.min_access_size,
VAR_0->ops->impl.max_access_size,
memory_region_write_accessor, VAR_0); }