static void cpu_common_reset(CPUState *cpu)

{

    CPUClass *cc = CPU_GET_CLASS(cpu);

    int i;



    if (qemu_loglevel_mask(CPU_LOG_RESET)) {

        qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);

        log_cpu_state(cpu, cc->reset_dump_flags);

    }



    cpu->interrupt_request = 0;

    cpu->halted = 0;

    cpu->mem_io_pc = 0;

    cpu->mem_io_vaddr = 0;

    cpu->icount_extra = 0;

    cpu->icount_decr.u32 = 0;

    cpu->can_do_io = 1;

    cpu->exception_index = -1;

    cpu->crash_occurred = false;



    if (tcg_enabled()) {

        for (i = 0; i < TB_JMP_CACHE_SIZE; ++i) {

            atomic_set(&cpu->tb_jmp_cache[i], NULL);

        }



#ifdef CONFIG_SOFTMMU

        tlb_flush(cpu, 0);

#endif

    }

}

static void cpu_common_reset(CPUState *cpu)

{

    CPUClass *cc = CPU_GET_CLASS(cpu);

    int i;



    if (qemu_loglevel_mask(CPU_LOG_RESET)) {

        qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);

        log_cpu_state(cpu, cc->reset_dump_flags);

    }



    cpu->interrupt_request = 0;

    cpu->halted = 0;

    cpu->mem_io_pc = 0;

    cpu->mem_io_vaddr = 0;

    cpu->icount_extra = 0;

    cpu->icount_decr.u32 = 0;

    cpu->can_do_io = 1;

    cpu->exception_index = -1;

    cpu->crash_occurred = false;



    if (tcg_enabled()) {

        for (i = 0; i < TB_JMP_CACHE_SIZE; ++i) {

            atomic_set(&cpu->tb_jmp_cache[i], NULL);

        }



#ifdef CONFIG_SOFTMMU

        tlb_flush(cpu, 0);

#endif

    }

}

        for (i = 0; i < TB_JMP_CACHE_SIZE; ++i) {             atomic_set(&cpu->tb_jmp_cache[i], NULL);     int i;         for (i = 0; i < TB_JMP_CACHE_SIZE; ++i) {             atomic_set(&cpu->tb_jmp_cache[i], NULL);
static void FUNC_0(CPUState *VAR_0)

{

    CPUClass *cc = CPU_GET_CLASS(VAR_0);

    int VAR_1;



    if (qemu_loglevel_mask(CPU_LOG_RESET)) {

        qemu_log("CPU Reset (CPU %d)\n", VAR_0->cpu_index);

        log_cpu_state(VAR_0, cc->reset_dump_flags);

    }



    VAR_0->interrupt_request = 0;

    VAR_0->halted = 0;

    VAR_0->mem_io_pc = 0;

    VAR_0->mem_io_vaddr = 0;

    VAR_0->icount_extra = 0;

    VAR_0->icount_decr.u32 = 0;

    VAR_0->can_do_io = 1;

    VAR_0->exception_index = -1;

    VAR_0->crash_occurred = false;



    if (tcg_enabled()) {

        for (VAR_1 = 0; VAR_1 < TB_JMP_CACHE_SIZE; ++VAR_1) {

            atomic_set(&VAR_0->tb_jmp_cache[VAR_1], NULL);

        }



#ifdef CONFIG_SOFTMMU

        tlb_flush(VAR_0, 0);

#endif

    }

}

static void FUNC_0(CPUState *VAR_0)
{ CPUClass *cc = CPU_GET_CLASS(VAR_0); int VAR_1; if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", VAR_0->cpu_index); log_cpu_state(VAR_0, cc->reset_dump_flags); } VAR_0->interrupt_request = 0; VAR_0->halted = 0; VAR_0->mem_io_pc = 0; VAR_0->mem_io_vaddr = 0; VAR_0->icount_extra = 0; VAR_0->icount_decr.u32 = 0; VAR_0->can_do_io = 1; VAR_0->exception_index = -1; VAR_0->crash_occurred = false; if (tcg_enabled()) { for (VAR_1 = 0; VAR_1 < TB_JMP_CACHE_SIZE; ++VAR_1) { atomic_set(&VAR_0->tb_jmp_cache[VAR_1], NULL); } #ifdef CONFIG_SOFTMMU
tlb_flush(VAR_0, 0); #endif
} }