void helper_icbi(target_ulong addr)

{

    addr &= ~(env->dcache_line_size - 1);

    /* Invalidate one cache line :

     * PowerPC specification says this is to be treated like a load

     * (not a fetch) by the MMU. To be sure it will be so,

     * do the load "by hand".

     */

    ldl(addr);

    tb_invalidate_page_range(addr, addr + env->icache_line_size);

}

void helper_icbi(target_ulong addr)

{

    addr &= ~(env->dcache_line_size - 1);

    









    ldl(addr);

    tb_invalidate_page_range(addr, addr + env->icache_line_size);

}

void FUNC_0(target_ulong VAR_0)

{

    VAR_0 &= ~(env->dcache_line_size - 1);

    









    ldl(VAR_0);

    tb_invalidate_page_range(VAR_0, VAR_0 + env->icache_line_size);

}

void FUNC_0(target_ulong VAR_0)
{ VAR_0 &= ~(env->dcache_line_size - 1); ldl(VAR_0); tb_invalidate_page_range(VAR_0, VAR_0 + env->icache_line_size); }