void pci_bridge_write_config(PCIDevice *d,

                             uint32_t address, uint32_t val, int len)

{

    PCIBridge *s = PCI_BRIDGE(d);

    uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);

    uint16_t newctl;



    pci_default_write_config(d, address, val, len);



    if (ranges_overlap(address, len, PCI_COMMAND, 2) ||



        /* io base/limit */

        ranges_overlap(address, len, PCI_IO_BASE, 2) ||



        /* memory base/limit, prefetchable base/limit and

           io base/limit upper 16 */

        ranges_overlap(address, len, PCI_MEMORY_BASE, 20) ||



        /* vga enable */

        ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {

        pci_bridge_update_mappings(s);

    }



    newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);

    if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {

        /* Trigger hot reset on 0->1 transition. */

        pci_bus_reset(&s->sec_bus);

    }

}

void pci_bridge_write_config(PCIDevice *d,

                             uint32_t address, uint32_t val, int len)

{

    PCIBridge *s = PCI_BRIDGE(d);

    uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);

    uint16_t newctl;



    pci_default_write_config(d, address, val, len);



    if (ranges_overlap(address, len, PCI_COMMAND, 2) ||



        

        ranges_overlap(address, len, PCI_IO_BASE, 2) ||



        



        ranges_overlap(address, len, PCI_MEMORY_BASE, 20) ||



        

        ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {

        pci_bridge_update_mappings(s);

    }



    newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);

    if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {

        

        pci_bus_reset(&s->sec_bus);

    }

}

void FUNC_0(PCIDevice *VAR_0,

                             uint32_t VAR_1, uint32_t VAR_2, int VAR_3)

{

    PCIBridge *s = PCI_BRIDGE(VAR_0);

    uint16_t oldctl = pci_get_word(VAR_0->config + PCI_BRIDGE_CONTROL);

    uint16_t newctl;



    pci_default_write_config(VAR_0, VAR_1, VAR_2, VAR_3);



    if (ranges_overlap(VAR_1, VAR_3, PCI_COMMAND, 2) ||



        

        ranges_overlap(VAR_1, VAR_3, PCI_IO_BASE, 2) ||



        



        ranges_overlap(VAR_1, VAR_3, PCI_MEMORY_BASE, 20) ||



        

        ranges_overlap(VAR_1, VAR_3, PCI_BRIDGE_CONTROL, 2)) {

        pci_bridge_update_mappings(s);

    }



    newctl = pci_get_word(VAR_0->config + PCI_BRIDGE_CONTROL);

    if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {

        

        pci_bus_reset(&s->sec_bus);

    }

}

void FUNC_0(PCIDevice *VAR_0,
uint32_t VAR_1, uint32_t VAR_2, int VAR_3)
{ PCIBridge *s = PCI_BRIDGE(VAR_0); uint16_t oldctl = pci_get_word(VAR_0->config + PCI_BRIDGE_CONTROL); uint16_t newctl; pci_default_write_config(VAR_0, VAR_1, VAR_2, VAR_3); if (ranges_overlap(VAR_1, VAR_3, PCI_COMMAND, 2) ||
ranges_overlap(VAR_1, VAR_3, PCI_IO_BASE, 2) ||
ranges_overlap(VAR_1, VAR_3, PCI_MEMORY_BASE, 20) ||
ranges_overlap(VAR_1, VAR_3, PCI_BRIDGE_CONTROL, 2)) { pci_bridge_update_mappings(s); } newctl = pci_get_word(VAR_0->config + PCI_BRIDGE_CONTROL); if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) { pci_bus_reset(&s->sec_bus); } }