static void memcard_write(void *opaque, target_phys_addr_t addr, uint64_t value,

                          unsigned size)

{

    MilkymistMemcardState *s = opaque;



    trace_milkymist_memcard_memory_write(addr, value);



    addr >>= 2;

    switch (addr) {

    case R_PENDING:

        /* clear rx pending bits */

        s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));

        update_pending_bits(s);

        break;

    case R_CMD:

        if (!s->enabled) {

            break;

        }

        if (s->ignore_next_cmd) {

            s->ignore_next_cmd = 0;

            break;

        }

        s->command[s->command_write_ptr] = value & 0xff;

        s->command_write_ptr = (s->command_write_ptr + 1) % 6;

        if (s->command_write_ptr == 0) {

            memcard_sd_command(s);

        }

        break;

    case R_DAT:

        if (!s->enabled) {

            break;

        }

        sd_write_data(s->card, (value >> 24) & 0xff);

        sd_write_data(s->card, (value >> 16) & 0xff);

        sd_write_data(s->card, (value >> 8) & 0xff);

        sd_write_data(s->card, value & 0xff);

        break;

    case R_ENABLE:

        s->regs[addr] = value;

        update_pending_bits(s);

        break;

    case R_CLK2XDIV:

    case R_START:

        s->regs[addr] = value;

        break;



    default:

        error_report("milkymist_memcard: write access to unknown register 0x"

                TARGET_FMT_plx, addr << 2);

        break;

    }

}

static void memcard_write(void *opaque, target_phys_addr_t addr, uint64_t value,

                          unsigned size)

{

    MilkymistMemcardState *s = opaque;



    trace_milkymist_memcard_memory_write(addr, value);



    addr >>= 2;

    switch (addr) {

    case R_PENDING:

        

        s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));

        update_pending_bits(s);

        break;

    case R_CMD:

        if (!s->enabled) {

            break;

        }

        if (s->ignore_next_cmd) {

            s->ignore_next_cmd = 0;

            break;

        }

        s->command[s->command_write_ptr] = value & 0xff;

        s->command_write_ptr = (s->command_write_ptr + 1) % 6;

        if (s->command_write_ptr == 0) {

            memcard_sd_command(s);

        }

        break;

    case R_DAT:

        if (!s->enabled) {

            break;

        }

        sd_write_data(s->card, (value >> 24) & 0xff);

        sd_write_data(s->card, (value >> 16) & 0xff);

        sd_write_data(s->card, (value >> 8) & 0xff);

        sd_write_data(s->card, value & 0xff);

        break;

    case R_ENABLE:

        s->regs[addr] = value;

        update_pending_bits(s);

        break;

    case R_CLK2XDIV:

    case R_START:

        s->regs[addr] = value;

        break;



    default:

        error_report("milkymist_memcard: write access to unknown register 0x"

                TARGET_FMT_plx, addr << 2);

        break;

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint64_t VAR_2,

                          unsigned VAR_3)

{

    MilkymistMemcardState *s = VAR_0;



    trace_milkymist_memcard_memory_write(VAR_1, VAR_2);



    VAR_1 >>= 2;

    switch (VAR_1) {

    case R_PENDING:

        

        s->regs[R_PENDING] &= ~(VAR_2 & (PENDING_CMD_RX | PENDING_DAT_RX));

        update_pending_bits(s);

        break;

    case R_CMD:

        if (!s->enabled) {

            break;

        }

        if (s->ignore_next_cmd) {

            s->ignore_next_cmd = 0;

            break;

        }

        s->command[s->command_write_ptr] = VAR_2 & 0xff;

        s->command_write_ptr = (s->command_write_ptr + 1) % 6;

        if (s->command_write_ptr == 0) {

            memcard_sd_command(s);

        }

        break;

    case R_DAT:

        if (!s->enabled) {

            break;

        }

        sd_write_data(s->card, (VAR_2 >> 24) & 0xff);

        sd_write_data(s->card, (VAR_2 >> 16) & 0xff);

        sd_write_data(s->card, (VAR_2 >> 8) & 0xff);

        sd_write_data(s->card, VAR_2 & 0xff);

        break;

    case R_ENABLE:

        s->regs[VAR_1] = VAR_2;

        update_pending_bits(s);

        break;

    case R_CLK2XDIV:

    case R_START:

        s->regs[VAR_1] = VAR_2;

        break;



    default:

        error_report("milkymist_memcard: write access to unknown register 0x"

                TARGET_FMT_plx, VAR_1 << 2);

        break;

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint64_t VAR_2,
unsigned VAR_3)
{ MilkymistMemcardState *s = VAR_0; trace_milkymist_memcard_memory_write(VAR_1, VAR_2); VAR_1 >>= 2; switch (VAR_1) { case R_PENDING:
s->regs[R_PENDING] &= ~(VAR_2 & (PENDING_CMD_RX | PENDING_DAT_RX)); update_pending_bits(s); break; case R_CMD:
if (!s->enabled) { break; } if (s->ignore_next_cmd) { s->ignore_next_cmd = 0; break; } s->command[s->command_write_ptr] = VAR_2 & 0xff; s->command_write_ptr = (s->command_write_ptr + 1) % 6; if (s->command_write_ptr == 0) { memcard_sd_command(s); } break; case R_DAT:
if (!s->enabled) { break; } sd_write_data(s->card, (VAR_2 >> 24) & 0xff); sd_write_data(s->card, (VAR_2 >> 16) & 0xff); sd_write_data(s->card, (VAR_2 >> 8) & 0xff); sd_write_data(s->card, VAR_2 & 0xff); break; case R_ENABLE:
s->regs[VAR_1] = VAR_2; update_pending_bits(s); break; case R_CLK2XDIV:
case R_START:
s->regs[VAR_1] = VAR_2; break; default:
error_report("milkymist_memcard: write access to unknown register 0x"
TARGET_FMT_plx, VAR_1 << 2); break; } }