static int mpc8544_load_device_tree(CPUPPCState *env,

                                    target_phys_addr_t addr,

                                    target_phys_addr_t ramsize,

                                    target_phys_addr_t initrd_base,

                                    target_phys_addr_t initrd_size,

                                    const char *kernel_cmdline)

{

    int ret = -1;

    uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)};

    int fdt_size;

    void *fdt;

    uint8_t hypercall[16];

    uint32_t clock_freq = 400000000;

    uint32_t tb_freq = 400000000;

    int i;

    char compatible[] = "MPC8544DS\0MPC85xxDS";

    char model[] = "MPC8544DS";

    char soc[128];

    char ser0[128];

    char ser1[128];

    char mpic[128];

    uint32_t mpic_ph;

    char gutil[128];

    char pci[128];

    uint32_t pci_map[7 * 8];

    uint32_t pci_ranges[12] = { 0x2000000, 0x0, 0xc0000000, 0xc0000000, 0x0,

                                0x20000000, 0x1000000, 0x0, 0x0, 0xe1000000,

                                0x0, 0x10000 };

    QemuOpts *machine_opts;

    const char *dumpdtb = NULL;



    fdt = create_device_tree(&fdt_size);

    if (fdt == NULL) {

        goto out;

    }



    /* Manipulate device tree in memory. */

    qemu_devtree_setprop_string(fdt, "/", "model", model);

    qemu_devtree_setprop(fdt, "/", "compatible", compatible,

                         sizeof(compatible));

    qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 1);

    qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 1);



    qemu_devtree_add_subnode(fdt, "/memory");

    qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");

    qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,

                         sizeof(mem_reg_property));



    qemu_devtree_add_subnode(fdt, "/chosen");

    if (initrd_size) {

        ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",

                                        initrd_base);

        if (ret < 0) {

            fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");

        }



        ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",

                                        (initrd_base + initrd_size));

        if (ret < 0) {

            fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");

        }

    }



    ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",

                                      kernel_cmdline);

    if (ret < 0)

        fprintf(stderr, "couldn't set /chosen/bootargs\n");



    if (kvm_enabled()) {

        /* Read out host's frequencies */

        clock_freq = kvmppc_get_clockfreq();

        tb_freq = kvmppc_get_tbfreq();



        /* indicate KVM hypercall interface */

        qemu_devtree_add_subnode(fdt, "/hypervisor");

        qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",

                                    "linux,kvm");

        kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));

        qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",

                             hypercall, sizeof(hypercall));

    }



    /* Create CPU nodes */

    qemu_devtree_add_subnode(fdt, "/cpus");

    qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1);

    qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0);



    /* We need to generate the cpu nodes in reverse order, so Linux can pick

       the first node as boot node and be happy */

    for (i = smp_cpus - 1; i >= 0; i--) {

        char cpu_name[128];

        uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);



        for (env = first_cpu; env != NULL; env = env->next_cpu) {

            if (env->cpu_index == i) {

                break;

            }

        }



        if (!env) {

            continue;

        }



        snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);

        qemu_devtree_add_subnode(fdt, cpu_name);

        qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);

        qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);

        qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");

        qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);

        qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",

                                  env->dcache_line_size);

        qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",

                                  env->icache_line_size);

        qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);

        qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);

        qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);

        if (env->cpu_index) {

            qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");

            qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");

            qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",

                                     cpu_release_addr);

        } else {

            qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");

        }

    }



    qemu_devtree_add_subnode(fdt, "/aliases");

    /* XXX These should go into their respective devices' code */

    snprintf(soc, sizeof(soc), "/soc8544@%x", MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(fdt, soc);

    qemu_devtree_setprop_string(fdt, soc, "device_type", "soc");

    qemu_devtree_setprop_string(fdt, soc, "compatible", "simple-bus");

    qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);

    qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);

    qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, MPC8544_CCSRBAR_BASE,

                               MPC8544_CCSRBAR_SIZE);

    qemu_devtree_setprop_cells(fdt, soc, "reg", MPC8544_CCSRBAR_BASE,

                               MPC8544_CCSRBAR_REGSIZE);

    /* XXX should contain a reasonable value */

    qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);



    snprintf(mpic, sizeof(mpic), "%s/pic@%x", soc,

             MPC8544_MPIC_REGS_BASE - MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(fdt, mpic);

    qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");

    qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic");

    qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_BASE -

                               MPC8544_CCSRBAR_BASE, 0x40000);

    qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);

    qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2);

    mpic_ph = qemu_devtree_alloc_phandle(fdt);

    qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);

    qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);

    qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0);



    /*

     * We have to generate ser1 first, because Linux takes the first

     * device it finds in the dt as serial output device. And we generate

     * devices in reverse order to the dt.

     */

    snprintf(ser1, sizeof(ser1), "%s/serial@%x", soc,

             MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(fdt, ser1);

    qemu_devtree_setprop_string(fdt, ser1, "device_type", "serial");

    qemu_devtree_setprop_string(fdt, ser1, "compatible", "ns16550");

    qemu_devtree_setprop_cells(fdt, ser1, "reg", MPC8544_SERIAL1_REGS_BASE -

                               MPC8544_CCSRBAR_BASE, 0x100);

    qemu_devtree_setprop_cell(fdt, ser1, "cell-index", 1);

    qemu_devtree_setprop_cell(fdt, ser1, "clock-frequency", 0);

    qemu_devtree_setprop_cells(fdt, ser1, "interrupts", 42, 2);

    qemu_devtree_setprop_phandle(fdt, ser1, "interrupt-parent", mpic);

    qemu_devtree_setprop_string(fdt, "/aliases", "serial1", ser1);



    snprintf(ser0, sizeof(ser0), "%s/serial@%x", soc,

             MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(fdt, ser0);

    qemu_devtree_setprop_string(fdt, ser0, "device_type", "serial");

    qemu_devtree_setprop_string(fdt, ser0, "compatible", "ns16550");

    qemu_devtree_setprop_cells(fdt, ser0, "reg", MPC8544_SERIAL0_REGS_BASE -

                               MPC8544_CCSRBAR_BASE, 0x100);

    qemu_devtree_setprop_cell(fdt, ser0, "cell-index", 0);

    qemu_devtree_setprop_cell(fdt, ser0, "clock-frequency", 0);

    qemu_devtree_setprop_cells(fdt, ser0, "interrupts", 42, 2);

    qemu_devtree_setprop_phandle(fdt, ser0, "interrupt-parent", mpic);

    qemu_devtree_setprop_string(fdt, "/aliases", "serial0", ser0);

    qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser0);



    snprintf(gutil, sizeof(gutil), "%s/global-utilities@%x", soc,

             MPC8544_UTIL_BASE - MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(fdt, gutil);

    qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");

    qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_BASE -

                               MPC8544_CCSRBAR_BASE, 0x1000);

    qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);



    snprintf(pci, sizeof(pci), "/pci@%x", MPC8544_PCI_REGS_BASE);

    qemu_devtree_add_subnode(fdt, pci);

    qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);

    qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");

    qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");

    qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,

                               0x0, 0x7);

    pci_map_create(fdt, pci_map, qemu_devtree_get_phandle(fdt, mpic));

    qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, sizeof(pci_map));

    qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);

    qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);

    qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);

    for (i = 0; i < 12; i++) {

        pci_ranges[i] = cpu_to_be32(pci_ranges[i]);

    }

    qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));

    qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE,

                               0x1000);

    qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);

    qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);

    qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);

    qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);

    qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);



    machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);

    if (machine_opts) {

        dumpdtb = qemu_opt_get(machine_opts, "dumpdtb");

    }

    if (dumpdtb) {

        /* Dump the dtb to a file and quit */

        FILE *f = fopen(dumpdtb, "wb");

        size_t len;

        len = fwrite(fdt, fdt_size, 1, f);

        fclose(f);

        if (len != fdt_size) {

            exit(1);

        }

        exit(0);

    }



    ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);

    if (ret < 0) {

        goto out;

    }

    g_free(fdt);

    ret = fdt_size;



out:



    return ret;

}

static int mpc8544_load_device_tree(CPUPPCState *env,

                                    target_phys_addr_t addr,

                                    target_phys_addr_t ramsize,

                                    target_phys_addr_t initrd_base,

                                    target_phys_addr_t initrd_size,

                                    const char *kernel_cmdline)

{

    int ret = -1;

    uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)};

    int fdt_size;

    void *fdt;

    uint8_t hypercall[16];

    uint32_t clock_freq = 400000000;

    uint32_t tb_freq = 400000000;

    int i;

    char compatible[] = "MPC8544DS\0MPC85xxDS";

    char model[] = "MPC8544DS";

    char soc[128];

    char ser0[128];

    char ser1[128];

    char mpic[128];

    uint32_t mpic_ph;

    char gutil[128];

    char pci[128];

    uint32_t pci_map[7 * 8];

    uint32_t pci_ranges[12] = { 0x2000000, 0x0, 0xc0000000, 0xc0000000, 0x0,

                                0x20000000, 0x1000000, 0x0, 0x0, 0xe1000000,

                                0x0, 0x10000 };

    QemuOpts *machine_opts;

    const char *dumpdtb = NULL;



    fdt = create_device_tree(&fdt_size);

    if (fdt == NULL) {

        goto out;

    }



    

    qemu_devtree_setprop_string(fdt, "/", "model", model);

    qemu_devtree_setprop(fdt, "/", "compatible", compatible,

                         sizeof(compatible));

    qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 1);

    qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 1);



    qemu_devtree_add_subnode(fdt, "/memory");

    qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");

    qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,

                         sizeof(mem_reg_property));



    qemu_devtree_add_subnode(fdt, "/chosen");

    if (initrd_size) {

        ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",

                                        initrd_base);

        if (ret < 0) {

            fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");

        }



        ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",

                                        (initrd_base + initrd_size));

        if (ret < 0) {

            fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");

        }

    }



    ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",

                                      kernel_cmdline);

    if (ret < 0)

        fprintf(stderr, "couldn't set /chosen/bootargs\n");



    if (kvm_enabled()) {

        

        clock_freq = kvmppc_get_clockfreq();

        tb_freq = kvmppc_get_tbfreq();



        

        qemu_devtree_add_subnode(fdt, "/hypervisor");

        qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",

                                    "linux,kvm");

        kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));

        qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",

                             hypercall, sizeof(hypercall));

    }



    

    qemu_devtree_add_subnode(fdt, "/cpus");

    qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1);

    qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0);



    



    for (i = smp_cpus - 1; i >= 0; i--) {

        char cpu_name[128];

        uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);



        for (env = first_cpu; env != NULL; env = env->next_cpu) {

            if (env->cpu_index == i) {

                break;

            }

        }



        if (!env) {

            continue;

        }



        snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);

        qemu_devtree_add_subnode(fdt, cpu_name);

        qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);

        qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);

        qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");

        qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);

        qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",

                                  env->dcache_line_size);

        qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",

                                  env->icache_line_size);

        qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);

        qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);

        qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);

        if (env->cpu_index) {

            qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");

            qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");

            qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",

                                     cpu_release_addr);

        } else {

            qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");

        }

    }



    qemu_devtree_add_subnode(fdt, "/aliases");

    

    snprintf(soc, sizeof(soc), "/soc8544@%x", MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(fdt, soc);

    qemu_devtree_setprop_string(fdt, soc, "device_type", "soc");

    qemu_devtree_setprop_string(fdt, soc, "compatible", "simple-bus");

    qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);

    qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);

    qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, MPC8544_CCSRBAR_BASE,

                               MPC8544_CCSRBAR_SIZE);

    qemu_devtree_setprop_cells(fdt, soc, "reg", MPC8544_CCSRBAR_BASE,

                               MPC8544_CCSRBAR_REGSIZE);

    

    qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);



    snprintf(mpic, sizeof(mpic), "%s/pic@%x", soc,

             MPC8544_MPIC_REGS_BASE - MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(fdt, mpic);

    qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");

    qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic");

    qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_BASE -

                               MPC8544_CCSRBAR_BASE, 0x40000);

    qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);

    qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2);

    mpic_ph = qemu_devtree_alloc_phandle(fdt);

    qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);

    qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);

    qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0);



    









    snprintf(ser1, sizeof(ser1), "%s/serial@%x", soc,

             MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(fdt, ser1);

    qemu_devtree_setprop_string(fdt, ser1, "device_type", "serial");

    qemu_devtree_setprop_string(fdt, ser1, "compatible", "ns16550");

    qemu_devtree_setprop_cells(fdt, ser1, "reg", MPC8544_SERIAL1_REGS_BASE -

                               MPC8544_CCSRBAR_BASE, 0x100);

    qemu_devtree_setprop_cell(fdt, ser1, "cell-index", 1);

    qemu_devtree_setprop_cell(fdt, ser1, "clock-frequency", 0);

    qemu_devtree_setprop_cells(fdt, ser1, "interrupts", 42, 2);

    qemu_devtree_setprop_phandle(fdt, ser1, "interrupt-parent", mpic);

    qemu_devtree_setprop_string(fdt, "/aliases", "serial1", ser1);



    snprintf(ser0, sizeof(ser0), "%s/serial@%x", soc,

             MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(fdt, ser0);

    qemu_devtree_setprop_string(fdt, ser0, "device_type", "serial");

    qemu_devtree_setprop_string(fdt, ser0, "compatible", "ns16550");

    qemu_devtree_setprop_cells(fdt, ser0, "reg", MPC8544_SERIAL0_REGS_BASE -

                               MPC8544_CCSRBAR_BASE, 0x100);

    qemu_devtree_setprop_cell(fdt, ser0, "cell-index", 0);

    qemu_devtree_setprop_cell(fdt, ser0, "clock-frequency", 0);

    qemu_devtree_setprop_cells(fdt, ser0, "interrupts", 42, 2);

    qemu_devtree_setprop_phandle(fdt, ser0, "interrupt-parent", mpic);

    qemu_devtree_setprop_string(fdt, "/aliases", "serial0", ser0);

    qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser0);



    snprintf(gutil, sizeof(gutil), "%s/global-utilities@%x", soc,

             MPC8544_UTIL_BASE - MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(fdt, gutil);

    qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");

    qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_BASE -

                               MPC8544_CCSRBAR_BASE, 0x1000);

    qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);



    snprintf(pci, sizeof(pci), "/pci@%x", MPC8544_PCI_REGS_BASE);

    qemu_devtree_add_subnode(fdt, pci);

    qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);

    qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");

    qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");

    qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,

                               0x0, 0x7);

    pci_map_create(fdt, pci_map, qemu_devtree_get_phandle(fdt, mpic));

    qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, sizeof(pci_map));

    qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);

    qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);

    qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);

    for (i = 0; i < 12; i++) {

        pci_ranges[i] = cpu_to_be32(pci_ranges[i]);

    }

    qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));

    qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE,

                               0x1000);

    qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);

    qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);

    qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);

    qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);

    qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);



    machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);

    if (machine_opts) {

        dumpdtb = qemu_opt_get(machine_opts, "dumpdtb");

    }

    if (dumpdtb) {

        

        FILE *f = fopen(dumpdtb, "wb");

        size_t len;

        len = fwrite(fdt, fdt_size, 1, f);

        fclose(f);

        if (len != fdt_size) {

            exit(1);

        }

        exit(0);

    }



    ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);

    if (ret < 0) {

        goto out;

    }

    g_free(fdt);

    ret = fdt_size;



out:



    return ret;

}

static int FUNC_0(CPUPPCState *VAR_0,

                                    target_phys_addr_t VAR_1,

                                    target_phys_addr_t VAR_2,

                                    target_phys_addr_t VAR_3,

                                    target_phys_addr_t VAR_4,

                                    const char *VAR_5)

{

    int VAR_6 = -1;

    uint32_t mem_reg_property[] = {0, cpu_to_be32(VAR_2)};

    int VAR_7;

    void *VAR_8;

    uint8_t hypercall[16];

    uint32_t clock_freq = 400000000;

    uint32_t tb_freq = 400000000;

    int VAR_9;

    char VAR_10[] = "MPC8544DS\0MPC85xxDS";

    char VAR_11[] = "MPC8544DS";

    char VAR_12[128];

    char VAR_13[128];

    char VAR_14[128];

    char VAR_15[128];

    uint32_t mpic_ph;

    char VAR_16[128];

    char VAR_17[128];

    uint32_t pci_map[7 * 8];

    uint32_t pci_ranges[12] = { 0x2000000, 0x0, 0xc0000000, 0xc0000000, 0x0,

                                0x20000000, 0x1000000, 0x0, 0x0, 0xe1000000,

                                0x0, 0x10000 };

    QemuOpts *machine_opts;

    const char *VAR_18 = NULL;



    VAR_8 = create_device_tree(&VAR_7);

    if (VAR_8 == NULL) {

        goto out;

    }



    

    qemu_devtree_setprop_string(VAR_8, "/", "VAR_11", VAR_11);

    qemu_devtree_setprop(VAR_8, "/", "VAR_10", VAR_10,

                         sizeof(VAR_10));

    qemu_devtree_setprop_cell(VAR_8, "/", "#address-cells", 1);

    qemu_devtree_setprop_cell(VAR_8, "/", "#size-cells", 1);



    qemu_devtree_add_subnode(VAR_8, "/memory");

    qemu_devtree_setprop_string(VAR_8, "/memory", "device_type", "memory");

    qemu_devtree_setprop(VAR_8, "/memory", "reg", mem_reg_property,

                         sizeof(mem_reg_property));



    qemu_devtree_add_subnode(VAR_8, "/chosen");

    if (VAR_4) {

        VAR_6 = qemu_devtree_setprop_cell(VAR_8, "/chosen", "linux,initrd-start",

                                        VAR_3);

        if (VAR_6 < 0) {

            fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");

        }



        VAR_6 = qemu_devtree_setprop_cell(VAR_8, "/chosen", "linux,initrd-end",

                                        (VAR_3 + VAR_4));

        if (VAR_6 < 0) {

            fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");

        }

    }



    VAR_6 = qemu_devtree_setprop_string(VAR_8, "/chosen", "bootargs",

                                      VAR_5);

    if (VAR_6 < 0)

        fprintf(stderr, "couldn't set /chosen/bootargs\n");



    if (kvm_enabled()) {

        

        clock_freq = kvmppc_get_clockfreq();

        tb_freq = kvmppc_get_tbfreq();



        

        qemu_devtree_add_subnode(VAR_8, "/hypervisor");

        qemu_devtree_setprop_string(VAR_8, "/hypervisor", "VAR_10",

                                    "linux,kvm");

        kvmppc_get_hypercall(VAR_0, hypercall, sizeof(hypercall));

        qemu_devtree_setprop(VAR_8, "/hypervisor", "hcall-instructions",

                             hypercall, sizeof(hypercall));

    }



    

    qemu_devtree_add_subnode(VAR_8, "/cpus");

    qemu_devtree_setprop_cell(VAR_8, "/cpus", "#address-cells", 1);

    qemu_devtree_setprop_cell(VAR_8, "/cpus", "#size-cells", 0);



    



    for (VAR_9 = smp_cpus - 1; VAR_9 >= 0; VAR_9--) {

        char VAR_19[128];

        uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (VAR_9 * 0x20);



        for (VAR_0 = first_cpu; VAR_0 != NULL; VAR_0 = VAR_0->next_cpu) {

            if (VAR_0->cpu_index == VAR_9) {

                break;

            }

        }



        if (!VAR_0) {

            continue;

        }



        snprintf(VAR_19, sizeof(VAR_19), "/cpus/PowerPC,8544@%x", VAR_0->cpu_index);

        qemu_devtree_add_subnode(VAR_8, VAR_19);

        qemu_devtree_setprop_cell(VAR_8, VAR_19, "clock-frequency", clock_freq);

        qemu_devtree_setprop_cell(VAR_8, VAR_19, "timebase-frequency", tb_freq);

        qemu_devtree_setprop_string(VAR_8, VAR_19, "device_type", "cpu");

        qemu_devtree_setprop_cell(VAR_8, VAR_19, "reg", VAR_0->cpu_index);

        qemu_devtree_setprop_cell(VAR_8, VAR_19, "d-cache-line-size",

                                  VAR_0->dcache_line_size);

        qemu_devtree_setprop_cell(VAR_8, VAR_19, "VAR_9-cache-line-size",

                                  VAR_0->icache_line_size);

        qemu_devtree_setprop_cell(VAR_8, VAR_19, "d-cache-size", 0x8000);

        qemu_devtree_setprop_cell(VAR_8, VAR_19, "VAR_9-cache-size", 0x8000);

        qemu_devtree_setprop_cell(VAR_8, VAR_19, "bus-frequency", 0);

        if (VAR_0->cpu_index) {

            qemu_devtree_setprop_string(VAR_8, VAR_19, "status", "disabled");

            qemu_devtree_setprop_string(VAR_8, VAR_19, "enable-method", "spin-table");

            qemu_devtree_setprop_u64(VAR_8, VAR_19, "cpu-release-VAR_1",

                                     cpu_release_addr);

        } else {

            qemu_devtree_setprop_string(VAR_8, VAR_19, "status", "okay");

        }

    }



    qemu_devtree_add_subnode(VAR_8, "/aliases");

    

    snprintf(VAR_12, sizeof(VAR_12), "/soc8544@%x", MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(VAR_8, VAR_12);

    qemu_devtree_setprop_string(VAR_8, VAR_12, "device_type", "VAR_12");

    qemu_devtree_setprop_string(VAR_8, VAR_12, "VAR_10", "simple-bus");

    qemu_devtree_setprop_cell(VAR_8, VAR_12, "#address-cells", 1);

    qemu_devtree_setprop_cell(VAR_8, VAR_12, "#size-cells", 1);

    qemu_devtree_setprop_cells(VAR_8, VAR_12, "ranges", 0x0, MPC8544_CCSRBAR_BASE,

                               MPC8544_CCSRBAR_SIZE);

    qemu_devtree_setprop_cells(VAR_8, VAR_12, "reg", MPC8544_CCSRBAR_BASE,

                               MPC8544_CCSRBAR_REGSIZE);

    

    qemu_devtree_setprop_cell(VAR_8, VAR_12, "bus-frequency", 0);



    snprintf(VAR_15, sizeof(VAR_15), "%s/pic@%x", VAR_12,

             MPC8544_MPIC_REGS_BASE - MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(VAR_8, VAR_15);

    qemu_devtree_setprop_string(VAR_8, VAR_15, "device_type", "open-pic");

    qemu_devtree_setprop_string(VAR_8, VAR_15, "VAR_10", "chrp,open-pic");

    qemu_devtree_setprop_cells(VAR_8, VAR_15, "reg", MPC8544_MPIC_REGS_BASE -

                               MPC8544_CCSRBAR_BASE, 0x40000);

    qemu_devtree_setprop_cell(VAR_8, VAR_15, "#address-cells", 0);

    qemu_devtree_setprop_cell(VAR_8, VAR_15, "#interrupt-cells", 2);

    mpic_ph = qemu_devtree_alloc_phandle(VAR_8);

    qemu_devtree_setprop_cell(VAR_8, VAR_15, "phandle", mpic_ph);

    qemu_devtree_setprop_cell(VAR_8, VAR_15, "linux,phandle", mpic_ph);

    qemu_devtree_setprop(VAR_8, VAR_15, "interrupt-controller", NULL, 0);



    









    snprintf(VAR_14, sizeof(VAR_14), "%s/serial@%x", VAR_12,

             MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(VAR_8, VAR_14);

    qemu_devtree_setprop_string(VAR_8, VAR_14, "device_type", "serial");

    qemu_devtree_setprop_string(VAR_8, VAR_14, "VAR_10", "ns16550");

    qemu_devtree_setprop_cells(VAR_8, VAR_14, "reg", MPC8544_SERIAL1_REGS_BASE -

                               MPC8544_CCSRBAR_BASE, 0x100);

    qemu_devtree_setprop_cell(VAR_8, VAR_14, "cell-index", 1);

    qemu_devtree_setprop_cell(VAR_8, VAR_14, "clock-frequency", 0);

    qemu_devtree_setprop_cells(VAR_8, VAR_14, "interrupts", 42, 2);

    qemu_devtree_setprop_phandle(VAR_8, VAR_14, "interrupt-parent", VAR_15);

    qemu_devtree_setprop_string(VAR_8, "/aliases", "serial1", VAR_14);



    snprintf(VAR_13, sizeof(VAR_13), "%s/serial@%x", VAR_12,

             MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(VAR_8, VAR_13);

    qemu_devtree_setprop_string(VAR_8, VAR_13, "device_type", "serial");

    qemu_devtree_setprop_string(VAR_8, VAR_13, "VAR_10", "ns16550");

    qemu_devtree_setprop_cells(VAR_8, VAR_13, "reg", MPC8544_SERIAL0_REGS_BASE -

                               MPC8544_CCSRBAR_BASE, 0x100);

    qemu_devtree_setprop_cell(VAR_8, VAR_13, "cell-index", 0);

    qemu_devtree_setprop_cell(VAR_8, VAR_13, "clock-frequency", 0);

    qemu_devtree_setprop_cells(VAR_8, VAR_13, "interrupts", 42, 2);

    qemu_devtree_setprop_phandle(VAR_8, VAR_13, "interrupt-parent", VAR_15);

    qemu_devtree_setprop_string(VAR_8, "/aliases", "serial0", VAR_13);

    qemu_devtree_setprop_string(VAR_8, "/chosen", "linux,stdout-path", VAR_13);



    snprintf(VAR_16, sizeof(VAR_16), "%s/global-utilities@%x", VAR_12,

             MPC8544_UTIL_BASE - MPC8544_CCSRBAR_BASE);

    qemu_devtree_add_subnode(VAR_8, VAR_16);

    qemu_devtree_setprop_string(VAR_8, VAR_16, "VAR_10", "fsl,mpc8544-guts");

    qemu_devtree_setprop_cells(VAR_8, VAR_16, "reg", MPC8544_UTIL_BASE -

                               MPC8544_CCSRBAR_BASE, 0x1000);

    qemu_devtree_setprop(VAR_8, VAR_16, "fsl,has-rstcr", NULL, 0);



    snprintf(VAR_17, sizeof(VAR_17), "/VAR_17@%x", MPC8544_PCI_REGS_BASE);

    qemu_devtree_add_subnode(VAR_8, VAR_17);

    qemu_devtree_setprop_cell(VAR_8, VAR_17, "cell-index", 0);

    qemu_devtree_setprop_string(VAR_8, VAR_17, "VAR_10", "fsl,mpc8540-VAR_17");

    qemu_devtree_setprop_string(VAR_8, VAR_17, "device_type", "VAR_17");

    qemu_devtree_setprop_cells(VAR_8, VAR_17, "interrupt-map-mask", 0xf800, 0x0,

                               0x0, 0x7);

    pci_map_create(VAR_8, pci_map, qemu_devtree_get_phandle(VAR_8, VAR_15));

    qemu_devtree_setprop(VAR_8, VAR_17, "interrupt-map", pci_map, sizeof(pci_map));

    qemu_devtree_setprop_phandle(VAR_8, VAR_17, "interrupt-parent", VAR_15);

    qemu_devtree_setprop_cells(VAR_8, VAR_17, "interrupts", 24, 2);

    qemu_devtree_setprop_cells(VAR_8, VAR_17, "bus-range", 0, 255);

    for (VAR_9 = 0; VAR_9 < 12; VAR_9++) {

        pci_ranges[VAR_9] = cpu_to_be32(pci_ranges[VAR_9]);

    }

    qemu_devtree_setprop(VAR_8, VAR_17, "ranges", pci_ranges, sizeof(pci_ranges));

    qemu_devtree_setprop_cells(VAR_8, VAR_17, "reg", MPC8544_PCI_REGS_BASE,

                               0x1000);

    qemu_devtree_setprop_cell(VAR_8, VAR_17, "clock-frequency", 66666666);

    qemu_devtree_setprop_cell(VAR_8, VAR_17, "#interrupt-cells", 1);

    qemu_devtree_setprop_cell(VAR_8, VAR_17, "#size-cells", 2);

    qemu_devtree_setprop_cell(VAR_8, VAR_17, "#address-cells", 3);

    qemu_devtree_setprop_string(VAR_8, "/aliases", "pci0", VAR_17);



    machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);

    if (machine_opts) {

        VAR_18 = qemu_opt_get(machine_opts, "VAR_18");

    }

    if (VAR_18) {

        

        FILE *f = fopen(VAR_18, "wb");

        size_t len;

        len = fwrite(VAR_8, VAR_7, 1, f);

        fclose(f);

        if (len != VAR_7) {

            exit(1);

        }

        exit(0);

    }



    VAR_6 = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, VAR_8, VAR_7, VAR_1);

    if (VAR_6 < 0) {

        goto out;

    }

    g_free(VAR_8);

    VAR_6 = VAR_7;



out:



    return VAR_6;

}

static int FUNC_0(CPUPPCState *VAR_0,
target_phys_addr_t VAR_1,
target_phys_addr_t VAR_2,
target_phys_addr_t VAR_3,
target_phys_addr_t VAR_4,
const char *VAR_5)
{ int VAR_6 = -1; uint32_t mem_reg_property[] = {0, cpu_to_be32(VAR_2)}; int VAR_7; void *VAR_8; uint8_t hypercall[16]; uint32_t clock_freq = 400000000; uint32_t tb_freq = 400000000; int VAR_9; char VAR_10[] = "MPC8544DS\0MPC85xxDS"; char VAR_11[] = "MPC8544DS"; char VAR_12[128]; char VAR_13[128]; char VAR_14[128]; char VAR_15[128]; uint32_t mpic_ph; char VAR_16[128]; char VAR_17[128]; uint32_t pci_map[7 * 8]; uint32_t pci_ranges[12] = { 0x2000000, 0x0, 0xc0000000, 0xc0000000, 0x0, 0x20000000, 0x1000000, 0x0, 0x0, 0xe1000000,
0x0, 0x10000 }; QemuOpts *machine_opts; const char *VAR_18 = NULL; VAR_8 = create_device_tree(&VAR_7); if (VAR_8 == NULL) { goto out; } qemu_devtree_setprop_string(VAR_8, "/", "VAR_11", VAR_11); qemu_devtree_setprop(VAR_8, "/", "VAR_10", VAR_10,
sizeof(VAR_10)); qemu_devtree_setprop_cell(VAR_8, "/", "#address-cells", 1); qemu_devtree_setprop_cell(VAR_8, "/", "#size-cells", 1); qemu_devtree_add_subnode(VAR_8, "/memory"); qemu_devtree_setprop_string(VAR_8, "/memory", "device_type", "memory"); qemu_devtree_setprop(VAR_8, "/memory", "reg", mem_reg_property,
sizeof(mem_reg_property)); qemu_devtree_add_subnode(VAR_8, "/chosen"); if (VAR_4) { VAR_6 = qemu_devtree_setprop_cell(VAR_8, "/chosen", "linux,initrd-start",
VAR_3); if (VAR_6 < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); } VAR_6 = qemu_devtree_setprop_cell(VAR_8, "/chosen", "linux,initrd-end",
(VAR_3 + VAR_4)); if (VAR_6 < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); } } VAR_6 = qemu_devtree_setprop_string(VAR_8, "/chosen", "bootargs",
VAR_5); if (VAR_6 < 0)
fprintf(stderr, "couldn't set /chosen/bootargs\n"); if (kvm_enabled()) { clock_freq = kvmppc_get_clockfreq(); tb_freq = kvmppc_get_tbfreq(); qemu_devtree_add_subnode(VAR_8, "/hypervisor"); qemu_devtree_setprop_string(VAR_8, "/hypervisor", "VAR_10",
"linux,kvm"); kvmppc_get_hypercall(VAR_0, hypercall, sizeof(hypercall)); qemu_devtree_setprop(VAR_8, "/hypervisor", "hcall-instructions",
hypercall, sizeof(hypercall)); } qemu_devtree_add_subnode(VAR_8, "/cpus"); qemu_devtree_setprop_cell(VAR_8, "/cpus", "#address-cells", 1); qemu_devtree_setprop_cell(VAR_8, "/cpus", "#size-cells", 0); for (VAR_9 = smp_cpus - 1; VAR_9 >= 0; VAR_9--) { char VAR_19[128]; uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (VAR_9 * 0x20); for (VAR_0 = first_cpu; VAR_0 != NULL; VAR_0 = VAR_0->next_cpu) { if (VAR_0->cpu_index == VAR_9) { break; } } if (!VAR_0) { continue; } snprintf(VAR_19, sizeof(VAR_19), "/cpus/PowerPC,8544@%x", VAR_0->cpu_index); qemu_devtree_add_subnode(VAR_8, VAR_19); qemu_devtree_setprop_cell(VAR_8, VAR_19, "clock-frequency", clock_freq); qemu_devtree_setprop_cell(VAR_8, VAR_19, "timebase-frequency", tb_freq); qemu_devtree_setprop_string(VAR_8, VAR_19, "device_type", "cpu"); qemu_devtree_setprop_cell(VAR_8, VAR_19, "reg", VAR_0->cpu_index); qemu_devtree_setprop_cell(VAR_8, VAR_19, "d-cache-line-size",
VAR_0->dcache_line_size); qemu_devtree_setprop_cell(VAR_8, VAR_19, "VAR_9-cache-line-size",
VAR_0->icache_line_size); qemu_devtree_setprop_cell(VAR_8, VAR_19, "d-cache-size", 0x8000); qemu_devtree_setprop_cell(VAR_8, VAR_19, "VAR_9-cache-size", 0x8000); qemu_devtree_setprop_cell(VAR_8, VAR_19, "bus-frequency", 0); if (VAR_0->cpu_index) { qemu_devtree_setprop_string(VAR_8, VAR_19, "status", "disabled"); qemu_devtree_setprop_string(VAR_8, VAR_19, "enable-method", "spin-table"); qemu_devtree_setprop_u64(VAR_8, VAR_19, "cpu-release-VAR_1",
cpu_release_addr); } else { qemu_devtree_setprop_string(VAR_8, VAR_19, "status", "okay"); } } qemu_devtree_add_subnode(VAR_8, "/aliases"); snprintf(VAR_12, sizeof(VAR_12), "/soc8544@%x", MPC8544_CCSRBAR_BASE); qemu_devtree_add_subnode(VAR_8, VAR_12); qemu_devtree_setprop_string(VAR_8, VAR_12, "device_type", "VAR_12"); qemu_devtree_setprop_string(VAR_8, VAR_12, "VAR_10", "simple-bus"); qemu_devtree_setprop_cell(VAR_8, VAR_12, "#address-cells", 1); qemu_devtree_setprop_cell(VAR_8, VAR_12, "#size-cells", 1); qemu_devtree_setprop_cells(VAR_8, VAR_12, "ranges", 0x0, MPC8544_CCSRBAR_BASE,
MPC8544_CCSRBAR_SIZE); qemu_devtree_setprop_cells(VAR_8, VAR_12, "reg", MPC8544_CCSRBAR_BASE,
MPC8544_CCSRBAR_REGSIZE); qemu_devtree_setprop_cell(VAR_8, VAR_12, "bus-frequency", 0); snprintf(VAR_15, sizeof(VAR_15), "%s/pic@%x", VAR_12,
MPC8544_MPIC_REGS_BASE - MPC8544_CCSRBAR_BASE); qemu_devtree_add_subnode(VAR_8, VAR_15); qemu_devtree_setprop_string(VAR_8, VAR_15, "device_type", "open-pic"); qemu_devtree_setprop_string(VAR_8, VAR_15, "VAR_10", "chrp,open-pic"); qemu_devtree_setprop_cells(VAR_8, VAR_15, "reg", MPC8544_MPIC_REGS_BASE -
MPC8544_CCSRBAR_BASE, 0x40000); qemu_devtree_setprop_cell(VAR_8, VAR_15, "#address-cells", 0); qemu_devtree_setprop_cell(VAR_8, VAR_15, "#interrupt-cells", 2); mpic_ph = qemu_devtree_alloc_phandle(VAR_8); qemu_devtree_setprop_cell(VAR_8, VAR_15, "phandle", mpic_ph); qemu_devtree_setprop_cell(VAR_8, VAR_15, "linux,phandle", mpic_ph); qemu_devtree_setprop(VAR_8, VAR_15, "interrupt-controller", NULL, 0); snprintf(VAR_14, sizeof(VAR_14), "%s/serial@%x", VAR_12,
MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE); qemu_devtree_add_subnode(VAR_8, VAR_14); qemu_devtree_setprop_string(VAR_8, VAR_14, "device_type", "serial"); qemu_devtree_setprop_string(VAR_8, VAR_14, "VAR_10", "ns16550"); qemu_devtree_setprop_cells(VAR_8, VAR_14, "reg", MPC8544_SERIAL1_REGS_BASE -
MPC8544_CCSRBAR_BASE, 0x100); qemu_devtree_setprop_cell(VAR_8, VAR_14, "cell-index", 1); qemu_devtree_setprop_cell(VAR_8, VAR_14, "clock-frequency", 0); qemu_devtree_setprop_cells(VAR_8, VAR_14, "interrupts", 42, 2); qemu_devtree_setprop_phandle(VAR_8, VAR_14, "interrupt-parent", VAR_15); qemu_devtree_setprop_string(VAR_8, "/aliases", "serial1", VAR_14); snprintf(VAR_13, sizeof(VAR_13), "%s/serial@%x", VAR_12,
MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE); qemu_devtree_add_subnode(VAR_8, VAR_13); qemu_devtree_setprop_string(VAR_8, VAR_13, "device_type", "serial"); qemu_devtree_setprop_string(VAR_8, VAR_13, "VAR_10", "ns16550"); qemu_devtree_setprop_cells(VAR_8, VAR_13, "reg", MPC8544_SERIAL0_REGS_BASE -
MPC8544_CCSRBAR_BASE, 0x100); qemu_devtree_setprop_cell(VAR_8, VAR_13, "cell-index", 0); qemu_devtree_setprop_cell(VAR_8, VAR_13, "clock-frequency", 0); qemu_devtree_setprop_cells(VAR_8, VAR_13, "interrupts", 42, 2); qemu_devtree_setprop_phandle(VAR_8, VAR_13, "interrupt-parent", VAR_15); qemu_devtree_setprop_string(VAR_8, "/aliases", "serial0", VAR_13); qemu_devtree_setprop_string(VAR_8, "/chosen", "linux,stdout-path", VAR_13); snprintf(VAR_16, sizeof(VAR_16), "%s/global-utilities@%x", VAR_12,
MPC8544_UTIL_BASE - MPC8544_CCSRBAR_BASE); qemu_devtree_add_subnode(VAR_8, VAR_16); qemu_devtree_setprop_string(VAR_8, VAR_16, "VAR_10", "fsl,mpc8544-guts"); qemu_devtree_setprop_cells(VAR_8, VAR_16, "reg", MPC8544_UTIL_BASE -
MPC8544_CCSRBAR_BASE, 0x1000); qemu_devtree_setprop(VAR_8, VAR_16, "fsl,has-rstcr", NULL, 0); snprintf(VAR_17, sizeof(VAR_17), "/VAR_17@%x", MPC8544_PCI_REGS_BASE); qemu_devtree_add_subnode(VAR_8, VAR_17); qemu_devtree_setprop_cell(VAR_8, VAR_17, "cell-index", 0); qemu_devtree_setprop_string(VAR_8, VAR_17, "VAR_10", "fsl,mpc8540-VAR_17"); qemu_devtree_setprop_string(VAR_8, VAR_17, "device_type", "VAR_17"); qemu_devtree_setprop_cells(VAR_8, VAR_17, "interrupt-map-mask", 0xf800, 0x0,
0x0, 0x7); pci_map_create(VAR_8, pci_map, qemu_devtree_get_phandle(VAR_8, VAR_15)); qemu_devtree_setprop(VAR_8, VAR_17, "interrupt-map", pci_map, sizeof(pci_map)); qemu_devtree_setprop_phandle(VAR_8, VAR_17, "interrupt-parent", VAR_15); qemu_devtree_setprop_cells(VAR_8, VAR_17, "interrupts", 24, 2); qemu_devtree_setprop_cells(VAR_8, VAR_17, "bus-range", 0, 255); for (VAR_9 = 0; VAR_9 < 12; VAR_9++) { pci_ranges[VAR_9] = cpu_to_be32(pci_ranges[VAR_9]); } qemu_devtree_setprop(VAR_8, VAR_17, "ranges", pci_ranges, sizeof(pci_ranges)); qemu_devtree_setprop_cells(VAR_8, VAR_17, "reg", MPC8544_PCI_REGS_BASE,
0x1000); qemu_devtree_setprop_cell(VAR_8, VAR_17, "clock-frequency", 66666666); qemu_devtree_setprop_cell(VAR_8, VAR_17, "#interrupt-cells", 1); qemu_devtree_setprop_cell(VAR_8, VAR_17, "#size-cells", 2); qemu_devtree_setprop_cell(VAR_8, VAR_17, "#address-cells", 3); qemu_devtree_setprop_string(VAR_8, "/aliases", "pci0", VAR_17); machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); if (machine_opts) { VAR_18 = qemu_opt_get(machine_opts, "VAR_18"); } if (VAR_18) { FILE *f = fopen(VAR_18, "wb"); size_t len; len = fwrite(VAR_8, VAR_7, 1, f); fclose(f); if (len != VAR_7) { exit(1); } exit(0); } VAR_6 = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, VAR_8, VAR_7, VAR_1); if (VAR_6 < 0) { goto out; } g_free(VAR_8); VAR_6 = VAR_7; out:
return VAR_6; }