static void tcx_rstip_writel(void *opaque, hwaddr addr,

                             uint64_t val, unsigned size)

{

    TCXState *s = opaque;

    int i;

    uint32_t col;



    if (!(addr & 4)) {

        s->tmpblit = val;

    } else {

        addr = (addr >> 3) & 0xfffff;

        col = cpu_to_be32(s->tmpblit);

        if (s->depth == 24) {

            for (i = 0; i < 32; i++) {

                if (val & 0x80000000) {

                    s->vram[addr + i] = s->tmpblit;

                    s->vram24[addr + i] = col;

                    s->cplane[addr + i] = col;

                }

                val <<= 1;

            }

        } else {

            for (i = 0; i < 32; i++)  {

                if (val & 0x80000000) {

                    s->vram[addr + i] = s->tmpblit;

                }

                val <<= 1;

            }

        }

        memory_region_set_dirty(&s->vram_mem, addr, 32);

    }

}

static void tcx_rstip_writel(void *opaque, hwaddr addr,

                             uint64_t val, unsigned size)

{

    TCXState *s = opaque;

    int i;

    uint32_t col;



    if (!(addr & 4)) {

        s->tmpblit = val;

    } else {

        addr = (addr >> 3) & 0xfffff;

        col = cpu_to_be32(s->tmpblit);

        if (s->depth == 24) {

            for (i = 0; i < 32; i++) {

                if (val & 0x80000000) {

                    s->vram[addr + i] = s->tmpblit;

                    s->vram24[addr + i] = col;

                    s->cplane[addr + i] = col;

                }

                val <<= 1;

            }

        } else {

            for (i = 0; i < 32; i++)  {

                if (val & 0x80000000) {

                    s->vram[addr + i] = s->tmpblit;

                }

                val <<= 1;

            }

        }

        memory_region_set_dirty(&s->vram_mem, addr, 32);

    }

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1,

                             uint64_t VAR_2, unsigned VAR_3)

{

    TCXState *s = VAR_0;

    int VAR_4;

    uint32_t col;



    if (!(VAR_1 & 4)) {

        s->tmpblit = VAR_2;

    } else {

        VAR_1 = (VAR_1 >> 3) & 0xfffff;

        col = cpu_to_be32(s->tmpblit);

        if (s->depth == 24) {

            for (VAR_4 = 0; VAR_4 < 32; VAR_4++) {

                if (VAR_2 & 0x80000000) {

                    s->vram[VAR_1 + VAR_4] = s->tmpblit;

                    s->vram24[VAR_1 + VAR_4] = col;

                    s->cplane[VAR_1 + VAR_4] = col;

                }

                VAR_2 <<= 1;

            }

        } else {

            for (VAR_4 = 0; VAR_4 < 32; VAR_4++)  {

                if (VAR_2 & 0x80000000) {

                    s->vram[VAR_1 + VAR_4] = s->tmpblit;

                }

                VAR_2 <<= 1;

            }

        }

        memory_region_set_dirty(&s->vram_mem, VAR_1, 32);

    }

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ TCXState *s = VAR_0; int VAR_4; uint32_t col; if (!(VAR_1 & 4)) { s->tmpblit = VAR_2; } else { VAR_1 = (VAR_1 >> 3) & 0xfffff; col = cpu_to_be32(s->tmpblit); if (s->depth == 24) { for (VAR_4 = 0; VAR_4 < 32; VAR_4++) { if (VAR_2 & 0x80000000) { s->vram[VAR_1 + VAR_4] = s->tmpblit; s->vram24[VAR_1 + VAR_4] = col; s->cplane[VAR_1 + VAR_4] = col; } VAR_2 <<= 1; } } else { for (VAR_4 = 0; VAR_4 < 32; VAR_4++)  { if (VAR_2 & 0x80000000) { s->vram[VAR_1 + VAR_4] = s->tmpblit; } VAR_2 <<= 1; } } memory_region_set_dirty(&s->vram_mem, VAR_1, 32); } }