static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx)

{

    struct Vmxnet3_TxCompDesc txcq_descr;

    PCIDevice *d = PCI_DEVICE(s);



    VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);




    txcq_descr.txdIdx = tx_ridx;

    txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);



    vmxnet3_ring_write_curr_cell(d, &s->txq_descr[qidx].comp_ring, &txcq_descr);



    /* Flush changes in TX descriptor before changing the counter value */

    smp_wmb();



    vmxnet3_inc_tx_completion_counter(s, qidx);

    vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);

}
static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx)

{

    struct Vmxnet3_TxCompDesc txcq_descr;

    PCIDevice *d = PCI_DEVICE(s);



    VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);




    txcq_descr.txdIdx = tx_ridx;

    txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);



    vmxnet3_ring_write_curr_cell(d, &s->txq_descr[qidx].comp_ring, &txcq_descr);



    

    smp_wmb();



    vmxnet3_inc_tx_completion_counter(s, qidx);

    vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);

}
static void FUNC_0(VMXNET3State *VAR_0, int VAR_1, uint32_t VAR_2)

{

    struct Vmxnet3_TxCompDesc VAR_3;

    PCIDevice *d = PCI_DEVICE(VAR_0);



    VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", VAR_1, &VAR_0->txq_descr[VAR_1].comp_ring);




    VAR_3.txdIdx = VAR_2;

    VAR_3.gen = vmxnet3_ring_curr_gen(&VAR_0->txq_descr[VAR_1].comp_ring);



    vmxnet3_ring_write_curr_cell(d, &VAR_0->txq_descr[VAR_1].comp_ring, &VAR_3);



    

    smp_wmb();



    vmxnet3_inc_tx_completion_counter(VAR_0, VAR_1);

    vmxnet3_trigger_interrupt(VAR_0, VAR_0->txq_descr[VAR_1].intr_idx);

}
static void FUNC_0(VMXNET3State *VAR_0, int VAR_1, uint32_t VAR_2)
{ struct Vmxnet3_TxCompDesc VAR_3; PCIDevice *d = PCI_DEVICE(VAR_0); VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", VAR_1, &VAR_0->txq_descr[VAR_1].comp_ring); VAR_3.txdIdx = VAR_2; VAR_3.gen = vmxnet3_ring_curr_gen(&VAR_0->txq_descr[VAR_1].comp_ring); vmxnet3_ring_write_curr_cell(d, &VAR_0->txq_descr[VAR_1].comp_ring, &VAR_3); smp_wmb(); vmxnet3_inc_tx_completion_counter(VAR_0, VAR_1); vmxnet3_trigger_interrupt(VAR_0, VAR_0->txq_descr[VAR_1].intr_idx); }