static void tmu2_write(void *opaque, target_phys_addr_t addr, uint64_t value,

                       unsigned size)

{

    MilkymistTMU2State *s = opaque;



    trace_milkymist_tmu2_memory_write(addr, value);



    addr >>= 2;

    switch (addr) {

    case R_CTL:

        s->regs[addr] = value;

        if (value & CTL_START_BUSY) {

            tmu2_start(s);

        }

        break;

    case R_BRIGHTNESS:

    case R_HMESHLAST:

    case R_VMESHLAST:

    case R_CHROMAKEY:

    case R_VERTICESADDR:

    case R_TEXFBUF:

    case R_TEXHRES:

    case R_TEXVRES:

    case R_TEXHMASK:

    case R_TEXVMASK:

    case R_DSTFBUF:

    case R_DSTHRES:

    case R_DSTVRES:

    case R_DSTHOFFSET:

    case R_DSTVOFFSET:

    case R_DSTSQUAREW:

    case R_DSTSQUAREH:

    case R_ALPHA:

        s->regs[addr] = value;

        break;



    default:

        error_report("milkymist_tmu2: write access to unknown register 0x"

                TARGET_FMT_plx, addr << 2);

        break;

    }



    tmu2_check_registers(s);

}

static void tmu2_write(void *opaque, target_phys_addr_t addr, uint64_t value,

                       unsigned size)

{

    MilkymistTMU2State *s = opaque;



    trace_milkymist_tmu2_memory_write(addr, value);



    addr >>= 2;

    switch (addr) {

    case R_CTL:

        s->regs[addr] = value;

        if (value & CTL_START_BUSY) {

            tmu2_start(s);

        }

        break;

    case R_BRIGHTNESS:

    case R_HMESHLAST:

    case R_VMESHLAST:

    case R_CHROMAKEY:

    case R_VERTICESADDR:

    case R_TEXFBUF:

    case R_TEXHRES:

    case R_TEXVRES:

    case R_TEXHMASK:

    case R_TEXVMASK:

    case R_DSTFBUF:

    case R_DSTHRES:

    case R_DSTVRES:

    case R_DSTHOFFSET:

    case R_DSTVOFFSET:

    case R_DSTSQUAREW:

    case R_DSTSQUAREH:

    case R_ALPHA:

        s->regs[addr] = value;

        break;



    default:

        error_report("milkymist_tmu2: write access to unknown register 0x"

                TARGET_FMT_plx, addr << 2);

        break;

    }



    tmu2_check_registers(s);

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint64_t VAR_2,

                       unsigned VAR_3)

{

    MilkymistTMU2State *s = VAR_0;



    trace_milkymist_tmu2_memory_write(VAR_1, VAR_2);



    VAR_1 >>= 2;

    switch (VAR_1) {

    case R_CTL:

        s->regs[VAR_1] = VAR_2;

        if (VAR_2 & CTL_START_BUSY) {

            tmu2_start(s);

        }

        break;

    case R_BRIGHTNESS:

    case R_HMESHLAST:

    case R_VMESHLAST:

    case R_CHROMAKEY:

    case R_VERTICESADDR:

    case R_TEXFBUF:

    case R_TEXHRES:

    case R_TEXVRES:

    case R_TEXHMASK:

    case R_TEXVMASK:

    case R_DSTFBUF:

    case R_DSTHRES:

    case R_DSTVRES:

    case R_DSTHOFFSET:

    case R_DSTVOFFSET:

    case R_DSTSQUAREW:

    case R_DSTSQUAREH:

    case R_ALPHA:

        s->regs[VAR_1] = VAR_2;

        break;



    default:

        error_report("milkymist_tmu2: write access to unknown register 0x"

                TARGET_FMT_plx, VAR_1 << 2);

        break;

    }



    tmu2_check_registers(s);

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint64_t VAR_2,
unsigned VAR_3)
{ MilkymistTMU2State *s = VAR_0; trace_milkymist_tmu2_memory_write(VAR_1, VAR_2); VAR_1 >>= 2; switch (VAR_1) { case R_CTL:
s->regs[VAR_1] = VAR_2; if (VAR_2 & CTL_START_BUSY) { tmu2_start(s); } break; case R_BRIGHTNESS:
case R_HMESHLAST:
case R_VMESHLAST:
case R_CHROMAKEY:
case R_VERTICESADDR:
case R_TEXFBUF:
case R_TEXHRES:
case R_TEXVRES:
case R_TEXHMASK:
case R_TEXVMASK:
case R_DSTFBUF:
case R_DSTHRES:
case R_DSTVRES:
case R_DSTHOFFSET:
case R_DSTVOFFSET:
case R_DSTSQUAREW:
case R_DSTSQUAREH:
case R_ALPHA:
s->regs[VAR_1] = VAR_2; break; default:
error_report("milkymist_tmu2: write access to unknown register 0x"
TARGET_FMT_plx, VAR_1 << 2); break; } tmu2_check_registers(s); }