int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,

                     target_ulong address, int rw, int access_type)

{

    uint8_t ASID = env->CP0_EntryHi & 0xFF;

    int i;



    for (i = 0; i < env->tlb->tlb_in_use; i++) {

        r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];

        /* 1k pages are not supported. */

        target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);

        target_ulong tag = address & ~mask;

        target_ulong VPN = tlb->VPN & ~mask;

#if defined(TARGET_MIPS64)

        tag &= env->SEGMask;

#endif



        /* Check ASID, virtual page number & size */

        if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {

            /* TLB match */

            int n = !!(address & mask & ~(mask >> 1));

            /* Check access rights */

            if (!(n ? tlb->V1 : tlb->V0)) {

                return TLBRET_INVALID;

            }

            if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {

                return TLBRET_XI;

            }

            if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {

                return TLBRET_RI;

            }

            if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {

                *physical = tlb->PFN[n] | (address & (mask >> 1));

                *prot = PAGE_READ;

                if (n ? tlb->D1 : tlb->D0)

                    *prot |= PAGE_WRITE;

                return TLBRET_MATCH;

            }

            return TLBRET_DIRTY;

        }

    }

    return TLBRET_NOMATCH;

}

int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,

                     target_ulong address, int rw, int access_type)

{

    uint8_t ASID = env->CP0_EntryHi & 0xFF;

    int i;



    for (i = 0; i < env->tlb->tlb_in_use; i++) {

        r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];

        

        target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);

        target_ulong tag = address & ~mask;

        target_ulong VPN = tlb->VPN & ~mask;

#if defined(TARGET_MIPS64)

        tag &= env->SEGMask;

#endif



        

        if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {

            

            int n = !!(address & mask & ~(mask >> 1));

            

            if (!(n ? tlb->V1 : tlb->V0)) {

                return TLBRET_INVALID;

            }

            if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {

                return TLBRET_XI;

            }

            if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {

                return TLBRET_RI;

            }

            if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {

                *physical = tlb->PFN[n] | (address & (mask >> 1));

                *prot = PAGE_READ;

                if (n ? tlb->D1 : tlb->D0)

                    *prot |= PAGE_WRITE;

                return TLBRET_MATCH;

            }

            return TLBRET_DIRTY;

        }

    }

    return TLBRET_NOMATCH;

}

int FUNC_0 (CPUMIPSState *VAR_0, hwaddr *VAR_1, int *VAR_2,

                     target_ulong VAR_3, int VAR_4, int VAR_5)

{

    uint8_t ASID = VAR_0->CP0_EntryHi & 0xFF;

    int VAR_6;



    for (VAR_6 = 0; VAR_6 < VAR_0->tlb->tlb_in_use; VAR_6++) {

        r4k_tlb_t *tlb = &VAR_0->tlb->mmu.r4k.tlb[VAR_6];

        

        target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);

        target_ulong tag = VAR_3 & ~mask;

        target_ulong VPN = tlb->VPN & ~mask;

#if defined(TARGET_MIPS64)

        tag &= VAR_0->SEGMask;

#endif



        

        if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {

            

            int n = !!(VAR_3 & mask & ~(mask >> 1));

            

            if (!(n ? tlb->V1 : tlb->V0)) {

                return TLBRET_INVALID;

            }

            if (VAR_4 == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {

                return TLBRET_XI;

            }

            if (VAR_4 == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {

                return TLBRET_RI;

            }

            if (VAR_4 != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {

                *VAR_1 = tlb->PFN[n] | (VAR_3 & (mask >> 1));

                *VAR_2 = PAGE_READ;

                if (n ? tlb->D1 : tlb->D0)

                    *VAR_2 |= PAGE_WRITE;

                return TLBRET_MATCH;

            }

            return TLBRET_DIRTY;

        }

    }

    return TLBRET_NOMATCH;

}

int FUNC_0 (CPUMIPSState *VAR_0, hwaddr *VAR_1, int *VAR_2,
target_ulong VAR_3, int VAR_4, int VAR_5)
{ uint8_t ASID = VAR_0->CP0_EntryHi & 0xFF; int VAR_6; for (VAR_6 = 0; VAR_6 < VAR_0->tlb->tlb_in_use; VAR_6++) { r4k_tlb_t *tlb = &VAR_0->tlb->mmu.r4k.tlb[VAR_6]; target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); target_ulong tag = VAR_3 & ~mask; target_ulong VPN = tlb->VPN & ~mask; #if defined(TARGET_MIPS64)
tag &= VAR_0->SEGMask; #endif
if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { int n = !!(VAR_3 & mask & ~(mask >> 1)); if (!(n ? tlb->V1 : tlb->V0)) { return TLBRET_INVALID; } if (VAR_4 == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) { return TLBRET_XI; } if (VAR_4 == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) { return TLBRET_RI; } if (VAR_4 != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { *VAR_1 = tlb->PFN[n] | (VAR_3 & (mask >> 1)); *VAR_2 = PAGE_READ; if (n ? tlb->D1 : tlb->D0)
*VAR_2 |= PAGE_WRITE; return TLBRET_MATCH; } return TLBRET_DIRTY; } } return TLBRET_NOMATCH; }