static void gic_dist_writel(void *opaque, target_phys_addr_t offset,

                            uint32_t value)

{

    GICState *s = (GICState *)opaque;

    if (offset == 0xf00) {

        int cpu;

        int irq;

        int mask;



        cpu = gic_get_current_cpu(s);

        irq = value & 0x3ff;

        switch ((value >> 24) & 3) {

        case 0:

            mask = (value >> 16) & ALL_CPU_MASK;

            break;

        case 1:

            mask = ALL_CPU_MASK ^ (1 << cpu);

            break;

        case 2:

            mask = 1 << cpu;

            break;

        default:

            DPRINTF("Bad Soft Int target filter\n");

            mask = ALL_CPU_MASK;

            break;

        }

        GIC_SET_PENDING(irq, mask);

        gic_update(s);

        return;

    }

    gic_dist_writew(opaque, offset, value & 0xffff);

    gic_dist_writew(opaque, offset + 2, value >> 16);

}

static void gic_dist_writel(void *opaque, target_phys_addr_t offset,

                            uint32_t value)

{

    GICState *s = (GICState *)opaque;

    if (offset == 0xf00) {

        int cpu;

        int irq;

        int mask;



        cpu = gic_get_current_cpu(s);

        irq = value & 0x3ff;

        switch ((value >> 24) & 3) {

        case 0:

            mask = (value >> 16) & ALL_CPU_MASK;

            break;

        case 1:

            mask = ALL_CPU_MASK ^ (1 << cpu);

            break;

        case 2:

            mask = 1 << cpu;

            break;

        default:

            DPRINTF("Bad Soft Int target filter\n");

            mask = ALL_CPU_MASK;

            break;

        }

        GIC_SET_PENDING(irq, mask);

        gic_update(s);

        return;

    }

    gic_dist_writew(opaque, offset, value & 0xffff);

    gic_dist_writew(opaque, offset + 2, value >> 16);

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                            uint32_t VAR_2)

{

    GICState *s = (GICState *)VAR_0;

    if (VAR_1 == 0xf00) {

        int VAR_3;

        int VAR_4;

        int VAR_5;



        VAR_3 = gic_get_current_cpu(s);

        VAR_4 = VAR_2 & 0x3ff;

        switch ((VAR_2 >> 24) & 3) {

        case 0:

            VAR_5 = (VAR_2 >> 16) & ALL_CPU_MASK;

            break;

        case 1:

            VAR_5 = ALL_CPU_MASK ^ (1 << VAR_3);

            break;

        case 2:

            VAR_5 = 1 << VAR_3;

            break;

        default:

            DPRINTF("Bad Soft Int target filter\n");

            VAR_5 = ALL_CPU_MASK;

            break;

        }

        GIC_SET_PENDING(VAR_4, VAR_5);

        gic_update(s);

        return;

    }

    gic_dist_writew(VAR_0, VAR_1, VAR_2 & 0xffff);

    gic_dist_writew(VAR_0, VAR_1 + 2, VAR_2 >> 16);

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint32_t VAR_2)
{ GICState *s = (GICState *)VAR_0; if (VAR_1 == 0xf00) { int VAR_3; int VAR_4; int VAR_5; VAR_3 = gic_get_current_cpu(s); VAR_4 = VAR_2 & 0x3ff; switch ((VAR_2 >> 24) & 3) { case 0:
VAR_5 = (VAR_2 >> 16) & ALL_CPU_MASK; break; case 1:
VAR_5 = ALL_CPU_MASK ^ (1 << VAR_3); break; case 2:
VAR_5 = 1 << VAR_3; break; default:
DPRINTF("Bad Soft Int target filter\n"); VAR_5 = ALL_CPU_MASK; break; } GIC_SET_PENDING(VAR_4, VAR_5); gic_update(s); return; } gic_dist_writew(VAR_0, VAR_1, VAR_2 & 0xffff); gic_dist_writew(VAR_0, VAR_1 + 2, VAR_2 >> 16); }