static void kvm_fixup_page_sizes(PowerPCCPU *cpu)

{

    static struct kvm_ppc_smmu_info smmu_info;

    static bool has_smmu_info;

    CPUPPCState *env = &cpu->env;

    long rampagesize;

    int iq, ik, jq, jk;



    /* We only handle page sizes for 64-bit server guests for now */

    if (!(env->mmu_model & POWERPC_MMU_64)) {

        return;

    }



    /* Collect MMU info from kernel if not already */

    if (!has_smmu_info) {

        kvm_get_smmu_info(cpu, &smmu_info);

        has_smmu_info = true;

    }



    rampagesize = getrampagesize();



    /* Convert to QEMU form */

    memset(&env->sps, 0, sizeof(env->sps));



    for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) {

        struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq];

        struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik];



        if (!kvm_valid_page_size(smmu_info.flags, rampagesize,

                                 ksps->page_shift)) {

            continue;

        }

        qsps->page_shift = ksps->page_shift;

        qsps->slb_enc = ksps->slb_enc;

        for (jk = jq = 0; jk < KVM_PPC_PAGE_SIZES_MAX_SZ; jk++) {

            if (!kvm_valid_page_size(smmu_info.flags, rampagesize,

                                     ksps->enc[jk].page_shift)) {

                continue;

            }

            qsps->enc[jq].page_shift = ksps->enc[jk].page_shift;

            qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc;

            if (++jq >= PPC_PAGE_SIZES_MAX_SZ) {

                break;

            }

        }

        if (++iq >= PPC_PAGE_SIZES_MAX_SZ) {

            break;

        }

    }

    env->slb_nr = smmu_info.slb_size;

    if (smmu_info.flags & KVM_PPC_1T_SEGMENTS) {

        env->mmu_model |= POWERPC_MMU_1TSEG;

    } else {

        env->mmu_model &= ~POWERPC_MMU_1TSEG;

    }

}

static void kvm_fixup_page_sizes(PowerPCCPU *cpu)

{

    static struct kvm_ppc_smmu_info smmu_info;

    static bool has_smmu_info;

    CPUPPCState *env = &cpu->env;

    long rampagesize;

    int iq, ik, jq, jk;



    

    if (!(env->mmu_model & POWERPC_MMU_64)) {

        return;

    }



    

    if (!has_smmu_info) {

        kvm_get_smmu_info(cpu, &smmu_info);

        has_smmu_info = true;

    }



    rampagesize = getrampagesize();



    

    memset(&env->sps, 0, sizeof(env->sps));



    for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) {

        struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq];

        struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik];



        if (!kvm_valid_page_size(smmu_info.flags, rampagesize,

                                 ksps->page_shift)) {

            continue;

        }

        qsps->page_shift = ksps->page_shift;

        qsps->slb_enc = ksps->slb_enc;

        for (jk = jq = 0; jk < KVM_PPC_PAGE_SIZES_MAX_SZ; jk++) {

            if (!kvm_valid_page_size(smmu_info.flags, rampagesize,

                                     ksps->enc[jk].page_shift)) {

                continue;

            }

            qsps->enc[jq].page_shift = ksps->enc[jk].page_shift;

            qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc;

            if (++jq >= PPC_PAGE_SIZES_MAX_SZ) {

                break;

            }

        }

        if (++iq >= PPC_PAGE_SIZES_MAX_SZ) {

            break;

        }

    }

    env->slb_nr = smmu_info.slb_size;

    if (smmu_info.flags & KVM_PPC_1T_SEGMENTS) {

        env->mmu_model |= POWERPC_MMU_1TSEG;

    } else {

        env->mmu_model &= ~POWERPC_MMU_1TSEG;

    }

}

static void FUNC_0(PowerPCCPU *VAR_0)

{

    static struct kvm_ppc_smmu_info VAR_1;

    static bool VAR_2;

    CPUPPCState *env = &VAR_0->env;

    long VAR_3;

    int VAR_4, VAR_5, VAR_6, VAR_7;



    

    if (!(env->mmu_model & POWERPC_MMU_64)) {

        return;

    }



    

    if (!VAR_2) {

        kvm_get_smmu_info(VAR_0, &VAR_1);

        VAR_2 = true;

    }



    VAR_3 = getrampagesize();



    

    memset(&env->sps, 0, sizeof(env->sps));



    for (VAR_5 = VAR_4 = 0; VAR_5 < KVM_PPC_PAGE_SIZES_MAX_SZ; VAR_5++) {

        struct ppc_one_seg_page_size *qsps = &env->sps.sps[VAR_4];

        struct kvm_ppc_one_seg_page_size *ksps = &VAR_1.sps[VAR_5];



        if (!kvm_valid_page_size(VAR_1.flags, VAR_3,

                                 ksps->page_shift)) {

            continue;

        }

        qsps->page_shift = ksps->page_shift;

        qsps->slb_enc = ksps->slb_enc;

        for (VAR_7 = VAR_6 = 0; VAR_7 < KVM_PPC_PAGE_SIZES_MAX_SZ; VAR_7++) {

            if (!kvm_valid_page_size(VAR_1.flags, VAR_3,

                                     ksps->enc[VAR_7].page_shift)) {

                continue;

            }

            qsps->enc[VAR_6].page_shift = ksps->enc[VAR_7].page_shift;

            qsps->enc[VAR_6].pte_enc = ksps->enc[VAR_7].pte_enc;

            if (++VAR_6 >= PPC_PAGE_SIZES_MAX_SZ) {

                break;

            }

        }

        if (++VAR_4 >= PPC_PAGE_SIZES_MAX_SZ) {

            break;

        }

    }

    env->slb_nr = VAR_1.slb_size;

    if (VAR_1.flags & KVM_PPC_1T_SEGMENTS) {

        env->mmu_model |= POWERPC_MMU_1TSEG;

    } else {

        env->mmu_model &= ~POWERPC_MMU_1TSEG;

    }

}

static void FUNC_0(PowerPCCPU *VAR_0)
{ static struct kvm_ppc_smmu_info VAR_1; static bool VAR_2; CPUPPCState *env = &VAR_0->env; long VAR_3; int VAR_4, VAR_5, VAR_6, VAR_7; if (!(env->mmu_model & POWERPC_MMU_64)) { return; } if (!VAR_2) { kvm_get_smmu_info(VAR_0, &VAR_1); VAR_2 = true; } VAR_3 = getrampagesize(); memset(&env->sps, 0, sizeof(env->sps)); for (VAR_5 = VAR_4 = 0; VAR_5 < KVM_PPC_PAGE_SIZES_MAX_SZ; VAR_5++) { struct ppc_one_seg_page_size *qsps = &env->sps.sps[VAR_4]; struct kvm_ppc_one_seg_page_size *ksps = &VAR_1.sps[VAR_5]; if (!kvm_valid_page_size(VAR_1.flags, VAR_3,
ksps->page_shift)) { continue; } qsps->page_shift = ksps->page_shift; qsps->slb_enc = ksps->slb_enc; for (VAR_7 = VAR_6 = 0; VAR_7 < KVM_PPC_PAGE_SIZES_MAX_SZ; VAR_7++) { if (!kvm_valid_page_size(VAR_1.flags, VAR_3,
ksps->enc[VAR_7].page_shift)) { continue; } qsps->enc[VAR_6].page_shift = ksps->enc[VAR_7].page_shift; qsps->enc[VAR_6].pte_enc = ksps->enc[VAR_7].pte_enc; if (++VAR_6 >= PPC_PAGE_SIZES_MAX_SZ) { break; } } if (++VAR_4 >= PPC_PAGE_SIZES_MAX_SZ) { break; } } env->slb_nr = VAR_1.slb_size; if (VAR_1.flags & KVM_PPC_1T_SEGMENTS) { env->mmu_model |= POWERPC_MMU_1TSEG; } else { env->mmu_model &= ~POWERPC_MMU_1TSEG; } }