uart_write(void *opaque, hwaddr addr,

           uint64_t val64, unsigned int size)

{

    XilinxUARTLite *s = opaque;

    uint32_t value = val64;

    unsigned char ch = value;



    addr >>= 2;

    switch (addr)

    {

        case R_STATUS:

            hw_error("write to UART STATUS?\n");

            break;



        case R_CTRL:

            if (value & CONTROL_RST_RX) {

                s->rx_fifo_pos = 0;

                s->rx_fifo_len = 0;

            }

            s->regs[addr] = value;

            break;



        case R_TX:

            if (s->chr)

                qemu_chr_fe_write(s->chr, &ch, 1);



            s->regs[addr] = value;



            /* hax.  */

            s->regs[R_STATUS] |= STATUS_IE;

            break;



        default:

            DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));

            if (addr < ARRAY_SIZE(s->regs))

                s->regs[addr] = value;

            break;

    }

    uart_update_status(s);

    uart_update_irq(s);

}

uart_write(void *opaque, hwaddr addr,

           uint64_t val64, unsigned int size)

{

    XilinxUARTLite *s = opaque;

    uint32_t value = val64;

    unsigned char ch = value;



    addr >>= 2;

    switch (addr)

    {

        case R_STATUS:

            hw_error("write to UART STATUS?\n");

            break;



        case R_CTRL:

            if (value & CONTROL_RST_RX) {

                s->rx_fifo_pos = 0;

                s->rx_fifo_len = 0;

            }

            s->regs[addr] = value;

            break;



        case R_TX:

            if (s->chr)

                qemu_chr_fe_write(s->chr, &ch, 1);



            s->regs[addr] = value;



            

            s->regs[R_STATUS] |= STATUS_IE;

            break;



        default:

            DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));

            if (addr < ARRAY_SIZE(s->regs))

                s->regs[addr] = value;

            break;

    }

    uart_update_status(s);

    uart_update_irq(s);

}

                qemu_chr_fe_write(s->chr, &ch, 1);                 qemu_chr_fe_write(s->chr, &ch, 1);
FUNC_0(void *VAR_0, hwaddr VAR_1,

           uint64_t VAR_2, unsigned int VAR_3)

{

    XilinxUARTLite *s = VAR_0;

    uint32_t value = VAR_2;

    unsigned char VAR_4 = value;



    VAR_1 >>= 2;

    switch (VAR_1)

    {

        case R_STATUS:

            hw_error("write to UART STATUS?\n");

            break;



        case R_CTRL:

            if (value & CONTROL_RST_RX) {

                s->rx_fifo_pos = 0;

                s->rx_fifo_len = 0;

            }

            s->regs[VAR_1] = value;

            break;



        case R_TX:

            if (s->chr)

                qemu_chr_fe_write(s->chr, &VAR_4, 1);



            s->regs[VAR_1] = value;



            

            s->regs[R_STATUS] |= STATUS_IE;

            break;



        default:

            DUART(printf("%s VAR_1=%x v=%x\n", __func__, VAR_1, value));

            if (VAR_1 < ARRAY_SIZE(s->regs))

                s->regs[VAR_1] = value;

            break;

    }

    uart_update_status(s);

    uart_update_irq(s);

}

FUNC_0(void *VAR_0, hwaddr VAR_1,
uint64_t VAR_2, unsigned int VAR_3)
{ XilinxUARTLite *s = VAR_0; uint32_t value = VAR_2; unsigned char VAR_4 = value; VAR_1 >>= 2; switch (VAR_1)
{ case R_STATUS:
hw_error("write to UART STATUS?\n"); break; case R_CTRL:
if (value & CONTROL_RST_RX) { s->rx_fifo_pos = 0; s->rx_fifo_len = 0; } s->regs[VAR_1] = value; break; case R_TX:
if (s->chr)
qemu_chr_fe_write(s->chr, &VAR_4, 1); s->regs[VAR_1] = value; s->regs[R_STATUS] |= STATUS_IE; break; default:
DUART(printf("%s VAR_1=%x v=%x\n", __func__, VAR_1, value)); if (VAR_1 < ARRAY_SIZE(s->regs))
s->regs[VAR_1] = value; break; } uart_update_status(s); uart_update_irq(s); }