static void xilinx_spips_write(void *opaque, hwaddr addr,

                                        uint64_t value, unsigned size)

{

    int mask = ~0;

    int man_start_com = 0;

    XilinxSPIPS *s = opaque;



    DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);

    addr >>= 2;

    switch (addr) {

    case R_CONFIG:

        mask = 0x0002FFFF;

        if (value & MAN_START_COM) {

            man_start_com = 1;

        }

        break;

    case R_INTR_STATUS:

        mask = IXR_ALL;

        s->regs[R_INTR_STATUS] &= ~(mask & value);

        goto no_reg_update;

    case R_INTR_DIS:

        mask = IXR_ALL;

        s->regs[R_INTR_MASK] &= ~(mask & value);

        goto no_reg_update;

    case R_INTR_EN:

        mask = IXR_ALL;

        s->regs[R_INTR_MASK] |= mask & value;

        goto no_reg_update;

    case R_EN:

        mask = 0x1;

        break;

    case R_SLAVE_IDLE_COUNT:

        mask = 0xFF;

        break;

    case R_RX_DATA:

    case R_INTR_MASK:

    case R_MOD_ID:

        mask = 0;

        break;

    case R_TX_DATA:

        tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes);

        goto no_reg_update;

    case R_TXD1:

        tx_data_bytes(s, (uint32_t)value, 1);

        goto no_reg_update;

    case R_TXD2:

        tx_data_bytes(s, (uint32_t)value, 2);

        goto no_reg_update;

    case R_TXD3:

        tx_data_bytes(s, (uint32_t)value, 3);

        goto no_reg_update;

    }

    s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);

no_reg_update:

    xilinx_spips_update_cs_lines(s);

    if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) ||

            (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) {

        xilinx_spips_flush_txfifo(s);

    }

    xilinx_spips_update_cs_lines(s);

    xilinx_spips_update_ixr(s);

}

static void xilinx_spips_write(void *opaque, hwaddr addr,

                                        uint64_t value, unsigned size)

{

    int mask = ~0;

    int man_start_com = 0;

    XilinxSPIPS *s = opaque;



    DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);

    addr >>= 2;

    switch (addr) {

    case R_CONFIG:

        mask = 0x0002FFFF;

        if (value & MAN_START_COM) {

            man_start_com = 1;

        }

        break;

    case R_INTR_STATUS:

        mask = IXR_ALL;

        s->regs[R_INTR_STATUS] &= ~(mask & value);

        goto no_reg_update;

    case R_INTR_DIS:

        mask = IXR_ALL;

        s->regs[R_INTR_MASK] &= ~(mask & value);

        goto no_reg_update;

    case R_INTR_EN:

        mask = IXR_ALL;

        s->regs[R_INTR_MASK] |= mask & value;

        goto no_reg_update;

    case R_EN:

        mask = 0x1;

        break;

    case R_SLAVE_IDLE_COUNT:

        mask = 0xFF;

        break;

    case R_RX_DATA:

    case R_INTR_MASK:

    case R_MOD_ID:

        mask = 0;

        break;

    case R_TX_DATA:

        tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes);

        goto no_reg_update;

    case R_TXD1:

        tx_data_bytes(s, (uint32_t)value, 1);

        goto no_reg_update;

    case R_TXD2:

        tx_data_bytes(s, (uint32_t)value, 2);

        goto no_reg_update;

    case R_TXD3:

        tx_data_bytes(s, (uint32_t)value, 3);

        goto no_reg_update;

    }

    s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);

no_reg_update:

    xilinx_spips_update_cs_lines(s);

    if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) ||

            (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) {

        xilinx_spips_flush_txfifo(s);

    }

    xilinx_spips_update_cs_lines(s);

    xilinx_spips_update_ixr(s);

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1,

                                        uint64_t VAR_2, unsigned VAR_3)

{

    int VAR_4 = ~0;

    int VAR_5 = 0;

    XilinxSPIPS *s = VAR_0;



    DB_PRINT("VAR_1=" TARGET_FMT_plx " = %x\n", VAR_1, (unsigned)VAR_2);

    VAR_1 >>= 2;

    switch (VAR_1) {

    case R_CONFIG:

        VAR_4 = 0x0002FFFF;

        if (VAR_2 & MAN_START_COM) {

            VAR_5 = 1;

        }

        break;

    case R_INTR_STATUS:

        VAR_4 = IXR_ALL;

        s->regs[R_INTR_STATUS] &= ~(VAR_4 & VAR_2);

        goto no_reg_update;

    case R_INTR_DIS:

        VAR_4 = IXR_ALL;

        s->regs[R_INTR_MASK] &= ~(VAR_4 & VAR_2);

        goto no_reg_update;

    case R_INTR_EN:

        VAR_4 = IXR_ALL;

        s->regs[R_INTR_MASK] |= VAR_4 & VAR_2;

        goto no_reg_update;

    case R_EN:

        VAR_4 = 0x1;

        break;

    case R_SLAVE_IDLE_COUNT:

        VAR_4 = 0xFF;

        break;

    case R_RX_DATA:

    case R_INTR_MASK:

    case R_MOD_ID:

        VAR_4 = 0;

        break;

    case R_TX_DATA:

        tx_data_bytes(s, (uint32_t)VAR_2, s->num_txrx_bytes);

        goto no_reg_update;

    case R_TXD1:

        tx_data_bytes(s, (uint32_t)VAR_2, 1);

        goto no_reg_update;

    case R_TXD2:

        tx_data_bytes(s, (uint32_t)VAR_2, 2);

        goto no_reg_update;

    case R_TXD3:

        tx_data_bytes(s, (uint32_t)VAR_2, 3);

        goto no_reg_update;

    }

    s->regs[VAR_1] = (s->regs[VAR_1] & ~VAR_4) | (VAR_2 & VAR_4);

no_reg_update:

    xilinx_spips_update_cs_lines(s);

    if ((VAR_5 && s->regs[R_CONFIG] & MAN_START_EN) ||

            (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) {

        xilinx_spips_flush_txfifo(s);

    }

    xilinx_spips_update_cs_lines(s);

    xilinx_spips_update_ixr(s);

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ int VAR_4 = ~0; int VAR_5 = 0; XilinxSPIPS *s = VAR_0; DB_PRINT("VAR_1=" TARGET_FMT_plx " = %x\n", VAR_1, (unsigned)VAR_2); VAR_1 >>= 2; switch (VAR_1) { case R_CONFIG:
VAR_4 = 0x0002FFFF; if (VAR_2 & MAN_START_COM) { VAR_5 = 1; } break; case R_INTR_STATUS:
VAR_4 = IXR_ALL; s->regs[R_INTR_STATUS] &= ~(VAR_4 & VAR_2); goto no_reg_update; case R_INTR_DIS:
VAR_4 = IXR_ALL; s->regs[R_INTR_MASK] &= ~(VAR_4 & VAR_2); goto no_reg_update; case R_INTR_EN:
VAR_4 = IXR_ALL; s->regs[R_INTR_MASK] |= VAR_4 & VAR_2; goto no_reg_update; case R_EN:
VAR_4 = 0x1; break; case R_SLAVE_IDLE_COUNT:
VAR_4 = 0xFF; break; case R_RX_DATA:
case R_INTR_MASK:
case R_MOD_ID:
VAR_4 = 0; break; case R_TX_DATA:
tx_data_bytes(s, (uint32_t)VAR_2, s->num_txrx_bytes); goto no_reg_update; case R_TXD1:
tx_data_bytes(s, (uint32_t)VAR_2, 1); goto no_reg_update; case R_TXD2:
tx_data_bytes(s, (uint32_t)VAR_2, 2); goto no_reg_update; case R_TXD3:
tx_data_bytes(s, (uint32_t)VAR_2, 3); goto no_reg_update; } s->regs[VAR_1] = (s->regs[VAR_1] & ~VAR_4) | (VAR_2 & VAR_4); no_reg_update:
xilinx_spips_update_cs_lines(s); if ((VAR_5 && s->regs[R_CONFIG] & MAN_START_EN) ||
(fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) { xilinx_spips_flush_txfifo(s); } xilinx_spips_update_cs_lines(s); xilinx_spips_update_ixr(s); }