static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)

{

    /* Return true if it is not valid for us to switch to

     * this CPU mode (ie all the UNPREDICTABLE cases in

     * the ARM ARM CPSRWriteByInstr pseudocode).




    /* Changes to or from Hyp via MSR and CPS are illegal. */


        ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||

         mode == ARM_CPU_MODE_HYP)) {





    switch (mode) {

    case ARM_CPU_MODE_USR:

        return 0;

    case ARM_CPU_MODE_SYS:

    case ARM_CPU_MODE_SVC:

    case ARM_CPU_MODE_ABT:

    case ARM_CPU_MODE_UND:

    case ARM_CPU_MODE_IRQ:

    case ARM_CPU_MODE_FIQ:

        /* Note that we don't implement the IMPDEF NSACR.RFR which in v7

         * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)











        return 0;

    case ARM_CPU_MODE_HYP:

        return !arm_feature(env, ARM_FEATURE_EL2)

            || arm_current_el(env) < 2 || arm_is_secure(env);

    case ARM_CPU_MODE_MON:

        return arm_current_el(env) < 3;

    default:



static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)

{

    











        ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||

         mode == ARM_CPU_MODE_HYP)) {





    switch (mode) {

    case ARM_CPU_MODE_USR:

        return 0;

    case ARM_CPU_MODE_SYS:

    case ARM_CPU_MODE_SVC:

    case ARM_CPU_MODE_ABT:

    case ARM_CPU_MODE_UND:

    case ARM_CPU_MODE_IRQ:

    case ARM_CPU_MODE_FIQ:

        /* Note that we don't implement the IMPDEF NSACR.RFR which in v7

         * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)











        return 0;

    case ARM_CPU_MODE_HYP:

        return !arm_feature(env, ARM_FEATURE_EL2)

            || arm_current_el(env) < 2 || arm_is_secure(env);

    case ARM_CPU_MODE_MON:

        return arm_current_el(env) < 3;

    default:



static int FUNC_0(CPUARMState *VAR_0, int VAR_1, CPSRWriteType VAR_2)

{

    











        ((VAR_0->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||

         VAR_1 == ARM_CPU_MODE_HYP)) {





    switch (VAR_1) {

    case ARM_CPU_MODE_USR:

        return 0;

    case ARM_CPU_MODE_SYS:

    case ARM_CPU_MODE_SVC:

    case ARM_CPU_MODE_ABT:

    case ARM_CPU_MODE_UND:

    case ARM_CPU_MODE_IRQ:

    case ARM_CPU_MODE_FIQ:

        /* Note that we don't implement the IMPDEF NSACR.RFR which in v7

         * allows FIQ VAR_1 to be Secure-only. (In v8 this doesn't exist.)











        return 0;

    case ARM_CPU_MODE_HYP:

        return !arm_feature(VAR_0, ARM_FEATURE_EL2)

            || arm_current_el(VAR_0) < 2 || arm_is_secure(VAR_0);

    case ARM_CPU_MODE_MON:

        return arm_current_el(VAR_0) < 3;

    default:



static int FUNC_0(CPUARMState *VAR_0, int VAR_1, CPSRWriteType VAR_2)
{ ((VAR_0->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
VAR_1 == ARM_CPU_MODE_HYP)) { switch (VAR_1) { case ARM_CPU_MODE_USR:
return 0; case ARM_CPU_MODE_SYS:
case ARM_CPU_MODE_SVC:
case ARM_CPU_MODE_ABT:
case ARM_CPU_MODE_UND:
case ARM_CPU_MODE_IRQ:
case ARM_CPU_MODE_FIQ:
/* Note that we don't implement the IMPDEF NSACR.RFR which in v7
* allows FIQ VAR_1 to be Secure-only. (In v8 this doesn't exist.)
return 0; case ARM_CPU_MODE_HYP:
return !arm_feature(VAR_0, ARM_FEATURE_EL2)
|| arm_current_el(VAR_0) < 2 || arm_is_secure(VAR_0); case ARM_CPU_MODE_MON:
return arm_current_el(VAR_0) < 3;