static void pfpu_write(void *opaque, target_phys_addr_t addr, uint64_t value,

                       unsigned size)

{

    MilkymistPFPUState *s = opaque;



    trace_milkymist_pfpu_memory_write(addr, value);



    addr >>= 2;

    switch (addr) {

    case R_CTL:

        if (value & CTL_START_BUSY) {

            pfpu_start(s);

        }

        break;

    case R_MESHBASE:

    case R_HMESHLAST:

    case R_VMESHLAST:

    case R_CODEPAGE:

    case R_VERTICES:

    case R_COLLISIONS:

    case R_STRAYWRITES:

    case R_LASTDMA:

    case R_PC:

    case R_DREGBASE:

    case R_CODEBASE:

        s->regs[addr] = value;

        break;

    case GPR_BEGIN ...  GPR_END:

        s->gp_regs[addr - GPR_BEGIN] = value;

        break;

    case MICROCODE_BEGIN ...  MICROCODE_END:

        s->microcode[get_microcode_address(s, addr)] = value;

        break;



    default:

        error_report("milkymist_pfpu: write access to unknown register 0x"

                TARGET_FMT_plx, addr << 2);

        break;

    }

}

static void pfpu_write(void *opaque, target_phys_addr_t addr, uint64_t value,

                       unsigned size)

{

    MilkymistPFPUState *s = opaque;



    trace_milkymist_pfpu_memory_write(addr, value);



    addr >>= 2;

    switch (addr) {

    case R_CTL:

        if (value & CTL_START_BUSY) {

            pfpu_start(s);

        }

        break;

    case R_MESHBASE:

    case R_HMESHLAST:

    case R_VMESHLAST:

    case R_CODEPAGE:

    case R_VERTICES:

    case R_COLLISIONS:

    case R_STRAYWRITES:

    case R_LASTDMA:

    case R_PC:

    case R_DREGBASE:

    case R_CODEBASE:

        s->regs[addr] = value;

        break;

    case GPR_BEGIN ...  GPR_END:

        s->gp_regs[addr - GPR_BEGIN] = value;

        break;

    case MICROCODE_BEGIN ...  MICROCODE_END:

        s->microcode[get_microcode_address(s, addr)] = value;

        break;



    default:

        error_report("milkymist_pfpu: write access to unknown register 0x"

                TARGET_FMT_plx, addr << 2);

        break;

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint64_t VAR_2,

                       unsigned VAR_3)

{

    MilkymistPFPUState *s = VAR_0;



    trace_milkymist_pfpu_memory_write(VAR_1, VAR_2);



    VAR_1 >>= 2;

    switch (VAR_1) {

    case R_CTL:

        if (VAR_2 & CTL_START_BUSY) {

            pfpu_start(s);

        }

        break;

    case R_MESHBASE:

    case R_HMESHLAST:

    case R_VMESHLAST:

    case R_CODEPAGE:

    case R_VERTICES:

    case R_COLLISIONS:

    case R_STRAYWRITES:

    case R_LASTDMA:

    case R_PC:

    case R_DREGBASE:

    case R_CODEBASE:

        s->regs[VAR_1] = VAR_2;

        break;

    case GPR_BEGIN ...  GPR_END:

        s->gp_regs[VAR_1 - GPR_BEGIN] = VAR_2;

        break;

    case MICROCODE_BEGIN ...  MICROCODE_END:

        s->microcode[get_microcode_address(s, VAR_1)] = VAR_2;

        break;



    default:

        error_report("milkymist_pfpu: write access to unknown register 0x"

                TARGET_FMT_plx, VAR_1 << 2);

        break;

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint64_t VAR_2,
unsigned VAR_3)
{ MilkymistPFPUState *s = VAR_0; trace_milkymist_pfpu_memory_write(VAR_1, VAR_2); VAR_1 >>= 2; switch (VAR_1) { case R_CTL:
if (VAR_2 & CTL_START_BUSY) { pfpu_start(s); } break; case R_MESHBASE:
case R_HMESHLAST:
case R_VMESHLAST:
case R_CODEPAGE:
case R_VERTICES:
case R_COLLISIONS:
case R_STRAYWRITES:
case R_LASTDMA:
case R_PC:
case R_DREGBASE:
case R_CODEBASE:
s->regs[VAR_1] = VAR_2; break; case GPR_BEGIN ...  GPR_END:
s->gp_regs[VAR_1 - GPR_BEGIN] = VAR_2; break; case MICROCODE_BEGIN ...  MICROCODE_END:
s->microcode[get_microcode_address(s, VAR_1)] = VAR_2; break; default:
error_report("milkymist_pfpu: write access to unknown register 0x"
TARGET_FMT_plx, VAR_1 << 2); break; } }