static void openpic_reset(DeviceState *d)

{

    OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(d));

    int i;



    opp->glbc = GLBC_RESET;

    /* Initialise controller registers */

    opp->frep = ((opp->nb_irqs -1) << FREP_NIRQ_SHIFT) |

                ((opp->nb_cpus -1) << FREP_NCPU_SHIFT) |

                (opp->vid << FREP_VID_SHIFT);



    opp->pint = 0;

    opp->spve = -1 & opp->spve_mask;

    opp->tifr = opp->tifr_reset;

    /* Initialise IRQ sources */

    for (i = 0; i < opp->max_irq; i++) {

        opp->src[i].ipvp = opp->ipvp_reset;

        opp->src[i].ide  = opp->ide_reset;

    }

    /* Initialise IRQ destinations */

    for (i = 0; i < MAX_CPU; i++) {

        opp->dst[i].pctp      = 15;

        opp->dst[i].pcsr      = 0x00000000;

        memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));

        opp->dst[i].raised.next = -1;

        memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));

        opp->dst[i].servicing.next = -1;

    }

    /* Initialise timers */

    for (i = 0; i < MAX_TMR; i++) {

        opp->timers[i].ticc = 0;

        opp->timers[i].tibc = TIBC_CI;

    }

    /* Go out of RESET state */

    opp->glbc = 0;

}

static void openpic_reset(DeviceState *d)

{

    OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(d));

    int i;



    opp->glbc = GLBC_RESET;

    

    opp->frep = ((opp->nb_irqs -1) << FREP_NIRQ_SHIFT) |

                ((opp->nb_cpus -1) << FREP_NCPU_SHIFT) |

                (opp->vid << FREP_VID_SHIFT);



    opp->pint = 0;

    opp->spve = -1 & opp->spve_mask;

    opp->tifr = opp->tifr_reset;

    

    for (i = 0; i < opp->max_irq; i++) {

        opp->src[i].ipvp = opp->ipvp_reset;

        opp->src[i].ide  = opp->ide_reset;

    }

    

    for (i = 0; i < MAX_CPU; i++) {

        opp->dst[i].pctp      = 15;

        opp->dst[i].pcsr      = 0x00000000;

        memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));

        opp->dst[i].raised.next = -1;

        memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));

        opp->dst[i].servicing.next = -1;

    }

    

    for (i = 0; i < MAX_TMR; i++) {

        opp->timers[i].ticc = 0;

        opp->timers[i].tibc = TIBC_CI;

    }

    

    opp->glbc = 0;

}

static void FUNC_0(DeviceState *VAR_0)

{

    OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(VAR_0));

    int VAR_1;



    opp->glbc = GLBC_RESET;

    

    opp->frep = ((opp->nb_irqs -1) << FREP_NIRQ_SHIFT) |

                ((opp->nb_cpus -1) << FREP_NCPU_SHIFT) |

                (opp->vid << FREP_VID_SHIFT);



    opp->pint = 0;

    opp->spve = -1 & opp->spve_mask;

    opp->tifr = opp->tifr_reset;

    

    for (VAR_1 = 0; VAR_1 < opp->max_irq; VAR_1++) {

        opp->src[VAR_1].ipvp = opp->ipvp_reset;

        opp->src[VAR_1].ide  = opp->ide_reset;

    }

    

    for (VAR_1 = 0; VAR_1 < MAX_CPU; VAR_1++) {

        opp->dst[VAR_1].pctp      = 15;

        opp->dst[VAR_1].pcsr      = 0x00000000;

        memset(&opp->dst[VAR_1].raised, 0, sizeof(IRQ_queue_t));

        opp->dst[VAR_1].raised.next = -1;

        memset(&opp->dst[VAR_1].servicing, 0, sizeof(IRQ_queue_t));

        opp->dst[VAR_1].servicing.next = -1;

    }

    

    for (VAR_1 = 0; VAR_1 < MAX_TMR; VAR_1++) {

        opp->timers[VAR_1].ticc = 0;

        opp->timers[VAR_1].tibc = TIBC_CI;

    }

    

    opp->glbc = 0;

}

static void FUNC_0(DeviceState *VAR_0)
{ OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(VAR_0)); int VAR_1; opp->glbc = GLBC_RESET; opp->frep = ((opp->nb_irqs -1) << FREP_NIRQ_SHIFT) |
((opp->nb_cpus -1) << FREP_NCPU_SHIFT) |
(opp->vid << FREP_VID_SHIFT); opp->pint = 0; opp->spve = -1 & opp->spve_mask; opp->tifr = opp->tifr_reset; for (VAR_1 = 0; VAR_1 < opp->max_irq; VAR_1++) { opp->src[VAR_1].ipvp = opp->ipvp_reset; opp->src[VAR_1].ide  = opp->ide_reset; } for (VAR_1 = 0; VAR_1 < MAX_CPU; VAR_1++) { opp->dst[VAR_1].pctp      = 15; opp->dst[VAR_1].pcsr      = 0x00000000; memset(&opp->dst[VAR_1].raised, 0, sizeof(IRQ_queue_t)); opp->dst[VAR_1].raised.next = -1; memset(&opp->dst[VAR_1].servicing, 0, sizeof(IRQ_queue_t)); opp->dst[VAR_1].servicing.next = -1; } for (VAR_1 = 0; VAR_1 < MAX_TMR; VAR_1++) { opp->timers[VAR_1].ticc = 0; opp->timers[VAR_1].tibc = TIBC_CI; } opp->glbc = 0; }