void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)

{

    switch (fs) {

    case 1:

        /* UFR Alias - Reset Status FR */

        if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {

            return;

        }

        if (env->CP0_Config5 & (1 << CP0C5_UFR)) {

            env->CP0_Status &= ~(1 << CP0St_FR);

            compute_hflags(env);

        } else {

            helper_raise_exception(env, EXCP_RI);

        }

        break;

    case 4:

        /* UNFR Alias - Set Status FR */

        if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {

            return;

        }

        if (env->CP0_Config5 & (1 << CP0C5_UFR)) {

            env->CP0_Status |= (1 << CP0St_FR);

            compute_hflags(env);

        } else {

            helper_raise_exception(env, EXCP_RI);

        }

        break;

    case 25:

        if (arg1 & 0xffffff00)

            return;

        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |

                     ((arg1 & 0x1) << 23);

        break;

    case 26:

        if (arg1 & 0x007c0000)

            return;

        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);

        break;

    case 28:

        if (arg1 & 0x007c0000)

            return;

        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |

                     ((arg1 & 0x4) << 22);

        break;

    case 31:

        if (arg1 & 0x007c0000)

            return;

        env->active_fpu.fcr31 = arg1;

        break;

    default:

        return;

    }

    /* set rounding mode */

    restore_rounding_mode(env);

    /* set flush-to-zero mode */

    restore_flush_mode(env);

    set_float_exception_flags(0, &env->active_fpu.fp_status);

    if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))

        do_raise_exception(env, EXCP_FPE, GETPC());

}

void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)

{

    switch (fs) {

    case 1:

        

        if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {

            return;

        }

        if (env->CP0_Config5 & (1 << CP0C5_UFR)) {

            env->CP0_Status &= ~(1 << CP0St_FR);

            compute_hflags(env);

        } else {

            helper_raise_exception(env, EXCP_RI);

        }

        break;

    case 4:

        

        if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {

            return;

        }

        if (env->CP0_Config5 & (1 << CP0C5_UFR)) {

            env->CP0_Status |= (1 << CP0St_FR);

            compute_hflags(env);

        } else {

            helper_raise_exception(env, EXCP_RI);

        }

        break;

    case 25:

        if (arg1 & 0xffffff00)

            return;

        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |

                     ((arg1 & 0x1) << 23);

        break;

    case 26:

        if (arg1 & 0x007c0000)

            return;

        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);

        break;

    case 28:

        if (arg1 & 0x007c0000)

            return;

        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |

                     ((arg1 & 0x4) << 22);

        break;

    case 31:

        if (arg1 & 0x007c0000)

            return;

        env->active_fpu.fcr31 = arg1;

        break;

    default:

        return;

    }

    

    restore_rounding_mode(env);

    

    restore_flush_mode(env);

    set_float_exception_flags(0, &env->active_fpu.fp_status);

    if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))

        do_raise_exception(env, EXCP_FPE, GETPC());

}

void FUNC_0(CPUMIPSState *VAR_0, target_ulong VAR_1, uint32_t VAR_2, uint32_t VAR_3)

{

    switch (VAR_2) {

    case 1:

        

        if (!((VAR_0->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (VAR_3 == 0))) {

            return;

        }

        if (VAR_0->CP0_Config5 & (1 << CP0C5_UFR)) {

            VAR_0->CP0_Status &= ~(1 << CP0St_FR);

            compute_hflags(VAR_0);

        } else {

            helper_raise_exception(VAR_0, EXCP_RI);

        }

        break;

    case 4:

        

        if (!((VAR_0->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (VAR_3 == 0))) {

            return;

        }

        if (VAR_0->CP0_Config5 & (1 << CP0C5_UFR)) {

            VAR_0->CP0_Status |= (1 << CP0St_FR);

            compute_hflags(VAR_0);

        } else {

            helper_raise_exception(VAR_0, EXCP_RI);

        }

        break;

    case 25:

        if (VAR_1 & 0xffffff00)

            return;

        VAR_0->active_fpu.fcr31 = (VAR_0->active_fpu.fcr31 & 0x017fffff) | ((VAR_1 & 0xfe) << 24) |

                     ((VAR_1 & 0x1) << 23);

        break;

    case 26:

        if (VAR_1 & 0x007c0000)

            return;

        VAR_0->active_fpu.fcr31 = (VAR_0->active_fpu.fcr31 & 0xfffc0f83) | (VAR_1 & 0x0003f07c);

        break;

    case 28:

        if (VAR_1 & 0x007c0000)

            return;

        VAR_0->active_fpu.fcr31 = (VAR_0->active_fpu.fcr31 & 0xfefff07c) | (VAR_1 & 0x00000f83) |

                     ((VAR_1 & 0x4) << 22);

        break;

    case 31:

        if (VAR_1 & 0x007c0000)

            return;

        VAR_0->active_fpu.fcr31 = VAR_1;

        break;

    default:

        return;

    }

    

    restore_rounding_mode(VAR_0);

    

    restore_flush_mode(VAR_0);

    set_float_exception_flags(0, &VAR_0->active_fpu.fp_status);

    if ((GET_FP_ENABLE(VAR_0->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(VAR_0->active_fpu.fcr31))

        do_raise_exception(VAR_0, EXCP_FPE, GETPC());

}

void FUNC_0(CPUMIPSState *VAR_0, target_ulong VAR_1, uint32_t VAR_2, uint32_t VAR_3)
{ switch (VAR_2) { case 1:
if (!((VAR_0->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (VAR_3 == 0))) { return; } if (VAR_0->CP0_Config5 & (1 << CP0C5_UFR)) { VAR_0->CP0_Status &= ~(1 << CP0St_FR); compute_hflags(VAR_0); } else { helper_raise_exception(VAR_0, EXCP_RI); } break; case 4:
if (!((VAR_0->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (VAR_3 == 0))) { return; } if (VAR_0->CP0_Config5 & (1 << CP0C5_UFR)) { VAR_0->CP0_Status |= (1 << CP0St_FR); compute_hflags(VAR_0); } else { helper_raise_exception(VAR_0, EXCP_RI); } break; case 25:
if (VAR_1 & 0xffffff00)
return; VAR_0->active_fpu.fcr31 = (VAR_0->active_fpu.fcr31 & 0x017fffff) | ((VAR_1 & 0xfe) << 24) |
((VAR_1 & 0x1) << 23); break; case 26:
if (VAR_1 & 0x007c0000)
return; VAR_0->active_fpu.fcr31 = (VAR_0->active_fpu.fcr31 & 0xfffc0f83) | (VAR_1 & 0x0003f07c); break; case 28:
if (VAR_1 & 0x007c0000)
return; VAR_0->active_fpu.fcr31 = (VAR_0->active_fpu.fcr31 & 0xfefff07c) | (VAR_1 & 0x00000f83) |
((VAR_1 & 0x4) << 22); break; case 31:
if (VAR_1 & 0x007c0000)
return; VAR_0->active_fpu.fcr31 = VAR_1; break; default:
return; } restore_rounding_mode(VAR_0); restore_flush_mode(VAR_0); set_float_exception_flags(0, &VAR_0->active_fpu.fp_status); if ((GET_FP_ENABLE(VAR_0->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(VAR_0->active_fpu.fcr31))
do_raise_exception(VAR_0, EXCP_FPE, GETPC()); }