static void imx_fec_do_tx(IMXFECState *s)

{

    int frame_size = 0;

    uint8_t frame[ENET_MAX_FRAME_SIZE];

    uint8_t *ptr = frame;

    uint32_t addr = s->tx_descriptor;



    while (1) {

        IMXFECBufDesc bd;

        int len;



        imx_fec_read_bd(&bd, addr);

        FEC_PRINTF("tx_bd %x flags %04x len %d data %08x\n",

                   addr, bd.flags, bd.length, bd.data);

        if ((bd.flags & ENET_BD_R) == 0) {

            /* Run out of descriptors to transmit.  */

            FEC_PRINTF("tx_bd ran out of descriptors to transmit\n");

            break;

        }

        len = bd.length;

        if (frame_size + len > ENET_MAX_FRAME_SIZE) {

            len = ENET_MAX_FRAME_SIZE - frame_size;

            s->regs[ENET_EIR] |= ENET_INT_BABT;

        }

        dma_memory_read(&address_space_memory, bd.data, ptr, len);

        ptr += len;

        frame_size += len;

        if (bd.flags & ENET_BD_L) {

            /* Last buffer in frame.  */

            qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size);

            ptr = frame;

            frame_size = 0;

            s->regs[ENET_EIR] |= ENET_INT_TXF;

        }

        s->regs[ENET_EIR] |= ENET_INT_TXB;

        bd.flags &= ~ENET_BD_R;

        /* Write back the modified descriptor.  */

        imx_fec_write_bd(&bd, addr);

        /* Advance to the next descriptor.  */

        if ((bd.flags & ENET_BD_W) != 0) {

            addr = s->regs[ENET_TDSR];

        } else {

            addr += sizeof(bd);

        }

    }



    s->tx_descriptor = addr;



    imx_eth_update(s);

}

static void imx_fec_do_tx(IMXFECState *s)

{

    int frame_size = 0;

    uint8_t frame[ENET_MAX_FRAME_SIZE];

    uint8_t *ptr = frame;

    uint32_t addr = s->tx_descriptor;



    while (1) {

        IMXFECBufDesc bd;

        int len;



        imx_fec_read_bd(&bd, addr);

        FEC_PRINTF("tx_bd %x flags %04x len %d data %08x\n",

                   addr, bd.flags, bd.length, bd.data);

        if ((bd.flags & ENET_BD_R) == 0) {

            

            FEC_PRINTF("tx_bd ran out of descriptors to transmit\n");

            break;

        }

        len = bd.length;

        if (frame_size + len > ENET_MAX_FRAME_SIZE) {

            len = ENET_MAX_FRAME_SIZE - frame_size;

            s->regs[ENET_EIR] |= ENET_INT_BABT;

        }

        dma_memory_read(&address_space_memory, bd.data, ptr, len);

        ptr += len;

        frame_size += len;

        if (bd.flags & ENET_BD_L) {

            

            qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size);

            ptr = frame;

            frame_size = 0;

            s->regs[ENET_EIR] |= ENET_INT_TXF;

        }

        s->regs[ENET_EIR] |= ENET_INT_TXB;

        bd.flags &= ~ENET_BD_R;

        

        imx_fec_write_bd(&bd, addr);

        

        if ((bd.flags & ENET_BD_W) != 0) {

            addr = s->regs[ENET_TDSR];

        } else {

            addr += sizeof(bd);

        }

    }



    s->tx_descriptor = addr;



    imx_eth_update(s);

}

static void FUNC_0(IMXFECState *VAR_0)

{

    int VAR_1 = 0;

    uint8_t frame[ENET_MAX_FRAME_SIZE];

    uint8_t *ptr = frame;

    uint32_t addr = VAR_0->tx_descriptor;



    while (1) {

        IMXFECBufDesc bd;

        int VAR_2;



        imx_fec_read_bd(&bd, addr);

        FEC_PRINTF("tx_bd %x flags %04x VAR_2 %d data %08x\n",

                   addr, bd.flags, bd.length, bd.data);

        if ((bd.flags & ENET_BD_R) == 0) {

            

            FEC_PRINTF("tx_bd ran out of descriptors to transmit\n");

            break;

        }

        VAR_2 = bd.length;

        if (VAR_1 + VAR_2 > ENET_MAX_FRAME_SIZE) {

            VAR_2 = ENET_MAX_FRAME_SIZE - VAR_1;

            VAR_0->regs[ENET_EIR] |= ENET_INT_BABT;

        }

        dma_memory_read(&address_space_memory, bd.data, ptr, VAR_2);

        ptr += VAR_2;

        VAR_1 += VAR_2;

        if (bd.flags & ENET_BD_L) {

            

            qemu_send_packet(qemu_get_queue(VAR_0->nic), frame, VAR_1);

            ptr = frame;

            VAR_1 = 0;

            VAR_0->regs[ENET_EIR] |= ENET_INT_TXF;

        }

        VAR_0->regs[ENET_EIR] |= ENET_INT_TXB;

        bd.flags &= ~ENET_BD_R;

        

        imx_fec_write_bd(&bd, addr);

        

        if ((bd.flags & ENET_BD_W) != 0) {

            addr = VAR_0->regs[ENET_TDSR];

        } else {

            addr += sizeof(bd);

        }

    }



    VAR_0->tx_descriptor = addr;



    imx_eth_update(VAR_0);

}

static void FUNC_0(IMXFECState *VAR_0)
{ int VAR_1 = 0; uint8_t frame[ENET_MAX_FRAME_SIZE]; uint8_t *ptr = frame; uint32_t addr = VAR_0->tx_descriptor; while (1) { IMXFECBufDesc bd; int VAR_2; imx_fec_read_bd(&bd, addr); FEC_PRINTF("tx_bd %x flags %04x VAR_2 %d data %08x\n",
addr, bd.flags, bd.length, bd.data); if ((bd.flags & ENET_BD_R) == 0) { FEC_PRINTF("tx_bd ran out of descriptors to transmit\n"); break; } VAR_2 = bd.length; if (VAR_1 + VAR_2 > ENET_MAX_FRAME_SIZE) { VAR_2 = ENET_MAX_FRAME_SIZE - VAR_1; VAR_0->regs[ENET_EIR] |= ENET_INT_BABT; } dma_memory_read(&address_space_memory, bd.data, ptr, VAR_2); ptr += VAR_2; VAR_1 += VAR_2; if (bd.flags & ENET_BD_L) { qemu_send_packet(qemu_get_queue(VAR_0->nic), frame, VAR_1); ptr = frame; VAR_1 = 0; VAR_0->regs[ENET_EIR] |= ENET_INT_TXF; } VAR_0->regs[ENET_EIR] |= ENET_INT_TXB; bd.flags &= ~ENET_BD_R; imx_fec_write_bd(&bd, addr); if ((bd.flags & ENET_BD_W) != 0) { addr = VAR_0->regs[ENET_TDSR]; } else { addr += sizeof(bd); } } VAR_0->tx_descriptor = addr; imx_eth_update(VAR_0); }