static struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,

                qemu_irq *irq, omap_clk clk)

{

    int iomemtype;

    struct omap_rtc_s *s = (struct omap_rtc_s *)

            qemu_mallocz(sizeof(struct omap_rtc_s));



    s->irq = irq[0];

    s->alarm = irq[1];

    s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s);



    omap_rtc_reset(s);



    iomemtype = cpu_register_io_memory(omap_rtc_readfn,

                    omap_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);

    cpu_register_physical_memory(base, 0x800, iomemtype);



    return s;

}

static struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,

                qemu_irq *irq, omap_clk clk)

{

    int iomemtype;

    struct omap_rtc_s *s = (struct omap_rtc_s *)

            qemu_mallocz(sizeof(struct omap_rtc_s));



    s->irq = irq[0];

    s->alarm = irq[1];

    s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s);



    omap_rtc_reset(s);



    iomemtype = cpu_register_io_memory(omap_rtc_readfn,

                    omap_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);

    cpu_register_physical_memory(base, 0x800, iomemtype);



    return s;

}

static struct omap_rtc_s *FUNC_0(target_phys_addr_t VAR_0,

                qemu_irq *VAR_1, omap_clk VAR_2)

{

    int VAR_3;

    struct omap_rtc_s *VAR_4 = (struct omap_rtc_s *)

            qemu_mallocz(sizeof(struct omap_rtc_s));



    VAR_4->VAR_1 = VAR_1[0];

    VAR_4->alarm = VAR_1[1];

    VAR_4->VAR_2 = qemu_new_timer(rt_clock, omap_rtc_tick, VAR_4);



    omap_rtc_reset(VAR_4);



    VAR_3 = cpu_register_io_memory(omap_rtc_readfn,

                    omap_rtc_writefn, VAR_4, DEVICE_NATIVE_ENDIAN);

    cpu_register_physical_memory(VAR_0, 0x800, VAR_3);



    return VAR_4;

}

static struct omap_rtc_s *FUNC_0(target_phys_addr_t VAR_0,
qemu_irq *VAR_1, omap_clk VAR_2)
{ int VAR_3; struct omap_rtc_s *VAR_4 = (struct omap_rtc_s *)
qemu_mallocz(sizeof(struct omap_rtc_s)); VAR_4->VAR_1 = VAR_1[0]; VAR_4->alarm = VAR_1[1]; VAR_4->VAR_2 = qemu_new_timer(rt_clock, omap_rtc_tick, VAR_4); omap_rtc_reset(VAR_4); VAR_3 = cpu_register_io_memory(omap_rtc_readfn,
omap_rtc_writefn, VAR_4, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(VAR_0, 0x800, VAR_3); return VAR_4; }