static void uart_write(void *opaque, target_phys_addr_t offset,

                          uint64_t value, unsigned size)

{

    UartState *s = (UartState *)opaque;



    DB_PRINT(" offset:%x data:%08x\n", offset, (unsigned)value);

    offset >>= 2;

    switch (offset) {

    case R_IER: /* ier (wts imr) */

        s->r[R_IMR] |= value;

        break;

    case R_IDR: /* idr (wtc imr) */

        s->r[R_IMR] &= ~value;

        break;

    case R_IMR: /* imr (read only) */

        break;

    case R_CISR: /* cisr (wtc) */

        s->r[R_CISR] &= ~value;

        break;

    case R_TX_RX: /* UARTDR */

        switch (s->r[R_MR] & UART_MR_CHMODE) {

        case NORMAL_MODE:

            uart_write_tx_fifo(s, (uint8_t *) &value, 1);

            break;

        case LOCAL_LOOPBACK:

            uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);

            break;

        }

        break;

    default:

        s->r[offset] = value;

    }



    switch (offset) {

    case R_CR:

        uart_ctrl_update(s);

        break;

    case R_MR:

        uart_parameters_setup(s);

        break;

    }

}

static void uart_write(void *opaque, target_phys_addr_t offset,

                          uint64_t value, unsigned size)

{

    UartState *s = (UartState *)opaque;



    DB_PRINT(" offset:%x data:%08x\n", offset, (unsigned)value);

    offset >>= 2;

    switch (offset) {

    case R_IER: 

        s->r[R_IMR] |= value;

        break;

    case R_IDR: 

        s->r[R_IMR] &= ~value;

        break;

    case R_IMR: 

        break;

    case R_CISR: 

        s->r[R_CISR] &= ~value;

        break;

    case R_TX_RX: 

        switch (s->r[R_MR] & UART_MR_CHMODE) {

        case NORMAL_MODE:

            uart_write_tx_fifo(s, (uint8_t *) &value, 1);

            break;

        case LOCAL_LOOPBACK:

            uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);

            break;

        }

        break;

    default:

        s->r[offset] = value;

    }



    switch (offset) {

    case R_CR:

        uart_ctrl_update(s);

        break;

    case R_MR:

        uart_parameters_setup(s);

        break;

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                          uint64_t VAR_2, unsigned VAR_3)

{

    UartState *s = (UartState *)VAR_0;



    DB_PRINT(" VAR_1:%x data:%08x\n", VAR_1, (unsigned)VAR_2);

    VAR_1 >>= 2;

    switch (VAR_1) {

    case R_IER: 

        s->r[R_IMR] |= VAR_2;

        break;

    case R_IDR: 

        s->r[R_IMR] &= ~VAR_2;

        break;

    case R_IMR: 

        break;

    case R_CISR: 

        s->r[R_CISR] &= ~VAR_2;

        break;

    case R_TX_RX: 

        switch (s->r[R_MR] & UART_MR_CHMODE) {

        case NORMAL_MODE:

            uart_write_tx_fifo(s, (uint8_t *) &VAR_2, 1);

            break;

        case LOCAL_LOOPBACK:

            uart_write_rx_fifo(VAR_0, (uint8_t *) &VAR_2, 1);

            break;

        }

        break;

    default:

        s->r[VAR_1] = VAR_2;

    }



    switch (VAR_1) {

    case R_CR:

        uart_ctrl_update(s);

        break;

    case R_MR:

        uart_parameters_setup(s);

        break;

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ UartState *s = (UartState *)VAR_0; DB_PRINT(" VAR_1:%x data:%08x\n", VAR_1, (unsigned)VAR_2); VAR_1 >>= 2; switch (VAR_1) { case R_IER:
s->r[R_IMR] |= VAR_2; break; case R_IDR:
s->r[R_IMR] &= ~VAR_2; break; case R_IMR:
break; case R_CISR:
s->r[R_CISR] &= ~VAR_2; break; case R_TX_RX:
switch (s->r[R_MR] & UART_MR_CHMODE) { case NORMAL_MODE:
uart_write_tx_fifo(s, (uint8_t *) &VAR_2, 1); break; case LOCAL_LOOPBACK:
uart_write_rx_fifo(VAR_0, (uint8_t *) &VAR_2, 1); break; } break; default:
s->r[VAR_1] = VAR_2; } switch (VAR_1) { case R_CR:
uart_ctrl_update(s); break; case R_MR:
uart_parameters_setup(s); break; } }