static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,

                                unsigned len)

{

    OpenPICState *opp = opaque;

    int idx;



    DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);

    if (addr & 0xF)

        return;

    idx = (addr >> 6) & 0x3;

    addr = addr & 0x30;



    if (addr == 0x0) {

        /* TIFR (TFRR) */

        opp->tifr = val;

        return;

    }

    switch (addr & 0x30) {

    case 0x00: /* TICC (GTCCR) */

        break;

    case 0x10: /* TIBC (GTBCR) */

        if ((opp->timers[idx].ticc & TICC_TOG) != 0 &&

            (val & TIBC_CI) == 0 &&

            (opp->timers[idx].tibc & TIBC_CI) != 0) {

            opp->timers[idx].ticc &= ~TICC_TOG;

        }

        opp->timers[idx].tibc = val;

        break;

    case 0x20: /* TIVP (GTIVPR) */

        write_IRQreg_ipvp(opp, opp->irq_tim0 + idx, val);

        break;

    case 0x30: /* TIDE (GTIDR) */

        write_IRQreg_ide(opp, opp->irq_tim0 + idx, val);

        break;

    }

}

static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,

                                unsigned len)

{

    OpenPICState *opp = opaque;

    int idx;



    DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);

    if (addr & 0xF)

        return;

    idx = (addr >> 6) & 0x3;

    addr = addr & 0x30;



    if (addr == 0x0) {

        

        opp->tifr = val;

        return;

    }

    switch (addr & 0x30) {

    case 0x00: 

        break;

    case 0x10: 

        if ((opp->timers[idx].ticc & TICC_TOG) != 0 &&

            (val & TIBC_CI) == 0 &&

            (opp->timers[idx].tibc & TIBC_CI) != 0) {

            opp->timers[idx].ticc &= ~TICC_TOG;

        }

        opp->timers[idx].tibc = val;

        break;

    case 0x20: 

        write_IRQreg_ipvp(opp, opp->irq_tim0 + idx, val);

        break;

    case 0x30: 

        write_IRQreg_ide(opp, opp->irq_tim0 + idx, val);

        break;

    }

}

    if (addr & 0xF)     if (addr & 0xF)     if (addr & 0xF)     if (addr & 0xF)     if (addr & 0xF)     if (addr & 0xF)     if (addr & 0xF)
static void FUNC_0(void *VAR_0, hwaddr VAR_1, uint64_t VAR_2,

                                unsigned VAR_3)

{

    OpenPICState *opp = VAR_0;

    int VAR_4;



    DPRINTF("%s: VAR_1 %08x <= %08x\n", __func__, VAR_1, VAR_2);

    if (VAR_1 & 0xF)

        return;

    VAR_4 = (VAR_1 >> 6) & 0x3;

    VAR_1 = VAR_1 & 0x30;



    if (VAR_1 == 0x0) {

        

        opp->tifr = VAR_2;

        return;

    }

    switch (VAR_1 & 0x30) {

    case 0x00: 

        break;

    case 0x10: 

        if ((opp->timers[VAR_4].ticc & TICC_TOG) != 0 &&

            (VAR_2 & TIBC_CI) == 0 &&

            (opp->timers[VAR_4].tibc & TIBC_CI) != 0) {

            opp->timers[VAR_4].ticc &= ~TICC_TOG;

        }

        opp->timers[VAR_4].tibc = VAR_2;

        break;

    case 0x20: 

        write_IRQreg_ipvp(opp, opp->irq_tim0 + VAR_4, VAR_2);

        break;

    case 0x30: 

        write_IRQreg_ide(opp, opp->irq_tim0 + VAR_4, VAR_2);

        break;

    }

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1, uint64_t VAR_2,
unsigned VAR_3)
{ OpenPICState *opp = VAR_0; int VAR_4; DPRINTF("%s: VAR_1 %08x <= %08x\n", __func__, VAR_1, VAR_2); if (VAR_1 & 0xF)
return; VAR_4 = (VAR_1 >> 6) & 0x3; VAR_1 = VAR_1 & 0x30; if (VAR_1 == 0x0) { opp->tifr = VAR_2; return; } switch (VAR_1 & 0x30) { case 0x00:
break; case 0x10:
if ((opp->timers[VAR_4].ticc & TICC_TOG) != 0 &&
(VAR_2 & TIBC_CI) == 0 &&
(opp->timers[VAR_4].tibc & TIBC_CI) != 0) { opp->timers[VAR_4].ticc &= ~TICC_TOG; } opp->timers[VAR_4].tibc = VAR_2; break; case 0x20:
write_IRQreg_ipvp(opp, opp->irq_tim0 + VAR_4, VAR_2); break; case 0x30:
write_IRQreg_ide(opp, opp->irq_tim0 + VAR_4, VAR_2); break; } }