static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,

                                   uint64_t value, unsigned size)

{

    struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;



    if (size < 2) {

        return omap_badwidth_write16(opaque, addr, value);

    }



    switch (addr) {

    case 0x00:	/* TIPB_CNTL */

        s->control = value & 0xffff;

        break;



    case 0x04:	/* TIPB_BUS_ALLOC */

        s->alloc = value & 0x003f;

        break;



    case 0x08:	/* MPU_TIPB_CNTL */

        s->buffer = value & 0x0003;

        break;



    case 0x0c:	/* ENHANCED_TIPB_CNTL */

        s->width_intr = !(value & 2);

        s->enh_control = value & 0x000f;

        break;



    case 0x10:	/* ADDRESS_DBG */

    case 0x14:	/* DATA_DEBUG_LOW */

    case 0x18:	/* DATA_DEBUG_HIGH */

    case 0x1c:	/* DEBUG_CNTR_SIG */

        OMAP_RO_REG(addr);

        break;



    default:

        OMAP_BAD_REG(addr);

    }

}

static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,

                                   uint64_t value, unsigned size)

{

    struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;



    if (size < 2) {

        return omap_badwidth_write16(opaque, addr, value);

    }



    switch (addr) {

    case 0x00:	

        s->control = value & 0xffff;

        break;



    case 0x04:	

        s->alloc = value & 0x003f;

        break;



    case 0x08:	

        s->buffer = value & 0x0003;

        break;



    case 0x0c:	

        s->width_intr = !(value & 2);

        s->enh_control = value & 0x000f;

        break;



    case 0x10:	

    case 0x14:	

    case 0x18:	

    case 0x1c:	

        OMAP_RO_REG(addr);

        break;



    default:

        OMAP_BAD_REG(addr);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                                   uint64_t VAR_2, unsigned VAR_3)

{

    struct omap_tipb_bridge_s *VAR_4 = (struct omap_tipb_bridge_s *) VAR_0;



    if (VAR_3 < 2) {

        return omap_badwidth_write16(VAR_0, VAR_1, VAR_2);

    }



    switch (VAR_1) {

    case 0x00:	

        VAR_4->control = VAR_2 & 0xffff;

        break;



    case 0x04:	

        VAR_4->alloc = VAR_2 & 0x003f;

        break;



    case 0x08:	

        VAR_4->buffer = VAR_2 & 0x0003;

        break;



    case 0x0c:	

        VAR_4->width_intr = !(VAR_2 & 2);

        VAR_4->enh_control = VAR_2 & 0x000f;

        break;



    case 0x10:	

    case 0x14:	

    case 0x18:	

    case 0x1c:	

        OMAP_RO_REG(VAR_1);

        break;



    default:

        OMAP_BAD_REG(VAR_1);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ struct omap_tipb_bridge_s *VAR_4 = (struct omap_tipb_bridge_s *) VAR_0; if (VAR_3 < 2) { return omap_badwidth_write16(VAR_0, VAR_1, VAR_2); } switch (VAR_1) { case 0x00:
VAR_4->control = VAR_2 & 0xffff; break; case 0x04:
VAR_4->alloc = VAR_2 & 0x003f; break; case 0x08:
VAR_4->buffer = VAR_2 & 0x0003; break; case 0x0c:
VAR_4->width_intr = !(VAR_2 & 2); VAR_4->enh_control = VAR_2 & 0x000f; break; case 0x10:
case 0x14:
case 0x18:
case 0x1c:
OMAP_RO_REG(VAR_1); break; default:
OMAP_BAD_REG(VAR_1); } }