static void omap_uwire_write(void *opaque, target_phys_addr_t addr,

                             uint64_t value, unsigned size)

{

    struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;



    if (size != 2) {

        return omap_badwidth_write16(opaque, addr, value);

    }



    switch (offset) {

    case 0x00:	/* TDR */

        s->txbuf = value;				/* TD */

        if ((s->setup[4] & (1 << 2)) &&			/* AUTO_TX_EN */

                        ((s->setup[4] & (1 << 3)) ||	/* CS_TOGGLE_TX_EN */

                         (s->control & (1 << 12)))) {	/* CS_CMD */

            s->control |= 1 << 14;			/* CSRB */

            omap_uwire_transfer_start(s);

        }

        break;



    case 0x04:	/* CSR */

        s->control = value & 0x1fff;

        if (value & (1 << 13))				/* START */

            omap_uwire_transfer_start(s);

        break;



    case 0x08:	/* SR1 */

        s->setup[0] = value & 0x003f;

        break;



    case 0x0c:	/* SR2 */

        s->setup[1] = value & 0x0fc0;

        break;



    case 0x10:	/* SR3 */

        s->setup[2] = value & 0x0003;

        break;



    case 0x14:	/* SR4 */

        s->setup[3] = value & 0x0001;

        break;



    case 0x18:	/* SR5 */

        s->setup[4] = value & 0x000f;

        break;



    default:

        OMAP_BAD_REG(addr);

        return;

    }

}

static void omap_uwire_write(void *opaque, target_phys_addr_t addr,

                             uint64_t value, unsigned size)

{

    struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;



    if (size != 2) {

        return omap_badwidth_write16(opaque, addr, value);

    }



    switch (offset) {

    case 0x00:	

        s->txbuf = value;				

        if ((s->setup[4] & (1 << 2)) &&			

                        ((s->setup[4] & (1 << 3)) ||	

                         (s->control & (1 << 12)))) {	

            s->control |= 1 << 14;			

            omap_uwire_transfer_start(s);

        }

        break;



    case 0x04:	

        s->control = value & 0x1fff;

        if (value & (1 << 13))				

            omap_uwire_transfer_start(s);

        break;



    case 0x08:	

        s->setup[0] = value & 0x003f;

        break;



    case 0x0c:	

        s->setup[1] = value & 0x0fc0;

        break;



    case 0x10:	

        s->setup[2] = value & 0x0003;

        break;



    case 0x14:	

        s->setup[3] = value & 0x0001;

        break;



    case 0x18:	

        s->setup[4] = value & 0x000f;

        break;



    default:

        OMAP_BAD_REG(addr);

        return;

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                             uint64_t VAR_2, unsigned VAR_3)

{

    struct omap_uwire_s *VAR_4 = (struct omap_uwire_s *) VAR_0;

    int VAR_5 = VAR_1 & OMAP_MPUI_REG_MASK;



    if (VAR_3 != 2) {

        return omap_badwidth_write16(VAR_0, VAR_1, VAR_2);

    }



    switch (VAR_5) {

    case 0x00:	

        VAR_4->txbuf = VAR_2;				

        if ((VAR_4->setup[4] & (1 << 2)) &&			

                        ((VAR_4->setup[4] & (1 << 3)) ||	

                         (VAR_4->control & (1 << 12)))) {	

            VAR_4->control |= 1 << 14;			

            omap_uwire_transfer_start(VAR_4);

        }

        break;



    case 0x04:	

        VAR_4->control = VAR_2 & 0x1fff;

        if (VAR_2 & (1 << 13))				

            omap_uwire_transfer_start(VAR_4);

        break;



    case 0x08:	

        VAR_4->setup[0] = VAR_2 & 0x003f;

        break;



    case 0x0c:	

        VAR_4->setup[1] = VAR_2 & 0x0fc0;

        break;



    case 0x10:	

        VAR_4->setup[2] = VAR_2 & 0x0003;

        break;



    case 0x14:	

        VAR_4->setup[3] = VAR_2 & 0x0001;

        break;



    case 0x18:	

        VAR_4->setup[4] = VAR_2 & 0x000f;

        break;



    default:

        OMAP_BAD_REG(VAR_1);

        return;

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ struct omap_uwire_s *VAR_4 = (struct omap_uwire_s *) VAR_0; int VAR_5 = VAR_1 & OMAP_MPUI_REG_MASK; if (VAR_3 != 2) { return omap_badwidth_write16(VAR_0, VAR_1, VAR_2); } switch (VAR_5) { case 0x00:
VAR_4->txbuf = VAR_2; if ((VAR_4->setup[4] & (1 << 2)) &&
((VAR_4->setup[4] & (1 << 3)) ||
(VAR_4->control & (1 << 12)))) { VAR_4->control |= 1 << 14; omap_uwire_transfer_start(VAR_4); } break; case 0x04:
VAR_4->control = VAR_2 & 0x1fff; if (VAR_2 & (1 << 13))
omap_uwire_transfer_start(VAR_4); break; case 0x08:
VAR_4->setup[0] = VAR_2 & 0x003f; break; case 0x0c:
VAR_4->setup[1] = VAR_2 & 0x0fc0; break; case 0x10:
VAR_4->setup[2] = VAR_2 & 0x0003; break; case 0x14:
VAR_4->setup[3] = VAR_2 & 0x0001; break; case 0x18:
VAR_4->setup[4] = VAR_2 & 0x000f; break; default:
OMAP_BAD_REG(VAR_1); return; } }