void gicv3_cpuif_update(GICv3CPUState *cs)
{
    /* Tell the CPU about its highest priority pending interrupt */
    int irqlevel = 0;
    int fiqlevel = 0;
    ARMCPU *cpu = ARM_CPU(cs->cpu);
    CPUARMState *env = &cpu->env;
    trace_gicv3_cpuif_update(gicv3_redist_affid(cs), cs->hppi.irq,
                             cs->hppi.grp, cs->hppi.prio);
    if (cs->hppi.grp == GICV3_G1 && !arm_feature(env, ARM_FEATURE_EL3)) {
        /* If a Security-enabled GIC sends a G1S interrupt to a
         * Security-disabled CPU, we must treat it as if it were G0.
         */
        cs->hppi.grp = GICV3_G0;
    }
    if (icc_hppi_can_preempt(cs)) {
        /* We have an interrupt: should we signal it as IRQ or FIQ?
         * This is described in the GICv3 spec section 4.6.2.
         */
        bool isfiq;
        switch (cs->hppi.grp) {
        case GICV3_G0:
            isfiq = true;
            break;
        case GICV3_G1:
            isfiq = (!arm_is_secure(env) ||
                     (arm_current_el(env) == 3 && arm_el_is_aa64(env, 3)));
            break;
        case GICV3_G1NS:
            isfiq = arm_is_secure(env);
            break;
        default:
            g_assert_not_reached();
        }
        if (isfiq) {
            fiqlevel = 1;
        } else {
            irqlevel = 1;
        }
    }
    trace_gicv3_cpuif_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel);
    qemu_set_irq(cs->parent_fiq, fiqlevel);
    qemu_set_irq(cs->parent_irq, irqlevel);
}
void gicv3_cpuif_update(GICv3CPUState *cs)
{
    
    int irqlevel = 0;
    int fiqlevel = 0;
    ARMCPU *cpu = ARM_CPU(cs->cpu);
    CPUARMState *env = &cpu->env;
    trace_gicv3_cpuif_update(gicv3_redist_affid(cs), cs->hppi.irq,
                             cs->hppi.grp, cs->hppi.prio);
    if (cs->hppi.grp == GICV3_G1 && !arm_feature(env, ARM_FEATURE_EL3)) {
        


        cs->hppi.grp = GICV3_G0;
    }
    if (icc_hppi_can_preempt(cs)) {
        


        bool isfiq;
        switch (cs->hppi.grp) {
        case GICV3_G0:
            isfiq = true;
            break;
        case GICV3_G1:
            isfiq = (!arm_is_secure(env) ||
                     (arm_current_el(env) == 3 && arm_el_is_aa64(env, 3)));
            break;
        case GICV3_G1NS:
            isfiq = arm_is_secure(env);
            break;
        default:
            g_assert_not_reached();
        }
        if (isfiq) {
            fiqlevel = 1;
        } else {
            irqlevel = 1;
        }
    }
    trace_gicv3_cpuif_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel);
    qemu_set_irq(cs->parent_fiq, fiqlevel);
    qemu_set_irq(cs->parent_irq, irqlevel);
}
void FUNC_0(GICv3CPUState *VAR_0)
{
    
    int VAR_1 = 0;
    int VAR_2 = 0;
    ARMCPU *cpu = ARM_CPU(VAR_0->cpu);
    CPUARMState *env = &cpu->env;
    trace_gicv3_cpuif_update(gicv3_redist_affid(VAR_0), VAR_0->hppi.irq,
                             VAR_0->hppi.grp, VAR_0->hppi.prio);
    if (VAR_0->hppi.grp == GICV3_G1 && !arm_feature(env, ARM_FEATURE_EL3)) {
        


        VAR_0->hppi.grp = GICV3_G0;
    }
    if (icc_hppi_can_preempt(VAR_0)) {
        


        bool isfiq;
        switch (VAR_0->hppi.grp) {
        case GICV3_G0:
            isfiq = true;
            break;
        case GICV3_G1:
            isfiq = (!arm_is_secure(env) ||
                     (arm_current_el(env) == 3 && arm_el_is_aa64(env, 3)));
            break;
        case GICV3_G1NS:
            isfiq = arm_is_secure(env);
            break;
        default:
            g_assert_not_reached();
        }
        if (isfiq) {
            VAR_2 = 1;
        } else {
            VAR_1 = 1;
        }
    }
    trace_gicv3_cpuif_set_irqs(gicv3_redist_affid(VAR_0), VAR_2, VAR_1);
    qemu_set_irq(VAR_0->parent_fiq, VAR_2);
    qemu_set_irq(VAR_0->parent_irq, VAR_1);
}
void FUNC_0(GICv3CPUState *VAR_0)
{ int VAR_1 = 0; int VAR_2 = 0; ARMCPU *cpu = ARM_CPU(VAR_0->cpu); CPUARMState *env = &cpu->env; trace_gicv3_cpuif_update(gicv3_redist_affid(VAR_0), VAR_0->hppi.irq,
VAR_0->hppi.grp, VAR_0->hppi.prio); if (VAR_0->hppi.grp == GICV3_G1 && !arm_feature(env, ARM_FEATURE_EL3)) { VAR_0->hppi.grp = GICV3_G0; } if (icc_hppi_can_preempt(VAR_0)) { bool isfiq; switch (VAR_0->hppi.grp) { case GICV3_G0:
isfiq = true; break; case GICV3_G1:
isfiq = (!arm_is_secure(env) ||
(arm_current_el(env) == 3 && arm_el_is_aa64(env, 3))); break; case GICV3_G1NS:
isfiq = arm_is_secure(env); break; default:
g_assert_not_reached(); } if (isfiq) { VAR_2 = 1; } else { VAR_1 = 1; } } trace_gicv3_cpuif_set_irqs(gicv3_redist_affid(VAR_0), VAR_2, VAR_1); qemu_set_irq(VAR_0->parent_fiq, VAR_2); qemu_set_irq(VAR_0->parent_irq, VAR_1); }