void do_interrupt(CPUState *env)

{

    int intno = env->exception_index;



#ifdef DEBUG_PCALL

    if (qemu_loglevel_mask(CPU_LOG_INT)) {

        static int count;

        const char *name;



        if (intno < 0 || intno >= 0x180)

            name = "Unknown";

        else if (intno >= 0x100)

            name = "Trap Instruction";

        else if (intno >= 0xc0)

            name = "Window Fill";

        else if (intno >= 0x80)

            name = "Window Spill";

        else {

            name = excp_names[intno];

            if (!name)

                name = "Unknown";

        }



        qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64

                " SP=%016" PRIx64 "\n",

                count, name, intno,

                env->pc,

                env->npc, env->regwptr[6]);

        log_cpu_state(env, 0);

#if 0

        {

            int i;

            uint8_t *ptr;



            qemu_log("       code=");

            ptr = (uint8_t *)env->pc;

            for(i = 0; i < 16; i++) {

                qemu_log(" %02x", ldub(ptr + i));

            }

            qemu_log("\n");

        }

#endif

        count++;

    }

#endif

#if !defined(CONFIG_USER_ONLY)

    if (env->tl >= env->maxtl) {

        cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"

                  " Error state", env->exception_index, env->tl, env->maxtl);

        return;

    }

#endif

    if (env->tl < env->maxtl - 1) {

        env->tl++;

    } else {

        env->pstate |= PS_RED;

        if (env->tl < env->maxtl)

            env->tl++;

    }

    env->tsptr = &env->ts[env->tl & MAXTL_MASK];

    env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |

        ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |

        GET_CWP64(env);

    env->tsptr->tpc = env->pc;

    env->tsptr->tnpc = env->npc;

    env->tsptr->tt = intno;

    if (!(env->def->features & CPU_FEATURE_GL)) {

        switch (intno) {

        case TT_IVEC:

            change_pstate(PS_PEF | PS_PRIV | PS_IG);

            break;

        case TT_TFAULT:

        case TT_TMISS:

        case TT_DFAULT:

        case TT_DMISS:

        case TT_DPROT:

            change_pstate(PS_PEF | PS_PRIV | PS_MG);

            break;

        default:

            change_pstate(PS_PEF | PS_PRIV | PS_AG);

            break;

        }

    }

    if (intno == TT_CLRWIN)

        cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));

    else if ((intno & 0x1c0) == TT_SPILL)

        cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));

    else if ((intno & 0x1c0) == TT_FILL)

        cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));

    env->tbr &= ~0x7fffULL;

    env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);

    env->pc = env->tbr;

    env->npc = env->pc + 4;

    env->exception_index = 0;

}

void do_interrupt(CPUState *env)

{

    int intno = env->exception_index;



#ifdef DEBUG_PCALL

    if (qemu_loglevel_mask(CPU_LOG_INT)) {

        static int count;

        const char *name;



        if (intno < 0 || intno >= 0x180)

            name = "Unknown";

        else if (intno >= 0x100)

            name = "Trap Instruction";

        else if (intno >= 0xc0)

            name = "Window Fill";

        else if (intno >= 0x80)

            name = "Window Spill";

        else {

            name = excp_names[intno];

            if (!name)

                name = "Unknown";

        }



        qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64

                " SP=%016" PRIx64 "\n",

                count, name, intno,

                env->pc,

                env->npc, env->regwptr[6]);

        log_cpu_state(env, 0);

#if 0

        {

            int i;

            uint8_t *ptr;



            qemu_log("       code=");

            ptr = (uint8_t *)env->pc;

            for(i = 0; i < 16; i++) {

                qemu_log(" %02x", ldub(ptr + i));

            }

            qemu_log("\n");

        }

#endif

        count++;

    }

#endif

#if !defined(CONFIG_USER_ONLY)

    if (env->tl >= env->maxtl) {

        cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"

                  " Error state", env->exception_index, env->tl, env->maxtl);

        return;

    }

#endif

    if (env->tl < env->maxtl - 1) {

        env->tl++;

    } else {

        env->pstate |= PS_RED;

        if (env->tl < env->maxtl)

            env->tl++;

    }

    env->tsptr = &env->ts[env->tl & MAXTL_MASK];

    env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |

        ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |

        GET_CWP64(env);

    env->tsptr->tpc = env->pc;

    env->tsptr->tnpc = env->npc;

    env->tsptr->tt = intno;

    if (!(env->def->features & CPU_FEATURE_GL)) {

        switch (intno) {

        case TT_IVEC:

            change_pstate(PS_PEF | PS_PRIV | PS_IG);

            break;

        case TT_TFAULT:

        case TT_TMISS:

        case TT_DFAULT:

        case TT_DMISS:

        case TT_DPROT:

            change_pstate(PS_PEF | PS_PRIV | PS_MG);

            break;

        default:

            change_pstate(PS_PEF | PS_PRIV | PS_AG);

            break;

        }

    }

    if (intno == TT_CLRWIN)

        cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));

    else if ((intno & 0x1c0) == TT_SPILL)

        cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));

    else if ((intno & 0x1c0) == TT_FILL)

        cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));

    env->tbr &= ~0x7fffULL;

    env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);

    env->pc = env->tbr;

    env->npc = env->pc + 4;

    env->exception_index = 0;

}

    if (!(env->def->features & CPU_FEATURE_GL)) {         switch (intno) {         case TT_IVEC:             change_pstate(PS_PEF | PS_PRIV | PS_IG);             break;         case TT_TFAULT:         case TT_TMISS:         case TT_DFAULT:         case TT_DMISS:         case TT_DPROT:             change_pstate(PS_PEF | PS_PRIV | PS_MG);             break;         default:             change_pstate(PS_PEF | PS_PRIV | PS_AG);             break;
void FUNC_0(CPUState *VAR_0)

{

    int VAR_1 = VAR_0->exception_index;



#ifdef DEBUG_PCALL

    if (qemu_loglevel_mask(CPU_LOG_INT)) {

        static int count;

        const char *name;



        if (VAR_1 < 0 || VAR_1 >= 0x180)

            name = "Unknown";

        else if (VAR_1 >= 0x100)

            name = "Trap Instruction";

        else if (VAR_1 >= 0xc0)

            name = "Window Fill";

        else if (VAR_1 >= 0x80)

            name = "Window Spill";

        else {

            name = excp_names[VAR_1];

            if (!name)

                name = "Unknown";

        }



        qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64

                " SP=%016" PRIx64 "\n",

                count, name, VAR_1,

                VAR_0->pc,

                VAR_0->npc, VAR_0->regwptr[6]);

        log_cpu_state(VAR_0, 0);

#if 0

        {

            int i;

            uint8_t *ptr;



            qemu_log("       code=");

            ptr = (uint8_t *)VAR_0->pc;

            for(i = 0; i < 16; i++) {

                qemu_log(" %02x", ldub(ptr + i));

            }

            qemu_log("\n");

        }

#endif

        count++;

    }

#endif

#if !defined(CONFIG_USER_ONLY)

    if (VAR_0->tl >= VAR_0->maxtl) {

        cpu_abort(VAR_0, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"

                  " Error state", VAR_0->exception_index, VAR_0->tl, VAR_0->maxtl);

        return;

    }

#endif

    if (VAR_0->tl < VAR_0->maxtl - 1) {

        VAR_0->tl++;

    } else {

        VAR_0->pstate |= PS_RED;

        if (VAR_0->tl < VAR_0->maxtl)

            VAR_0->tl++;

    }

    VAR_0->tsptr = &VAR_0->ts[VAR_0->tl & MAXTL_MASK];

    VAR_0->tsptr->tstate = ((uint64_t)GET_CCR(VAR_0) << 32) |

        ((VAR_0->asi & 0xff) << 24) | ((VAR_0->pstate & 0xf3f) << 8) |

        GET_CWP64(VAR_0);

    VAR_0->tsptr->tpc = VAR_0->pc;

    VAR_0->tsptr->tnpc = VAR_0->npc;

    VAR_0->tsptr->tt = VAR_1;

    if (!(VAR_0->def->features & CPU_FEATURE_GL)) {

        switch (VAR_1) {

        case TT_IVEC:

            change_pstate(PS_PEF | PS_PRIV | PS_IG);

            break;

        case TT_TFAULT:

        case TT_TMISS:

        case TT_DFAULT:

        case TT_DMISS:

        case TT_DPROT:

            change_pstate(PS_PEF | PS_PRIV | PS_MG);

            break;

        default:

            change_pstate(PS_PEF | PS_PRIV | PS_AG);

            break;

        }

    }

    if (VAR_1 == TT_CLRWIN)

        cpu_set_cwp(VAR_0, cpu_cwp_dec(VAR_0, VAR_0->cwp - 1));

    else if ((VAR_1 & 0x1c0) == TT_SPILL)

        cpu_set_cwp(VAR_0, cpu_cwp_dec(VAR_0, VAR_0->cwp - VAR_0->cansave - 2));

    else if ((VAR_1 & 0x1c0) == TT_FILL)

        cpu_set_cwp(VAR_0, cpu_cwp_inc(VAR_0, VAR_0->cwp + 1));

    VAR_0->tbr &= ~0x7fffULL;

    VAR_0->tbr |= ((VAR_0->tl > 1) ? 1 << 14 : 0) | (VAR_1 << 5);

    VAR_0->pc = VAR_0->tbr;

    VAR_0->npc = VAR_0->pc + 4;

    VAR_0->exception_index = 0;

}

void FUNC_0(CPUState *VAR_0)
{ int VAR_1 = VAR_0->exception_index; #ifdef DEBUG_PCALL
if (qemu_loglevel_mask(CPU_LOG_INT)) { static int count; const char *name; if (VAR_1 < 0 || VAR_1 >= 0x180)
name = "Unknown"; else if (VAR_1 >= 0x100)
name = "Trap Instruction"; else if (VAR_1 >= 0xc0)
name = "Window Fill"; else if (VAR_1 >= 0x80)
name = "Window Spill"; else { name = excp_names[VAR_1]; if (!name)
name = "Unknown"; } qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
" SP=%016" PRIx64 "\n",
count, name, VAR_1,
VAR_0->pc,
VAR_0->npc, VAR_0->regwptr[6]); log_cpu_state(VAR_0, 0); #if 0
{ int i; uint8_t *ptr; qemu_log("       code="); ptr = (uint8_t *)VAR_0->pc; for(i = 0; i < 16; i++) { qemu_log(" %02x", ldub(ptr + i)); } qemu_log("\n"); } #endif
count++; } #endif
#if !defined(CONFIG_USER_ONLY)
if (VAR_0->tl >= VAR_0->maxtl) { cpu_abort(VAR_0, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
" Error state", VAR_0->exception_index, VAR_0->tl, VAR_0->maxtl); return; } #endif
if (VAR_0->tl < VAR_0->maxtl - 1) { VAR_0->tl++; } else { VAR_0->pstate |= PS_RED; if (VAR_0->tl < VAR_0->maxtl)
VAR_0->tl++; } VAR_0->tsptr = &VAR_0->ts[VAR_0->tl & MAXTL_MASK]; VAR_0->tsptr->tstate = ((uint64_t)GET_CCR(VAR_0) << 32) |
((VAR_0->asi & 0xff) << 24) | ((VAR_0->pstate & 0xf3f) << 8) |
GET_CWP64(VAR_0); VAR_0->tsptr->tpc = VAR_0->pc; VAR_0->tsptr->tnpc = VAR_0->npc; VAR_0->tsptr->tt = VAR_1; if (!(VAR_0->def->features & CPU_FEATURE_GL)) { switch (VAR_1) { case TT_IVEC:
change_pstate(PS_PEF | PS_PRIV | PS_IG); break; case TT_TFAULT:
case TT_TMISS:
case TT_DFAULT:
case TT_DMISS:
case TT_DPROT:
change_pstate(PS_PEF | PS_PRIV | PS_MG); break; default:
change_pstate(PS_PEF | PS_PRIV | PS_AG); break; } } if (VAR_1 == TT_CLRWIN)
cpu_set_cwp(VAR_0, cpu_cwp_dec(VAR_0, VAR_0->cwp - 1)); else if ((VAR_1 & 0x1c0) == TT_SPILL)
cpu_set_cwp(VAR_0, cpu_cwp_dec(VAR_0, VAR_0->cwp - VAR_0->cansave - 2)); else if ((VAR_1 & 0x1c0) == TT_FILL)
cpu_set_cwp(VAR_0, cpu_cwp_inc(VAR_0, VAR_0->cwp + 1)); VAR_0->tbr &= ~0x7fffULL; VAR_0->tbr |= ((VAR_0->tl > 1) ? 1 << 14 : 0) | (VAR_1 << 5); VAR_0->pc = VAR_0->tbr; VAR_0->npc = VAR_0->pc + 4; VAR_0->exception_index = 0; }