struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,

                CPUState *env, qemu_irq *pic, int lines)

{

    int iomemtype;

    struct pxa2xx_gpio_info_s *s;



    s = (struct pxa2xx_gpio_info_s *)

            qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s));

    memset(s, 0, sizeof(struct pxa2xx_gpio_info_s));

    s->base = base;

    s->pic = pic;

    s->lines = lines;

    s->cpu_env = env;



    iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn,

                    pxa2xx_gpio_writefn, s);

    cpu_register_physical_memory(base, 0x00000fff, iomemtype);



    register_savevm("pxa2xx_gpio", 0, 0,

                    pxa2xx_gpio_save, pxa2xx_gpio_load, s);



    return s;

}

struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,

                CPUState *env, qemu_irq *pic, int lines)

{

    int iomemtype;

    struct pxa2xx_gpio_info_s *s;



    s = (struct pxa2xx_gpio_info_s *)

            qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s));

    memset(s, 0, sizeof(struct pxa2xx_gpio_info_s));

    s->base = base;

    s->pic = pic;

    s->lines = lines;

    s->cpu_env = env;



    iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn,

                    pxa2xx_gpio_writefn, s);

    cpu_register_physical_memory(base, 0x00000fff, iomemtype);



    register_savevm("pxa2xx_gpio", 0, 0,

                    pxa2xx_gpio_save, pxa2xx_gpio_load, s);



    return s;

}

    cpu_register_physical_memory(base, 0x00000fff, iomemtype);     cpu_register_physical_memory(base, 0x00000fff, iomemtype);     cpu_register_physical_memory(base, 0x00000fff, iomemtype);     cpu_register_physical_memory(base, 0x00000fff, iomemtype);     cpu_register_physical_memory(base, 0x00000fff, iomemtype);     cpu_register_physical_memory(base, 0x00000fff, iomemtype);     cpu_register_physical_memory(base, 0x00000fff, iomemtype);     cpu_register_physical_memory(base, 0x00000fff, iomemtype);     cpu_register_physical_memory(base, 0x00000fff, iomemtype);     cpu_register_physical_memory(base, 0x00000fff, iomemtype);     cpu_register_physical_memory(base, 0x00000fff, iomemtype);     cpu_register_physical_memory(base, 0x00000fff, iomemtype);
struct pxa2xx_gpio_info_s *FUNC_0(target_phys_addr_t VAR_0,

                CPUState *VAR_1, qemu_irq *VAR_2, int VAR_3)

{

    int VAR_4;

    struct pxa2xx_gpio_info_s *VAR_5;



    VAR_5 = (struct pxa2xx_gpio_info_s *)

            qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s));

    memset(VAR_5, 0, sizeof(struct pxa2xx_gpio_info_s));

    VAR_5->VAR_0 = VAR_0;

    VAR_5->VAR_2 = VAR_2;

    VAR_5->VAR_3 = VAR_3;

    VAR_5->cpu_env = VAR_1;



    VAR_4 = cpu_register_io_memory(0, pxa2xx_gpio_readfn,

                    pxa2xx_gpio_writefn, VAR_5);

    cpu_register_physical_memory(VAR_0, 0x00000fff, VAR_4);



    register_savevm("pxa2xx_gpio", 0, 0,

                    pxa2xx_gpio_save, pxa2xx_gpio_load, VAR_5);



    return VAR_5;

}

struct pxa2xx_gpio_info_s *FUNC_0(target_phys_addr_t VAR_0,
CPUState *VAR_1, qemu_irq *VAR_2, int VAR_3)
{ int VAR_4; struct pxa2xx_gpio_info_s *VAR_5; VAR_5 = (struct pxa2xx_gpio_info_s *)
qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s)); memset(VAR_5, 0, sizeof(struct pxa2xx_gpio_info_s)); VAR_5->VAR_0 = VAR_0; VAR_5->VAR_2 = VAR_2; VAR_5->VAR_3 = VAR_3; VAR_5->cpu_env = VAR_1; VAR_4 = cpu_register_io_memory(0, pxa2xx_gpio_readfn,
pxa2xx_gpio_writefn, VAR_5); cpu_register_physical_memory(VAR_0, 0x00000fff, VAR_4); register_savevm("pxa2xx_gpio", 0, 0,
pxa2xx_gpio_save, pxa2xx_gpio_load, VAR_5); return VAR_5; }