static int ppce500_load_device_tree(MachineState *machine,

                                    PPCE500Params *params,

                                    hwaddr addr,

                                    hwaddr initrd_base,

                                    hwaddr initrd_size,

                                    hwaddr kernel_base,

                                    hwaddr kernel_size,

                                    bool dry_run)

{

    CPUPPCState *env = first_cpu->env_ptr;

    int ret = -1;

    uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };

    int fdt_size;

    void *fdt;

    uint8_t hypercall[16];

    uint32_t clock_freq = 400000000;

    uint32_t tb_freq = 400000000;

    int i;

    char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";

    char soc[128];

    char mpic[128];

    uint32_t mpic_ph;

    uint32_t msi_ph;

    char gutil[128];

    char pci[128];

    char msi[128];

    uint32_t *pci_map = NULL;

    int len;

    uint32_t pci_ranges[14] =

        {

            0x2000000, 0x0, params->pci_mmio_bus_base,

            params->pci_mmio_base >> 32, params->pci_mmio_base,

            0x0, 0x20000000,



            0x1000000, 0x0, 0x0,

            params->pci_pio_base >> 32, params->pci_pio_base,

            0x0, 0x10000,

        };

    QemuOpts *machine_opts = qemu_get_machine_opts();

    const char *dtb_file = qemu_opt_get(machine_opts, "dtb");

    const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");



    if (dtb_file) {

        char *filename;

        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);

        if (!filename) {

            goto out;

        }



        fdt = load_device_tree(filename, &fdt_size);


        if (!fdt) {

            goto out;

        }

        goto done;

    }



    fdt = create_device_tree(&fdt_size);

    if (fdt == NULL) {

        goto out;

    }



    /* Manipulate device tree in memory. */

    qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);

    qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);



    qemu_fdt_add_subnode(fdt, "/memory");

    qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");

    qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,

                     sizeof(mem_reg_property));



    qemu_fdt_add_subnode(fdt, "/chosen");

    if (initrd_size) {

        ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",

                                    initrd_base);

        if (ret < 0) {

            fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");

        }



        ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",

                                    (initrd_base + initrd_size));

        if (ret < 0) {

            fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");

        }



    }



    if (kernel_base != -1ULL) {

        qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",

                                     kernel_base >> 32, kernel_base,

                                     kernel_size >> 32, kernel_size);

    }



    ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",

                                      machine->kernel_cmdline);

    if (ret < 0)

        fprintf(stderr, "couldn't set /chosen/bootargs\n");



    if (kvm_enabled()) {

        /* Read out host's frequencies */

        clock_freq = kvmppc_get_clockfreq();

        tb_freq = kvmppc_get_tbfreq();



        /* indicate KVM hypercall interface */

        qemu_fdt_add_subnode(fdt, "/hypervisor");

        qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",

                                "linux,kvm");

        kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));

        qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",

                         hypercall, sizeof(hypercall));

        /* if KVM supports the idle hcall, set property indicating this */

        if (kvmppc_get_hasidle(env)) {

            qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);

        }

    }



    /* Create CPU nodes */

    qemu_fdt_add_subnode(fdt, "/cpus");

    qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);

    qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);



    /* We need to generate the cpu nodes in reverse order, so Linux can pick

       the first node as boot node and be happy */

    for (i = smp_cpus - 1; i >= 0; i--) {

        CPUState *cpu;

        PowerPCCPU *pcpu;

        char cpu_name[128];

        uint64_t cpu_release_addr = params->spin_base + (i * 0x20);



        cpu = qemu_get_cpu(i);

        if (cpu == NULL) {

            continue;

        }

        env = cpu->env_ptr;

        pcpu = POWERPC_CPU(cpu);



        snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x",

                 ppc_get_vcpu_dt_id(pcpu));

        qemu_fdt_add_subnode(fdt, cpu_name);

        qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);

        qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);

        qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");

        qemu_fdt_setprop_cell(fdt, cpu_name, "reg",

                              ppc_get_vcpu_dt_id(pcpu));

        qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",

                              env->dcache_line_size);

        qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",

                              env->icache_line_size);

        qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);

        qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);

        qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);

        if (cpu->cpu_index) {

            qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");

            qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",

                                    "spin-table");

            qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",

                                 cpu_release_addr);

        } else {

            qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");

        }

    }



    qemu_fdt_add_subnode(fdt, "/aliases");

    /* XXX These should go into their respective devices' code */

    snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base);

    qemu_fdt_add_subnode(fdt, soc);

    qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");

    qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,

                     sizeof(compatible_sb));

    qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);

    qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);

    qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,

                           params->ccsrbar_base >> 32, params->ccsrbar_base,

                           MPC8544_CCSRBAR_SIZE);

    /* XXX should contain a reasonable value */

    qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);



    snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);

    qemu_fdt_add_subnode(fdt, mpic);

    qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");

    qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");

    qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,

                           0x40000);

    qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);

    qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);

    mpic_ph = qemu_fdt_alloc_phandle(fdt);

    qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);

    qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);

    qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);



    /*

     * We have to generate ser1 first, because Linux takes the first

     * device it finds in the dt as serial output device. And we generate

     * devices in reverse order to the dt.

     */

    if (serial_hds[1]) {

        dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,

                         soc, mpic, "serial1", 1, false);

    }



    if (serial_hds[0]) {

        dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,

                         soc, mpic, "serial0", 0, true);

    }



    snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,

             MPC8544_UTIL_OFFSET);

    qemu_fdt_add_subnode(fdt, gutil);

    qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");

    qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);

    qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);



    snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);

    qemu_fdt_add_subnode(fdt, msi);

    qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");

    qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);

    msi_ph = qemu_fdt_alloc_phandle(fdt);

    qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);

    qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);

    qemu_fdt_setprop_cells(fdt, msi, "interrupts",

        0xe0, 0x0,

        0xe1, 0x0,

        0xe2, 0x0,

        0xe3, 0x0,

        0xe4, 0x0,

        0xe5, 0x0,

        0xe6, 0x0,

        0xe7, 0x0);

    qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);

    qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);



    snprintf(pci, sizeof(pci), "/pci@%llx",

             params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);

    qemu_fdt_add_subnode(fdt, pci);

    qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);

    qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");

    qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");

    qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,

                           0x0, 0x7);

    pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),

                             params->pci_first_slot, params->pci_nr_slots,

                             &len);

    qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);

    qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);

    qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);

    qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);

    for (i = 0; i < 14; i++) {

        pci_ranges[i] = cpu_to_be32(pci_ranges[i]);

    }

    qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);

    qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));

    qemu_fdt_setprop_cells(fdt, pci, "reg",

                           (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,

                           (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),

                           0, 0x1000);

    qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);

    qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);

    qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);

    qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);

    qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);



    if (params->has_mpc8xxx_gpio) {

        create_dt_mpc8xxx_gpio(fdt, soc, mpic);

    }



    if (params->has_platform_bus) {

        platform_bus_create_devtree(params, fdt, mpic);

    }



    params->fixup_devtree(params, fdt);



    if (toplevel_compat) {

        qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,

                         strlen(toplevel_compat) + 1);

    }



done:

    if (!dry_run) {

        qemu_fdt_dumpdtb(fdt, fdt_size);

        cpu_physical_memory_write(addr, fdt, fdt_size);

    }

    ret = fdt_size;



out:

    g_free(pci_map);



    return ret;

}
static int ppce500_load_device_tree(MachineState *machine,

                                    PPCE500Params *params,

                                    hwaddr addr,

                                    hwaddr initrd_base,

                                    hwaddr initrd_size,

                                    hwaddr kernel_base,

                                    hwaddr kernel_size,

                                    bool dry_run)

{

    CPUPPCState *env = first_cpu->env_ptr;

    int ret = -1;

    uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };

    int fdt_size;

    void *fdt;

    uint8_t hypercall[16];

    uint32_t clock_freq = 400000000;

    uint32_t tb_freq = 400000000;

    int i;

    char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";

    char soc[128];

    char mpic[128];

    uint32_t mpic_ph;

    uint32_t msi_ph;

    char gutil[128];

    char pci[128];

    char msi[128];

    uint32_t *pci_map = NULL;

    int len;

    uint32_t pci_ranges[14] =

        {

            0x2000000, 0x0, params->pci_mmio_bus_base,

            params->pci_mmio_base >> 32, params->pci_mmio_base,

            0x0, 0x20000000,



            0x1000000, 0x0, 0x0,

            params->pci_pio_base >> 32, params->pci_pio_base,

            0x0, 0x10000,

        };

    QemuOpts *machine_opts = qemu_get_machine_opts();

    const char *dtb_file = qemu_opt_get(machine_opts, "dtb");

    const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");



    if (dtb_file) {

        char *filename;

        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);

        if (!filename) {

            goto out;

        }



        fdt = load_device_tree(filename, &fdt_size);


        if (!fdt) {

            goto out;

        }

        goto done;

    }



    fdt = create_device_tree(&fdt_size);

    if (fdt == NULL) {

        goto out;

    }



    

    qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);

    qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);



    qemu_fdt_add_subnode(fdt, "/memory");

    qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");

    qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,

                     sizeof(mem_reg_property));



    qemu_fdt_add_subnode(fdt, "/chosen");

    if (initrd_size) {

        ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",

                                    initrd_base);

        if (ret < 0) {

            fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");

        }



        ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",

                                    (initrd_base + initrd_size));

        if (ret < 0) {

            fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");

        }



    }



    if (kernel_base != -1ULL) {

        qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",

                                     kernel_base >> 32, kernel_base,

                                     kernel_size >> 32, kernel_size);

    }



    ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",

                                      machine->kernel_cmdline);

    if (ret < 0)

        fprintf(stderr, "couldn't set /chosen/bootargs\n");



    if (kvm_enabled()) {

        

        clock_freq = kvmppc_get_clockfreq();

        tb_freq = kvmppc_get_tbfreq();



        

        qemu_fdt_add_subnode(fdt, "/hypervisor");

        qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",

                                "linux,kvm");

        kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));

        qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",

                         hypercall, sizeof(hypercall));

        

        if (kvmppc_get_hasidle(env)) {

            qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);

        }

    }



    

    qemu_fdt_add_subnode(fdt, "/cpus");

    qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);

    qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);



    



    for (i = smp_cpus - 1; i >= 0; i--) {

        CPUState *cpu;

        PowerPCCPU *pcpu;

        char cpu_name[128];

        uint64_t cpu_release_addr = params->spin_base + (i * 0x20);



        cpu = qemu_get_cpu(i);

        if (cpu == NULL) {

            continue;

        }

        env = cpu->env_ptr;

        pcpu = POWERPC_CPU(cpu);



        snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x",

                 ppc_get_vcpu_dt_id(pcpu));

        qemu_fdt_add_subnode(fdt, cpu_name);

        qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);

        qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);

        qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");

        qemu_fdt_setprop_cell(fdt, cpu_name, "reg",

                              ppc_get_vcpu_dt_id(pcpu));

        qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",

                              env->dcache_line_size);

        qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",

                              env->icache_line_size);

        qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);

        qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);

        qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);

        if (cpu->cpu_index) {

            qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");

            qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",

                                    "spin-table");

            qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",

                                 cpu_release_addr);

        } else {

            qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");

        }

    }



    qemu_fdt_add_subnode(fdt, "/aliases");

    

    snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base);

    qemu_fdt_add_subnode(fdt, soc);

    qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");

    qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,

                     sizeof(compatible_sb));

    qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);

    qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);

    qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,

                           params->ccsrbar_base >> 32, params->ccsrbar_base,

                           MPC8544_CCSRBAR_SIZE);

    

    qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);



    snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);

    qemu_fdt_add_subnode(fdt, mpic);

    qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");

    qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");

    qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,

                           0x40000);

    qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);

    qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);

    mpic_ph = qemu_fdt_alloc_phandle(fdt);

    qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);

    qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);

    qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);



    









    if (serial_hds[1]) {

        dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,

                         soc, mpic, "serial1", 1, false);

    }



    if (serial_hds[0]) {

        dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,

                         soc, mpic, "serial0", 0, true);

    }



    snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,

             MPC8544_UTIL_OFFSET);

    qemu_fdt_add_subnode(fdt, gutil);

    qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");

    qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);

    qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);



    snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);

    qemu_fdt_add_subnode(fdt, msi);

    qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");

    qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);

    msi_ph = qemu_fdt_alloc_phandle(fdt);

    qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);

    qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);

    qemu_fdt_setprop_cells(fdt, msi, "interrupts",

        0xe0, 0x0,

        0xe1, 0x0,

        0xe2, 0x0,

        0xe3, 0x0,

        0xe4, 0x0,

        0xe5, 0x0,

        0xe6, 0x0,

        0xe7, 0x0);

    qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);

    qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);



    snprintf(pci, sizeof(pci), "/pci@%llx",

             params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);

    qemu_fdt_add_subnode(fdt, pci);

    qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);

    qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");

    qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");

    qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,

                           0x0, 0x7);

    pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),

                             params->pci_first_slot, params->pci_nr_slots,

                             &len);

    qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);

    qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);

    qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);

    qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);

    for (i = 0; i < 14; i++) {

        pci_ranges[i] = cpu_to_be32(pci_ranges[i]);

    }

    qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);

    qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));

    qemu_fdt_setprop_cells(fdt, pci, "reg",

                           (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,

                           (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),

                           0, 0x1000);

    qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);

    qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);

    qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);

    qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);

    qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);



    if (params->has_mpc8xxx_gpio) {

        create_dt_mpc8xxx_gpio(fdt, soc, mpic);

    }



    if (params->has_platform_bus) {

        platform_bus_create_devtree(params, fdt, mpic);

    }



    params->fixup_devtree(params, fdt);



    if (toplevel_compat) {

        qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,

                         strlen(toplevel_compat) + 1);

    }



done:

    if (!dry_run) {

        qemu_fdt_dumpdtb(fdt, fdt_size);

        cpu_physical_memory_write(addr, fdt, fdt_size);

    }

    ret = fdt_size;



out:

    g_free(pci_map);



    return ret;

}
static int FUNC_0(MachineState *VAR_0,

                                    PPCE500Params *VAR_1,

                                    hwaddr VAR_2,

                                    hwaddr VAR_3,

                                    hwaddr VAR_4,

                                    hwaddr VAR_5,

                                    hwaddr VAR_6,

                                    bool VAR_7)

{

    CPUPPCState *env = first_cpu->env_ptr;

    int VAR_8 = -1;

    uint64_t mem_reg_property[] = { 0, cpu_to_be64(VAR_0->ram_size) };

    int VAR_9;

    void *VAR_10;

    uint8_t hypercall[16];

    uint32_t clock_freq = 400000000;

    uint32_t tb_freq = 400000000;

    int VAR_11;

    char VAR_12[] = "fsl,mpc8544-immr\0simple-bus";

    char VAR_13[128];

    char VAR_14[128];

    uint32_t mpic_ph;

    uint32_t msi_ph;

    char VAR_15[128];

    char VAR_16[128];

    char VAR_17[128];

    uint32_t *pci_map = NULL;

    int VAR_18;

    uint32_t pci_ranges[14] =

        {

            0x2000000, 0x0, VAR_1->pci_mmio_bus_base,

            VAR_1->pci_mmio_base >> 32, VAR_1->pci_mmio_base,

            0x0, 0x20000000,



            0x1000000, 0x0, 0x0,

            VAR_1->pci_pio_base >> 32, VAR_1->pci_pio_base,

            0x0, 0x10000,

        };

    QemuOpts *machine_opts = qemu_get_machine_opts();

    const char *VAR_19 = qemu_opt_get(machine_opts, "dtb");

    const char *VAR_20 = qemu_opt_get(machine_opts, "dt_compatible");



    if (VAR_19) {

        char *VAR_21;

        VAR_21 = qemu_find_file(QEMU_FILE_TYPE_BIOS, VAR_19);

        if (!VAR_21) {

            goto out;

        }



        VAR_10 = load_device_tree(VAR_21, &VAR_9);


        if (!VAR_10) {

            goto out;

        }

        goto done;

    }



    VAR_10 = create_device_tree(&VAR_9);

    if (VAR_10 == NULL) {

        goto out;

    }



    

    qemu_fdt_setprop_cell(VAR_10, "/", "#address-cells", 2);

    qemu_fdt_setprop_cell(VAR_10, "/", "#size-cells", 2);



    qemu_fdt_add_subnode(VAR_10, "/memory");

    qemu_fdt_setprop_string(VAR_10, "/memory", "device_type", "memory");

    qemu_fdt_setprop(VAR_10, "/memory", "reg", mem_reg_property,

                     sizeof(mem_reg_property));



    qemu_fdt_add_subnode(VAR_10, "/chosen");

    if (VAR_4) {

        VAR_8 = qemu_fdt_setprop_cell(VAR_10, "/chosen", "linux,initrd-start",

                                    VAR_3);

        if (VAR_8 < 0) {

            fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");

        }



        VAR_8 = qemu_fdt_setprop_cell(VAR_10, "/chosen", "linux,initrd-end",

                                    (VAR_3 + VAR_4));

        if (VAR_8 < 0) {

            fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");

        }



    }



    if (VAR_5 != -1ULL) {

        qemu_fdt_setprop_cells(VAR_10, "/chosen", "qemu,boot-kernel",

                                     VAR_5 >> 32, VAR_5,

                                     VAR_6 >> 32, VAR_6);

    }



    VAR_8 = qemu_fdt_setprop_string(VAR_10, "/chosen", "bootargs",

                                      VAR_0->kernel_cmdline);

    if (VAR_8 < 0)

        fprintf(stderr, "couldn't set /chosen/bootargs\n");



    if (kvm_enabled()) {

        

        clock_freq = kvmppc_get_clockfreq();

        tb_freq = kvmppc_get_tbfreq();



        

        qemu_fdt_add_subnode(VAR_10, "/hypervisor");

        qemu_fdt_setprop_string(VAR_10, "/hypervisor", "compatible",

                                "linux,kvm");

        kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));

        qemu_fdt_setprop(VAR_10, "/hypervisor", "hcall-instructions",

                         hypercall, sizeof(hypercall));

        

        if (kvmppc_get_hasidle(env)) {

            qemu_fdt_setprop(VAR_10, "/hypervisor", "has-idle", NULL, 0);

        }

    }



    

    qemu_fdt_add_subnode(VAR_10, "/cpus");

    qemu_fdt_setprop_cell(VAR_10, "/cpus", "#address-cells", 1);

    qemu_fdt_setprop_cell(VAR_10, "/cpus", "#size-cells", 0);



    



    for (VAR_11 = smp_cpus - 1; VAR_11 >= 0; VAR_11--) {

        CPUState *cpu;

        PowerPCCPU *pcpu;

        char VAR_22[128];

        uint64_t cpu_release_addr = VAR_1->spin_base + (VAR_11 * 0x20);



        cpu = qemu_get_cpu(VAR_11);

        if (cpu == NULL) {

            continue;

        }

        env = cpu->env_ptr;

        pcpu = POWERPC_CPU(cpu);



        snprintf(VAR_22, sizeof(VAR_22), "/cpus/PowerPC,8544@%x",

                 ppc_get_vcpu_dt_id(pcpu));

        qemu_fdt_add_subnode(VAR_10, VAR_22);

        qemu_fdt_setprop_cell(VAR_10, VAR_22, "clock-frequency", clock_freq);

        qemu_fdt_setprop_cell(VAR_10, VAR_22, "timebase-frequency", tb_freq);

        qemu_fdt_setprop_string(VAR_10, VAR_22, "device_type", "cpu");

        qemu_fdt_setprop_cell(VAR_10, VAR_22, "reg",

                              ppc_get_vcpu_dt_id(pcpu));

        qemu_fdt_setprop_cell(VAR_10, VAR_22, "d-cache-line-size",

                              env->dcache_line_size);

        qemu_fdt_setprop_cell(VAR_10, VAR_22, "VAR_11-cache-line-size",

                              env->icache_line_size);

        qemu_fdt_setprop_cell(VAR_10, VAR_22, "d-cache-size", 0x8000);

        qemu_fdt_setprop_cell(VAR_10, VAR_22, "VAR_11-cache-size", 0x8000);

        qemu_fdt_setprop_cell(VAR_10, VAR_22, "bus-frequency", 0);

        if (cpu->cpu_index) {

            qemu_fdt_setprop_string(VAR_10, VAR_22, "status", "disabled");

            qemu_fdt_setprop_string(VAR_10, VAR_22, "enable-method",

                                    "spin-table");

            qemu_fdt_setprop_u64(VAR_10, VAR_22, "cpu-release-VAR_2",

                                 cpu_release_addr);

        } else {

            qemu_fdt_setprop_string(VAR_10, VAR_22, "status", "okay");

        }

    }



    qemu_fdt_add_subnode(VAR_10, "/aliases");

    

    snprintf(VAR_13, sizeof(VAR_13), "/VAR_13@%"PRIx64, VAR_1->ccsrbar_base);

    qemu_fdt_add_subnode(VAR_10, VAR_13);

    qemu_fdt_setprop_string(VAR_10, VAR_13, "device_type", "VAR_13");

    qemu_fdt_setprop(VAR_10, VAR_13, "compatible", VAR_12,

                     sizeof(VAR_12));

    qemu_fdt_setprop_cell(VAR_10, VAR_13, "#address-cells", 1);

    qemu_fdt_setprop_cell(VAR_10, VAR_13, "#size-cells", 1);

    qemu_fdt_setprop_cells(VAR_10, VAR_13, "ranges", 0x0,

                           VAR_1->ccsrbar_base >> 32, VAR_1->ccsrbar_base,

                           MPC8544_CCSRBAR_SIZE);

    

    qemu_fdt_setprop_cell(VAR_10, VAR_13, "bus-frequency", 0);



    snprintf(VAR_14, sizeof(VAR_14), "%s/pic@%llx", VAR_13, MPC8544_MPIC_REGS_OFFSET);

    qemu_fdt_add_subnode(VAR_10, VAR_14);

    qemu_fdt_setprop_string(VAR_10, VAR_14, "device_type", "open-pic");

    qemu_fdt_setprop_string(VAR_10, VAR_14, "compatible", "fsl,VAR_14");

    qemu_fdt_setprop_cells(VAR_10, VAR_14, "reg", MPC8544_MPIC_REGS_OFFSET,

                           0x40000);

    qemu_fdt_setprop_cell(VAR_10, VAR_14, "#address-cells", 0);

    qemu_fdt_setprop_cell(VAR_10, VAR_14, "#interrupt-cells", 2);

    mpic_ph = qemu_fdt_alloc_phandle(VAR_10);

    qemu_fdt_setprop_cell(VAR_10, VAR_14, "phandle", mpic_ph);

    qemu_fdt_setprop_cell(VAR_10, VAR_14, "linux,phandle", mpic_ph);

    qemu_fdt_setprop(VAR_10, VAR_14, "interrupt-controller", NULL, 0);



    









    if (serial_hds[1]) {

        dt_serial_create(VAR_10, MPC8544_SERIAL1_REGS_OFFSET,

                         VAR_13, VAR_14, "serial1", 1, false);

    }



    if (serial_hds[0]) {

        dt_serial_create(VAR_10, MPC8544_SERIAL0_REGS_OFFSET,

                         VAR_13, VAR_14, "serial0", 0, true);

    }



    snprintf(VAR_15, sizeof(VAR_15), "%s/global-utilities@%llx", VAR_13,

             MPC8544_UTIL_OFFSET);

    qemu_fdt_add_subnode(VAR_10, VAR_15);

    qemu_fdt_setprop_string(VAR_10, VAR_15, "compatible", "fsl,mpc8544-guts");

    qemu_fdt_setprop_cells(VAR_10, VAR_15, "reg", MPC8544_UTIL_OFFSET, 0x1000);

    qemu_fdt_setprop(VAR_10, VAR_15, "fsl,has-rstcr", NULL, 0);



    snprintf(VAR_17, sizeof(VAR_17), "/%s/VAR_17@%llx", VAR_13, MPC8544_MSI_REGS_OFFSET);

    qemu_fdt_add_subnode(VAR_10, VAR_17);

    qemu_fdt_setprop_string(VAR_10, VAR_17, "compatible", "fsl,VAR_14-VAR_17");

    qemu_fdt_setprop_cells(VAR_10, VAR_17, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);

    msi_ph = qemu_fdt_alloc_phandle(VAR_10);

    qemu_fdt_setprop_cells(VAR_10, VAR_17, "VAR_17-available-ranges", 0x0, 0x100);

    qemu_fdt_setprop_phandle(VAR_10, VAR_17, "interrupt-parent", VAR_14);

    qemu_fdt_setprop_cells(VAR_10, VAR_17, "interrupts",

        0xe0, 0x0,

        0xe1, 0x0,

        0xe2, 0x0,

        0xe3, 0x0,

        0xe4, 0x0,

        0xe5, 0x0,

        0xe6, 0x0,

        0xe7, 0x0);

    qemu_fdt_setprop_cell(VAR_10, VAR_17, "phandle", msi_ph);

    qemu_fdt_setprop_cell(VAR_10, VAR_17, "linux,phandle", msi_ph);



    snprintf(VAR_16, sizeof(VAR_16), "/VAR_16@%llx",

             VAR_1->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);

    qemu_fdt_add_subnode(VAR_10, VAR_16);

    qemu_fdt_setprop_cell(VAR_10, VAR_16, "cell-index", 0);

    qemu_fdt_setprop_string(VAR_10, VAR_16, "compatible", "fsl,mpc8540-VAR_16");

    qemu_fdt_setprop_string(VAR_10, VAR_16, "device_type", "VAR_16");

    qemu_fdt_setprop_cells(VAR_10, VAR_16, "interrupt-map-mask", 0xf800, 0x0,

                           0x0, 0x7);

    pci_map = pci_map_create(VAR_10, qemu_fdt_get_phandle(VAR_10, VAR_14),

                             VAR_1->pci_first_slot, VAR_1->pci_nr_slots,

                             &VAR_18);

    qemu_fdt_setprop(VAR_10, VAR_16, "interrupt-map", pci_map, VAR_18);

    qemu_fdt_setprop_phandle(VAR_10, VAR_16, "interrupt-parent", VAR_14);

    qemu_fdt_setprop_cells(VAR_10, VAR_16, "interrupts", 24, 2);

    qemu_fdt_setprop_cells(VAR_10, VAR_16, "bus-range", 0, 255);

    for (VAR_11 = 0; VAR_11 < 14; VAR_11++) {

        pci_ranges[VAR_11] = cpu_to_be32(pci_ranges[VAR_11]);

    }

    qemu_fdt_setprop_cell(VAR_10, VAR_16, "fsl,VAR_17", msi_ph);

    qemu_fdt_setprop(VAR_10, VAR_16, "ranges", pci_ranges, sizeof(pci_ranges));

    qemu_fdt_setprop_cells(VAR_10, VAR_16, "reg",

                           (VAR_1->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,

                           (VAR_1->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),

                           0, 0x1000);

    qemu_fdt_setprop_cell(VAR_10, VAR_16, "clock-frequency", 66666666);

    qemu_fdt_setprop_cell(VAR_10, VAR_16, "#interrupt-cells", 1);

    qemu_fdt_setprop_cell(VAR_10, VAR_16, "#size-cells", 2);

    qemu_fdt_setprop_cell(VAR_10, VAR_16, "#address-cells", 3);

    qemu_fdt_setprop_string(VAR_10, "/aliases", "pci0", VAR_16);



    if (VAR_1->has_mpc8xxx_gpio) {

        create_dt_mpc8xxx_gpio(VAR_10, VAR_13, VAR_14);

    }



    if (VAR_1->has_platform_bus) {

        platform_bus_create_devtree(VAR_1, VAR_10, VAR_14);

    }



    VAR_1->fixup_devtree(VAR_1, VAR_10);



    if (VAR_20) {

        qemu_fdt_setprop(VAR_10, "/", "compatible", VAR_20,

                         strlen(VAR_20) + 1);

    }



done:

    if (!VAR_7) {

        qemu_fdt_dumpdtb(VAR_10, VAR_9);

        cpu_physical_memory_write(VAR_2, VAR_10, VAR_9);

    }

    VAR_8 = VAR_9;



out:

    g_free(pci_map);



    return VAR_8;

}
static int FUNC_0(MachineState *VAR_0,
PPCE500Params *VAR_1,
hwaddr VAR_2,
hwaddr VAR_3,
hwaddr VAR_4,
hwaddr VAR_5,
hwaddr VAR_6,
bool VAR_7)
{ CPUPPCState *env = first_cpu->env_ptr; int VAR_8 = -1; uint64_t mem_reg_property[] = { 0, cpu_to_be64(VAR_0->ram_size) }; int VAR_9; void *VAR_10; uint8_t hypercall[16]; uint32_t clock_freq = 400000000; uint32_t tb_freq = 400000000; int VAR_11; char VAR_12[] = "fsl,mpc8544-immr\0simple-bus"; char VAR_13[128]; char VAR_14[128]; uint32_t mpic_ph; uint32_t msi_ph; char VAR_15[128]; char VAR_16[128]; char VAR_17[128]; uint32_t *pci_map = NULL; int VAR_18; uint32_t pci_ranges[14] =
{ 0x2000000, 0x0, VAR_1->pci_mmio_bus_base,
VAR_1->pci_mmio_base >> 32, VAR_1->pci_mmio_base,
0x0, 0x20000000,
0x1000000, 0x0, 0x0,
VAR_1->pci_pio_base >> 32, VAR_1->pci_pio_base,
0x0, 0x10000,
}; QemuOpts *machine_opts = qemu_get_machine_opts(); const char *VAR_19 = qemu_opt_get(machine_opts, "dtb"); const char *VAR_20 = qemu_opt_get(machine_opts, "dt_compatible"); if (VAR_19) { char *VAR_21; VAR_21 = qemu_find_file(QEMU_FILE_TYPE_BIOS, VAR_19); if (!VAR_21) { goto out; } VAR_10 = load_device_tree(VAR_21, &VAR_9); if (!VAR_10) { goto out; } goto done; } VAR_10 = create_device_tree(&VAR_9); if (VAR_10 == NULL) { goto out; } qemu_fdt_setprop_cell(VAR_10, "/", "#address-cells", 2); qemu_fdt_setprop_cell(VAR_10, "/", "#size-cells", 2); qemu_fdt_add_subnode(VAR_10, "/memory"); qemu_fdt_setprop_string(VAR_10, "/memory", "device_type", "memory"); qemu_fdt_setprop(VAR_10, "/memory", "reg", mem_reg_property,
sizeof(mem_reg_property)); qemu_fdt_add_subnode(VAR_10, "/chosen"); if (VAR_4) { VAR_8 = qemu_fdt_setprop_cell(VAR_10, "/chosen", "linux,initrd-start",
VAR_3); if (VAR_8 < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); } VAR_8 = qemu_fdt_setprop_cell(VAR_10, "/chosen", "linux,initrd-end",
(VAR_3 + VAR_4)); if (VAR_8 < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); } } if (VAR_5 != -1ULL) { qemu_fdt_setprop_cells(VAR_10, "/chosen", "qemu,boot-kernel",
VAR_5 >> 32, VAR_5,
VAR_6 >> 32, VAR_6); } VAR_8 = qemu_fdt_setprop_string(VAR_10, "/chosen", "bootargs",
VAR_0->kernel_cmdline); if (VAR_8 < 0)
fprintf(stderr, "couldn't set /chosen/bootargs\n"); if (kvm_enabled()) { clock_freq = kvmppc_get_clockfreq(); tb_freq = kvmppc_get_tbfreq(); qemu_fdt_add_subnode(VAR_10, "/hypervisor"); qemu_fdt_setprop_string(VAR_10, "/hypervisor", "compatible",
"linux,kvm"); kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); qemu_fdt_setprop(VAR_10, "/hypervisor", "hcall-instructions",
hypercall, sizeof(hypercall)); if (kvmppc_get_hasidle(env)) { qemu_fdt_setprop(VAR_10, "/hypervisor", "has-idle", NULL, 0); } } qemu_fdt_add_subnode(VAR_10, "/cpus"); qemu_fdt_setprop_cell(VAR_10, "/cpus", "#address-cells", 1); qemu_fdt_setprop_cell(VAR_10, "/cpus", "#size-cells", 0); for (VAR_11 = smp_cpus - 1; VAR_11 >= 0; VAR_11--) { CPUState *cpu; PowerPCCPU *pcpu; char VAR_22[128]; uint64_t cpu_release_addr = VAR_1->spin_base + (VAR_11 * 0x20); cpu = qemu_get_cpu(VAR_11); if (cpu == NULL) { continue; } env = cpu->env_ptr; pcpu = POWERPC_CPU(cpu); snprintf(VAR_22, sizeof(VAR_22), "/cpus/PowerPC,8544@%x",
ppc_get_vcpu_dt_id(pcpu)); qemu_fdt_add_subnode(VAR_10, VAR_22); qemu_fdt_setprop_cell(VAR_10, VAR_22, "clock-frequency", clock_freq); qemu_fdt_setprop_cell(VAR_10, VAR_22, "timebase-frequency", tb_freq); qemu_fdt_setprop_string(VAR_10, VAR_22, "device_type", "cpu"); qemu_fdt_setprop_cell(VAR_10, VAR_22, "reg",
ppc_get_vcpu_dt_id(pcpu)); qemu_fdt_setprop_cell(VAR_10, VAR_22, "d-cache-line-size",
env->dcache_line_size); qemu_fdt_setprop_cell(VAR_10, VAR_22, "VAR_11-cache-line-size",
env->icache_line_size); qemu_fdt_setprop_cell(VAR_10, VAR_22, "d-cache-size", 0x8000); qemu_fdt_setprop_cell(VAR_10, VAR_22, "VAR_11-cache-size", 0x8000); qemu_fdt_setprop_cell(VAR_10, VAR_22, "bus-frequency", 0); if (cpu->cpu_index) { qemu_fdt_setprop_string(VAR_10, VAR_22, "status", "disabled"); qemu_fdt_setprop_string(VAR_10, VAR_22, "enable-method",
"spin-table"); qemu_fdt_setprop_u64(VAR_10, VAR_22, "cpu-release-VAR_2",
cpu_release_addr); } else { qemu_fdt_setprop_string(VAR_10, VAR_22, "status", "okay"); } } qemu_fdt_add_subnode(VAR_10, "/aliases"); snprintf(VAR_13, sizeof(VAR_13), "/VAR_13@%"PRIx64, VAR_1->ccsrbar_base); qemu_fdt_add_subnode(VAR_10, VAR_13); qemu_fdt_setprop_string(VAR_10, VAR_13, "device_type", "VAR_13"); qemu_fdt_setprop(VAR_10, VAR_13, "compatible", VAR_12,
sizeof(VAR_12)); qemu_fdt_setprop_cell(VAR_10, VAR_13, "#address-cells", 1); qemu_fdt_setprop_cell(VAR_10, VAR_13, "#size-cells", 1); qemu_fdt_setprop_cells(VAR_10, VAR_13, "ranges", 0x0,
VAR_1->ccsrbar_base >> 32, VAR_1->ccsrbar_base,
MPC8544_CCSRBAR_SIZE); qemu_fdt_setprop_cell(VAR_10, VAR_13, "bus-frequency", 0); snprintf(VAR_14, sizeof(VAR_14), "%s/pic@%llx", VAR_13, MPC8544_MPIC_REGS_OFFSET); qemu_fdt_add_subnode(VAR_10, VAR_14); qemu_fdt_setprop_string(VAR_10, VAR_14, "device_type", "open-pic"); qemu_fdt_setprop_string(VAR_10, VAR_14, "compatible", "fsl,VAR_14"); qemu_fdt_setprop_cells(VAR_10, VAR_14, "reg", MPC8544_MPIC_REGS_OFFSET,
0x40000); qemu_fdt_setprop_cell(VAR_10, VAR_14, "#address-cells", 0); qemu_fdt_setprop_cell(VAR_10, VAR_14, "#interrupt-cells", 2); mpic_ph = qemu_fdt_alloc_phandle(VAR_10); qemu_fdt_setprop_cell(VAR_10, VAR_14, "phandle", mpic_ph); qemu_fdt_setprop_cell(VAR_10, VAR_14, "linux,phandle", mpic_ph); qemu_fdt_setprop(VAR_10, VAR_14, "interrupt-controller", NULL, 0); if (serial_hds[1]) { dt_serial_create(VAR_10, MPC8544_SERIAL1_REGS_OFFSET,
VAR_13, VAR_14, "serial1", 1, false); } if (serial_hds[0]) { dt_serial_create(VAR_10, MPC8544_SERIAL0_REGS_OFFSET,
VAR_13, VAR_14, "serial0", 0, true); } snprintf(VAR_15, sizeof(VAR_15), "%s/global-utilities@%llx", VAR_13,
MPC8544_UTIL_OFFSET); qemu_fdt_add_subnode(VAR_10, VAR_15); qemu_fdt_setprop_string(VAR_10, VAR_15, "compatible", "fsl,mpc8544-guts"); qemu_fdt_setprop_cells(VAR_10, VAR_15, "reg", MPC8544_UTIL_OFFSET, 0x1000); qemu_fdt_setprop(VAR_10, VAR_15, "fsl,has-rstcr", NULL, 0); snprintf(VAR_17, sizeof(VAR_17), "/%s/VAR_17@%llx", VAR_13, MPC8544_MSI_REGS_OFFSET); qemu_fdt_add_subnode(VAR_10, VAR_17); qemu_fdt_setprop_string(VAR_10, VAR_17, "compatible", "fsl,VAR_14-VAR_17"); qemu_fdt_setprop_cells(VAR_10, VAR_17, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); msi_ph = qemu_fdt_alloc_phandle(VAR_10); qemu_fdt_setprop_cells(VAR_10, VAR_17, "VAR_17-available-ranges", 0x0, 0x100); qemu_fdt_setprop_phandle(VAR_10, VAR_17, "interrupt-parent", VAR_14); qemu_fdt_setprop_cells(VAR_10, VAR_17, "interrupts",
0xe0, 0x0,
0xe1, 0x0,
0xe2, 0x0,
0xe3, 0x0,
0xe4, 0x0,
0xe5, 0x0,
0xe6, 0x0,
0xe7, 0x0); qemu_fdt_setprop_cell(VAR_10, VAR_17, "phandle", msi_ph); qemu_fdt_setprop_cell(VAR_10, VAR_17, "linux,phandle", msi_ph); snprintf(VAR_16, sizeof(VAR_16), "/VAR_16@%llx",
VAR_1->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); qemu_fdt_add_subnode(VAR_10, VAR_16); qemu_fdt_setprop_cell(VAR_10, VAR_16, "cell-index", 0); qemu_fdt_setprop_string(VAR_10, VAR_16, "compatible", "fsl,mpc8540-VAR_16"); qemu_fdt_setprop_string(VAR_10, VAR_16, "device_type", "VAR_16"); qemu_fdt_setprop_cells(VAR_10, VAR_16, "interrupt-map-mask", 0xf800, 0x0,
0x0, 0x7); pci_map = pci_map_create(VAR_10, qemu_fdt_get_phandle(VAR_10, VAR_14),
VAR_1->pci_first_slot, VAR_1->pci_nr_slots,
&VAR_18); qemu_fdt_setprop(VAR_10, VAR_16, "interrupt-map", pci_map, VAR_18); qemu_fdt_setprop_phandle(VAR_10, VAR_16, "interrupt-parent", VAR_14); qemu_fdt_setprop_cells(VAR_10, VAR_16, "interrupts", 24, 2); qemu_fdt_setprop_cells(VAR_10, VAR_16, "bus-range", 0, 255); for (VAR_11 = 0; VAR_11 < 14; VAR_11++) { pci_ranges[VAR_11] = cpu_to_be32(pci_ranges[VAR_11]); } qemu_fdt_setprop_cell(VAR_10, VAR_16, "fsl,VAR_17", msi_ph); qemu_fdt_setprop(VAR_10, VAR_16, "ranges", pci_ranges, sizeof(pci_ranges)); qemu_fdt_setprop_cells(VAR_10, VAR_16, "reg",
(VAR_1->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
(VAR_1->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
0, 0x1000); qemu_fdt_setprop_cell(VAR_10, VAR_16, "clock-frequency", 66666666); qemu_fdt_setprop_cell(VAR_10, VAR_16, "#interrupt-cells", 1); qemu_fdt_setprop_cell(VAR_10, VAR_16, "#size-cells", 2); qemu_fdt_setprop_cell(VAR_10, VAR_16, "#address-cells", 3); qemu_fdt_setprop_string(VAR_10, "/aliases", "pci0", VAR_16); if (VAR_1->has_mpc8xxx_gpio) { create_dt_mpc8xxx_gpio(VAR_10, VAR_13, VAR_14); } if (VAR_1->has_platform_bus) { platform_bus_create_devtree(VAR_1, VAR_10, VAR_14); } VAR_1->fixup_devtree(VAR_1, VAR_10); if (VAR_20) { qemu_fdt_setprop(VAR_10, "/", "compatible", VAR_20,
strlen(VAR_20) + 1); } done:
if (!VAR_7) { qemu_fdt_dumpdtb(VAR_10, VAR_9); cpu_physical_memory_write(VAR_2, VAR_10, VAR_9); } VAR_8 = VAR_9; out:
g_free(pci_map); return VAR_8; }