static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,

                                   uint32_t val)

{

    PCIBonitoState *s = opaque;

    uint32_t pciaddr;

    uint16_t status;



    DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x \n", addr, val);

    assert((addr&0x3)==0);



    pciaddr = bonito_sbridge_pciaddr(s, addr);



    if (pciaddr == 0xffffffff) {

        return;

    }



    /* set the pci address in s->config_reg */

    s->pcihost->config_reg = (pciaddr) | (1u << 31);

    pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 4);



    /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */

    status = pci_get_word(s->dev.config + PCI_STATUS);

    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);

    pci_set_word(s->dev.config + PCI_STATUS, status);

}

static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,

                                   uint32_t val)

{

    PCIBonitoState *s = opaque;

    uint32_t pciaddr;

    uint16_t status;



    DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x \n", addr, val);

    assert((addr&0x3)==0);



    pciaddr = bonito_sbridge_pciaddr(s, addr);



    if (pciaddr == 0xffffffff) {

        return;

    }



    

    s->pcihost->config_reg = (pciaddr) | (1u << 31);

    pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 4);



    

    status = pci_get_word(s->dev.config + PCI_STATUS);

    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);

    pci_set_word(s->dev.config + PCI_STATUS, status);

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                                   uint32_t VAR_2)

{

    PCIBonitoState *s = VAR_0;

    uint32_t pciaddr;

    uint16_t status;



    DPRINTF("FUNC_0 "TARGET_FMT_plx" VAR_2 %x \n", VAR_1, VAR_2);

    assert((VAR_1&0x3)==0);



    pciaddr = bonito_sbridge_pciaddr(s, VAR_1);



    if (pciaddr == 0xffffffff) {

        return;

    }



    

    s->pcihost->config_reg = (pciaddr) | (1u << 31);

    pci_data_write(s->pcihost->bus, s->pcihost->config_reg, VAR_2, 4);



    

    status = pci_get_word(s->dev.config + PCI_STATUS);

    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);

    pci_set_word(s->dev.config + PCI_STATUS, status);

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint32_t VAR_2)
{ PCIBonitoState *s = VAR_0; uint32_t pciaddr; uint16_t status; DPRINTF("FUNC_0 "TARGET_FMT_plx" VAR_2 %x \n", VAR_1, VAR_2); assert((VAR_1&0x3)==0); pciaddr = bonito_sbridge_pciaddr(s, VAR_1); if (pciaddr == 0xffffffff) { return; } s->pcihost->config_reg = (pciaddr) | (1u << 31); pci_data_write(s->pcihost->bus, s->pcihost->config_reg, VAR_2, 4); status = pci_get_word(s->dev.config + PCI_STATUS); status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); pci_set_word(s->dev.config + PCI_STATUS, status); }