int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

                               int mmu_idx, int is_softmmu)

{

    unsigned int hit;

    unsigned int mmu_available;

    int r = 1;

    int prot;



    mmu_available = 0;

    if (env->pvr.regs[0] & PVR0_USE_MMU) {

        mmu_available = 1;

        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)

            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {

            mmu_available = 0;

        }

    }



    /* Translate if the MMU is available and enabled.  */

    if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {

        target_ulong vaddr, paddr;

        struct microblaze_mmu_lookup lu;



        hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);

        if (hit) {

            vaddr = address & TARGET_PAGE_MASK;

            paddr = lu.paddr + vaddr - lu.vaddr;



            DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",

                     mmu_idx, vaddr, paddr, lu.prot));

            r = tlb_set_page(env, vaddr,

                             paddr, lu.prot, mmu_idx, is_softmmu);

        } else {

            env->sregs[SR_EAR] = address;

            DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address));



            switch (lu.err) {

                case ERR_PROT:

                    env->sregs[SR_ESR] = rw == 2 ? 17 : 16;

                    env->sregs[SR_ESR] |= (rw == 1) << 10;

                    break;

                case ERR_MISS:

                    env->sregs[SR_ESR] = rw == 2 ? 19 : 18;

                    env->sregs[SR_ESR] |= (rw == 1) << 10;

                    break;

                default:

                    abort();

                    break;

            }



            if (env->exception_index == EXCP_MMU) {

                cpu_abort(env, "recursive faults\n");

            }



            /* TLB miss.  */

            env->exception_index = EXCP_MMU;

        }

    } else {

        /* MMU disabled or not available.  */

        address &= TARGET_PAGE_MASK;

        prot = PAGE_BITS;

        r = tlb_set_page(env, address, address, prot, mmu_idx, is_softmmu);

    }

    return r;

}

int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

                               int mmu_idx, int is_softmmu)

{

    unsigned int hit;

    unsigned int mmu_available;

    int r = 1;

    int prot;



    mmu_available = 0;

    if (env->pvr.regs[0] & PVR0_USE_MMU) {

        mmu_available = 1;

        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)

            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {

            mmu_available = 0;

        }

    }



    

    if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {

        target_ulong vaddr, paddr;

        struct microblaze_mmu_lookup lu;



        hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);

        if (hit) {

            vaddr = address & TARGET_PAGE_MASK;

            paddr = lu.paddr + vaddr - lu.vaddr;



            DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",

                     mmu_idx, vaddr, paddr, lu.prot));

            r = tlb_set_page(env, vaddr,

                             paddr, lu.prot, mmu_idx, is_softmmu);

        } else {

            env->sregs[SR_EAR] = address;

            DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address));



            switch (lu.err) {

                case ERR_PROT:

                    env->sregs[SR_ESR] = rw == 2 ? 17 : 16;

                    env->sregs[SR_ESR] |= (rw == 1) << 10;

                    break;

                case ERR_MISS:

                    env->sregs[SR_ESR] = rw == 2 ? 19 : 18;

                    env->sregs[SR_ESR] |= (rw == 1) << 10;

                    break;

                default:

                    abort();

                    break;

            }



            if (env->exception_index == EXCP_MMU) {

                cpu_abort(env, "recursive faults\n");

            }



            

            env->exception_index = EXCP_MMU;

        }

    } else {

        

        address &= TARGET_PAGE_MASK;

        prot = PAGE_BITS;

        r = tlb_set_page(env, address, address, prot, mmu_idx, is_softmmu);

    }

    return r;

}

int FUNC_0 (CPUState *VAR_0, target_ulong VAR_1, int VAR_2,

                               int VAR_3, int VAR_4)

{

    unsigned int VAR_5;

    unsigned int VAR_6;

    int VAR_7 = 1;

    int VAR_8;



    VAR_6 = 0;

    if (VAR_0->pvr.regs[0] & PVR0_USE_MMU) {

        VAR_6 = 1;

        if ((VAR_0->pvr.regs[0] & PVR0_PVR_FULL_MASK)

            && (VAR_0->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {

            VAR_6 = 0;

        }

    }



    

    if (VAR_6 && (VAR_0->sregs[SR_MSR] & MSR_VM)) {

        target_ulong vaddr, paddr;

        struct microblaze_mmu_lookup VAR_9;



        VAR_5 = mmu_translate(&VAR_0->mmu, &VAR_9, VAR_1, VAR_2, VAR_3);

        if (VAR_5) {

            vaddr = VAR_1 & TARGET_PAGE_MASK;

            paddr = VAR_9.paddr + vaddr - VAR_9.vaddr;



            DMMU(qemu_log("MMU map mmu=%d v=%x p=%x VAR_8=%x\n",

                     VAR_3, vaddr, paddr, VAR_9.VAR_8));

            VAR_7 = tlb_set_page(VAR_0, vaddr,

                             paddr, VAR_9.VAR_8, VAR_3, VAR_4);

        } else {

            VAR_0->sregs[SR_EAR] = VAR_1;

            DMMU(qemu_log("mmu=%d miss v=%x\n", VAR_3, VAR_1));



            switch (VAR_9.err) {

                case ERR_PROT:

                    VAR_0->sregs[SR_ESR] = VAR_2 == 2 ? 17 : 16;

                    VAR_0->sregs[SR_ESR] |= (VAR_2 == 1) << 10;

                    break;

                case ERR_MISS:

                    VAR_0->sregs[SR_ESR] = VAR_2 == 2 ? 19 : 18;

                    VAR_0->sregs[SR_ESR] |= (VAR_2 == 1) << 10;

                    break;

                default:

                    abort();

                    break;

            }



            if (VAR_0->exception_index == EXCP_MMU) {

                cpu_abort(VAR_0, "recursive faults\n");

            }



            

            VAR_0->exception_index = EXCP_MMU;

        }

    } else {

        

        VAR_1 &= TARGET_PAGE_MASK;

        VAR_8 = PAGE_BITS;

        VAR_7 = tlb_set_page(VAR_0, VAR_1, VAR_1, VAR_8, VAR_3, VAR_4);

    }

    return VAR_7;

}

int FUNC_0 (CPUState *VAR_0, target_ulong VAR_1, int VAR_2,
int VAR_3, int VAR_4)
{ unsigned int VAR_5; unsigned int VAR_6; int VAR_7 = 1; int VAR_8; VAR_6 = 0; if (VAR_0->pvr.regs[0] & PVR0_USE_MMU) { VAR_6 = 1; if ((VAR_0->pvr.regs[0] & PVR0_PVR_FULL_MASK)
&& (VAR_0->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) { VAR_6 = 0; } } if (VAR_6 && (VAR_0->sregs[SR_MSR] & MSR_VM)) { target_ulong vaddr, paddr; struct microblaze_mmu_lookup VAR_9; VAR_5 = mmu_translate(&VAR_0->mmu, &VAR_9, VAR_1, VAR_2, VAR_3); if (VAR_5) { vaddr = VAR_1 & TARGET_PAGE_MASK; paddr = VAR_9.paddr + vaddr - VAR_9.vaddr; DMMU(qemu_log("MMU map mmu=%d v=%x p=%x VAR_8=%x\n",
VAR_3, vaddr, paddr, VAR_9.VAR_8)); VAR_7 = tlb_set_page(VAR_0, vaddr,
paddr, VAR_9.VAR_8, VAR_3, VAR_4); } else { VAR_0->sregs[SR_EAR] = VAR_1; DMMU(qemu_log("mmu=%d miss v=%x\n", VAR_3, VAR_1)); switch (VAR_9.err) { case ERR_PROT:
VAR_0->sregs[SR_ESR] = VAR_2 == 2 ? 17 : 16; VAR_0->sregs[SR_ESR] |= (VAR_2 == 1) << 10; break; case ERR_MISS:
VAR_0->sregs[SR_ESR] = VAR_2 == 2 ? 19 : 18; VAR_0->sregs[SR_ESR] |= (VAR_2 == 1) << 10; break; default:
abort(); break; } if (VAR_0->exception_index == EXCP_MMU) { cpu_abort(VAR_0, "recursive faults\n"); } VAR_0->exception_index = EXCP_MMU; } } else { VAR_1 &= TARGET_PAGE_MASK; VAR_8 = PAGE_BITS; VAR_7 = tlb_set_page(VAR_0, VAR_1, VAR_1, VAR_8, VAR_3, VAR_4); } return VAR_7; }