static int openpic_load(QEMUFile* f, void *opaque, int version_id)

{

    OpenPICState *opp = (OpenPICState *)opaque;

    unsigned int i;



    if (version_id != 1) {

        return -EINVAL;

    }



    qemu_get_be32s(f, &opp->gcr);

    qemu_get_be32s(f, &opp->vir);

    qemu_get_be32s(f, &opp->pir);

    qemu_get_be32s(f, &opp->spve);

    qemu_get_be32s(f, &opp->tfrr);



    qemu_get_be32s(f, &opp->nb_cpus);



    for (i = 0; i < opp->nb_cpus; i++) {

        qemu_get_sbe32s(f, &opp->dst[i].ctpr);

        openpic_load_IRQ_queue(f, &opp->dst[i].raised);

        openpic_load_IRQ_queue(f, &opp->dst[i].servicing);

        qemu_get_buffer(f, (uint8_t *)&opp->dst[i].outputs_active,

                        sizeof(opp->dst[i].outputs_active));

    }



    for (i = 0; i < OPENPIC_MAX_TMR; i++) {

        qemu_get_be32s(f, &opp->timers[i].tccr);

        qemu_get_be32s(f, &opp->timers[i].tbcr);

    }



    for (i = 0; i < opp->max_irq; i++) {

        uint32_t val;



        val = qemu_get_be32(f);

        write_IRQreg_idr(opp, i, val);

        val = qemu_get_be32(f);

        write_IRQreg_ivpr(opp, i, val);



        qemu_get_be32s(f, &opp->src[i].ivpr);

        qemu_get_be32s(f, &opp->src[i].idr);

        qemu_get_be32s(f, &opp->src[i].destmask);

        qemu_get_sbe32s(f, &opp->src[i].last_cpu);

        qemu_get_sbe32s(f, &opp->src[i].pending);

    }



    return 0;

}

static int openpic_load(QEMUFile* f, void *opaque, int version_id)

{

    OpenPICState *opp = (OpenPICState *)opaque;

    unsigned int i;



    if (version_id != 1) {

        return -EINVAL;

    }



    qemu_get_be32s(f, &opp->gcr);

    qemu_get_be32s(f, &opp->vir);

    qemu_get_be32s(f, &opp->pir);

    qemu_get_be32s(f, &opp->spve);

    qemu_get_be32s(f, &opp->tfrr);



    qemu_get_be32s(f, &opp->nb_cpus);



    for (i = 0; i < opp->nb_cpus; i++) {

        qemu_get_sbe32s(f, &opp->dst[i].ctpr);

        openpic_load_IRQ_queue(f, &opp->dst[i].raised);

        openpic_load_IRQ_queue(f, &opp->dst[i].servicing);

        qemu_get_buffer(f, (uint8_t *)&opp->dst[i].outputs_active,

                        sizeof(opp->dst[i].outputs_active));

    }



    for (i = 0; i < OPENPIC_MAX_TMR; i++) {

        qemu_get_be32s(f, &opp->timers[i].tccr);

        qemu_get_be32s(f, &opp->timers[i].tbcr);

    }



    for (i = 0; i < opp->max_irq; i++) {

        uint32_t val;



        val = qemu_get_be32(f);

        write_IRQreg_idr(opp, i, val);

        val = qemu_get_be32(f);

        write_IRQreg_ivpr(opp, i, val);



        qemu_get_be32s(f, &opp->src[i].ivpr);

        qemu_get_be32s(f, &opp->src[i].idr);

        qemu_get_be32s(f, &opp->src[i].destmask);

        qemu_get_sbe32s(f, &opp->src[i].last_cpu);

        qemu_get_sbe32s(f, &opp->src[i].pending);

    }



    return 0;

}

    unsigned int i;     qemu_get_be32s(f, &opp->nb_cpus);
static int FUNC_0(QEMUFile* VAR_0, void *VAR_1, int VAR_2)

{

    OpenPICState *opp = (OpenPICState *)VAR_1;

    unsigned int VAR_3;



    if (VAR_2 != 1) {

        return -EINVAL;

    }



    qemu_get_be32s(VAR_0, &opp->gcr);

    qemu_get_be32s(VAR_0, &opp->vir);

    qemu_get_be32s(VAR_0, &opp->pir);

    qemu_get_be32s(VAR_0, &opp->spve);

    qemu_get_be32s(VAR_0, &opp->tfrr);



    qemu_get_be32s(VAR_0, &opp->nb_cpus);



    for (VAR_3 = 0; VAR_3 < opp->nb_cpus; VAR_3++) {

        qemu_get_sbe32s(VAR_0, &opp->dst[VAR_3].ctpr);

        openpic_load_IRQ_queue(VAR_0, &opp->dst[VAR_3].raised);

        openpic_load_IRQ_queue(VAR_0, &opp->dst[VAR_3].servicing);

        qemu_get_buffer(VAR_0, (uint8_t *)&opp->dst[VAR_3].outputs_active,

                        sizeof(opp->dst[VAR_3].outputs_active));

    }



    for (VAR_3 = 0; VAR_3 < OPENPIC_MAX_TMR; VAR_3++) {

        qemu_get_be32s(VAR_0, &opp->timers[VAR_3].tccr);

        qemu_get_be32s(VAR_0, &opp->timers[VAR_3].tbcr);

    }



    for (VAR_3 = 0; VAR_3 < opp->max_irq; VAR_3++) {

        uint32_t val;



        val = qemu_get_be32(VAR_0);

        write_IRQreg_idr(opp, VAR_3, val);

        val = qemu_get_be32(VAR_0);

        write_IRQreg_ivpr(opp, VAR_3, val);



        qemu_get_be32s(VAR_0, &opp->src[VAR_3].ivpr);

        qemu_get_be32s(VAR_0, &opp->src[VAR_3].idr);

        qemu_get_be32s(VAR_0, &opp->src[VAR_3].destmask);

        qemu_get_sbe32s(VAR_0, &opp->src[VAR_3].last_cpu);

        qemu_get_sbe32s(VAR_0, &opp->src[VAR_3].pending);

    }



    return 0;

}

static int FUNC_0(QEMUFile* VAR_0, void *VAR_1, int VAR_2)
{ OpenPICState *opp = (OpenPICState *)VAR_1; unsigned int VAR_3; if (VAR_2 != 1) { return -EINVAL; } qemu_get_be32s(VAR_0, &opp->gcr); qemu_get_be32s(VAR_0, &opp->vir); qemu_get_be32s(VAR_0, &opp->pir); qemu_get_be32s(VAR_0, &opp->spve); qemu_get_be32s(VAR_0, &opp->tfrr); qemu_get_be32s(VAR_0, &opp->nb_cpus); for (VAR_3 = 0; VAR_3 < opp->nb_cpus; VAR_3++) { qemu_get_sbe32s(VAR_0, &opp->dst[VAR_3].ctpr); openpic_load_IRQ_queue(VAR_0, &opp->dst[VAR_3].raised); openpic_load_IRQ_queue(VAR_0, &opp->dst[VAR_3].servicing); qemu_get_buffer(VAR_0, (uint8_t *)&opp->dst[VAR_3].outputs_active,
sizeof(opp->dst[VAR_3].outputs_active)); } for (VAR_3 = 0; VAR_3 < OPENPIC_MAX_TMR; VAR_3++) { qemu_get_be32s(VAR_0, &opp->timers[VAR_3].tccr); qemu_get_be32s(VAR_0, &opp->timers[VAR_3].tbcr); } for (VAR_3 = 0; VAR_3 < opp->max_irq; VAR_3++) { uint32_t val; val = qemu_get_be32(VAR_0); write_IRQreg_idr(opp, VAR_3, val); val = qemu_get_be32(VAR_0); write_IRQreg_ivpr(opp, VAR_3, val); qemu_get_be32s(VAR_0, &opp->src[VAR_3].ivpr); qemu_get_be32s(VAR_0, &opp->src[VAR_3].idr); qemu_get_be32s(VAR_0, &opp->src[VAR_3].destmask); qemu_get_sbe32s(VAR_0, &opp->src[VAR_3].last_cpu); qemu_get_sbe32s(VAR_0, &opp->src[VAR_3].pending); } return 0; }