static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,

                             uint64_t value)

{

    ARMCPU *cpu = arm_env_get_cpu(env);



    if (env->cp15.contextidr_el1 != value && !arm_feature(env, ARM_FEATURE_MPU)

        && !extended_addresses_enabled(env)) {

        /* For VMSA (when not using the LPAE long descriptor page table

         * format) this register includes the ASID, so do a TLB flush.

         * For PMSA it is purely a process ID and no action is needed.

         */

        tlb_flush(CPU(cpu), 1);

    }

    env->cp15.contextidr_el1 = value;

}

static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,

                             uint64_t value)

{

    ARMCPU *cpu = arm_env_get_cpu(env);



    if (env->cp15.contextidr_el1 != value && !arm_feature(env, ARM_FEATURE_MPU)

        && !extended_addresses_enabled(env)) {

        







        tlb_flush(CPU(cpu), 1);

    }

    env->cp15.contextidr_el1 = value;

}

static void FUNC_0(CPUARMState *VAR_0, const ARMCPRegInfo *VAR_1,

                             uint64_t VAR_2)

{

    ARMCPU *cpu = arm_env_get_cpu(VAR_0);



    if (VAR_0->cp15.contextidr_el1 != VAR_2 && !arm_feature(VAR_0, ARM_FEATURE_MPU)

        && !extended_addresses_enabled(VAR_0)) {

        







        tlb_flush(CPU(cpu), 1);

    }

    VAR_0->cp15.contextidr_el1 = VAR_2;

}

static void FUNC_0(CPUARMState *VAR_0, const ARMCPRegInfo *VAR_1,
uint64_t VAR_2)
{ ARMCPU *cpu = arm_env_get_cpu(VAR_0); if (VAR_0->cp15.contextidr_el1 != VAR_2 && !arm_feature(VAR_0, ARM_FEATURE_MPU)
&& !extended_addresses_enabled(VAR_0)) { tlb_flush(CPU(cpu), 1); } VAR_0->cp15.contextidr_el1 = VAR_2; }