static void update_irq(struct xlx_pic *p)

{

    uint32_t i;



    /* level triggered interrupt */

    if (p->regs[R_MER] & 2) {

        p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr;

    }



    /* Update the pending register.  */

    p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER];



    /* Update the vector register.  */

    for (i = 0; i < 32; i++) {

        if (p->regs[R_IPR] & (1 << i))

            break;

    }

    if (i == 32)

        i = ~0;



    p->regs[R_IVR] = i;

    qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);

}

static void update_irq(struct xlx_pic *p)

{

    uint32_t i;



    

    if (p->regs[R_MER] & 2) {

        p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr;

    }



    

    p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER];



    

    for (i = 0; i < 32; i++) {

        if (p->regs[R_IPR] & (1 << i))

            break;

    }

    if (i == 32)

        i = ~0;



    p->regs[R_IVR] = i;

    qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);

}

        if (p->regs[R_IPR] & (1 << i))
static void FUNC_0(struct xlx_pic *VAR_0)

{

    uint32_t i;



    

    if (VAR_0->regs[R_MER] & 2) {

        VAR_0->regs[R_ISR] |= VAR_0->irq_pin_state & ~VAR_0->c_kind_of_intr;

    }



    

    VAR_0->regs[R_IPR] = VAR_0->regs[R_ISR] & VAR_0->regs[R_IER];



    

    for (i = 0; i < 32; i++) {

        if (VAR_0->regs[R_IPR] & (1 << i))

            break;

    }

    if (i == 32)

        i = ~0;



    VAR_0->regs[R_IVR] = i;

    qemu_set_irq(VAR_0->parent_irq, (VAR_0->regs[R_MER] & 1) && VAR_0->regs[R_IPR]);

}

static void FUNC_0(struct xlx_pic *VAR_0)
{ uint32_t i; if (VAR_0->regs[R_MER] & 2) { VAR_0->regs[R_ISR] |= VAR_0->irq_pin_state & ~VAR_0->c_kind_of_intr; } VAR_0->regs[R_IPR] = VAR_0->regs[R_ISR] & VAR_0->regs[R_IER]; for (i = 0; i < 32; i++) { if (VAR_0->regs[R_IPR] & (1 << i))
break; } if (i == 32)
i = ~0; VAR_0->regs[R_IVR] = i; qemu_set_irq(VAR_0->parent_irq, (VAR_0->regs[R_MER] & 1) && VAR_0->regs[R_IPR]); }