int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,

                          int rw, int access_type)

{

    int ret;



#if 0

    qemu_log("%s\n", __func__);

#endif

    if ((access_type == ACCESS_CODE && msr_ir == 0) ||

        (access_type != ACCESS_CODE && msr_dr == 0)) {

        /* No address translation */

        ret = check_physical(env, ctx, eaddr, rw);

    } else {

        ret = -1;

        switch (env->mmu_model) {

        case POWERPC_MMU_32B:

        case POWERPC_MMU_601:

        case POWERPC_MMU_SOFT_6xx:

        case POWERPC_MMU_SOFT_74xx:

#if defined(TARGET_PPC64)

        case POWERPC_MMU_620:

        case POWERPC_MMU_64B:

#endif

            /* Try to find a BAT */

            if (env->nb_BATs != 0)

                ret = get_bat(env, ctx, eaddr, rw, access_type);

            if (ret < 0) {

                /* We didn't match any BAT entry or don't have BATs */

                ret = get_segment(env, ctx, eaddr, rw, access_type);

            }

            break;

        case POWERPC_MMU_SOFT_4xx:

        case POWERPC_MMU_SOFT_4xx_Z:

            ret = mmu40x_get_physical_address(env, ctx, eaddr,

                                              rw, access_type);

            break;

        case POWERPC_MMU_BOOKE:

            ret = mmubooke_get_physical_address(env, ctx, eaddr,

                                                rw, access_type);

            break;

        case POWERPC_MMU_MPC8xx:

            /* XXX: TODO */

            cpu_abort(env, "MPC8xx MMU model is not implemented\n");

            break;

        case POWERPC_MMU_BOOKE_FSL:

            /* XXX: TODO */

            cpu_abort(env, "BookE FSL MMU model not implemented\n");

            return -1;

        case POWERPC_MMU_REAL:

            cpu_abort(env, "PowerPC in real mode do not do any translation\n");

            return -1;

        default:

            cpu_abort(env, "Unknown or invalid MMU model\n");

            return -1;

        }

    }

#if 0

    qemu_log("%s address " ADDRX " => %d " PADDRX "\n",

                __func__, eaddr, ret, ctx->raddr);

#endif



    return ret;

}

int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,

                          int rw, int access_type)

{

    int ret;



#if 0

    qemu_log("%s\n", __func__);

#endif

    if ((access_type == ACCESS_CODE && msr_ir == 0) ||

        (access_type != ACCESS_CODE && msr_dr == 0)) {

        

        ret = check_physical(env, ctx, eaddr, rw);

    } else {

        ret = -1;

        switch (env->mmu_model) {

        case POWERPC_MMU_32B:

        case POWERPC_MMU_601:

        case POWERPC_MMU_SOFT_6xx:

        case POWERPC_MMU_SOFT_74xx:

#if defined(TARGET_PPC64)

        case POWERPC_MMU_620:

        case POWERPC_MMU_64B:

#endif

            

            if (env->nb_BATs != 0)

                ret = get_bat(env, ctx, eaddr, rw, access_type);

            if (ret < 0) {

                

                ret = get_segment(env, ctx, eaddr, rw, access_type);

            }

            break;

        case POWERPC_MMU_SOFT_4xx:

        case POWERPC_MMU_SOFT_4xx_Z:

            ret = mmu40x_get_physical_address(env, ctx, eaddr,

                                              rw, access_type);

            break;

        case POWERPC_MMU_BOOKE:

            ret = mmubooke_get_physical_address(env, ctx, eaddr,

                                                rw, access_type);

            break;

        case POWERPC_MMU_MPC8xx:

            

            cpu_abort(env, "MPC8xx MMU model is not implemented\n");

            break;

        case POWERPC_MMU_BOOKE_FSL:

            

            cpu_abort(env, "BookE FSL MMU model not implemented\n");

            return -1;

        case POWERPC_MMU_REAL:

            cpu_abort(env, "PowerPC in real mode do not do any translation\n");

            return -1;

        default:

            cpu_abort(env, "Unknown or invalid MMU model\n");

            return -1;

        }

    }

#if 0

    qemu_log("%s address " ADDRX " => %d " PADDRX "\n",

                __func__, eaddr, ret, ctx->raddr);

#endif



    return ret;

}

int FUNC_0 (CPUState *VAR_0, mmu_ctx_t *VAR_1, target_ulong VAR_2,

                          int VAR_3, int VAR_4)

{

    int VAR_5;



#if 0

    qemu_log("%s\n", __func__);

#endif

    if ((VAR_4 == ACCESS_CODE && msr_ir == 0) ||

        (VAR_4 != ACCESS_CODE && msr_dr == 0)) {

        

        VAR_5 = check_physical(VAR_0, VAR_1, VAR_2, VAR_3);

    } else {

        VAR_5 = -1;

        switch (VAR_0->mmu_model) {

        case POWERPC_MMU_32B:

        case POWERPC_MMU_601:

        case POWERPC_MMU_SOFT_6xx:

        case POWERPC_MMU_SOFT_74xx:

#if defined(TARGET_PPC64)

        case POWERPC_MMU_620:

        case POWERPC_MMU_64B:

#endif

            

            if (VAR_0->nb_BATs != 0)

                VAR_5 = get_bat(VAR_0, VAR_1, VAR_2, VAR_3, VAR_4);

            if (VAR_5 < 0) {

                

                VAR_5 = get_segment(VAR_0, VAR_1, VAR_2, VAR_3, VAR_4);

            }

            break;

        case POWERPC_MMU_SOFT_4xx:

        case POWERPC_MMU_SOFT_4xx_Z:

            VAR_5 = mmu40x_get_physical_address(VAR_0, VAR_1, VAR_2,

                                              VAR_3, VAR_4);

            break;

        case POWERPC_MMU_BOOKE:

            VAR_5 = mmubooke_get_physical_address(VAR_0, VAR_1, VAR_2,

                                                VAR_3, VAR_4);

            break;

        case POWERPC_MMU_MPC8xx:

            

            cpu_abort(VAR_0, "MPC8xx MMU model is not implemented\n");

            break;

        case POWERPC_MMU_BOOKE_FSL:

            

            cpu_abort(VAR_0, "BookE FSL MMU model not implemented\n");

            return -1;

        case POWERPC_MMU_REAL:

            cpu_abort(VAR_0, "PowerPC in real mode do not do any translation\n");

            return -1;

        default:

            cpu_abort(VAR_0, "Unknown or invalid MMU model\n");

            return -1;

        }

    }

#if 0

    qemu_log("%s address " ADDRX " => %d " PADDRX "\n",

                __func__, VAR_2, VAR_5, VAR_1->raddr);

#endif



    return VAR_5;

}

int FUNC_0 (CPUState *VAR_0, mmu_ctx_t *VAR_1, target_ulong VAR_2,
int VAR_3, int VAR_4)
{ int VAR_5; #if 0
qemu_log("%s\n", __func__); #endif
if ((VAR_4 == ACCESS_CODE && msr_ir == 0) ||
(VAR_4 != ACCESS_CODE && msr_dr == 0)) { VAR_5 = check_physical(VAR_0, VAR_1, VAR_2, VAR_3); } else { VAR_5 = -1; switch (VAR_0->mmu_model) { case POWERPC_MMU_32B:
case POWERPC_MMU_601:
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
#if defined(TARGET_PPC64)
case POWERPC_MMU_620:
case POWERPC_MMU_64B:
#endif
if (VAR_0->nb_BATs != 0)
VAR_5 = get_bat(VAR_0, VAR_1, VAR_2, VAR_3, VAR_4); if (VAR_5 < 0) { VAR_5 = get_segment(VAR_0, VAR_1, VAR_2, VAR_3, VAR_4); } break; case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
VAR_5 = mmu40x_get_physical_address(VAR_0, VAR_1, VAR_2,
VAR_3, VAR_4); break; case POWERPC_MMU_BOOKE:
VAR_5 = mmubooke_get_physical_address(VAR_0, VAR_1, VAR_2,
VAR_3, VAR_4); break; case POWERPC_MMU_MPC8xx:
cpu_abort(VAR_0, "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE_FSL:
cpu_abort(VAR_0, "BookE FSL MMU model not implemented\n"); return -1; case POWERPC_MMU_REAL:
cpu_abort(VAR_0, "PowerPC in real mode do not do any translation\n"); return -1; default:
cpu_abort(VAR_0, "Unknown or invalid MMU model\n"); return -1; } } #if 0
qemu_log("%s address " ADDRX " => %d " PADDRX "\n",
__func__, VAR_2, VAR_5, VAR_1->raddr); #endif
return VAR_5; }