static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,

                                uint64_t val, unsigned size)

{

    CirrusVGAState *s = opaque;

    unsigned mode;



    addr &= s->cirrus_addr_mask;



    if (((s->vga.sr[0x17] & 0x44) == 0x44) &&

        ((addr & s->linear_mmio_mask) ==  s->linear_mmio_mask)) {

	/* memory-mapped I/O */

	cirrus_mmio_blt_write(s, addr & 0xff, val);

    } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {

	/* bitblt */

	*s->cirrus_srcptr++ = (uint8_t) val;

	if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {

	    cirrus_bitblt_cputovideo_next(s);

	}

    } else {

	/* video memory */

	if ((s->vga.gr[0x0B] & 0x14) == 0x14) {

	    addr <<= 4;

	} else if (s->vga.gr[0x0B] & 0x02) {

	    addr <<= 3;

	}

	addr &= s->cirrus_addr_mask;



	mode = s->vga.gr[0x05] & 0x7;

	if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {

	    *(s->vga.vram_ptr + addr) = (uint8_t) val;

            memory_region_set_dirty(&s->vga.vram, addr, 1);

	} else {

	    if ((s->vga.gr[0x0B] & 0x14) != 0x14) {

		cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);

	    } else {

		cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);

	    }

	}

    }

}

static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,

                                uint64_t val, unsigned size)

{

    CirrusVGAState *s = opaque;

    unsigned mode;



    addr &= s->cirrus_addr_mask;



    if (((s->vga.sr[0x17] & 0x44) == 0x44) &&

        ((addr & s->linear_mmio_mask) ==  s->linear_mmio_mask)) {

	

	cirrus_mmio_blt_write(s, addr & 0xff, val);

    } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {

	

	*s->cirrus_srcptr++ = (uint8_t) val;

	if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {

	    cirrus_bitblt_cputovideo_next(s);

	}

    } else {

	

	if ((s->vga.gr[0x0B] & 0x14) == 0x14) {

	    addr <<= 4;

	} else if (s->vga.gr[0x0B] & 0x02) {

	    addr <<= 3;

	}

	addr &= s->cirrus_addr_mask;



	mode = s->vga.gr[0x05] & 0x7;

	if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {

	    *(s->vga.vram_ptr + addr) = (uint8_t) val;

            memory_region_set_dirty(&s->vga.vram, addr, 1);

	} else {

	    if ((s->vga.gr[0x0B] & 0x14) != 0x14) {

		cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);

	    } else {

		cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);

	    }

	}

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                                uint64_t VAR_2, unsigned VAR_3)

{

    CirrusVGAState *s = VAR_0;

    unsigned VAR_4;



    VAR_1 &= s->cirrus_addr_mask;



    if (((s->vga.sr[0x17] & 0x44) == 0x44) &&

        ((VAR_1 & s->linear_mmio_mask) ==  s->linear_mmio_mask)) {

	

	cirrus_mmio_blt_write(s, VAR_1 & 0xff, VAR_2);

    } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {

	

	*s->cirrus_srcptr++ = (uint8_t) VAR_2;

	if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {

	    cirrus_bitblt_cputovideo_next(s);

	}

    } else {

	

	if ((s->vga.gr[0x0B] & 0x14) == 0x14) {

	    VAR_1 <<= 4;

	} else if (s->vga.gr[0x0B] & 0x02) {

	    VAR_1 <<= 3;

	}

	VAR_1 &= s->cirrus_addr_mask;



	VAR_4 = s->vga.gr[0x05] & 0x7;

	if (VAR_4 < 4 || VAR_4 > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {

	    *(s->vga.vram_ptr + VAR_1) = (uint8_t) VAR_2;

            memory_region_set_dirty(&s->vga.vram, VAR_1, 1);

	} else {

	    if ((s->vga.gr[0x0B] & 0x14) != 0x14) {

		cirrus_mem_writeb_mode4and5_8bpp(s, VAR_4, VAR_1, VAR_2);

	    } else {

		cirrus_mem_writeb_mode4and5_16bpp(s, VAR_4, VAR_1, VAR_2);

	    }

	}

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ CirrusVGAState *s = VAR_0; unsigned VAR_4; VAR_1 &= s->cirrus_addr_mask; if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
((VAR_1 & s->linear_mmio_mask) ==  s->linear_mmio_mask)) { cirrus_mmio_blt_write(s, VAR_1 & 0xff, VAR_2); } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { *s->cirrus_srcptr++ = (uint8_t) VAR_2; if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { cirrus_bitblt_cputovideo_next(s); } } else { if ((s->vga.gr[0x0B] & 0x14) == 0x14) { VAR_1 <<= 4; } else if (s->vga.gr[0x0B] & 0x02) { VAR_1 <<= 3; } VAR_1 &= s->cirrus_addr_mask; VAR_4 = s->vga.gr[0x05] & 0x7; if (VAR_4 < 4 || VAR_4 > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { *(s->vga.vram_ptr + VAR_1) = (uint8_t) VAR_2; memory_region_set_dirty(&s->vga.vram, VAR_1, 1); } else { if ((s->vga.gr[0x0B] & 0x14) != 0x14) { cirrus_mem_writeb_mode4and5_8bpp(s, VAR_4, VAR_1, VAR_2); } else { cirrus_mem_writeb_mode4and5_16bpp(s, VAR_4, VAR_1, VAR_2); } } } }