static int vga_load(QEMUFile *f, void *opaque, int version_id)

{

    VGAState *s = opaque;

    int is_vbe, i, ret;



    if (version_id > 2)

        return -EINVAL;



    if (s->pci_dev && version_id >= 2) {

        ret = pci_device_load(s->pci_dev, f);

        if (ret < 0)

            return ret;

    }



    qemu_get_be32s(f, &s->latch);

    qemu_get_8s(f, &s->sr_index);

    qemu_get_buffer(f, s->sr, 8);

    qemu_get_8s(f, &s->gr_index);

    qemu_get_buffer(f, s->gr, 16);

    qemu_get_8s(f, &s->ar_index);

    qemu_get_buffer(f, s->ar, 21);

    s->ar_flip_flop=qemu_get_be32(f);

    qemu_get_8s(f, &s->cr_index);

    qemu_get_buffer(f, s->cr, 256);

    qemu_get_8s(f, &s->msr);

    qemu_get_8s(f, &s->fcr);

    qemu_get_8s(f, &s->st00);

    qemu_get_8s(f, &s->st01);



    qemu_get_8s(f, &s->dac_state);

    qemu_get_8s(f, &s->dac_sub_index);

    qemu_get_8s(f, &s->dac_read_index);

    qemu_get_8s(f, &s->dac_write_index);

    qemu_get_buffer(f, s->dac_cache, 3);

    qemu_get_buffer(f, s->palette, 768);



    s->bank_offset=qemu_get_be32(f);

    is_vbe = qemu_get_byte(f);

#ifdef CONFIG_BOCHS_VBE

    if (!is_vbe)

        return -EINVAL;

    qemu_get_be16s(f, &s->vbe_index);

    for(i = 0; i < VBE_DISPI_INDEX_NB; i++)

        qemu_get_be16s(f, &s->vbe_regs[i]);

    qemu_get_be32s(f, &s->vbe_start_addr);

    qemu_get_be32s(f, &s->vbe_line_offset);

    qemu_get_be32s(f, &s->vbe_bank_mask);

#else

    if (is_vbe)

        return -EINVAL;

#endif



    /* force refresh */

    s->graphic_mode = -1;

    return 0;

}

static int vga_load(QEMUFile *f, void *opaque, int version_id)

{

    VGAState *s = opaque;

    int is_vbe, i, ret;



    if (version_id > 2)

        return -EINVAL;



    if (s->pci_dev && version_id >= 2) {

        ret = pci_device_load(s->pci_dev, f);

        if (ret < 0)

            return ret;

    }



    qemu_get_be32s(f, &s->latch);

    qemu_get_8s(f, &s->sr_index);

    qemu_get_buffer(f, s->sr, 8);

    qemu_get_8s(f, &s->gr_index);

    qemu_get_buffer(f, s->gr, 16);

    qemu_get_8s(f, &s->ar_index);

    qemu_get_buffer(f, s->ar, 21);

    s->ar_flip_flop=qemu_get_be32(f);

    qemu_get_8s(f, &s->cr_index);

    qemu_get_buffer(f, s->cr, 256);

    qemu_get_8s(f, &s->msr);

    qemu_get_8s(f, &s->fcr);

    qemu_get_8s(f, &s->st00);

    qemu_get_8s(f, &s->st01);



    qemu_get_8s(f, &s->dac_state);

    qemu_get_8s(f, &s->dac_sub_index);

    qemu_get_8s(f, &s->dac_read_index);

    qemu_get_8s(f, &s->dac_write_index);

    qemu_get_buffer(f, s->dac_cache, 3);

    qemu_get_buffer(f, s->palette, 768);



    s->bank_offset=qemu_get_be32(f);

    is_vbe = qemu_get_byte(f);

#ifdef CONFIG_BOCHS_VBE

    if (!is_vbe)

        return -EINVAL;

    qemu_get_be16s(f, &s->vbe_index);

    for(i = 0; i < VBE_DISPI_INDEX_NB; i++)

        qemu_get_be16s(f, &s->vbe_regs[i]);

    qemu_get_be32s(f, &s->vbe_start_addr);

    qemu_get_be32s(f, &s->vbe_line_offset);

    qemu_get_be32s(f, &s->vbe_bank_mask);

#else

    if (is_vbe)

        return -EINVAL;

#endif



    

    s->graphic_mode = -1;

    return 0;

}

    s->graphic_mode = -1;     s->graphic_mode = -1;     s->graphic_mode = -1;
static int FUNC_0(QEMUFile *VAR_0, void *VAR_1, int VAR_2)

{

    VGAState *s = VAR_1;

    int VAR_3, VAR_4, VAR_5;



    if (VAR_2 > 2)

        return -EINVAL;



    if (s->pci_dev && VAR_2 >= 2) {

        VAR_5 = pci_device_load(s->pci_dev, VAR_0);

        if (VAR_5 < 0)

            return VAR_5;

    }



    qemu_get_be32s(VAR_0, &s->latch);

    qemu_get_8s(VAR_0, &s->sr_index);

    qemu_get_buffer(VAR_0, s->sr, 8);

    qemu_get_8s(VAR_0, &s->gr_index);

    qemu_get_buffer(VAR_0, s->gr, 16);

    qemu_get_8s(VAR_0, &s->ar_index);

    qemu_get_buffer(VAR_0, s->ar, 21);

    s->ar_flip_flop=qemu_get_be32(VAR_0);

    qemu_get_8s(VAR_0, &s->cr_index);

    qemu_get_buffer(VAR_0, s->cr, 256);

    qemu_get_8s(VAR_0, &s->msr);

    qemu_get_8s(VAR_0, &s->fcr);

    qemu_get_8s(VAR_0, &s->st00);

    qemu_get_8s(VAR_0, &s->st01);



    qemu_get_8s(VAR_0, &s->dac_state);

    qemu_get_8s(VAR_0, &s->dac_sub_index);

    qemu_get_8s(VAR_0, &s->dac_read_index);

    qemu_get_8s(VAR_0, &s->dac_write_index);

    qemu_get_buffer(VAR_0, s->dac_cache, 3);

    qemu_get_buffer(VAR_0, s->palette, 768);



    s->bank_offset=qemu_get_be32(VAR_0);

    VAR_3 = qemu_get_byte(VAR_0);

#ifdef CONFIG_BOCHS_VBE

    if (!VAR_3)

        return -EINVAL;

    qemu_get_be16s(VAR_0, &s->vbe_index);

    for(VAR_4 = 0; VAR_4 < VBE_DISPI_INDEX_NB; VAR_4++)

        qemu_get_be16s(VAR_0, &s->vbe_regs[VAR_4]);

    qemu_get_be32s(VAR_0, &s->vbe_start_addr);

    qemu_get_be32s(VAR_0, &s->vbe_line_offset);

    qemu_get_be32s(VAR_0, &s->vbe_bank_mask);

#else

    if (VAR_3)

        return -EINVAL;

#endif



    

    s->graphic_mode = -1;

    return 0;

}

static int FUNC_0(QEMUFile *VAR_0, void *VAR_1, int VAR_2)
{ VGAState *s = VAR_1; int VAR_3, VAR_4, VAR_5; if (VAR_2 > 2)
return -EINVAL; if (s->pci_dev && VAR_2 >= 2) { VAR_5 = pci_device_load(s->pci_dev, VAR_0); if (VAR_5 < 0)
return VAR_5; } qemu_get_be32s(VAR_0, &s->latch); qemu_get_8s(VAR_0, &s->sr_index); qemu_get_buffer(VAR_0, s->sr, 8); qemu_get_8s(VAR_0, &s->gr_index); qemu_get_buffer(VAR_0, s->gr, 16); qemu_get_8s(VAR_0, &s->ar_index); qemu_get_buffer(VAR_0, s->ar, 21); s->ar_flip_flop=qemu_get_be32(VAR_0); qemu_get_8s(VAR_0, &s->cr_index); qemu_get_buffer(VAR_0, s->cr, 256); qemu_get_8s(VAR_0, &s->msr); qemu_get_8s(VAR_0, &s->fcr); qemu_get_8s(VAR_0, &s->st00); qemu_get_8s(VAR_0, &s->st01); qemu_get_8s(VAR_0, &s->dac_state); qemu_get_8s(VAR_0, &s->dac_sub_index); qemu_get_8s(VAR_0, &s->dac_read_index); qemu_get_8s(VAR_0, &s->dac_write_index); qemu_get_buffer(VAR_0, s->dac_cache, 3); qemu_get_buffer(VAR_0, s->palette, 768); s->bank_offset=qemu_get_be32(VAR_0); VAR_3 = qemu_get_byte(VAR_0); #ifdef CONFIG_BOCHS_VBE
if (!VAR_3)
return -EINVAL; qemu_get_be16s(VAR_0, &s->vbe_index); for(VAR_4 = 0; VAR_4 < VBE_DISPI_INDEX_NB; VAR_4++) qemu_get_be16s(VAR_0, &s->vbe_regs[VAR_4]); qemu_get_be32s(VAR_0, &s->vbe_start_addr); qemu_get_be32s(VAR_0, &s->vbe_line_offset); qemu_get_be32s(VAR_0, &s->vbe_bank_mask); #else
if (VAR_3)
return -EINVAL; #endif
s->graphic_mode = -1; return 0; }