static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished)

{

    AHCIPortRegs *pr = &s->dev[port].port_regs;

    IDEState *ide_state;

    uint8_t *sdb_fis;



    if (!s->dev[port].res_fis ||

        !(pr->cmd & PORT_CMD_FIS_RX)) {

        return;

    }



    sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS];

    ide_state = &s->dev[port].port.ifs[0];



    /* clear memory */

    *(uint32_t*)sdb_fis = 0;



    /* write values */

    sdb_fis[0] = ide_state->error;

    sdb_fis[2] = ide_state->status & 0x77;

    s->dev[port].finished |= finished;

    *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished);



    ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_SDB_FIS);

}

static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished)

{

    AHCIPortRegs *pr = &s->dev[port].port_regs;

    IDEState *ide_state;

    uint8_t *sdb_fis;



    if (!s->dev[port].res_fis ||

        !(pr->cmd & PORT_CMD_FIS_RX)) {

        return;

    }



    sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS];

    ide_state = &s->dev[port].port.ifs[0];



    

    *(uint32_t*)sdb_fis = 0;



    

    sdb_fis[0] = ide_state->error;

    sdb_fis[2] = ide_state->status & 0x77;

    s->dev[port].finished |= finished;

    *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished);



    ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_SDB_FIS);

}

    AHCIPortRegs *pr = &s->dev[port].port_regs;     sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS];     ide_state = &s->dev[port].port.ifs[0];     *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished);     ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_SDB_FIS);
static void FUNC_0(AHCIState *VAR_0, int VAR_1, uint32_t VAR_2)

{

    AHCIPortRegs *pr = &VAR_0->dev[VAR_1].port_regs;

    IDEState *ide_state;

    uint8_t *sdb_fis;



    if (!VAR_0->dev[VAR_1].res_fis ||

        !(pr->cmd & PORT_CMD_FIS_RX)) {

        return;

    }



    sdb_fis = &VAR_0->dev[VAR_1].res_fis[RES_FIS_SDBFIS];

    ide_state = &VAR_0->dev[VAR_1].VAR_1.ifs[0];



    

    *(uint32_t*)sdb_fis = 0;



    

    sdb_fis[0] = ide_state->error;

    sdb_fis[2] = ide_state->status & 0x77;

    VAR_0->dev[VAR_1].VAR_2 |= VAR_2;

    *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(VAR_0->dev[VAR_1].VAR_2);



    ahci_trigger_irq(VAR_0, &VAR_0->dev[VAR_1], PORT_IRQ_SDB_FIS);

}

static void FUNC_0(AHCIState *VAR_0, int VAR_1, uint32_t VAR_2)
{ AHCIPortRegs *pr = &VAR_0->dev[VAR_1].port_regs; IDEState *ide_state; uint8_t *sdb_fis; if (!VAR_0->dev[VAR_1].res_fis ||
!(pr->cmd & PORT_CMD_FIS_RX)) { return; } sdb_fis = &VAR_0->dev[VAR_1].res_fis[RES_FIS_SDBFIS]; ide_state = &VAR_0->dev[VAR_1].VAR_1.ifs[0]; *(uint32_t*)sdb_fis = 0; sdb_fis[0] = ide_state->error; sdb_fis[2] = ide_state->status & 0x77; VAR_0->dev[VAR_1].VAR_2 |= VAR_2; *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(VAR_0->dev[VAR_1].VAR_2); ahci_trigger_irq(VAR_0, &VAR_0->dev[VAR_1], PORT_IRQ_SDB_FIS); }