int check_hw_breakpoints(CPUX86State *env, int force_dr6_update)

{

    target_ulong dr6;

    int reg, type;

    int hit_enabled = 0;



    dr6 = env->dr[6] & ~0xf;

    for (reg = 0; reg < DR7_MAX_BP; reg++) {

        type = hw_breakpoint_type(env->dr[7], reg);

        if ((type == 0 && env->dr[reg] == env->eip) ||

            ((type & 1) && env->cpu_watchpoint[reg] &&

             (env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT))) {

            dr6 |= 1 << reg;

            if (hw_breakpoint_enabled(env->dr[7], reg)) {

                hit_enabled = 1;

            }

        }

    }

    if (hit_enabled || force_dr6_update)

        env->dr[6] = dr6;

    return hit_enabled;

}

int check_hw_breakpoints(CPUX86State *env, int force_dr6_update)

{

    target_ulong dr6;

    int reg, type;

    int hit_enabled = 0;



    dr6 = env->dr[6] & ~0xf;

    for (reg = 0; reg < DR7_MAX_BP; reg++) {

        type = hw_breakpoint_type(env->dr[7], reg);

        if ((type == 0 && env->dr[reg] == env->eip) ||

            ((type & 1) && env->cpu_watchpoint[reg] &&

             (env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT))) {

            dr6 |= 1 << reg;

            if (hw_breakpoint_enabled(env->dr[7], reg)) {

                hit_enabled = 1;

            }

        }

    }

    if (hit_enabled || force_dr6_update)

        env->dr[6] = dr6;

    return hit_enabled;

}

int check_hw_breakpoints(CPUX86State *env, int force_dr6_update)     int reg, type;     int hit_enabled = 0;         type = hw_breakpoint_type(env->dr[7], reg);         if ((type == 0 && env->dr[reg] == env->eip) ||             ((type & 1) && env->cpu_watchpoint[reg] &&              (env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT))) {                 hit_enabled = 1;     if (hit_enabled || force_dr6_update)
int FUNC_0(CPUX86State *VAR_0, int VAR_1)

{

    target_ulong dr6;

    int VAR_2, VAR_3;

    int VAR_4 = 0;



    dr6 = VAR_0->dr[6] & ~0xf;

    for (VAR_2 = 0; VAR_2 < DR7_MAX_BP; VAR_2++) {

        VAR_3 = hw_breakpoint_type(VAR_0->dr[7], VAR_2);

        if ((VAR_3 == 0 && VAR_0->dr[VAR_2] == VAR_0->eip) ||

            ((VAR_3 & 1) && VAR_0->cpu_watchpoint[VAR_2] &&

             (VAR_0->cpu_watchpoint[VAR_2]->flags & BP_WATCHPOINT_HIT))) {

            dr6 |= 1 << VAR_2;

            if (hw_breakpoint_enabled(VAR_0->dr[7], VAR_2)) {

                VAR_4 = 1;

            }

        }

    }

    if (VAR_4 || VAR_1)

        VAR_0->dr[6] = dr6;

    return VAR_4;

}

int FUNC_0(CPUX86State *VAR_0, int VAR_1)
{ target_ulong dr6; int VAR_2, VAR_3; int VAR_4 = 0; dr6 = VAR_0->dr[6] & ~0xf; for (VAR_2 = 0; VAR_2 < DR7_MAX_BP; VAR_2++) { VAR_3 = hw_breakpoint_type(VAR_0->dr[7], VAR_2); if ((VAR_3 == 0 && VAR_0->dr[VAR_2] == VAR_0->eip) ||
((VAR_3 & 1) && VAR_0->cpu_watchpoint[VAR_2] &&
(VAR_0->cpu_watchpoint[VAR_2]->flags & BP_WATCHPOINT_HIT))) { dr6 |= 1 << VAR_2; if (hw_breakpoint_enabled(VAR_0->dr[7], VAR_2)) { VAR_4 = 1; } } } if (VAR_4 || VAR_1)
VAR_0->dr[6] = dr6; return VAR_4; }