set_interrupt_cause(E1000State *s, int index, uint32_t val)

{

    if (val)

        val |= E1000_ICR_INT_ASSERTED;

    s->mac_reg[ICR] = val;

    s->mac_reg[ICS] = val;

    qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);

}

set_interrupt_cause(E1000State *s, int index, uint32_t val)

{

    if (val)

        val |= E1000_ICR_INT_ASSERTED;

    s->mac_reg[ICR] = val;

    s->mac_reg[ICS] = val;

    qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);

}

FUNC_0(E1000State *VAR_0, int VAR_1, uint32_t VAR_2)

{

    if (VAR_2)

        VAR_2 |= E1000_ICR_INT_ASSERTED;

    VAR_0->mac_reg[ICR] = VAR_2;

    VAR_0->mac_reg[ICS] = VAR_2;

    qemu_set_irq(VAR_0->dev.irq[0], (VAR_0->mac_reg[IMS] & VAR_0->mac_reg[ICR]) != 0);

}

FUNC_0(E1000State *VAR_0, int VAR_1, uint32_t VAR_2)
{ if (VAR_2)
VAR_2 |= E1000_ICR_INT_ASSERTED; VAR_0->mac_reg[ICR] = VAR_2; VAR_0->mac_reg[ICS] = VAR_2; qemu_set_irq(VAR_0->dev.irq[0], (VAR_0->mac_reg[IMS] & VAR_0->mac_reg[ICR]) != 0); }