static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,

                                   unsigned size)

{

    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;



    if (size != 4) {

        return omap_badwidth_read32(opaque, addr);

    }



    switch (offset) {

    case 0x00:	/* TVR */

        return s->timer.reset_val;



    case 0x04:	/* TCR */

        return omap_timer_read(&s->timer);



    case 0x08:	/* CR */

        return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;



    default:

        break;

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,

                                   unsigned size)

{

    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;



    if (size != 4) {

        return omap_badwidth_read32(opaque, addr);

    }



    switch (offset) {

    case 0x00:	

        return s->timer.reset_val;



    case 0x04:	

        return omap_timer_read(&s->timer);



    case 0x08:	

        return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;



    default:

        break;

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static uint64_t FUNC_0(void *opaque, target_phys_addr_t addr,

                                   unsigned size)

{

    struct omap_32khz_timer_s *VAR_0 = (struct omap_32khz_timer_s *) opaque;

    int VAR_1 = addr & OMAP_MPUI_REG_MASK;



    if (size != 4) {

        return omap_badwidth_read32(opaque, addr);

    }



    switch (VAR_1) {

    case 0x00:	

        return VAR_0->timer.reset_val;



    case 0x04:	

        return omap_timer_read(&VAR_0->timer);



    case 0x08:	

        return (VAR_0->timer.ar << 3) | (VAR_0->timer.it_ena << 2) | VAR_0->timer.st;



    default:

        break;

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static uint64_t FUNC_0(void *opaque, target_phys_addr_t addr,
unsigned size)
{ struct omap_32khz_timer_s *VAR_0 = (struct omap_32khz_timer_s *) opaque; int VAR_1 = addr & OMAP_MPUI_REG_MASK; if (size != 4) { return omap_badwidth_read32(opaque, addr); } switch (VAR_1) { case 0x00:
return VAR_0->timer.reset_val; case 0x04:
return omap_timer_read(&VAR_0->timer); case 0x08:
return (VAR_0->timer.ar << 3) | (VAR_0->timer.it_ena << 2) | VAR_0->timer.st; default:
break; } OMAP_BAD_REG(addr); return 0; }