int tcg_gen_code(TCGContext *s, TranslationBlock *tb)

{

#ifdef CONFIG_PROFILER

    TCGProfile *prof = &s->prof;

#endif

    int i, oi, oi_next, num_insns;



#ifdef CONFIG_PROFILER

    {

        int n;



        n = s->gen_op_buf[0].prev + 1;

        atomic_set(&prof->op_count, prof->op_count + n);

        if (n > prof->op_count_max) {

            atomic_set(&prof->op_count_max, n);

        }



        n = s->nb_temps;

        atomic_set(&prof->temp_count, prof->temp_count + n);

        if (n > prof->temp_count_max) {

            atomic_set(&prof->temp_count_max, n);

        }

    }

#endif



#ifdef DEBUG_DISAS

    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)

                 && qemu_log_in_addr_range(tb->pc))) {

        qemu_log_lock();

        qemu_log("OP:\n");

        tcg_dump_ops(s);

        qemu_log("\n");

        qemu_log_unlock();

    }

#endif



#ifdef CONFIG_PROFILER

    atomic_set(&prof->opt_time, prof->opt_time - profile_getclock());

#endif



#ifdef USE_TCG_OPTIMIZATIONS

    tcg_optimize(s);

#endif



#ifdef CONFIG_PROFILER

    atomic_set(&prof->opt_time, prof->opt_time + profile_getclock());

    atomic_set(&prof->la_time, prof->la_time - profile_getclock());

#endif



    liveness_pass_1(s);



    if (s->nb_indirects > 0) {

#ifdef DEBUG_DISAS

        if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND)

                     && qemu_log_in_addr_range(tb->pc))) {

            qemu_log_lock();

            qemu_log("OP before indirect lowering:\n");

            tcg_dump_ops(s);

            qemu_log("\n");

            qemu_log_unlock();

        }

#endif

        /* Replace indirect temps with direct temps.  */

        if (liveness_pass_2(s)) {

            /* If changes were made, re-run liveness.  */

            liveness_pass_1(s);

        }

    }



#ifdef CONFIG_PROFILER

    atomic_set(&prof->la_time, prof->la_time + profile_getclock());

#endif



#ifdef DEBUG_DISAS

    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT)

                 && qemu_log_in_addr_range(tb->pc))) {

        qemu_log_lock();

        qemu_log("OP after optimization and liveness analysis:\n");

        tcg_dump_ops(s);

        qemu_log("\n");

        qemu_log_unlock();

    }

#endif



    tcg_reg_alloc_start(s);



    s->code_buf = tb->tc.ptr;

    s->code_ptr = tb->tc.ptr;



#ifdef TCG_TARGET_NEED_LDST_LABELS

    s->ldst_labels = NULL;

#endif

#ifdef TCG_TARGET_NEED_POOL_LABELS

    s->pool_labels = NULL;

#endif



    num_insns = -1;

    for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {

        TCGOp * const op = &s->gen_op_buf[oi];

        TCGOpcode opc = op->opc;



        oi_next = op->next;

#ifdef CONFIG_PROFILER

        atomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] + 1);

#endif



        switch (opc) {

        case INDEX_op_mov_i32:

        case INDEX_op_mov_i64:

            tcg_reg_alloc_mov(s, op);

            break;

        case INDEX_op_movi_i32:

        case INDEX_op_movi_i64:

            tcg_reg_alloc_movi(s, op);

            break;

        case INDEX_op_insn_start:

            if (num_insns >= 0) {

                s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);

            }

            num_insns++;

            for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {

                target_ulong a;

#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS

                a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]);

#else

                a = op->args[i];

#endif

                s->gen_insn_data[num_insns][i] = a;

            }

            break;

        case INDEX_op_discard:

            temp_dead(s, arg_temp(op->args[0]));

            break;

        case INDEX_op_set_label:

            tcg_reg_alloc_bb_end(s, s->reserved_regs);

            tcg_out_label(s, arg_label(op->args[0]), s->code_ptr);

            break;

        case INDEX_op_call:

            tcg_reg_alloc_call(s, op);

            break;

        default:

            /* Sanity check that we've not introduced any unhandled opcodes. */

            tcg_debug_assert(tcg_op_supported(opc));

            /* Note: in order to speed up the code, it would be much

               faster to have specialized register allocator functions for

               some common argument patterns */

            tcg_reg_alloc_op(s, op);

            break;

        }

#ifdef CONFIG_DEBUG_TCG

        check_regs(s);

#endif

        /* Test for (pending) buffer overflow.  The assumption is that any

           one operation beginning below the high water mark cannot overrun

           the buffer completely.  Thus we can test for overflow after

           generating code without having to check during generation.  */

        if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {

            return -1;

        }

    }

    tcg_debug_assert(num_insns >= 0);

    s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);



    /* Generate TB finalization at the end of block */

#ifdef TCG_TARGET_NEED_LDST_LABELS

    if (!tcg_out_ldst_finalize(s)) {

        return -1;

    }

#endif

#ifdef TCG_TARGET_NEED_POOL_LABELS

    if (!tcg_out_pool_finalize(s)) {

        return -1;

    }

#endif



    /* flush instruction cache */

    flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);



    return tcg_current_code_size(s);

}

int tcg_gen_code(TCGContext *s, TranslationBlock *tb)

{

#ifdef CONFIG_PROFILER

    TCGProfile *prof = &s->prof;

#endif

    int i, oi, oi_next, num_insns;



#ifdef CONFIG_PROFILER

    {

        int n;



        n = s->gen_op_buf[0].prev + 1;

        atomic_set(&prof->op_count, prof->op_count + n);

        if (n > prof->op_count_max) {

            atomic_set(&prof->op_count_max, n);

        }



        n = s->nb_temps;

        atomic_set(&prof->temp_count, prof->temp_count + n);

        if (n > prof->temp_count_max) {

            atomic_set(&prof->temp_count_max, n);

        }

    }

#endif



#ifdef DEBUG_DISAS

    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)

                 && qemu_log_in_addr_range(tb->pc))) {

        qemu_log_lock();

        qemu_log("OP:\n");

        tcg_dump_ops(s);

        qemu_log("\n");

        qemu_log_unlock();

    }

#endif



#ifdef CONFIG_PROFILER

    atomic_set(&prof->opt_time, prof->opt_time - profile_getclock());

#endif



#ifdef USE_TCG_OPTIMIZATIONS

    tcg_optimize(s);

#endif



#ifdef CONFIG_PROFILER

    atomic_set(&prof->opt_time, prof->opt_time + profile_getclock());

    atomic_set(&prof->la_time, prof->la_time - profile_getclock());

#endif



    liveness_pass_1(s);



    if (s->nb_indirects > 0) {

#ifdef DEBUG_DISAS

        if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND)

                     && qemu_log_in_addr_range(tb->pc))) {

            qemu_log_lock();

            qemu_log("OP before indirect lowering:\n");

            tcg_dump_ops(s);

            qemu_log("\n");

            qemu_log_unlock();

        }

#endif

        

        if (liveness_pass_2(s)) {

            

            liveness_pass_1(s);

        }

    }



#ifdef CONFIG_PROFILER

    atomic_set(&prof->la_time, prof->la_time + profile_getclock());

#endif



#ifdef DEBUG_DISAS

    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT)

                 && qemu_log_in_addr_range(tb->pc))) {

        qemu_log_lock();

        qemu_log("OP after optimization and liveness analysis:\n");

        tcg_dump_ops(s);

        qemu_log("\n");

        qemu_log_unlock();

    }

#endif



    tcg_reg_alloc_start(s);



    s->code_buf = tb->tc.ptr;

    s->code_ptr = tb->tc.ptr;



#ifdef TCG_TARGET_NEED_LDST_LABELS

    s->ldst_labels = NULL;

#endif

#ifdef TCG_TARGET_NEED_POOL_LABELS

    s->pool_labels = NULL;

#endif



    num_insns = -1;

    for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {

        TCGOp * const op = &s->gen_op_buf[oi];

        TCGOpcode opc = op->opc;



        oi_next = op->next;

#ifdef CONFIG_PROFILER

        atomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] + 1);

#endif



        switch (opc) {

        case INDEX_op_mov_i32:

        case INDEX_op_mov_i64:

            tcg_reg_alloc_mov(s, op);

            break;

        case INDEX_op_movi_i32:

        case INDEX_op_movi_i64:

            tcg_reg_alloc_movi(s, op);

            break;

        case INDEX_op_insn_start:

            if (num_insns >= 0) {

                s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);

            }

            num_insns++;

            for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {

                target_ulong a;

#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS

                a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]);

#else

                a = op->args[i];

#endif

                s->gen_insn_data[num_insns][i] = a;

            }

            break;

        case INDEX_op_discard:

            temp_dead(s, arg_temp(op->args[0]));

            break;

        case INDEX_op_set_label:

            tcg_reg_alloc_bb_end(s, s->reserved_regs);

            tcg_out_label(s, arg_label(op->args[0]), s->code_ptr);

            break;

        case INDEX_op_call:

            tcg_reg_alloc_call(s, op);

            break;

        default:

            

            tcg_debug_assert(tcg_op_supported(opc));

            





            tcg_reg_alloc_op(s, op);

            break;

        }

#ifdef CONFIG_DEBUG_TCG

        check_regs(s);

#endif

        







        if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {

            return -1;

        }

    }

    tcg_debug_assert(num_insns >= 0);

    s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);



    

#ifdef TCG_TARGET_NEED_LDST_LABELS

    if (!tcg_out_ldst_finalize(s)) {

        return -1;

    }

#endif

#ifdef TCG_TARGET_NEED_POOL_LABELS

    if (!tcg_out_pool_finalize(s)) {

        return -1;

    }

#endif



    

    flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);



    return tcg_current_code_size(s);

}

#endif     for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {         TCGOp * const op = &s->gen_op_buf[oi];         oi_next = op->next;         TCGOp * const op = &s->gen_op_buf[oi];     for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {         oi_next = op->next;     int i, oi, oi_next, num_insns;         n = s->gen_op_buf[0].prev + 1;     for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {         TCGOp * const op = &s->gen_op_buf[oi];         oi_next = op->next;
int FUNC_0(TCGContext *VAR_0, TranslationBlock *VAR_1)

{

#ifdef CONFIG_PROFILER

    TCGProfile *prof = &VAR_0->prof;

#endif

    int VAR_2, VAR_3, VAR_4, VAR_5;



#ifdef CONFIG_PROFILER

    {

        int n;



        n = VAR_0->gen_op_buf[0].prev + 1;

        atomic_set(&prof->op_count, prof->op_count + n);

        if (n > prof->op_count_max) {

            atomic_set(&prof->op_count_max, n);

        }



        n = VAR_0->nb_temps;

        atomic_set(&prof->temp_count, prof->temp_count + n);

        if (n > prof->temp_count_max) {

            atomic_set(&prof->temp_count_max, n);

        }

    }

#endif



#ifdef DEBUG_DISAS

    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)

                 && qemu_log_in_addr_range(VAR_1->pc))) {

        qemu_log_lock();

        qemu_log("OP:\n");

        tcg_dump_ops(VAR_0);

        qemu_log("\n");

        qemu_log_unlock();

    }

#endif



#ifdef CONFIG_PROFILER

    atomic_set(&prof->opt_time, prof->opt_time - profile_getclock());

#endif



#ifdef USE_TCG_OPTIMIZATIONS

    tcg_optimize(VAR_0);

#endif



#ifdef CONFIG_PROFILER

    atomic_set(&prof->opt_time, prof->opt_time + profile_getclock());

    atomic_set(&prof->la_time, prof->la_time - profile_getclock());

#endif



    liveness_pass_1(VAR_0);



    if (VAR_0->nb_indirects > 0) {

#ifdef DEBUG_DISAS

        if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND)

                     && qemu_log_in_addr_range(VAR_1->pc))) {

            qemu_log_lock();

            qemu_log("OP before indirect lowering:\n");

            tcg_dump_ops(VAR_0);

            qemu_log("\n");

            qemu_log_unlock();

        }

#endif

        

        if (liveness_pass_2(VAR_0)) {

            

            liveness_pass_1(VAR_0);

        }

    }



#ifdef CONFIG_PROFILER

    atomic_set(&prof->la_time, prof->la_time + profile_getclock());

#endif



#ifdef DEBUG_DISAS

    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT)

                 && qemu_log_in_addr_range(VAR_1->pc))) {

        qemu_log_lock();

        qemu_log("OP after optimization and liveness analysis:\n");

        tcg_dump_ops(VAR_0);

        qemu_log("\n");

        qemu_log_unlock();

    }

#endif



    tcg_reg_alloc_start(VAR_0);



    VAR_0->code_buf = VAR_1->tc.ptr;

    VAR_0->code_ptr = VAR_1->tc.ptr;



#ifdef TCG_TARGET_NEED_LDST_LABELS

    VAR_0->ldst_labels = NULL;

#endif

#ifdef TCG_TARGET_NEED_POOL_LABELS

    VAR_0->pool_labels = NULL;

#endif



    VAR_5 = -1;

    for (VAR_3 = VAR_0->gen_op_buf[0].next; VAR_3 != 0; VAR_3 = VAR_4) {

        TCGOp * const op = &VAR_0->gen_op_buf[VAR_3];

        TCGOpcode opc = op->opc;



        VAR_4 = op->next;

#ifdef CONFIG_PROFILER

        atomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] + 1);

#endif



        switch (opc) {

        case INDEX_op_mov_i32:

        case INDEX_op_mov_i64:

            tcg_reg_alloc_mov(VAR_0, op);

            break;

        case INDEX_op_movi_i32:

        case INDEX_op_movi_i64:

            tcg_reg_alloc_movi(VAR_0, op);

            break;

        case INDEX_op_insn_start:

            if (VAR_5 >= 0) {

                VAR_0->gen_insn_end_off[VAR_5] = tcg_current_code_size(VAR_0);

            }

            VAR_5++;

            for (VAR_2 = 0; VAR_2 < TARGET_INSN_START_WORDS; ++VAR_2) {

                target_ulong a;

#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS

                a = deposit64(op->args[VAR_2 * 2], 32, 32, op->args[VAR_2 * 2 + 1]);

#else

                a = op->args[VAR_2];

#endif

                VAR_0->gen_insn_data[VAR_5][VAR_2] = a;

            }

            break;

        case INDEX_op_discard:

            temp_dead(VAR_0, arg_temp(op->args[0]));

            break;

        case INDEX_op_set_label:

            tcg_reg_alloc_bb_end(VAR_0, VAR_0->reserved_regs);

            tcg_out_label(VAR_0, arg_label(op->args[0]), VAR_0->code_ptr);

            break;

        case INDEX_op_call:

            tcg_reg_alloc_call(VAR_0, op);

            break;

        default:

            

            tcg_debug_assert(tcg_op_supported(opc));

            





            tcg_reg_alloc_op(VAR_0, op);

            break;

        }

#ifdef CONFIG_DEBUG_TCG

        check_regs(VAR_0);

#endif

        







        if (unlikely((void *)VAR_0->code_ptr > VAR_0->code_gen_highwater)) {

            return -1;

        }

    }

    tcg_debug_assert(VAR_5 >= 0);

    VAR_0->gen_insn_end_off[VAR_5] = tcg_current_code_size(VAR_0);



    

#ifdef TCG_TARGET_NEED_LDST_LABELS

    if (!tcg_out_ldst_finalize(VAR_0)) {

        return -1;

    }

#endif

#ifdef TCG_TARGET_NEED_POOL_LABELS

    if (!tcg_out_pool_finalize(VAR_0)) {

        return -1;

    }

#endif



    

    flush_icache_range((uintptr_t)VAR_0->code_buf, (uintptr_t)VAR_0->code_ptr);



    return tcg_current_code_size(VAR_0);

}

int FUNC_0(TCGContext *VAR_0, TranslationBlock *VAR_1)
{ #ifdef CONFIG_PROFILER
TCGProfile *prof = &VAR_0->prof; #endif
int VAR_2, VAR_3, VAR_4, VAR_5; #ifdef CONFIG_PROFILER
{ int n; n = VAR_0->gen_op_buf[0].prev + 1; atomic_set(&prof->op_count, prof->op_count + n); if (n > prof->op_count_max) { atomic_set(&prof->op_count_max, n); } n = VAR_0->nb_temps; atomic_set(&prof->temp_count, prof->temp_count + n); if (n > prof->temp_count_max) { atomic_set(&prof->temp_count_max, n); } } #endif
#ifdef DEBUG_DISAS
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)
&& qemu_log_in_addr_range(VAR_1->pc))) { qemu_log_lock(); qemu_log("OP:\n"); tcg_dump_ops(VAR_0); qemu_log("\n"); qemu_log_unlock(); } #endif
#ifdef CONFIG_PROFILER
atomic_set(&prof->opt_time, prof->opt_time - profile_getclock()); #endif
#ifdef USE_TCG_OPTIMIZATIONS
tcg_optimize(VAR_0); #endif
#ifdef CONFIG_PROFILER
atomic_set(&prof->opt_time, prof->opt_time + profile_getclock()); atomic_set(&prof->la_time, prof->la_time - profile_getclock()); #endif
liveness_pass_1(VAR_0); if (VAR_0->nb_indirects > 0) { #ifdef DEBUG_DISAS
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND)
&& qemu_log_in_addr_range(VAR_1->pc))) { qemu_log_lock(); qemu_log("OP before indirect lowering:\n"); tcg_dump_ops(VAR_0); qemu_log("\n"); qemu_log_unlock(); } #endif
if (liveness_pass_2(VAR_0)) { liveness_pass_1(VAR_0); } } #ifdef CONFIG_PROFILER
atomic_set(&prof->la_time, prof->la_time + profile_getclock()); #endif
#ifdef DEBUG_DISAS
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT)
&& qemu_log_in_addr_range(VAR_1->pc))) { qemu_log_lock(); qemu_log("OP after optimization and liveness analysis:\n"); tcg_dump_ops(VAR_0); qemu_log("\n"); qemu_log_unlock(); } #endif
tcg_reg_alloc_start(VAR_0); VAR_0->code_buf = VAR_1->tc.ptr; VAR_0->code_ptr = VAR_1->tc.ptr; #ifdef TCG_TARGET_NEED_LDST_LABELS
VAR_0->ldst_labels = NULL; #endif
#ifdef TCG_TARGET_NEED_POOL_LABELS
VAR_0->pool_labels = NULL; #endif
VAR_5 = -1; for (VAR_3 = VAR_0->gen_op_buf[0].next; VAR_3 != 0; VAR_3 = VAR_4) { TCGOp * const op = &VAR_0->gen_op_buf[VAR_3]; TCGOpcode opc = op->opc; VAR_4 = op->next; #ifdef CONFIG_PROFILER
atomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] + 1); #endif
switch (opc) { case INDEX_op_mov_i32:
case INDEX_op_mov_i64:
tcg_reg_alloc_mov(VAR_0, op); break; case INDEX_op_movi_i32:
case INDEX_op_movi_i64:
tcg_reg_alloc_movi(VAR_0, op); break; case INDEX_op_insn_start:
if (VAR_5 >= 0) { VAR_0->gen_insn_end_off[VAR_5] = tcg_current_code_size(VAR_0); } VAR_5++; for (VAR_2 = 0; VAR_2 < TARGET_INSN_START_WORDS; ++VAR_2) { target_ulong a; #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
a = deposit64(op->args[VAR_2 * 2], 32, 32, op->args[VAR_2 * 2 + 1]); #else
a = op->args[VAR_2]; #endif
VAR_0->gen_insn_data[VAR_5][VAR_2] = a; } break; case INDEX_op_discard:
temp_dead(VAR_0, arg_temp(op->args[0])); break; case INDEX_op_set_label:
tcg_reg_alloc_bb_end(VAR_0, VAR_0->reserved_regs); tcg_out_label(VAR_0, arg_label(op->args[0]), VAR_0->code_ptr); break; case INDEX_op_call:
tcg_reg_alloc_call(VAR_0, op); break; default:
tcg_debug_assert(tcg_op_supported(opc)); tcg_reg_alloc_op(VAR_0, op); break; } #ifdef CONFIG_DEBUG_TCG
check_regs(VAR_0); #endif
if (unlikely((void *)VAR_0->code_ptr > VAR_0->code_gen_highwater)) { return -1; } } tcg_debug_assert(VAR_5 >= 0); VAR_0->gen_insn_end_off[VAR_5] = tcg_current_code_size(VAR_0); #ifdef TCG_TARGET_NEED_LDST_LABELS
if (!tcg_out_ldst_finalize(VAR_0)) { return -1; } #endif
#ifdef TCG_TARGET_NEED_POOL_LABELS
if (!tcg_out_pool_finalize(VAR_0)) { return -1; } #endif
flush_icache_range((uintptr_t)VAR_0->code_buf, (uintptr_t)VAR_0->code_ptr); return tcg_current_code_size(VAR_0); }