static inline void decode(DisasContext *dc, uint32_t ir)

{

    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {

        tcg_gen_debug_insn_start(dc->pc);

    }



    dc->ir = ir;

    LOG_DIS("%8.8x\t", dc->ir);



    /* try guessing 'empty' instruction memory, although it may be a valid

     * instruction sequence (eg. srui r0, r0, 0) */

    if (dc->ir) {

        dc->nr_nops = 0;

    } else {

        LOG_DIS("nr_nops=%d\t", dc->nr_nops);

        dc->nr_nops++;

        if (dc->nr_nops > 4) {

            cpu_abort(dc->env, "fetching nop sequence\n");

        }

    }



    dc->opcode = EXTRACT_FIELD(ir, 26, 31);



    dc->imm5 = EXTRACT_FIELD(ir, 0, 4);

    dc->imm16 = EXTRACT_FIELD(ir, 0, 15);

    dc->imm26 = EXTRACT_FIELD(ir, 0, 25);



    dc->csr = EXTRACT_FIELD(ir, 21, 25);

    dc->r0 = EXTRACT_FIELD(ir, 21, 25);

    dc->r1 = EXTRACT_FIELD(ir, 16, 20);

    dc->r2 = EXTRACT_FIELD(ir, 11, 15);



    /* bit 31 seems to indicate insn type.  */

    if (ir & (1 << 31)) {

        dc->format = OP_FMT_RR;

    } else {

        dc->format = OP_FMT_RI;

    }



    assert(ARRAY_SIZE(decinfo) == 64);

    assert(dc->opcode < 64);



    decinfo[dc->opcode](dc);

}

static inline void decode(DisasContext *dc, uint32_t ir)

{

    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {

        tcg_gen_debug_insn_start(dc->pc);

    }



    dc->ir = ir;

    LOG_DIS("%8.8x\t", dc->ir);



    



    if (dc->ir) {

        dc->nr_nops = 0;

    } else {

        LOG_DIS("nr_nops=%d\t", dc->nr_nops);

        dc->nr_nops++;

        if (dc->nr_nops > 4) {

            cpu_abort(dc->env, "fetching nop sequence\n");

        }

    }



    dc->opcode = EXTRACT_FIELD(ir, 26, 31);



    dc->imm5 = EXTRACT_FIELD(ir, 0, 4);

    dc->imm16 = EXTRACT_FIELD(ir, 0, 15);

    dc->imm26 = EXTRACT_FIELD(ir, 0, 25);



    dc->csr = EXTRACT_FIELD(ir, 21, 25);

    dc->r0 = EXTRACT_FIELD(ir, 21, 25);

    dc->r1 = EXTRACT_FIELD(ir, 16, 20);

    dc->r2 = EXTRACT_FIELD(ir, 11, 15);



    

    if (ir & (1 << 31)) {

        dc->format = OP_FMT_RR;

    } else {

        dc->format = OP_FMT_RI;

    }



    assert(ARRAY_SIZE(decinfo) == 64);

    assert(dc->opcode < 64);



    decinfo[dc->opcode](dc);

}

    if (dc->ir) {         dc->nr_nops = 0;     } else {         LOG_DIS("nr_nops=%d\t", dc->nr_nops);         dc->nr_nops++;         if (dc->nr_nops > 4) {             cpu_abort(dc->env, "fetching nop sequence\n");
static inline void FUNC_0(DisasContext *VAR_0, uint32_t VAR_1)

{

    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {

        tcg_gen_debug_insn_start(VAR_0->pc);

    }



    VAR_0->VAR_1 = VAR_1;

    LOG_DIS("%8.8x\t", VAR_0->VAR_1);



    



    if (VAR_0->VAR_1) {

        VAR_0->nr_nops = 0;

    } else {

        LOG_DIS("nr_nops=%d\t", VAR_0->nr_nops);

        VAR_0->nr_nops++;

        if (VAR_0->nr_nops > 4) {

            cpu_abort(VAR_0->env, "fetching nop sequence\n");

        }

    }



    VAR_0->opcode = EXTRACT_FIELD(VAR_1, 26, 31);



    VAR_0->imm5 = EXTRACT_FIELD(VAR_1, 0, 4);

    VAR_0->imm16 = EXTRACT_FIELD(VAR_1, 0, 15);

    VAR_0->imm26 = EXTRACT_FIELD(VAR_1, 0, 25);



    VAR_0->csr = EXTRACT_FIELD(VAR_1, 21, 25);

    VAR_0->r0 = EXTRACT_FIELD(VAR_1, 21, 25);

    VAR_0->r1 = EXTRACT_FIELD(VAR_1, 16, 20);

    VAR_0->r2 = EXTRACT_FIELD(VAR_1, 11, 15);



    

    if (VAR_1 & (1 << 31)) {

        VAR_0->format = OP_FMT_RR;

    } else {

        VAR_0->format = OP_FMT_RI;

    }



    assert(ARRAY_SIZE(decinfo) == 64);

    assert(VAR_0->opcode < 64);



    decinfo[VAR_0->opcode](VAR_0);

}

static inline void FUNC_0(DisasContext *VAR_0, uint32_t VAR_1)
{ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(VAR_0->pc); } VAR_0->VAR_1 = VAR_1; LOG_DIS("%8.8x\t", VAR_0->VAR_1); if (VAR_0->VAR_1) { VAR_0->nr_nops = 0; } else { LOG_DIS("nr_nops=%d\t", VAR_0->nr_nops); VAR_0->nr_nops++; if (VAR_0->nr_nops > 4) { cpu_abort(VAR_0->env, "fetching nop sequence\n"); } } VAR_0->opcode = EXTRACT_FIELD(VAR_1, 26, 31); VAR_0->imm5 = EXTRACT_FIELD(VAR_1, 0, 4); VAR_0->imm16 = EXTRACT_FIELD(VAR_1, 0, 15); VAR_0->imm26 = EXTRACT_FIELD(VAR_1, 0, 25); VAR_0->csr = EXTRACT_FIELD(VAR_1, 21, 25); VAR_0->r0 = EXTRACT_FIELD(VAR_1, 21, 25); VAR_0->r1 = EXTRACT_FIELD(VAR_1, 16, 20); VAR_0->r2 = EXTRACT_FIELD(VAR_1, 11, 15); if (VAR_1 & (1 << 31)) { VAR_0->format = OP_FMT_RR; } else { VAR_0->format = OP_FMT_RI; } assert(ARRAY_SIZE(decinfo) == 64); assert(VAR_0->opcode < 64); decinfo[VAR_0->opcode](VAR_0); }