static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,

                                     enum device_endian endian)

{

    uint8_t *ptr;

    MemoryRegionSection *section;



    section = phys_page_find(addr >> TARGET_PAGE_BITS);



    if (!memory_region_is_ram(section->mr) || section->readonly) {

        addr = memory_region_section_addr(section, addr);

        if (memory_region_is_ram(section->mr)) {

            section = &phys_sections[phys_section_rom];

        }

#if defined(TARGET_WORDS_BIGENDIAN)

        if (endian == DEVICE_LITTLE_ENDIAN) {

            val = bswap16(val);

        }

#else

        if (endian == DEVICE_BIG_ENDIAN) {

            val = bswap16(val);

        }

#endif

        io_mem_write(section->mr, addr, val, 2);

    } else {

        unsigned long addr1;

        addr1 = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)

            + memory_region_section_addr(section, addr);

        /* RAM case */

        ptr = qemu_get_ram_ptr(addr1);

        switch (endian) {

        case DEVICE_LITTLE_ENDIAN:

            stw_le_p(ptr, val);

            break;

        case DEVICE_BIG_ENDIAN:

            stw_be_p(ptr, val);

            break;

        default:

            stw_p(ptr, val);

            break;

        }

        invalidate_and_set_dirty(addr1, 2);

    }

}

static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,

                                     enum device_endian endian)

{

    uint8_t *ptr;

    MemoryRegionSection *section;



    section = phys_page_find(addr >> TARGET_PAGE_BITS);



    if (!memory_region_is_ram(section->mr) || section->readonly) {

        addr = memory_region_section_addr(section, addr);

        if (memory_region_is_ram(section->mr)) {

            section = &phys_sections[phys_section_rom];

        }

#if defined(TARGET_WORDS_BIGENDIAN)

        if (endian == DEVICE_LITTLE_ENDIAN) {

            val = bswap16(val);

        }

#else

        if (endian == DEVICE_BIG_ENDIAN) {

            val = bswap16(val);

        }

#endif

        io_mem_write(section->mr, addr, val, 2);

    } else {

        unsigned long addr1;

        addr1 = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)

            + memory_region_section_addr(section, addr);

        

        ptr = qemu_get_ram_ptr(addr1);

        switch (endian) {

        case DEVICE_LITTLE_ENDIAN:

            stw_le_p(ptr, val);

            break;

        case DEVICE_BIG_ENDIAN:

            stw_be_p(ptr, val);

            break;

        default:

            stw_p(ptr, val);

            break;

        }

        invalidate_and_set_dirty(addr1, 2);

    }

}

static inline void FUNC_0(target_phys_addr_t VAR_0, uint32_t VAR_1,

                                     enum device_endian VAR_2)

{

    uint8_t *ptr;

    MemoryRegionSection *section;



    section = phys_page_find(VAR_0 >> TARGET_PAGE_BITS);



    if (!memory_region_is_ram(section->mr) || section->readonly) {

        VAR_0 = memory_region_section_addr(section, VAR_0);

        if (memory_region_is_ram(section->mr)) {

            section = &phys_sections[phys_section_rom];

        }

#if defined(TARGET_WORDS_BIGENDIAN)

        if (VAR_2 == DEVICE_LITTLE_ENDIAN) {

            VAR_1 = bswap16(VAR_1);

        }

#else

        if (VAR_2 == DEVICE_BIG_ENDIAN) {

            VAR_1 = bswap16(VAR_1);

        }

#endif

        io_mem_write(section->mr, VAR_0, VAR_1, 2);

    } else {

        unsigned long VAR_3;

        VAR_3 = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)

            + memory_region_section_addr(section, VAR_0);

        

        ptr = qemu_get_ram_ptr(VAR_3);

        switch (VAR_2) {

        case DEVICE_LITTLE_ENDIAN:

            stw_le_p(ptr, VAR_1);

            break;

        case DEVICE_BIG_ENDIAN:

            stw_be_p(ptr, VAR_1);

            break;

        default:

            stw_p(ptr, VAR_1);

            break;

        }

        invalidate_and_set_dirty(VAR_3, 2);

    }

}

static inline void FUNC_0(target_phys_addr_t VAR_0, uint32_t VAR_1,
enum device_endian VAR_2)
{ uint8_t *ptr; MemoryRegionSection *section; section = phys_page_find(VAR_0 >> TARGET_PAGE_BITS); if (!memory_region_is_ram(section->mr) || section->readonly) { VAR_0 = memory_region_section_addr(section, VAR_0); if (memory_region_is_ram(section->mr)) { section = &phys_sections[phys_section_rom]; } #if defined(TARGET_WORDS_BIGENDIAN)
if (VAR_2 == DEVICE_LITTLE_ENDIAN) { VAR_1 = bswap16(VAR_1); } #else
if (VAR_2 == DEVICE_BIG_ENDIAN) { VAR_1 = bswap16(VAR_1); } #endif
io_mem_write(section->mr, VAR_0, VAR_1, 2); } else { unsigned long VAR_3; VAR_3 = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
+ memory_region_section_addr(section, VAR_0); ptr = qemu_get_ram_ptr(VAR_3); switch (VAR_2) { case DEVICE_LITTLE_ENDIAN:
stw_le_p(ptr, VAR_1); break; case DEVICE_BIG_ENDIAN:
stw_be_p(ptr, VAR_1); break; default:
stw_p(ptr, VAR_1); break; } invalidate_and_set_dirty(VAR_3, 2); } }