void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)

{

    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);

    CPUState *cs = CPU(cpu);

    struct DisasContext ctx, *dc = &ctx;

    uint32_t pc_start;

    uint32_t next_page_start;

    int num_insns;

    int max_insns;



    pc_start = tb->pc;

    dc->tb = tb;



    dc->is_jmp = DISAS_NEXT;

    dc->ppc = pc_start;

    dc->pc = pc_start;

    dc->flags = cpu->env.cpucfgr;

    dc->mem_idx = cpu_mmu_index(&cpu->env, false);

    dc->synced_flags = dc->tb_flags = tb->flags;

    dc->delayed_branch = !!(dc->tb_flags & D_FLAG);

    dc->singlestep_enabled = cs->singlestep_enabled;



    next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;

    num_insns = 0;

    max_insns = tb->cflags & CF_COUNT_MASK;



    if (max_insns == 0) {

        max_insns = CF_COUNT_MASK;

    }

    if (max_insns > TCG_MAX_INSNS) {

        max_insns = TCG_MAX_INSNS;

    }



    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)

        && qemu_log_in_addr_range(pc_start)) {

        qemu_log_lock();

        qemu_log("----------------\n");

        qemu_log("IN: %s\n", lookup_symbol(pc_start));

    }



    gen_tb_start(tb);



    do {

        tcg_gen_insn_start(dc->pc);

        num_insns++;



        if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {

            tcg_gen_movi_tl(cpu_pc, dc->pc);

            gen_exception(dc, EXCP_DEBUG);

            dc->is_jmp = DISAS_UPDATE;

            /* The address covered by the breakpoint must be included in

               [tb->pc, tb->pc + tb->size) in order to for it to be

               properly cleared -- thus we increment the PC here so that

               the logic setting tb->size below does the right thing.  */

            dc->pc += 4;

            break;

        }



        if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {

            gen_io_start();

        }

        dc->ppc = dc->pc - 4;

        dc->npc = dc->pc + 4;

        tcg_gen_movi_tl(cpu_ppc, dc->ppc);

        tcg_gen_movi_tl(cpu_npc, dc->npc);

        disas_openrisc_insn(dc, cpu);

        dc->pc = dc->npc;

        /* delay slot */

        if (dc->delayed_branch) {

            dc->delayed_branch--;

            if (!dc->delayed_branch) {

                dc->tb_flags &= ~D_FLAG;

                gen_sync_flags(dc);

                tcg_gen_mov_tl(cpu_pc, jmp_pc);

                tcg_gen_mov_tl(cpu_npc, jmp_pc);

                tcg_gen_movi_tl(jmp_pc, 0);

                tcg_gen_exit_tb(0);

                dc->is_jmp = DISAS_JUMP;

                break;

            }

        }

    } while (!dc->is_jmp

             && !tcg_op_buf_full()

             && !cs->singlestep_enabled

             && !singlestep

             && (dc->pc < next_page_start)

             && num_insns < max_insns);



    if (tb->cflags & CF_LAST_IO) {

        gen_io_end();

    }

    if (dc->is_jmp == DISAS_NEXT) {

        dc->is_jmp = DISAS_UPDATE;

        tcg_gen_movi_tl(cpu_pc, dc->pc);

    }

    if (unlikely(cs->singlestep_enabled)) {

        if (dc->is_jmp == DISAS_NEXT) {

            tcg_gen_movi_tl(cpu_pc, dc->pc);

        }

        gen_exception(dc, EXCP_DEBUG);

    } else {

        switch (dc->is_jmp) {

        case DISAS_NEXT:

            gen_goto_tb(dc, 0, dc->pc);

            break;

        default:

        case DISAS_JUMP:

            break;

        case DISAS_UPDATE:

            /* indicate that the hash table must be used

               to find the next TB */

            tcg_gen_exit_tb(0);

            break;

        case DISAS_TB_JUMP:

            /* nothing more to generate */

            break;

        }

    }



    gen_tb_end(tb, num_insns);



    tb->size = dc->pc - pc_start;

    tb->icount = num_insns;



    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)

        && qemu_log_in_addr_range(pc_start)) {

        log_target_disas(cs, pc_start, tb->size, 0);

        qemu_log("\n");

        qemu_log_unlock();

    }

}

void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)

{

    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);

    CPUState *cs = CPU(cpu);

    struct DisasContext ctx, *dc = &ctx;

    uint32_t pc_start;

    uint32_t next_page_start;

    int num_insns;

    int max_insns;



    pc_start = tb->pc;

    dc->tb = tb;



    dc->is_jmp = DISAS_NEXT;

    dc->ppc = pc_start;

    dc->pc = pc_start;

    dc->flags = cpu->env.cpucfgr;

    dc->mem_idx = cpu_mmu_index(&cpu->env, false);

    dc->synced_flags = dc->tb_flags = tb->flags;

    dc->delayed_branch = !!(dc->tb_flags & D_FLAG);

    dc->singlestep_enabled = cs->singlestep_enabled;



    next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;

    num_insns = 0;

    max_insns = tb->cflags & CF_COUNT_MASK;



    if (max_insns == 0) {

        max_insns = CF_COUNT_MASK;

    }

    if (max_insns > TCG_MAX_INSNS) {

        max_insns = TCG_MAX_INSNS;

    }



    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)

        && qemu_log_in_addr_range(pc_start)) {

        qemu_log_lock();

        qemu_log("----------------\n");

        qemu_log("IN: %s\n", lookup_symbol(pc_start));

    }



    gen_tb_start(tb);



    do {

        tcg_gen_insn_start(dc->pc);

        num_insns++;



        if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {

            tcg_gen_movi_tl(cpu_pc, dc->pc);

            gen_exception(dc, EXCP_DEBUG);

            dc->is_jmp = DISAS_UPDATE;

            







            dc->pc += 4;

            break;

        }



        if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {

            gen_io_start();

        }

        dc->ppc = dc->pc - 4;

        dc->npc = dc->pc + 4;

        tcg_gen_movi_tl(cpu_ppc, dc->ppc);

        tcg_gen_movi_tl(cpu_npc, dc->npc);

        disas_openrisc_insn(dc, cpu);

        dc->pc = dc->npc;

        

        if (dc->delayed_branch) {

            dc->delayed_branch--;

            if (!dc->delayed_branch) {

                dc->tb_flags &= ~D_FLAG;

                gen_sync_flags(dc);

                tcg_gen_mov_tl(cpu_pc, jmp_pc);

                tcg_gen_mov_tl(cpu_npc, jmp_pc);

                tcg_gen_movi_tl(jmp_pc, 0);

                tcg_gen_exit_tb(0);

                dc->is_jmp = DISAS_JUMP;

                break;

            }

        }

    } while (!dc->is_jmp

             && !tcg_op_buf_full()

             && !cs->singlestep_enabled

             && !singlestep

             && (dc->pc < next_page_start)

             && num_insns < max_insns);



    if (tb->cflags & CF_LAST_IO) {

        gen_io_end();

    }

    if (dc->is_jmp == DISAS_NEXT) {

        dc->is_jmp = DISAS_UPDATE;

        tcg_gen_movi_tl(cpu_pc, dc->pc);

    }

    if (unlikely(cs->singlestep_enabled)) {

        if (dc->is_jmp == DISAS_NEXT) {

            tcg_gen_movi_tl(cpu_pc, dc->pc);

        }

        gen_exception(dc, EXCP_DEBUG);

    } else {

        switch (dc->is_jmp) {

        case DISAS_NEXT:

            gen_goto_tb(dc, 0, dc->pc);

            break;

        default:

        case DISAS_JUMP:

            break;

        case DISAS_UPDATE:

            



            tcg_gen_exit_tb(0);

            break;

        case DISAS_TB_JUMP:

            

            break;

        }

    }



    gen_tb_end(tb, num_insns);



    tb->size = dc->pc - pc_start;

    tb->icount = num_insns;



    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)

        && qemu_log_in_addr_range(pc_start)) {

        log_target_disas(cs, pc_start, tb->size, 0);

        qemu_log("\n");

        qemu_log_unlock();

    }

}

    dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
void FUNC_0(CPUOpenRISCState *VAR_0, struct TranslationBlock *VAR_1)

{

    OpenRISCCPU *cpu = openrisc_env_get_cpu(VAR_0);

    CPUState *cs = CPU(cpu);

    struct DisasContext VAR_2, *VAR_3 = &VAR_2;

    uint32_t pc_start;

    uint32_t next_page_start;

    int VAR_4;

    int VAR_5;



    pc_start = VAR_1->pc;

    VAR_3->VAR_1 = VAR_1;



    VAR_3->is_jmp = DISAS_NEXT;

    VAR_3->ppc = pc_start;

    VAR_3->pc = pc_start;

    VAR_3->flags = cpu->VAR_0.cpucfgr;

    VAR_3->mem_idx = cpu_mmu_index(&cpu->VAR_0, false);

    VAR_3->synced_flags = VAR_3->tb_flags = VAR_1->flags;

    VAR_3->delayed_branch = !!(VAR_3->tb_flags & D_FLAG);

    VAR_3->singlestep_enabled = cs->singlestep_enabled;



    next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;

    VAR_4 = 0;

    VAR_5 = VAR_1->cflags & CF_COUNT_MASK;



    if (VAR_5 == 0) {

        VAR_5 = CF_COUNT_MASK;

    }

    if (VAR_5 > TCG_MAX_INSNS) {

        VAR_5 = TCG_MAX_INSNS;

    }



    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)

        && qemu_log_in_addr_range(pc_start)) {

        qemu_log_lock();

        qemu_log("----------------\n");

        qemu_log("IN: %s\n", lookup_symbol(pc_start));

    }



    gen_tb_start(VAR_1);



    do {

        tcg_gen_insn_start(VAR_3->pc);

        VAR_4++;



        if (unlikely(cpu_breakpoint_test(cs, VAR_3->pc, BP_ANY))) {

            tcg_gen_movi_tl(cpu_pc, VAR_3->pc);

            gen_exception(VAR_3, EXCP_DEBUG);

            VAR_3->is_jmp = DISAS_UPDATE;

            







            VAR_3->pc += 4;

            break;

        }



        if (VAR_4 == VAR_5 && (VAR_1->cflags & CF_LAST_IO)) {

            gen_io_start();

        }

        VAR_3->ppc = VAR_3->pc - 4;

        VAR_3->npc = VAR_3->pc + 4;

        tcg_gen_movi_tl(cpu_ppc, VAR_3->ppc);

        tcg_gen_movi_tl(cpu_npc, VAR_3->npc);

        disas_openrisc_insn(VAR_3, cpu);

        VAR_3->pc = VAR_3->npc;

        

        if (VAR_3->delayed_branch) {

            VAR_3->delayed_branch--;

            if (!VAR_3->delayed_branch) {

                VAR_3->tb_flags &= ~D_FLAG;

                gen_sync_flags(VAR_3);

                tcg_gen_mov_tl(cpu_pc, jmp_pc);

                tcg_gen_mov_tl(cpu_npc, jmp_pc);

                tcg_gen_movi_tl(jmp_pc, 0);

                tcg_gen_exit_tb(0);

                VAR_3->is_jmp = DISAS_JUMP;

                break;

            }

        }

    } while (!VAR_3->is_jmp

             && !tcg_op_buf_full()

             && !cs->singlestep_enabled

             && !singlestep

             && (VAR_3->pc < next_page_start)

             && VAR_4 < VAR_5);



    if (VAR_1->cflags & CF_LAST_IO) {

        gen_io_end();

    }

    if (VAR_3->is_jmp == DISAS_NEXT) {

        VAR_3->is_jmp = DISAS_UPDATE;

        tcg_gen_movi_tl(cpu_pc, VAR_3->pc);

    }

    if (unlikely(cs->singlestep_enabled)) {

        if (VAR_3->is_jmp == DISAS_NEXT) {

            tcg_gen_movi_tl(cpu_pc, VAR_3->pc);

        }

        gen_exception(VAR_3, EXCP_DEBUG);

    } else {

        switch (VAR_3->is_jmp) {

        case DISAS_NEXT:

            gen_goto_tb(VAR_3, 0, VAR_3->pc);

            break;

        default:

        case DISAS_JUMP:

            break;

        case DISAS_UPDATE:

            



            tcg_gen_exit_tb(0);

            break;

        case DISAS_TB_JUMP:

            

            break;

        }

    }



    gen_tb_end(VAR_1, VAR_4);



    VAR_1->size = VAR_3->pc - pc_start;

    VAR_1->icount = VAR_4;



    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)

        && qemu_log_in_addr_range(pc_start)) {

        log_target_disas(cs, pc_start, VAR_1->size, 0);

        qemu_log("\n");

        qemu_log_unlock();

    }

}

void FUNC_0(CPUOpenRISCState *VAR_0, struct TranslationBlock *VAR_1)
{ OpenRISCCPU *cpu = openrisc_env_get_cpu(VAR_0); CPUState *cs = CPU(cpu); struct DisasContext VAR_2, *VAR_3 = &VAR_2; uint32_t pc_start; uint32_t next_page_start; int VAR_4; int VAR_5; pc_start = VAR_1->pc; VAR_3->VAR_1 = VAR_1; VAR_3->is_jmp = DISAS_NEXT; VAR_3->ppc = pc_start; VAR_3->pc = pc_start; VAR_3->flags = cpu->VAR_0.cpucfgr; VAR_3->mem_idx = cpu_mmu_index(&cpu->VAR_0, false); VAR_3->synced_flags = VAR_3->tb_flags = VAR_1->flags; VAR_3->delayed_branch = !!(VAR_3->tb_flags & D_FLAG); VAR_3->singlestep_enabled = cs->singlestep_enabled; next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; VAR_4 = 0; VAR_5 = VAR_1->cflags & CF_COUNT_MASK; if (VAR_5 == 0) { VAR_5 = CF_COUNT_MASK; } if (VAR_5 > TCG_MAX_INSNS) { VAR_5 = TCG_MAX_INSNS; } if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
&& qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); } gen_tb_start(VAR_1); do { tcg_gen_insn_start(VAR_3->pc); VAR_4++; if (unlikely(cpu_breakpoint_test(cs, VAR_3->pc, BP_ANY))) { tcg_gen_movi_tl(cpu_pc, VAR_3->pc); gen_exception(VAR_3, EXCP_DEBUG); VAR_3->is_jmp = DISAS_UPDATE; VAR_3->pc += 4; break; } if (VAR_4 == VAR_5 && (VAR_1->cflags & CF_LAST_IO)) { gen_io_start(); } VAR_3->ppc = VAR_3->pc - 4; VAR_3->npc = VAR_3->pc + 4; tcg_gen_movi_tl(cpu_ppc, VAR_3->ppc); tcg_gen_movi_tl(cpu_npc, VAR_3->npc); disas_openrisc_insn(VAR_3, cpu); VAR_3->pc = VAR_3->npc; if (VAR_3->delayed_branch) { VAR_3->delayed_branch--; if (!VAR_3->delayed_branch) { VAR_3->tb_flags &= ~D_FLAG; gen_sync_flags(VAR_3); tcg_gen_mov_tl(cpu_pc, jmp_pc); tcg_gen_mov_tl(cpu_npc, jmp_pc); tcg_gen_movi_tl(jmp_pc, 0); tcg_gen_exit_tb(0); VAR_3->is_jmp = DISAS_JUMP; break; } } } while (!VAR_3->is_jmp && !tcg_op_buf_full()
&& !cs->singlestep_enabled
&& !singlestep
&& (VAR_3->pc < next_page_start)
&& VAR_4 < VAR_5); if (VAR_1->cflags & CF_LAST_IO) { gen_io_end(); } if (VAR_3->is_jmp == DISAS_NEXT) { VAR_3->is_jmp = DISAS_UPDATE; tcg_gen_movi_tl(cpu_pc, VAR_3->pc); } if (unlikely(cs->singlestep_enabled)) { if (VAR_3->is_jmp == DISAS_NEXT) { tcg_gen_movi_tl(cpu_pc, VAR_3->pc); } gen_exception(VAR_3, EXCP_DEBUG); } else { switch (VAR_3->is_jmp) { case DISAS_NEXT:
gen_goto_tb(VAR_3, 0, VAR_3->pc); break; default:
case DISAS_JUMP:
break; case DISAS_UPDATE:
tcg_gen_exit_tb(0); break; case DISAS_TB_JUMP:
break; } } gen_tb_end(VAR_1, VAR_4); VAR_1->size = VAR_3->pc - pc_start; VAR_1->icount = VAR_4; if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
&& qemu_log_in_addr_range(pc_start)) { log_target_disas(cs, pc_start, VAR_1->size, 0); qemu_log("\n"); qemu_log_unlock(); } }