void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)

{

    MIPSCPU *cpu = mips_env_get_cpu(env);

    uint32_t val, old;

    uint32_t mask = env->CP0_Status_rw_bitmask;



    if (env->insn_flags & ISA_MIPS32R6) {

        if (extract32(env->CP0_Status, CP0St_KSU, 2) == 0x3) {

            mask &= ~(3 << CP0St_KSU);

        }

        mask &= ~(0x00180000 & arg1);

    }



    val = arg1 & mask;

    old = env->CP0_Status;

    env->CP0_Status = (env->CP0_Status & ~mask) | val;

    if (env->CP0_Config3 & (1 << CP0C3_MT)) {

        sync_c0_status(env, env, env->current_tc);

    } else {

        compute_hflags(env);

    }



    if (qemu_loglevel_mask(CPU_LOG_EXEC)) {

        qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",

                old, old & env->CP0_Cause & CP0Ca_IP_mask,

                val, val & env->CP0_Cause & CP0Ca_IP_mask,

                env->CP0_Cause);

        switch (env->hflags & MIPS_HFLAG_KSU) {

        case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;

        case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;

        case MIPS_HFLAG_KM: qemu_log("\n"); break;

        default:

            cpu_abort(CPU(cpu), "Invalid MMU mode!\n");

            break;

        }

    }

}

void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)

{

    MIPSCPU *cpu = mips_env_get_cpu(env);

    uint32_t val, old;

    uint32_t mask = env->CP0_Status_rw_bitmask;



    if (env->insn_flags & ISA_MIPS32R6) {

        if (extract32(env->CP0_Status, CP0St_KSU, 2) == 0x3) {

            mask &= ~(3 << CP0St_KSU);

        }

        mask &= ~(0x00180000 & arg1);

    }



    val = arg1 & mask;

    old = env->CP0_Status;

    env->CP0_Status = (env->CP0_Status & ~mask) | val;

    if (env->CP0_Config3 & (1 << CP0C3_MT)) {

        sync_c0_status(env, env, env->current_tc);

    } else {

        compute_hflags(env);

    }



    if (qemu_loglevel_mask(CPU_LOG_EXEC)) {

        qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",

                old, old & env->CP0_Cause & CP0Ca_IP_mask,

                val, val & env->CP0_Cause & CP0Ca_IP_mask,

                env->CP0_Cause);

        switch (env->hflags & MIPS_HFLAG_KSU) {

        case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;

        case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;

        case MIPS_HFLAG_KM: qemu_log("\n"); break;

        default:

            cpu_abort(CPU(cpu), "Invalid MMU mode!\n");

            break;

        }

    }

}

        if (extract32(env->CP0_Status, CP0St_KSU, 2) == 0x3) {         mask &= ~(0x00180000 & arg1);
void FUNC_0(CPUMIPSState *VAR_0, target_ulong VAR_1)

{

    MIPSCPU *cpu = mips_env_get_cpu(VAR_0);

    uint32_t val, old;

    uint32_t mask = VAR_0->CP0_Status_rw_bitmask;



    if (VAR_0->insn_flags & ISA_MIPS32R6) {

        if (extract32(VAR_0->CP0_Status, CP0St_KSU, 2) == 0x3) {

            mask &= ~(3 << CP0St_KSU);

        }

        mask &= ~(0x00180000 & VAR_1);

    }



    val = VAR_1 & mask;

    old = VAR_0->CP0_Status;

    VAR_0->CP0_Status = (VAR_0->CP0_Status & ~mask) | val;

    if (VAR_0->CP0_Config3 & (1 << CP0C3_MT)) {

        sync_c0_status(VAR_0, VAR_0, VAR_0->current_tc);

    } else {

        compute_hflags(VAR_0);

    }



    if (qemu_loglevel_mask(CPU_LOG_EXEC)) {

        qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",

                old, old & VAR_0->CP0_Cause & CP0Ca_IP_mask,

                val, val & VAR_0->CP0_Cause & CP0Ca_IP_mask,

                VAR_0->CP0_Cause);

        switch (VAR_0->hflags & MIPS_HFLAG_KSU) {

        case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;

        case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;

        case MIPS_HFLAG_KM: qemu_log("\n"); break;

        default:

            cpu_abort(CPU(cpu), "Invalid MMU mode!\n");

            break;

        }

    }

}

void FUNC_0(CPUMIPSState *VAR_0, target_ulong VAR_1)
{ MIPSCPU *cpu = mips_env_get_cpu(VAR_0); uint32_t val, old; uint32_t mask = VAR_0->CP0_Status_rw_bitmask; if (VAR_0->insn_flags & ISA_MIPS32R6) { if (extract32(VAR_0->CP0_Status, CP0St_KSU, 2) == 0x3) { mask &= ~(3 << CP0St_KSU); } mask &= ~(0x00180000 & VAR_1); } val = VAR_1 & mask; old = VAR_0->CP0_Status; VAR_0->CP0_Status = (VAR_0->CP0_Status & ~mask) | val; if (VAR_0->CP0_Config3 & (1 << CP0C3_MT)) { sync_c0_status(VAR_0, VAR_0, VAR_0->current_tc); } else { compute_hflags(VAR_0); } if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
old, old & VAR_0->CP0_Cause & CP0Ca_IP_mask,
val, val & VAR_0->CP0_Cause & CP0Ca_IP_mask,
VAR_0->CP0_Cause); switch (VAR_0->hflags & MIPS_HFLAG_KSU) { case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; default:
cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); break; } } }