static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,

                omap_clk clk)

{

    int iomemtype;



    s->pwl.base = base;

    omap_pwl_reset(s);



    iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,

                    omap_pwl_writefn, s);

    cpu_register_physical_memory(s->pwl.base, 0x800, iomemtype);



    omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);

}

static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,

                omap_clk clk)

{

    int iomemtype;



    s->pwl.base = base;

    omap_pwl_reset(s);



    iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,

                    omap_pwl_writefn, s);

    cpu_register_physical_memory(s->pwl.base, 0x800, iomemtype);



    omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);

}

static void FUNC_0(target_phys_addr_t VAR_0, struct omap_mpu_state_s *VAR_1,

                omap_clk VAR_2)

{

    int VAR_3;



    VAR_1->pwl.VAR_0 = VAR_0;

    omap_pwl_reset(VAR_1);



    VAR_3 = cpu_register_io_memory(0, omap_pwl_readfn,

                    omap_pwl_writefn, VAR_1);

    cpu_register_physical_memory(VAR_1->pwl.VAR_0, 0x800, VAR_3);



    omap_clk_adduser(VAR_2, qemu_allocate_irqs(omap_pwl_clk_update, VAR_1, 1)[0]);

}

static void FUNC_0(target_phys_addr_t VAR_0, struct omap_mpu_state_s *VAR_1,
omap_clk VAR_2)
{ int VAR_3; VAR_1->pwl.VAR_0 = VAR_0; omap_pwl_reset(VAR_1); VAR_3 = cpu_register_io_memory(0, omap_pwl_readfn,
omap_pwl_writefn, VAR_1); cpu_register_physical_memory(VAR_1->pwl.VAR_0, 0x800, VAR_3); omap_clk_adduser(VAR_2, qemu_allocate_irqs(omap_pwl_clk_update, VAR_1, 1)[0]); }