static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)

{

    CG3State *s = opaque;

    int val;



    switch (addr) {

    case CG3_REG_BT458_ADDR:

    case CG3_REG_BT458_COLMAP:

        val = 0;

        break;

    case CG3_REG_FBC_CTRL:

        val = s->regs[0];

        break;

    case CG3_REG_FBC_STATUS:

        /* monitor ID 6, board type = 1 (color) */

        val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR;

        break;

    case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:

        val = s->regs[addr - 0x10];

        break;

    default:

        qemu_log_mask(LOG_UNIMP,

                  "cg3: Unimplemented register read "

                  "reg 0x%" HWADDR_PRIx " size 0x%x\n",

                  addr, size);

        val = 0;

        break;

    }

    DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr);

    return val;

}

static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)

{

    CG3State *s = opaque;

    int val;



    switch (addr) {

    case CG3_REG_BT458_ADDR:

    case CG3_REG_BT458_COLMAP:

        val = 0;

        break;

    case CG3_REG_FBC_CTRL:

        val = s->regs[0];

        break;

    case CG3_REG_FBC_STATUS:

        

        val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR;

        break;

    case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:

        val = s->regs[addr - 0x10];

        break;

    default:

        qemu_log_mask(LOG_UNIMP,

                  "cg3: Unimplemented register read "

                  "reg 0x%" HWADDR_PRIx " size 0x%x\n",

                  addr, size);

        val = 0;

        break;

    }

    DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr);

    return val;

}

    case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:     case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:
static uint64_t FUNC_0(void *opaque, hwaddr addr, unsigned size)

{

    CG3State *s = opaque;

    int VAR_0;



    switch (addr) {

    case CG3_REG_BT458_ADDR:

    case CG3_REG_BT458_COLMAP:

        VAR_0 = 0;

        break;

    case CG3_REG_FBC_CTRL:

        VAR_0 = s->regs[0];

        break;

    case CG3_REG_FBC_STATUS:

        

        VAR_0 = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR;

        break;

    case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:

        VAR_0 = s->regs[addr - 0x10];

        break;

    default:

        qemu_log_mask(LOG_UNIMP,

                  "cg3: Unimplemented register read "

                  "reg 0x%" HWADDR_PRIx " size 0x%x\n",

                  addr, size);

        VAR_0 = 0;

        break;

    }

    DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", VAR_0, addr);

    return VAR_0;

}

static uint64_t FUNC_0(void *opaque, hwaddr addr, unsigned size)
{ CG3State *s = opaque; int VAR_0; switch (addr) { case CG3_REG_BT458_ADDR:
case CG3_REG_BT458_COLMAP:
VAR_0 = 0; break; case CG3_REG_FBC_CTRL:
VAR_0 = s->regs[0]; break; case CG3_REG_FBC_STATUS:
VAR_0 = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR; break; case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:
VAR_0 = s->regs[addr - 0x10]; break; default:
qemu_log_mask(LOG_UNIMP,
"cg3: Unimplemented register read "
"reg 0x%" HWADDR_PRIx " size 0x%x\n",
addr, size); VAR_0 = 0; break; } DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", VAR_0, addr); return VAR_0; }