CharDriverState *uart_hci_init(qemu_irq wakeup)

{

    struct csrhci_s *s = (struct csrhci_s *)

            g_malloc0(sizeof(struct csrhci_s));



    s->chr.opaque = s;

    s->chr.chr_write = csrhci_write;

    s->chr.chr_ioctl = csrhci_ioctl;




    s->hci = qemu_next_hci();

    s->hci->opaque = s;

    s->hci->evt_recv = csrhci_out_hci_packet_event;

    s->hci->acl_recv = csrhci_out_hci_packet_acl;



    s->out_tm = qemu_new_timer_ns(vm_clock, csrhci_out_tick, s);

    s->pins = qemu_allocate_irqs(csrhci_pins, s, __csrhci_pins);

    csrhci_reset(s);



    return &s->chr;

}
CharDriverState *uart_hci_init(qemu_irq wakeup)

{

    struct csrhci_s *s = (struct csrhci_s *)

            g_malloc0(sizeof(struct csrhci_s));



    s->chr.opaque = s;

    s->chr.chr_write = csrhci_write;

    s->chr.chr_ioctl = csrhci_ioctl;




    s->hci = qemu_next_hci();

    s->hci->opaque = s;

    s->hci->evt_recv = csrhci_out_hci_packet_event;

    s->hci->acl_recv = csrhci_out_hci_packet_acl;



    s->out_tm = qemu_new_timer_ns(vm_clock, csrhci_out_tick, s);

    s->pins = qemu_allocate_irqs(csrhci_pins, s, __csrhci_pins);

    csrhci_reset(s);



    return &s->chr;

}
CharDriverState *FUNC_0(qemu_irq wakeup)

{

    struct csrhci_s *VAR_0 = (struct csrhci_s *)

            g_malloc0(sizeof(struct csrhci_s));



    VAR_0->chr.opaque = VAR_0;

    VAR_0->chr.chr_write = csrhci_write;

    VAR_0->chr.chr_ioctl = csrhci_ioctl;




    VAR_0->hci = qemu_next_hci();

    VAR_0->hci->opaque = VAR_0;

    VAR_0->hci->evt_recv = csrhci_out_hci_packet_event;

    VAR_0->hci->acl_recv = csrhci_out_hci_packet_acl;



    VAR_0->out_tm = qemu_new_timer_ns(vm_clock, csrhci_out_tick, VAR_0);

    VAR_0->pins = qemu_allocate_irqs(csrhci_pins, VAR_0, __csrhci_pins);

    csrhci_reset(VAR_0);



    return &VAR_0->chr;

}
CharDriverState *FUNC_0(qemu_irq wakeup)
{ struct csrhci_s *VAR_0 = (struct csrhci_s *)
g_malloc0(sizeof(struct csrhci_s)); VAR_0->chr.opaque = VAR_0; VAR_0->chr.chr_write = csrhci_write; VAR_0->chr.chr_ioctl = csrhci_ioctl; VAR_0->hci = qemu_next_hci(); VAR_0->hci->opaque = VAR_0; VAR_0->hci->evt_recv = csrhci_out_hci_packet_event; VAR_0->hci->acl_recv = csrhci_out_hci_packet_acl; VAR_0->out_tm = qemu_new_timer_ns(vm_clock, csrhci_out_tick, VAR_0); VAR_0->pins = qemu_allocate_irqs(csrhci_pins, VAR_0, __csrhci_pins); csrhci_reset(VAR_0); return &VAR_0->chr; }