static int get_physical_address_code(CPUState *env,

                                     target_phys_addr_t *physical, int *prot,

                                     target_ulong address, int is_user)

{

    target_ulong mask;

    unsigned int i;



    if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */

        *physical = address;

        *prot = PAGE_EXEC;

        return 0;

    }



    for (i = 0; i < 64; i++) {

        switch ((env->itlb_tte[i] >> 61) & 3) {

        default:

        case 0x0: // 8k

            mask = 0xffffffffffffe000ULL;

            break;

        case 0x1: // 64k

            mask = 0xffffffffffff0000ULL;

            break;

        case 0x2: // 512k

            mask = 0xfffffffffff80000ULL;

            break;

        case 0x3: // 4M

            mask = 0xffffffffffc00000ULL;

                break;

        }

        // ctx match, vaddr match, valid?

        if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&

            (address & mask) == (env->itlb_tag[i] & mask) &&

            (env->itlb_tte[i] & 0x8000000000000000ULL)) {

            // access ok?

            if ((env->itlb_tte[i] & 0x4) && is_user) {

                if (env->immuregs[3]) /* Fault status register */

                    env->immuregs[3] = 2; /* overflow (not read before

                                             another fault) */

                env->immuregs[3] |= (is_user << 3) | 1;

                env->exception_index = TT_TFAULT;

#ifdef DEBUG_MMU

                printf("TFAULT at 0x%" PRIx64 "\n", address);

#endif

                return 1;

            }

            *physical = ((env->itlb_tte[i] & mask) | (address & ~mask)) &

                        0x1ffffffe000ULL;

            *prot = PAGE_EXEC;

            return 0;

        }

    }

#ifdef DEBUG_MMU

    printf("TMISS at 0x%" PRIx64 "\n", address);

#endif

    /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */

    env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);

    env->exception_index = TT_TMISS;

    return 1;

}

static int get_physical_address_code(CPUState *env,

                                     target_phys_addr_t *physical, int *prot,

                                     target_ulong address, int is_user)

{

    target_ulong mask;

    unsigned int i;



    if ((env->lsu & IMMU_E) == 0) { 

        *physical = address;

        *prot = PAGE_EXEC;

        return 0;

    }



    for (i = 0; i < 64; i++) {

        switch ((env->itlb_tte[i] >> 61) & 3) {

        default:

        case 0x0: 

            mask = 0xffffffffffffe000ULL;

            break;

        case 0x1: 

            mask = 0xffffffffffff0000ULL;

            break;

        case 0x2: 

            mask = 0xfffffffffff80000ULL;

            break;

        case 0x3: 

            mask = 0xffffffffffc00000ULL;

                break;

        }

        

        if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&

            (address & mask) == (env->itlb_tag[i] & mask) &&

            (env->itlb_tte[i] & 0x8000000000000000ULL)) {

            

            if ((env->itlb_tte[i] & 0x4) && is_user) {

                if (env->immuregs[3]) 

                    env->immuregs[3] = 2; 



                env->immuregs[3] |= (is_user << 3) | 1;

                env->exception_index = TT_TFAULT;

#ifdef DEBUG_MMU

                printf("TFAULT at 0x%" PRIx64 "\n", address);

#endif

                return 1;

            }

            *physical = ((env->itlb_tte[i] & mask) | (address & ~mask)) &

                        0x1ffffffe000ULL;

            *prot = PAGE_EXEC;

            return 0;

        }

    }

#ifdef DEBUG_MMU

    printf("TMISS at 0x%" PRIx64 "\n", address);

#endif

    

    env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);

    env->exception_index = TT_TMISS;

    return 1;

}

static int FUNC_0(CPUState *VAR_0,

                                     target_phys_addr_t *VAR_1, int *VAR_2,

                                     target_ulong VAR_3, int VAR_4)

{

    target_ulong mask;

    unsigned int VAR_5;



    if ((VAR_0->lsu & IMMU_E) == 0) { 

        *VAR_1 = VAR_3;

        *VAR_2 = PAGE_EXEC;

        return 0;

    }



    for (VAR_5 = 0; VAR_5 < 64; VAR_5++) {

        switch ((VAR_0->itlb_tte[VAR_5] >> 61) & 3) {

        default:

        case 0x0: 

            mask = 0xffffffffffffe000ULL;

            break;

        case 0x1: 

            mask = 0xffffffffffff0000ULL;

            break;

        case 0x2: 

            mask = 0xfffffffffff80000ULL;

            break;

        case 0x3: 

            mask = 0xffffffffffc00000ULL;

                break;

        }

        

        if (VAR_0->dmmuregs[1] == (VAR_0->itlb_tag[VAR_5] & 0x1fff) &&

            (VAR_3 & mask) == (VAR_0->itlb_tag[VAR_5] & mask) &&

            (VAR_0->itlb_tte[VAR_5] & 0x8000000000000000ULL)) {

            

            if ((VAR_0->itlb_tte[VAR_5] & 0x4) && VAR_4) {

                if (VAR_0->immuregs[3]) 

                    VAR_0->immuregs[3] = 2; 



                VAR_0->immuregs[3] |= (VAR_4 << 3) | 1;

                VAR_0->exception_index = TT_TFAULT;

#ifdef DEBUG_MMU

                printf("TFAULT at 0x%" PRIx64 "\n", VAR_3);

#endif

                return 1;

            }

            *VAR_1 = ((VAR_0->itlb_tte[VAR_5] & mask) | (VAR_3 & ~mask)) &

                        0x1ffffffe000ULL;

            *VAR_2 = PAGE_EXEC;

            return 0;

        }

    }

#ifdef DEBUG_MMU

    printf("TMISS at 0x%" PRIx64 "\n", VAR_3);

#endif

    

    VAR_0->immuregs[6] = (VAR_3 & ~0x1fffULL) | (VAR_0->dmmuregs[1] & 0x1fff);

    VAR_0->exception_index = TT_TMISS;

    return 1;

}

static int FUNC_0(CPUState *VAR_0,
target_phys_addr_t *VAR_1, int *VAR_2,
target_ulong VAR_3, int VAR_4)
{ target_ulong mask; unsigned int VAR_5; if ((VAR_0->lsu & IMMU_E) == 0) { *VAR_1 = VAR_3; *VAR_2 = PAGE_EXEC; return 0; } for (VAR_5 = 0; VAR_5 < 64; VAR_5++) { switch ((VAR_0->itlb_tte[VAR_5] >> 61) & 3) { default:
case 0x0:
mask = 0xffffffffffffe000ULL; break; case 0x1:
mask = 0xffffffffffff0000ULL; break; case 0x2:
mask = 0xfffffffffff80000ULL; break; case 0x3:
mask = 0xffffffffffc00000ULL; break; } if (VAR_0->dmmuregs[1] == (VAR_0->itlb_tag[VAR_5] & 0x1fff) &&
(VAR_3 & mask) == (VAR_0->itlb_tag[VAR_5] & mask) &&
(VAR_0->itlb_tte[VAR_5] & 0x8000000000000000ULL)) { if ((VAR_0->itlb_tte[VAR_5] & 0x4) && VAR_4) { if (VAR_0->immuregs[3])
VAR_0->immuregs[3] = 2; VAR_0->immuregs[3] |= (VAR_4 << 3) | 1; VAR_0->exception_index = TT_TFAULT; #ifdef DEBUG_MMU
printf("TFAULT at 0x%" PRIx64 "\n", VAR_3); #endif
return 1; } *VAR_1 = ((VAR_0->itlb_tte[VAR_5] & mask) | (VAR_3 & ~mask)) &
0x1ffffffe000ULL; *VAR_2 = PAGE_EXEC; return 0; } } #ifdef DEBUG_MMU
printf("TMISS at 0x%" PRIx64 "\n", VAR_3); #endif
VAR_0->immuregs[6] = (VAR_3 & ~0x1fffULL) | (VAR_0->dmmuregs[1] & 0x1fff); VAR_0->exception_index = TT_TMISS; return 1; }