int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,

                            uint8_t bar_nr)

{

    int ret;

    char *name;



    /*

     * Migration compatibility dictates that this remains a 4k

     * BAR with the vector table in the lower half and PBA in

     * the upper half.  Do not use these elsewhere!

     */

#define MSIX_EXCLUSIVE_BAR_SIZE 4096

#define MSIX_EXCLUSIVE_BAR_TABLE_OFFSET 0

#define MSIX_EXCLUSIVE_BAR_PBA_OFFSET (MSIX_EXCLUSIVE_BAR_SIZE / 2)

#define MSIX_EXCLUSIVE_CAP_OFFSET 0



    if (nentries * PCI_MSIX_ENTRY_SIZE > MSIX_EXCLUSIVE_BAR_PBA_OFFSET) {

        return -EINVAL;

    }



    name = g_strdup_printf("%s-msix", dev->name);

    memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, MSIX_EXCLUSIVE_BAR_SIZE);

    g_free(name);



    ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,

                    MSIX_EXCLUSIVE_BAR_TABLE_OFFSET, &dev->msix_exclusive_bar,

                    bar_nr, MSIX_EXCLUSIVE_BAR_PBA_OFFSET,

                    MSIX_EXCLUSIVE_CAP_OFFSET);

    if (ret) {

        return ret;

    }



    pci_register_bar(dev, bar_nr, PCI_BASE_ADDRESS_SPACE_MEMORY,

                     &dev->msix_exclusive_bar);



    return 0;

}

int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,

                            uint8_t bar_nr)

{

    int ret;

    char *name;



    









#define MSIX_EXCLUSIVE_BAR_SIZE 4096

#define MSIX_EXCLUSIVE_BAR_TABLE_OFFSET 0

#define MSIX_EXCLUSIVE_BAR_PBA_OFFSET (MSIX_EXCLUSIVE_BAR_SIZE / 2)

#define MSIX_EXCLUSIVE_CAP_OFFSET 0



    if (nentries * PCI_MSIX_ENTRY_SIZE > MSIX_EXCLUSIVE_BAR_PBA_OFFSET) {

        return -EINVAL;

    }



    name = g_strdup_printf("%s-msix", dev->name);

    memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, MSIX_EXCLUSIVE_BAR_SIZE);

    g_free(name);



    ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,

                    MSIX_EXCLUSIVE_BAR_TABLE_OFFSET, &dev->msix_exclusive_bar,

                    bar_nr, MSIX_EXCLUSIVE_BAR_PBA_OFFSET,

                    MSIX_EXCLUSIVE_CAP_OFFSET);

    if (ret) {

        return ret;

    }



    pci_register_bar(dev, bar_nr, PCI_BASE_ADDRESS_SPACE_MEMORY,

                     &dev->msix_exclusive_bar);



    return 0;

}

int FUNC_0(PCIDevice *VAR_0, unsigned short VAR_1,

                            uint8_t VAR_2)

{

    int VAR_3;

    char *VAR_4;



    









#define MSIX_EXCLUSIVE_BAR_SIZE 4096

#define MSIX_EXCLUSIVE_BAR_TABLE_OFFSET 0

#define MSIX_EXCLUSIVE_BAR_PBA_OFFSET (MSIX_EXCLUSIVE_BAR_SIZE / 2)

#define MSIX_EXCLUSIVE_CAP_OFFSET 0



    if (VAR_1 * PCI_MSIX_ENTRY_SIZE > MSIX_EXCLUSIVE_BAR_PBA_OFFSET) {

        return -EINVAL;

    }



    VAR_4 = g_strdup_printf("%s-msix", VAR_0->VAR_4);

    memory_region_init(&VAR_0->msix_exclusive_bar, OBJECT(VAR_0), VAR_4, MSIX_EXCLUSIVE_BAR_SIZE);

    g_free(VAR_4);



    VAR_3 = msix_init(VAR_0, VAR_1, &VAR_0->msix_exclusive_bar, VAR_2,

                    MSIX_EXCLUSIVE_BAR_TABLE_OFFSET, &VAR_0->msix_exclusive_bar,

                    VAR_2, MSIX_EXCLUSIVE_BAR_PBA_OFFSET,

                    MSIX_EXCLUSIVE_CAP_OFFSET);

    if (VAR_3) {

        return VAR_3;

    }



    pci_register_bar(VAR_0, VAR_2, PCI_BASE_ADDRESS_SPACE_MEMORY,

                     &VAR_0->msix_exclusive_bar);



    return 0;

}

int FUNC_0(PCIDevice *VAR_0, unsigned short VAR_1,
uint8_t VAR_2)
{ int VAR_3; char *VAR_4; #define MSIX_EXCLUSIVE_BAR_SIZE 4096
#define MSIX_EXCLUSIVE_BAR_TABLE_OFFSET 0
#define MSIX_EXCLUSIVE_BAR_PBA_OFFSET (MSIX_EXCLUSIVE_BAR_SIZE / 2)
#define MSIX_EXCLUSIVE_CAP_OFFSET 0
if (VAR_1 * PCI_MSIX_ENTRY_SIZE > MSIX_EXCLUSIVE_BAR_PBA_OFFSET) { return -EINVAL; } VAR_4 = g_strdup_printf("%s-msix", VAR_0->VAR_4); memory_region_init(&VAR_0->msix_exclusive_bar, OBJECT(VAR_0), VAR_4, MSIX_EXCLUSIVE_BAR_SIZE); g_free(VAR_4); VAR_3 = msix_init(VAR_0, VAR_1, &VAR_0->msix_exclusive_bar, VAR_2,
MSIX_EXCLUSIVE_BAR_TABLE_OFFSET, &VAR_0->msix_exclusive_bar,
VAR_2, MSIX_EXCLUSIVE_BAR_PBA_OFFSET,
MSIX_EXCLUSIVE_CAP_OFFSET); if (VAR_3) { return VAR_3; } pci_register_bar(VAR_0, VAR_2, PCI_BASE_ADDRESS_SPACE_MEMORY,
&VAR_0->msix_exclusive_bar); return 0; }