static int vscsi_send_iu(VSCSIState *s, vscsi_req *req,

                         uint64_t length, uint8_t format)

{

    long rc, rc1;



    /* First copy the SRP */

    rc = spapr_vio_dma_write(&s->vdev, req->crq.s.IU_data_ptr,

                             &req->iu, length);

    if (rc) {

        fprintf(stderr, "vscsi_send_iu: DMA write failure !\n");

    }



    req->crq.s.valid = 0x80;

    req->crq.s.format = format;

    req->crq.s.reserved = 0x00;

    req->crq.s.timeout = cpu_to_be16(0x0000);

    req->crq.s.IU_length = cpu_to_be16(length);

    req->crq.s.IU_data_ptr = req->iu.srp.rsp.tag; /* right byte order */



    if (rc == 0) {

        req->crq.s.status = 0x99; /* Just needs to be non-zero */

    } else {

        req->crq.s.status = 0x00;

    }



    rc1 = spapr_vio_send_crq(&s->vdev, req->crq.raw);

    if (rc1) {

        fprintf(stderr, "vscsi_send_iu: Error sending response\n");

        return rc1;

    }



    return rc;

}

static int vscsi_send_iu(VSCSIState *s, vscsi_req *req,

                         uint64_t length, uint8_t format)

{

    long rc, rc1;



    

    rc = spapr_vio_dma_write(&s->vdev, req->crq.s.IU_data_ptr,

                             &req->iu, length);

    if (rc) {

        fprintf(stderr, "vscsi_send_iu: DMA write failure !\n");

    }



    req->crq.s.valid = 0x80;

    req->crq.s.format = format;

    req->crq.s.reserved = 0x00;

    req->crq.s.timeout = cpu_to_be16(0x0000);

    req->crq.s.IU_length = cpu_to_be16(length);

    req->crq.s.IU_data_ptr = req->iu.srp.rsp.tag; 



    if (rc == 0) {

        req->crq.s.status = 0x99; 

    } else {

        req->crq.s.status = 0x00;

    }



    rc1 = spapr_vio_send_crq(&s->vdev, req->crq.raw);

    if (rc1) {

        fprintf(stderr, "vscsi_send_iu: Error sending response\n");

        return rc1;

    }



    return rc;

}

        req->crq.s.status = 0x00;
static int FUNC_0(VSCSIState *VAR_0, vscsi_req *VAR_1,

                         uint64_t VAR_2, uint8_t VAR_3)

{

    long VAR_4, VAR_5;



    

    VAR_4 = spapr_vio_dma_write(&VAR_0->vdev, VAR_1->crq.VAR_0.IU_data_ptr,

                             &VAR_1->iu, VAR_2);

    if (VAR_4) {

        fprintf(stderr, "FUNC_0: DMA write failure !\n");

    }



    VAR_1->crq.VAR_0.valid = 0x80;

    VAR_1->crq.VAR_0.VAR_3 = VAR_3;

    VAR_1->crq.VAR_0.reserved = 0x00;

    VAR_1->crq.VAR_0.timeout = cpu_to_be16(0x0000);

    VAR_1->crq.VAR_0.IU_length = cpu_to_be16(VAR_2);

    VAR_1->crq.VAR_0.IU_data_ptr = VAR_1->iu.srp.rsp.tag; 



    if (VAR_4 == 0) {

        VAR_1->crq.VAR_0.status = 0x99; 

    } else {

        VAR_1->crq.VAR_0.status = 0x00;

    }



    VAR_5 = spapr_vio_send_crq(&VAR_0->vdev, VAR_1->crq.raw);

    if (VAR_5) {

        fprintf(stderr, "FUNC_0: Error sending response\n");

        return VAR_5;

    }



    return VAR_4;

}

static int FUNC_0(VSCSIState *VAR_0, vscsi_req *VAR_1,
uint64_t VAR_2, uint8_t VAR_3)
{ long VAR_4, VAR_5; VAR_4 = spapr_vio_dma_write(&VAR_0->vdev, VAR_1->crq.VAR_0.IU_data_ptr,
&VAR_1->iu, VAR_2); if (VAR_4) { fprintf(stderr, "FUNC_0: DMA write failure !\n"); } VAR_1->crq.VAR_0.valid = 0x80; VAR_1->crq.VAR_0.VAR_3 = VAR_3; VAR_1->crq.VAR_0.reserved = 0x00; VAR_1->crq.VAR_0.timeout = cpu_to_be16(0x0000); VAR_1->crq.VAR_0.IU_length = cpu_to_be16(VAR_2); VAR_1->crq.VAR_0.IU_data_ptr = VAR_1->iu.srp.rsp.tag; if (VAR_4 == 0) { VAR_1->crq.VAR_0.status = 0x99; } else { VAR_1->crq.VAR_0.status = 0x00; } VAR_5 = spapr_vio_send_crq(&VAR_0->vdev, VAR_1->crq.raw); if (VAR_5) { fprintf(stderr, "FUNC_0: Error sending response\n"); return VAR_5; } return VAR_4; }