static void virtio_pci_modern_regions_init(VirtIOPCIProxy *proxy)

{

    static const MemoryRegionOps common_ops = {

        .read = virtio_pci_common_read,

        .write = virtio_pci_common_write,

        .impl = {

            .min_access_size = 1,

            .max_access_size = 4,

        },

        .endianness = DEVICE_LITTLE_ENDIAN,

    };

    static const MemoryRegionOps isr_ops = {

        .read = virtio_pci_isr_read,

        .write = virtio_pci_isr_write,

        .impl = {

            .min_access_size = 1,

            .max_access_size = 4,

        },

        .endianness = DEVICE_LITTLE_ENDIAN,

    };

    static const MemoryRegionOps device_ops = {

        .read = virtio_pci_device_read,

        .write = virtio_pci_device_write,

        .impl = {

            .min_access_size = 1,

            .max_access_size = 4,

        },

        .endianness = DEVICE_LITTLE_ENDIAN,

    };

    static const MemoryRegionOps notify_ops = {

        .read = virtio_pci_notify_read,

        .write = virtio_pci_notify_write,

        .impl = {

            .min_access_size = 1,

            .max_access_size = 4,

        },

        .endianness = DEVICE_LITTLE_ENDIAN,

    };



    memory_region_init_io(&proxy->common.mr, OBJECT(proxy),

                          &common_ops,

                          proxy,

                          "virtio-pci-common", 0x1000);

    proxy->common.offset = 0x0;

    proxy->common.type = VIRTIO_PCI_CAP_COMMON_CFG;



    memory_region_init_io(&proxy->isr.mr, OBJECT(proxy),

                          &isr_ops,

                          proxy,

                          "virtio-pci-isr", 0x1000);

    proxy->isr.offset = 0x1000;

    proxy->isr.type = VIRTIO_PCI_CAP_ISR_CFG;



    memory_region_init_io(&proxy->device.mr, OBJECT(proxy),

                          &device_ops,

                          virtio_bus_get_device(&proxy->bus),

                          "virtio-pci-device", 0x1000);

    proxy->device.offset = 0x2000;

    proxy->device.type = VIRTIO_PCI_CAP_DEVICE_CFG;



    memory_region_init_io(&proxy->notify.mr, OBJECT(proxy),

                          &notify_ops,

                          virtio_bus_get_device(&proxy->bus),

                          "virtio-pci-notify",

                          QEMU_VIRTIO_PCI_QUEUE_MEM_MULT *

                          VIRTIO_QUEUE_MAX);

    proxy->notify.offset = 0x3000;

    proxy->notify.type = VIRTIO_PCI_CAP_NOTIFY_CFG;

}

static void virtio_pci_modern_regions_init(VirtIOPCIProxy *proxy)

{

    static const MemoryRegionOps common_ops = {

        .read = virtio_pci_common_read,

        .write = virtio_pci_common_write,

        .impl = {

            .min_access_size = 1,

            .max_access_size = 4,

        },

        .endianness = DEVICE_LITTLE_ENDIAN,

    };

    static const MemoryRegionOps isr_ops = {

        .read = virtio_pci_isr_read,

        .write = virtio_pci_isr_write,

        .impl = {

            .min_access_size = 1,

            .max_access_size = 4,

        },

        .endianness = DEVICE_LITTLE_ENDIAN,

    };

    static const MemoryRegionOps device_ops = {

        .read = virtio_pci_device_read,

        .write = virtio_pci_device_write,

        .impl = {

            .min_access_size = 1,

            .max_access_size = 4,

        },

        .endianness = DEVICE_LITTLE_ENDIAN,

    };

    static const MemoryRegionOps notify_ops = {

        .read = virtio_pci_notify_read,

        .write = virtio_pci_notify_write,

        .impl = {

            .min_access_size = 1,

            .max_access_size = 4,

        },

        .endianness = DEVICE_LITTLE_ENDIAN,

    };



    memory_region_init_io(&proxy->common.mr, OBJECT(proxy),

                          &common_ops,

                          proxy,

                          "virtio-pci-common", 0x1000);

    proxy->common.offset = 0x0;

    proxy->common.type = VIRTIO_PCI_CAP_COMMON_CFG;



    memory_region_init_io(&proxy->isr.mr, OBJECT(proxy),

                          &isr_ops,

                          proxy,

                          "virtio-pci-isr", 0x1000);

    proxy->isr.offset = 0x1000;

    proxy->isr.type = VIRTIO_PCI_CAP_ISR_CFG;



    memory_region_init_io(&proxy->device.mr, OBJECT(proxy),

                          &device_ops,

                          virtio_bus_get_device(&proxy->bus),

                          "virtio-pci-device", 0x1000);

    proxy->device.offset = 0x2000;

    proxy->device.type = VIRTIO_PCI_CAP_DEVICE_CFG;



    memory_region_init_io(&proxy->notify.mr, OBJECT(proxy),

                          &notify_ops,

                          virtio_bus_get_device(&proxy->bus),

                          "virtio-pci-notify",

                          QEMU_VIRTIO_PCI_QUEUE_MEM_MULT *

                          VIRTIO_QUEUE_MAX);

    proxy->notify.offset = 0x3000;

    proxy->notify.type = VIRTIO_PCI_CAP_NOTIFY_CFG;

}

static void FUNC_0(VirtIOPCIProxy *VAR_0)

{

    static const MemoryRegionOps VAR_1 = {

        .read = virtio_pci_common_read,

        .write = virtio_pci_common_write,

        .impl = {

            .min_access_size = 1,

            .max_access_size = 4,

        },

        .endianness = DEVICE_LITTLE_ENDIAN,

    };

    static const MemoryRegionOps VAR_2 = {

        .read = virtio_pci_isr_read,

        .write = virtio_pci_isr_write,

        .impl = {

            .min_access_size = 1,

            .max_access_size = 4,

        },

        .endianness = DEVICE_LITTLE_ENDIAN,

    };

    static const MemoryRegionOps VAR_3 = {

        .read = virtio_pci_device_read,

        .write = virtio_pci_device_write,

        .impl = {

            .min_access_size = 1,

            .max_access_size = 4,

        },

        .endianness = DEVICE_LITTLE_ENDIAN,

    };

    static const MemoryRegionOps VAR_4 = {

        .read = virtio_pci_notify_read,

        .write = virtio_pci_notify_write,

        .impl = {

            .min_access_size = 1,

            .max_access_size = 4,

        },

        .endianness = DEVICE_LITTLE_ENDIAN,

    };



    memory_region_init_io(&VAR_0->common.mr, OBJECT(VAR_0),

                          &VAR_1,

                          VAR_0,

                          "virtio-pci-common", 0x1000);

    VAR_0->common.offset = 0x0;

    VAR_0->common.type = VIRTIO_PCI_CAP_COMMON_CFG;



    memory_region_init_io(&VAR_0->isr.mr, OBJECT(VAR_0),

                          &VAR_2,

                          VAR_0,

                          "virtio-pci-isr", 0x1000);

    VAR_0->isr.offset = 0x1000;

    VAR_0->isr.type = VIRTIO_PCI_CAP_ISR_CFG;



    memory_region_init_io(&VAR_0->device.mr, OBJECT(VAR_0),

                          &VAR_3,

                          virtio_bus_get_device(&VAR_0->bus),

                          "virtio-pci-device", 0x1000);

    VAR_0->device.offset = 0x2000;

    VAR_0->device.type = VIRTIO_PCI_CAP_DEVICE_CFG;



    memory_region_init_io(&VAR_0->notify.mr, OBJECT(VAR_0),

                          &VAR_4,

                          virtio_bus_get_device(&VAR_0->bus),

                          "virtio-pci-notify",

                          QEMU_VIRTIO_PCI_QUEUE_MEM_MULT *

                          VIRTIO_QUEUE_MAX);

    VAR_0->notify.offset = 0x3000;

    VAR_0->notify.type = VIRTIO_PCI_CAP_NOTIFY_CFG;

}

static void FUNC_0(VirtIOPCIProxy *VAR_0)
{ static const MemoryRegionOps VAR_1 = { .read = virtio_pci_common_read,
.write = virtio_pci_common_write,
.impl = { .min_access_size = 1,
.max_access_size = 4,
}, .endianness = DEVICE_LITTLE_ENDIAN,
}; static const MemoryRegionOps VAR_2 = { .read = virtio_pci_isr_read,
.write = virtio_pci_isr_write,
.impl = { .min_access_size = 1,
.max_access_size = 4,
}, .endianness = DEVICE_LITTLE_ENDIAN,
}; static const MemoryRegionOps VAR_3 = { .read = virtio_pci_device_read,
.write = virtio_pci_device_write,
.impl = { .min_access_size = 1,
.max_access_size = 4,
}, .endianness = DEVICE_LITTLE_ENDIAN,
}; static const MemoryRegionOps VAR_4 = { .read = virtio_pci_notify_read,
.write = virtio_pci_notify_write,
.impl = { .min_access_size = 1,
.max_access_size = 4,
}, .endianness = DEVICE_LITTLE_ENDIAN,
}; memory_region_init_io(&VAR_0->common.mr, OBJECT(VAR_0),
&VAR_1,
VAR_0,
"virtio-pci-common", 0x1000); VAR_0->common.offset = 0x0; VAR_0->common.type = VIRTIO_PCI_CAP_COMMON_CFG; memory_region_init_io(&VAR_0->isr.mr, OBJECT(VAR_0),
&VAR_2,
VAR_0,
"virtio-pci-isr", 0x1000); VAR_0->isr.offset = 0x1000; VAR_0->isr.type = VIRTIO_PCI_CAP_ISR_CFG; memory_region_init_io(&VAR_0->device.mr, OBJECT(VAR_0),
&VAR_3,
virtio_bus_get_device(&VAR_0->bus),
"virtio-pci-device", 0x1000); VAR_0->device.offset = 0x2000; VAR_0->device.type = VIRTIO_PCI_CAP_DEVICE_CFG; memory_region_init_io(&VAR_0->notify.mr, OBJECT(VAR_0),
&VAR_4,
virtio_bus_get_device(&VAR_0->bus),
"virtio-pci-notify",
QEMU_VIRTIO_PCI_QUEUE_MEM_MULT *
VIRTIO_QUEUE_MAX); VAR_0->notify.offset = 0x3000; VAR_0->notify.type = VIRTIO_PCI_CAP_NOTIFY_CFG; }