void pci_register_bar(PCIDevice *pci_dev, int region_num,

                            pcibus_t size, int type,

                            PCIMapIORegionFunc *map_func)

{

    PCIIORegion *r;

    uint32_t addr;

    uint64_t wmask;



    if ((unsigned int)region_num >= PCI_NUM_REGIONS)

        return;



    if (size & (size-1)) {

        fprintf(stderr, "ERROR: PCI region size must be pow2 "

                    "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);

        exit(1);

    }



    r = &pci_dev->io_regions[region_num];

    r->addr = PCI_BAR_UNMAPPED;

    r->size = size;

    r->filtered_size = size;

    r->type = type;

    r->map_func = map_func;



    wmask = ~(size - 1);

    addr = pci_bar(pci_dev, region_num);

    if (region_num == PCI_ROM_SLOT) {

        /* ROM enable bit is writeable */

        wmask |= PCI_ROM_ADDRESS_ENABLE;

    }

    pci_set_long(pci_dev->config + addr, type);

    if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&

        r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {

        pci_set_quad(pci_dev->wmask + addr, wmask);

        pci_set_quad(pci_dev->cmask + addr, ~0ULL);

    } else {

        pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);

        pci_set_long(pci_dev->cmask + addr, 0xffffffff);

    }

}

void pci_register_bar(PCIDevice *pci_dev, int region_num,

                            pcibus_t size, int type,

                            PCIMapIORegionFunc *map_func)

{

    PCIIORegion *r;

    uint32_t addr;

    uint64_t wmask;



    if ((unsigned int)region_num >= PCI_NUM_REGIONS)

        return;



    if (size & (size-1)) {

        fprintf(stderr, "ERROR: PCI region size must be pow2 "

                    "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);

        exit(1);

    }



    r = &pci_dev->io_regions[region_num];

    r->addr = PCI_BAR_UNMAPPED;

    r->size = size;

    r->filtered_size = size;

    r->type = type;

    r->map_func = map_func;



    wmask = ~(size - 1);

    addr = pci_bar(pci_dev, region_num);

    if (region_num == PCI_ROM_SLOT) {

        

        wmask |= PCI_ROM_ADDRESS_ENABLE;

    }

    pci_set_long(pci_dev->config + addr, type);

    if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&

        r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {

        pci_set_quad(pci_dev->wmask + addr, wmask);

        pci_set_quad(pci_dev->cmask + addr, ~0ULL);

    } else {

        pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);

        pci_set_long(pci_dev->cmask + addr, 0xffffffff);

    }

}

void FUNC_0(PCIDevice *VAR_0, int VAR_1,

                            pcibus_t VAR_2, int VAR_3,

                            PCIMapIORegionFunc *VAR_4)

{

    PCIIORegion *r;

    uint32_t addr;

    uint64_t wmask;



    if ((unsigned int)VAR_1 >= PCI_NUM_REGIONS)

        return;



    if (VAR_2 & (VAR_2-1)) {

        fprintf(stderr, "ERROR: PCI region VAR_2 must be pow2 "

                    "VAR_3=0x%x, VAR_2=0x%"FMT_PCIBUS"\n", VAR_3, VAR_2);

        exit(1);

    }



    r = &VAR_0->io_regions[VAR_1];

    r->addr = PCI_BAR_UNMAPPED;

    r->VAR_2 = VAR_2;

    r->filtered_size = VAR_2;

    r->VAR_3 = VAR_3;

    r->VAR_4 = VAR_4;



    wmask = ~(VAR_2 - 1);

    addr = pci_bar(VAR_0, VAR_1);

    if (VAR_1 == PCI_ROM_SLOT) {

        

        wmask |= PCI_ROM_ADDRESS_ENABLE;

    }

    pci_set_long(VAR_0->config + addr, VAR_3);

    if (!(r->VAR_3 & PCI_BASE_ADDRESS_SPACE_IO) &&

        r->VAR_3 & PCI_BASE_ADDRESS_MEM_TYPE_64) {

        pci_set_quad(VAR_0->wmask + addr, wmask);

        pci_set_quad(VAR_0->cmask + addr, ~0ULL);

    } else {

        pci_set_long(VAR_0->wmask + addr, wmask & 0xffffffff);

        pci_set_long(VAR_0->cmask + addr, 0xffffffff);

    }

}

void FUNC_0(PCIDevice *VAR_0, int VAR_1,
pcibus_t VAR_2, int VAR_3,
PCIMapIORegionFunc *VAR_4)
{ PCIIORegion *r; uint32_t addr; uint64_t wmask; if ((unsigned int)VAR_1 >= PCI_NUM_REGIONS)
return; if (VAR_2 & (VAR_2-1)) { fprintf(stderr, "ERROR: PCI region VAR_2 must be pow2 "
"VAR_3=0x%x, VAR_2=0x%"FMT_PCIBUS"\n", VAR_3, VAR_2); exit(1); } r = &VAR_0->io_regions[VAR_1]; r->addr = PCI_BAR_UNMAPPED; r->VAR_2 = VAR_2; r->filtered_size = VAR_2; r->VAR_3 = VAR_3; r->VAR_4 = VAR_4; wmask = ~(VAR_2 - 1); addr = pci_bar(VAR_0, VAR_1); if (VAR_1 == PCI_ROM_SLOT) { wmask |= PCI_ROM_ADDRESS_ENABLE; } pci_set_long(VAR_0->config + addr, VAR_3); if (!(r->VAR_3 & PCI_BASE_ADDRESS_SPACE_IO) &&
r->VAR_3 & PCI_BASE_ADDRESS_MEM_TYPE_64) { pci_set_quad(VAR_0->wmask + addr, wmask); pci_set_quad(VAR_0->cmask + addr, ~0ULL); } else { pci_set_long(VAR_0->wmask + addr, wmask & 0xffffffff); pci_set_long(VAR_0->cmask + addr, 0xffffffff); } }