grlib_apbuart_writel(void *opaque, target_phys_addr_t addr, uint32_t value)

{

    UART          *uart = opaque;

    unsigned char  c    = 0;



    addr &= 0xff;



    /* Unit registers */

    switch (addr) {

    case DATA_OFFSET:

        c = value & 0xFF;

        qemu_chr_write(uart->chr, &c, 1);

        return;



    case STATUS_OFFSET:

        /* Read Only */

        return;



    case CONTROL_OFFSET:

        /* Not supported */

        return;



    case SCALER_OFFSET:

        /* Not supported */

        return;



    default:

        break;

    }



    trace_grlib_apbuart_unknown_register("write", addr);

}

grlib_apbuart_writel(void *opaque, target_phys_addr_t addr, uint32_t value)

{

    UART          *uart = opaque;

    unsigned char  c    = 0;



    addr &= 0xff;



    

    switch (addr) {

    case DATA_OFFSET:

        c = value & 0xFF;

        qemu_chr_write(uart->chr, &c, 1);

        return;



    case STATUS_OFFSET:

        

        return;



    case CONTROL_OFFSET:

        

        return;



    case SCALER_OFFSET:

        

        return;



    default:

        break;

    }



    trace_grlib_apbuart_unknown_register("write", addr);

}

    trace_grlib_apbuart_unknown_register("write", addr);
FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint32_t VAR_2)

{

    UART          *uart = VAR_0;

    unsigned char  VAR_3    = 0;



    VAR_1 &= 0xff;



    

    switch (VAR_1) {

    case DATA_OFFSET:

        VAR_3 = VAR_2 & 0xFF;

        qemu_chr_write(uart->chr, &VAR_3, 1);

        return;



    case STATUS_OFFSET:

        

        return;



    case CONTROL_OFFSET:

        

        return;



    case SCALER_OFFSET:

        

        return;



    default:

        break;

    }



    trace_grlib_apbuart_unknown_register("write", VAR_1);

}

FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint32_t VAR_2)
{ UART          *uart = VAR_0; unsigned char  VAR_3    = 0; VAR_1 &= 0xff; switch (VAR_1) { case DATA_OFFSET:
VAR_3 = VAR_2 & 0xFF; qemu_chr_write(uart->chr, &VAR_3, 1); return; case STATUS_OFFSET:
return; case CONTROL_OFFSET:
return; case SCALER_OFFSET:
return; default:
break; } trace_grlib_apbuart_unknown_register("write", VAR_1); }