static void write_cont (void *opaque, uint32_t nport, uint32_t data)

{

    struct dma_cont *d = opaque;

    int iport, ichan;



    iport = (nport >> d->dshift) & 0x0f;

    switch (iport) {

    case 8:                     /* command */

        if (data && (data | CMD_NOT_SUPPORTED)) {

            log ("command %#x not supported\n", data);

            goto error;

        }

        d->command = data;

        break;



    case 9:

        ichan = data & 3;

        if (data & 4) {

            d->status |= 1 << (ichan + 4);

        }

        else {

            d->status &= ~(1 << (ichan + 4));

        }

        d->status &= ~(1 << ichan);

        break;



    case 0xa:                   /* single mask */

        if (data & 4)

            d->mask |= 1 << (data & 3);

        else

            d->mask &= ~(1 << (data & 3));

        break;



    case 0xb:                   /* mode */

        {

            ichan = data & 3;

#ifdef DEBUG_DMA

            int op;

            int ai;

            int dir;

            int opmode;



            op = (data >> 2) & 3;

            ai = (data >> 4) & 1;

            dir = (data >> 5) & 1;

            opmode = (data >> 6) & 3;



            linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",

                   ichan, op, ai, dir, opmode);

#endif



            d->regs[ichan].mode = data;

            break;

        }



    case 0xc:                   /* clear flip flop */

        d->flip_flop = 0;

        break;



    case 0xd:                   /* reset */

        d->flip_flop = 0;

        d->mask = ~0;

        d->status = 0;

        d->command = 0;

        break;



    case 0xe:                   /* clear mask for all channels */

        d->mask = 0;

        break;



    case 0xf:                   /* write mask for all channels */

        d->mask = data;

        break;



    default:

        log ("dma: unknown iport %#x\n", iport);

        goto error;

    }



#ifdef DEBUG_DMA

    if (0xc != iport) {

        linfo ("nport %#06x, ichan % 2d, val %#06x\n",

               nport, ichan, data);

    }

#endif

    return;



 error:

    abort ();

}

static void write_cont (void *opaque, uint32_t nport, uint32_t data)

{

    struct dma_cont *d = opaque;

    int iport, ichan;



    iport = (nport >> d->dshift) & 0x0f;

    switch (iport) {

    case 8:                     

        if (data && (data | CMD_NOT_SUPPORTED)) {

            log ("command %#x not supported\n", data);

            goto error;

        }

        d->command = data;

        break;



    case 9:

        ichan = data & 3;

        if (data & 4) {

            d->status |= 1 << (ichan + 4);

        }

        else {

            d->status &= ~(1 << (ichan + 4));

        }

        d->status &= ~(1 << ichan);

        break;



    case 0xa:                   

        if (data & 4)

            d->mask |= 1 << (data & 3);

        else

            d->mask &= ~(1 << (data & 3));

        break;



    case 0xb:                   

        {

            ichan = data & 3;

#ifdef DEBUG_DMA

            int op;

            int ai;

            int dir;

            int opmode;



            op = (data >> 2) & 3;

            ai = (data >> 4) & 1;

            dir = (data >> 5) & 1;

            opmode = (data >> 6) & 3;



            linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",

                   ichan, op, ai, dir, opmode);

#endif



            d->regs[ichan].mode = data;

            break;

        }



    case 0xc:                   

        d->flip_flop = 0;

        break;



    case 0xd:                   

        d->flip_flop = 0;

        d->mask = ~0;

        d->status = 0;

        d->command = 0;

        break;



    case 0xe:                   

        d->mask = 0;

        break;



    case 0xf:                   

        d->mask = data;

        break;



    default:

        log ("dma: unknown iport %#x\n", iport);

        goto error;

    }



#ifdef DEBUG_DMA

    if (0xc != iport) {

        linfo ("nport %#06x, ichan % 2d, val %#06x\n",

               nport, ichan, data);

    }

#endif

    return;



 error:

    abort ();

}

static void FUNC_0 (void *VAR_0, uint32_t VAR_1, uint32_t VAR_2)

{

    struct dma_cont *VAR_3 = VAR_0;

    int VAR_4, VAR_5;



    VAR_4 = (VAR_1 >> VAR_3->dshift) & 0x0f;

    switch (VAR_4) {

    case 8:                     

        if (VAR_2 && (VAR_2 | CMD_NOT_SUPPORTED)) {

            log ("command %#x not supported\n", VAR_2);

            goto error;

        }

        VAR_3->command = VAR_2;

        break;



    case 9:

        VAR_5 = VAR_2 & 3;

        if (VAR_2 & 4) {

            VAR_3->status |= 1 << (VAR_5 + 4);

        }

        else {

            VAR_3->status &= ~(1 << (VAR_5 + 4));

        }

        VAR_3->status &= ~(1 << VAR_5);

        break;



    case 0xa:                   

        if (VAR_2 & 4)

            VAR_3->mask |= 1 << (VAR_2 & 3);

        else

            VAR_3->mask &= ~(1 << (VAR_2 & 3));

        break;



    case 0xb:                   

        {

            VAR_5 = VAR_2 & 3;

#ifdef DEBUG_DMA

            int op;

            int ai;

            int dir;

            int opmode;



            op = (VAR_2 >> 2) & 3;

            ai = (VAR_2 >> 4) & 1;

            dir = (VAR_2 >> 5) & 1;

            opmode = (VAR_2 >> 6) & 3;



            linfo ("VAR_5 %VAR_3, op %VAR_3, ai %VAR_3, dir %VAR_3, opmode %VAR_3\n",

                   VAR_5, op, ai, dir, opmode);

#endif



            VAR_3->regs[VAR_5].mode = VAR_2;

            break;

        }



    case 0xc:                   

        VAR_3->flip_flop = 0;

        break;



    case 0xd:                   

        VAR_3->flip_flop = 0;

        VAR_3->mask = ~0;

        VAR_3->status = 0;

        VAR_3->command = 0;

        break;



    case 0xe:                   

        VAR_3->mask = 0;

        break;



    case 0xf:                   

        VAR_3->mask = VAR_2;

        break;



    default:

        log ("dma: unknown VAR_4 %#x\n", VAR_4);

        goto error;

    }



#ifdef DEBUG_DMA

    if (0xc != VAR_4) {

        linfo ("VAR_1 %#06x, VAR_5 % 2d, val %#06x\n",

               VAR_1, VAR_5, VAR_2);

    }

#endif

    return;



 error:

    abort ();

}

static void FUNC_0 (void *VAR_0, uint32_t VAR_1, uint32_t VAR_2)
{ struct dma_cont *VAR_3 = VAR_0; int VAR_4, VAR_5; VAR_4 = (VAR_1 >> VAR_3->dshift) & 0x0f; switch (VAR_4) { case 8:
if (VAR_2 && (VAR_2 | CMD_NOT_SUPPORTED)) { log ("command %#x not supported\n", VAR_2); goto error; } VAR_3->command = VAR_2; break; case 9:
VAR_5 = VAR_2 & 3; if (VAR_2 & 4) { VAR_3->status |= 1 << (VAR_5 + 4); } else { VAR_3->status &= ~(1 << (VAR_5 + 4)); } VAR_3->status &= ~(1 << VAR_5); break; case 0xa:
if (VAR_2 & 4)
VAR_3->mask |= 1 << (VAR_2 & 3); else
VAR_3->mask &= ~(1 << (VAR_2 & 3)); break; case 0xb:
{ VAR_5 = VAR_2 & 3; #ifdef DEBUG_DMA
int op; int ai; int dir; int opmode; op = (VAR_2 >> 2) & 3; ai = (VAR_2 >> 4) & 1; dir = (VAR_2 >> 5) & 1; opmode = (VAR_2 >> 6) & 3; linfo ("VAR_5 %VAR_3, op %VAR_3, ai %VAR_3, dir %VAR_3, opmode %VAR_3\n",
VAR_5, op, ai, dir, opmode); #endif
VAR_3->regs[VAR_5].mode = VAR_2; break; } case 0xc:
VAR_3->flip_flop = 0; break; case 0xd:
VAR_3->flip_flop = 0; VAR_3->mask = ~0; VAR_3->status = 0; VAR_3->command = 0; break; case 0xe:
VAR_3->mask = 0; break; case 0xf:
VAR_3->mask = VAR_2; break; default:
log ("dma: unknown VAR_4 %#x\n", VAR_4); goto error; } #ifdef DEBUG_DMA
if (0xc != VAR_4) { linfo ("VAR_1 %#06x, VAR_5 % 2d, val %#06x\n",
VAR_1, VAR_5, VAR_2); } #endif
return; error:
abort (); }