static int fdctrl_init_common(FDCtrl *fdctrl)

{

    int i, j;

    static int command_tables_inited = 0;



    /* Fill 'command_to_handler' lookup table */

    if (!command_tables_inited) {

        command_tables_inited = 1;

        for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {

            for (j = 0; j < sizeof(command_to_handler); j++) {

                if ((j & handlers[i].mask) == handlers[i].value) {

                    command_to_handler[j] = i;

                }

            }

        }

    }



    FLOPPY_DPRINTF("init controller\n");

    fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);

    fdctrl->fifo_size = 512;

    fdctrl->result_timer = qemu_new_timer(vm_clock,

                                          fdctrl_result_timer, fdctrl);



    fdctrl->version = 0x90; /* Intel 82078 controller */

    fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */

    fdctrl->num_floppies = MAX_FD;



    if (fdctrl->dma_chann != -1)

        DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);

    fdctrl_connect_drives(fdctrl);



    return 0;

}

static int fdctrl_init_common(FDCtrl *fdctrl)

{

    int i, j;

    static int command_tables_inited = 0;



    

    if (!command_tables_inited) {

        command_tables_inited = 1;

        for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {

            for (j = 0; j < sizeof(command_to_handler); j++) {

                if ((j & handlers[i].mask) == handlers[i].value) {

                    command_to_handler[j] = i;

                }

            }

        }

    }



    FLOPPY_DPRINTF("init controller\n");

    fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);

    fdctrl->fifo_size = 512;

    fdctrl->result_timer = qemu_new_timer(vm_clock,

                                          fdctrl_result_timer, fdctrl);



    fdctrl->version = 0x90; 

    fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; 

    fdctrl->num_floppies = MAX_FD;



    if (fdctrl->dma_chann != -1)

        DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);

    fdctrl_connect_drives(fdctrl);



    return 0;

}

    fdctrl_connect_drives(fdctrl);     return 0;
static int FUNC_0(FDCtrl *VAR_0)

{

    int VAR_1, VAR_2;

    static int VAR_3 = 0;



    

    if (!VAR_3) {

        VAR_3 = 1;

        for (VAR_1 = ARRAY_SIZE(handlers) - 1; VAR_1 >= 0; VAR_1--) {

            for (VAR_2 = 0; VAR_2 < sizeof(command_to_handler); VAR_2++) {

                if ((VAR_2 & handlers[VAR_1].mask) == handlers[VAR_1].value) {

                    command_to_handler[VAR_2] = VAR_1;

                }

            }

        }

    }



    FLOPPY_DPRINTF("init controller\n");

    VAR_0->fifo = qemu_memalign(512, FD_SECTOR_LEN);

    VAR_0->fifo_size = 512;

    VAR_0->result_timer = qemu_new_timer(vm_clock,

                                          fdctrl_result_timer, VAR_0);



    VAR_0->version = 0x90; 

    VAR_0->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; 

    VAR_0->num_floppies = MAX_FD;



    if (VAR_0->dma_chann != -1)

        DMA_register_channel(VAR_0->dma_chann, &fdctrl_transfer_handler, VAR_0);

    fdctrl_connect_drives(VAR_0);



    return 0;

}

static int FUNC_0(FDCtrl *VAR_0)
{ int VAR_1, VAR_2; static int VAR_3 = 0; if (!VAR_3) { VAR_3 = 1; for (VAR_1 = ARRAY_SIZE(handlers) - 1; VAR_1 >= 0; VAR_1--) { for (VAR_2 = 0; VAR_2 < sizeof(command_to_handler); VAR_2++) { if ((VAR_2 & handlers[VAR_1].mask) == handlers[VAR_1].value) { command_to_handler[VAR_2] = VAR_1; } } } } FLOPPY_DPRINTF("init controller\n"); VAR_0->fifo = qemu_memalign(512, FD_SECTOR_LEN); VAR_0->fifo_size = 512; VAR_0->result_timer = qemu_new_timer(vm_clock,
fdctrl_result_timer, VAR_0); VAR_0->version = 0x90; VAR_0->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; VAR_0->num_floppies = MAX_FD; if (VAR_0->dma_chann != -1)
DMA_register_channel(VAR_0->dma_chann, &fdctrl_transfer_handler, VAR_0); fdctrl_connect_drives(VAR_0); return 0; }