static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)

{

    int havesib;

    int base, disp;

    int index;

    int scale;

    int opreg;

    int mod, rm, code, override, must_add_seg;



    /* XXX: add a generation time variable to tell if base == 0 in DS/ES/SS */

    override = -1;

    must_add_seg = s->addseg;

    if (s->prefix & (PREFIX_CS | PREFIX_SS | PREFIX_DS | 

                     PREFIX_ES | PREFIX_FS | PREFIX_GS)) {

        if (s->prefix & PREFIX_ES)

            override = R_ES;

        else if (s->prefix & PREFIX_CS)

            override = R_CS;

        else if (s->prefix & PREFIX_SS)

            override = R_SS;

        else if (s->prefix & PREFIX_DS)

            override = R_DS;

        else if (s->prefix & PREFIX_FS)

            override = R_FS;

        else

            override = R_GS;

        must_add_seg = 1;

    }



    mod = (modrm >> 6) & 3;

    rm = modrm & 7;



    if (s->aflag) {



        havesib = 0;

        base = rm;

        index = 0;

        scale = 0;

        

        if (base == 4) {

            havesib = 1;

            code = ldub(s->pc++);

            scale = (code >> 6) & 3;

            index = (code >> 3) & 7;

            base = code & 7;

        }



        switch (mod) {

        case 0:

            if (base == 5) {

                base = -1;

                disp = ldl(s->pc);

                s->pc += 4;

            } else {

                disp = 0;

            }

            break;

        case 1:

            disp = (int8_t)ldub(s->pc++);

            break;

        default:

        case 2:

            disp = ldl(s->pc);

            s->pc += 4;

            break;

        }

        

        if (base >= 0) {

            gen_op_movl_A0_reg[base]();

            if (disp != 0)

                gen_op_addl_A0_im(disp);

        } else {

            gen_op_movl_A0_im(disp);

        }

        if (havesib && (index != 4 || scale != 0)) {

            gen_op_addl_A0_reg_sN[scale][index]();

        }

        if (must_add_seg) {

            if (override < 0) {

                if (base == R_EBP || base == R_ESP)

                    override = R_SS;

                else

                    override = R_DS;

            }

            gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));

        }

    } else {

        switch (mod) {

        case 0:

            if (rm == 6) {

                disp = lduw(s->pc);

                s->pc += 2;

                gen_op_movl_A0_im(disp);

                rm = 0; /* avoid SS override */

                goto no_rm;

            } else {

                disp = 0;

            }

            break;

        case 1:

            disp = (int8_t)ldub(s->pc++);

            break;

        default:

        case 2:

            disp = lduw(s->pc);

            s->pc += 2;

            break;

        }

        switch(rm) {

        case 0:

            gen_op_movl_A0_reg[R_EBX]();

            gen_op_addl_A0_reg_sN[0][R_ESI]();

            break;

        case 1:

            gen_op_movl_A0_reg[R_EBX]();

            gen_op_addl_A0_reg_sN[0][R_EDI]();

            break;

        case 2:

            gen_op_movl_A0_reg[R_EBP]();

            gen_op_addl_A0_reg_sN[0][R_ESI]();

            break;

        case 3:

            gen_op_movl_A0_reg[R_EBP]();

            gen_op_addl_A0_reg_sN[0][R_EDI]();

            break;

        case 4:

            gen_op_movl_A0_reg[R_ESI]();

            break;

        case 5:

            gen_op_movl_A0_reg[R_EDI]();

            break;

        case 6:

            gen_op_movl_A0_reg[R_EBP]();

            break;

        default:

        case 7:

            gen_op_movl_A0_reg[R_EBX]();

            break;

        }

        if (disp != 0)

            gen_op_addl_A0_im(disp);

        gen_op_andl_A0_ffff();

    no_rm:

        if (must_add_seg) {

            if (override < 0) {

                if (rm == 2 || rm == 3 || rm == 6)

                    override = R_SS;

                else

                    override = R_DS;

            }

            gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));

        }

    }



    opreg = OR_A0;

    disp = 0;

    *reg_ptr = opreg;

    *offset_ptr = disp;

}

static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)

{

    int havesib;

    int base, disp;

    int index;

    int scale;

    int opreg;

    int mod, rm, code, override, must_add_seg;



    

    override = -1;

    must_add_seg = s->addseg;

    if (s->prefix & (PREFIX_CS | PREFIX_SS | PREFIX_DS | 

                     PREFIX_ES | PREFIX_FS | PREFIX_GS)) {

        if (s->prefix & PREFIX_ES)

            override = R_ES;

        else if (s->prefix & PREFIX_CS)

            override = R_CS;

        else if (s->prefix & PREFIX_SS)

            override = R_SS;

        else if (s->prefix & PREFIX_DS)

            override = R_DS;

        else if (s->prefix & PREFIX_FS)

            override = R_FS;

        else

            override = R_GS;

        must_add_seg = 1;

    }



    mod = (modrm >> 6) & 3;

    rm = modrm & 7;



    if (s->aflag) {



        havesib = 0;

        base = rm;

        index = 0;

        scale = 0;

        

        if (base == 4) {

            havesib = 1;

            code = ldub(s->pc++);

            scale = (code >> 6) & 3;

            index = (code >> 3) & 7;

            base = code & 7;

        }



        switch (mod) {

        case 0:

            if (base == 5) {

                base = -1;

                disp = ldl(s->pc);

                s->pc += 4;

            } else {

                disp = 0;

            }

            break;

        case 1:

            disp = (int8_t)ldub(s->pc++);

            break;

        default:

        case 2:

            disp = ldl(s->pc);

            s->pc += 4;

            break;

        }

        

        if (base >= 0) {

            gen_op_movl_A0_reg[base]();

            if (disp != 0)

                gen_op_addl_A0_im(disp);

        } else {

            gen_op_movl_A0_im(disp);

        }

        if (havesib && (index != 4 || scale != 0)) {

            gen_op_addl_A0_reg_sN[scale][index]();

        }

        if (must_add_seg) {

            if (override < 0) {

                if (base == R_EBP || base == R_ESP)

                    override = R_SS;

                else

                    override = R_DS;

            }

            gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));

        }

    } else {

        switch (mod) {

        case 0:

            if (rm == 6) {

                disp = lduw(s->pc);

                s->pc += 2;

                gen_op_movl_A0_im(disp);

                rm = 0; 

                goto no_rm;

            } else {

                disp = 0;

            }

            break;

        case 1:

            disp = (int8_t)ldub(s->pc++);

            break;

        default:

        case 2:

            disp = lduw(s->pc);

            s->pc += 2;

            break;

        }

        switch(rm) {

        case 0:

            gen_op_movl_A0_reg[R_EBX]();

            gen_op_addl_A0_reg_sN[0][R_ESI]();

            break;

        case 1:

            gen_op_movl_A0_reg[R_EBX]();

            gen_op_addl_A0_reg_sN[0][R_EDI]();

            break;

        case 2:

            gen_op_movl_A0_reg[R_EBP]();

            gen_op_addl_A0_reg_sN[0][R_ESI]();

            break;

        case 3:

            gen_op_movl_A0_reg[R_EBP]();

            gen_op_addl_A0_reg_sN[0][R_EDI]();

            break;

        case 4:

            gen_op_movl_A0_reg[R_ESI]();

            break;

        case 5:

            gen_op_movl_A0_reg[R_EDI]();

            break;

        case 6:

            gen_op_movl_A0_reg[R_EBP]();

            break;

        default:

        case 7:

            gen_op_movl_A0_reg[R_EBX]();

            break;

        }

        if (disp != 0)

            gen_op_addl_A0_im(disp);

        gen_op_andl_A0_ffff();

    no_rm:

        if (must_add_seg) {

            if (override < 0) {

                if (rm == 2 || rm == 3 || rm == 6)

                    override = R_SS;

                else

                    override = R_DS;

            }

            gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));

        }

    }



    opreg = OR_A0;

    disp = 0;

    *reg_ptr = opreg;

    *offset_ptr = disp;

}

static void FUNC_0(DisasContext *VAR_0, int VAR_1, int *VAR_2, int *VAR_3)

{

    int VAR_4;

    int VAR_5, VAR_6;

    int VAR_7;

    int VAR_8;

    int VAR_9;

    int VAR_10, VAR_11, VAR_12, VAR_13, VAR_14;



    

    VAR_13 = -1;

    VAR_14 = VAR_0->addseg;

    if (VAR_0->prefix & (PREFIX_CS | PREFIX_SS | PREFIX_DS | 

                     PREFIX_ES | PREFIX_FS | PREFIX_GS)) {

        if (VAR_0->prefix & PREFIX_ES)

            VAR_13 = R_ES;

        else if (VAR_0->prefix & PREFIX_CS)

            VAR_13 = R_CS;

        else if (VAR_0->prefix & PREFIX_SS)

            VAR_13 = R_SS;

        else if (VAR_0->prefix & PREFIX_DS)

            VAR_13 = R_DS;

        else if (VAR_0->prefix & PREFIX_FS)

            VAR_13 = R_FS;

        else

            VAR_13 = R_GS;

        VAR_14 = 1;

    }



    VAR_10 = (VAR_1 >> 6) & 3;

    VAR_11 = VAR_1 & 7;



    if (VAR_0->aflag) {



        VAR_4 = 0;

        VAR_5 = VAR_11;

        VAR_7 = 0;

        VAR_8 = 0;

        

        if (VAR_5 == 4) {

            VAR_4 = 1;

            VAR_12 = ldub(VAR_0->pc++);

            VAR_8 = (VAR_12 >> 6) & 3;

            VAR_7 = (VAR_12 >> 3) & 7;

            VAR_5 = VAR_12 & 7;

        }



        switch (VAR_10) {

        case 0:

            if (VAR_5 == 5) {

                VAR_5 = -1;

                VAR_6 = ldl(VAR_0->pc);

                VAR_0->pc += 4;

            } else {

                VAR_6 = 0;

            }

            break;

        case 1:

            VAR_6 = (int8_t)ldub(VAR_0->pc++);

            break;

        default:

        case 2:

            VAR_6 = ldl(VAR_0->pc);

            VAR_0->pc += 4;

            break;

        }

        

        if (VAR_5 >= 0) {

            gen_op_movl_A0_reg[VAR_5]();

            if (VAR_6 != 0)

                gen_op_addl_A0_im(VAR_6);

        } else {

            gen_op_movl_A0_im(VAR_6);

        }

        if (VAR_4 && (VAR_7 != 4 || VAR_8 != 0)) {

            gen_op_addl_A0_reg_sN[VAR_8][VAR_7]();

        }

        if (VAR_14) {

            if (VAR_13 < 0) {

                if (VAR_5 == R_EBP || VAR_5 == R_ESP)

                    VAR_13 = R_SS;

                else

                    VAR_13 = R_DS;

            }

            gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[VAR_13].VAR_5));

        }

    } else {

        switch (VAR_10) {

        case 0:

            if (VAR_11 == 6) {

                VAR_6 = lduw(VAR_0->pc);

                VAR_0->pc += 2;

                gen_op_movl_A0_im(VAR_6);

                VAR_11 = 0; 

                goto no_rm;

            } else {

                VAR_6 = 0;

            }

            break;

        case 1:

            VAR_6 = (int8_t)ldub(VAR_0->pc++);

            break;

        default:

        case 2:

            VAR_6 = lduw(VAR_0->pc);

            VAR_0->pc += 2;

            break;

        }

        switch(VAR_11) {

        case 0:

            gen_op_movl_A0_reg[R_EBX]();

            gen_op_addl_A0_reg_sN[0][R_ESI]();

            break;

        case 1:

            gen_op_movl_A0_reg[R_EBX]();

            gen_op_addl_A0_reg_sN[0][R_EDI]();

            break;

        case 2:

            gen_op_movl_A0_reg[R_EBP]();

            gen_op_addl_A0_reg_sN[0][R_ESI]();

            break;

        case 3:

            gen_op_movl_A0_reg[R_EBP]();

            gen_op_addl_A0_reg_sN[0][R_EDI]();

            break;

        case 4:

            gen_op_movl_A0_reg[R_ESI]();

            break;

        case 5:

            gen_op_movl_A0_reg[R_EDI]();

            break;

        case 6:

            gen_op_movl_A0_reg[R_EBP]();

            break;

        default:

        case 7:

            gen_op_movl_A0_reg[R_EBX]();

            break;

        }

        if (VAR_6 != 0)

            gen_op_addl_A0_im(VAR_6);

        gen_op_andl_A0_ffff();

    no_rm:

        if (VAR_14) {

            if (VAR_13 < 0) {

                if (VAR_11 == 2 || VAR_11 == 3 || VAR_11 == 6)

                    VAR_13 = R_SS;

                else

                    VAR_13 = R_DS;

            }

            gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[VAR_13].VAR_5));

        }

    }



    VAR_9 = OR_A0;

    VAR_6 = 0;

    *VAR_2 = VAR_9;

    *VAR_3 = VAR_6;

}

static void FUNC_0(DisasContext *VAR_0, int VAR_1, int *VAR_2, int *VAR_3)
{ int VAR_4; int VAR_5, VAR_6; int VAR_7; int VAR_8; int VAR_9; int VAR_10, VAR_11, VAR_12, VAR_13, VAR_14; VAR_13 = -1; VAR_14 = VAR_0->addseg; if (VAR_0->prefix & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
PREFIX_ES | PREFIX_FS | PREFIX_GS)) { if (VAR_0->prefix & PREFIX_ES)
VAR_13 = R_ES; else if (VAR_0->prefix & PREFIX_CS)
VAR_13 = R_CS; else if (VAR_0->prefix & PREFIX_SS)
VAR_13 = R_SS; else if (VAR_0->prefix & PREFIX_DS)
VAR_13 = R_DS; else if (VAR_0->prefix & PREFIX_FS)
VAR_13 = R_FS; else
VAR_13 = R_GS; VAR_14 = 1; } VAR_10 = (VAR_1 >> 6) & 3; VAR_11 = VAR_1 & 7; if (VAR_0->aflag) { VAR_4 = 0; VAR_5 = VAR_11; VAR_7 = 0; VAR_8 = 0; if (VAR_5 == 4) { VAR_4 = 1; VAR_12 = ldub(VAR_0->pc++); VAR_8 = (VAR_12 >> 6) & 3; VAR_7 = (VAR_12 >> 3) & 7; VAR_5 = VAR_12 & 7; } switch (VAR_10) { case 0:
if (VAR_5 == 5) { VAR_5 = -1; VAR_6 = ldl(VAR_0->pc); VAR_0->pc += 4; } else { VAR_6 = 0; } break; case 1:
VAR_6 = (int8_t)ldub(VAR_0->pc++); break; default:
case 2:
VAR_6 = ldl(VAR_0->pc); VAR_0->pc += 4; break; } if (VAR_5 >= 0) { gen_op_movl_A0_reg[VAR_5](); if (VAR_6 != 0)
gen_op_addl_A0_im(VAR_6); } else { gen_op_movl_A0_im(VAR_6); } if (VAR_4 && (VAR_7 != 4 || VAR_8 != 0)) { gen_op_addl_A0_reg_sN[VAR_8][VAR_7](); } if (VAR_14) { if (VAR_13 < 0) { if (VAR_5 == R_EBP || VAR_5 == R_ESP)
VAR_13 = R_SS; else
VAR_13 = R_DS; } gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[VAR_13].VAR_5)); } } else { switch (VAR_10) { case 0:
if (VAR_11 == 6) { VAR_6 = lduw(VAR_0->pc); VAR_0->pc += 2; gen_op_movl_A0_im(VAR_6); VAR_11 = 0; goto no_rm; } else { VAR_6 = 0; } break; case 1:
VAR_6 = (int8_t)ldub(VAR_0->pc++); break; default:
case 2:
VAR_6 = lduw(VAR_0->pc); VAR_0->pc += 2; break; } switch(VAR_11) { case 0:
gen_op_movl_A0_reg[R_EBX](); gen_op_addl_A0_reg_sN[0][R_ESI](); break; case 1:
gen_op_movl_A0_reg[R_EBX](); gen_op_addl_A0_reg_sN[0][R_EDI](); break; case 2:
gen_op_movl_A0_reg[R_EBP](); gen_op_addl_A0_reg_sN[0][R_ESI](); break; case 3:
gen_op_movl_A0_reg[R_EBP](); gen_op_addl_A0_reg_sN[0][R_EDI](); break; case 4:
gen_op_movl_A0_reg[R_ESI](); break; case 5:
gen_op_movl_A0_reg[R_EDI](); break; case 6:
gen_op_movl_A0_reg[R_EBP](); break; default:
case 7:
gen_op_movl_A0_reg[R_EBX](); break; } if (VAR_6 != 0)
gen_op_addl_A0_im(VAR_6); gen_op_andl_A0_ffff(); no_rm:
if (VAR_14) { if (VAR_13 < 0) { if (VAR_11 == 2 || VAR_11 == 3 || VAR_11 == 6)
VAR_13 = R_SS; else
VAR_13 = R_DS; } gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[VAR_13].VAR_5)); } } VAR_9 = OR_A0; VAR_6 = 0; *VAR_2 = VAR_9; *VAR_3 = VAR_6; }