static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst,

                                  TCGArg lhs, TCGArg rhs, int rhs_is_const)

{

    /* Emit either the reg,imm or reg,reg form of a data-processing insn.

     * rhs must satisfy the "rI" constraint.

     */

    if (rhs_is_const) {

        int rot = encode_imm(rhs);

        assert(rot >= 0);

        tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));

    } else {

        tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));

    }

}

static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst,

                                  TCGArg lhs, TCGArg rhs, int rhs_is_const)

{

    





    if (rhs_is_const) {

        int rot = encode_imm(rhs);

        assert(rot >= 0);

        tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));

    } else {

        tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));

    }

}

static inline void FUNC_0(TCGContext *VAR_0, int VAR_1, int VAR_2, TCGArg VAR_3,

                                  TCGArg VAR_4, TCGArg VAR_5, int VAR_6)

{

    





    if (VAR_6) {

        int VAR_7 = encode_imm(VAR_5);

        assert(VAR_7 >= 0);

        tcg_out_dat_imm(VAR_0, VAR_1, VAR_2, VAR_3, VAR_4, rotl(VAR_5, VAR_7) | (VAR_7 << 7));

    } else {

        tcg_out_dat_reg(VAR_0, VAR_1, VAR_2, VAR_3, VAR_4, VAR_5, SHIFT_IMM_LSL(0));

    }

}

static inline void FUNC_0(TCGContext *VAR_0, int VAR_1, int VAR_2, TCGArg VAR_3,
TCGArg VAR_4, TCGArg VAR_5, int VAR_6)
{ if (VAR_6) { int VAR_7 = encode_imm(VAR_5); assert(VAR_7 >= 0); tcg_out_dat_imm(VAR_0, VAR_1, VAR_2, VAR_3, VAR_4, rotl(VAR_5, VAR_7) | (VAR_7 << 7)); } else { tcg_out_dat_reg(VAR_0, VAR_1, VAR_2, VAR_3, VAR_4, VAR_5, SHIFT_IMM_LSL(0)); } }