int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,

                          int rw, int access_type, int check_BATs)

{

    int ret;

#if 0

    if (loglevel != 0) {

        fprintf(logfile, "%s\n", __func__);

    }

#endif

    if ((access_type == ACCESS_CODE && msr_ir == 0) ||

        (access_type != ACCESS_CODE && msr_dr == 0)) {

        /* No address translation */

        ret = check_physical(env, ctx, eaddr, rw);

    } else {

        ret = -1;

        switch (env->mmu_model) {

        case POWERPC_MMU_32B:

        case POWERPC_MMU_SOFT_6xx:

        case POWERPC_MMU_SOFT_74xx:

            /* Try to find a BAT */

            if (check_BATs)

                ret = get_bat(env, ctx, eaddr, rw, access_type);

            /* No break here */

#if defined(TARGET_PPC64)

        case POWERPC_MMU_64B:

        case POWERPC_MMU_64BRIDGE:

#endif

            if (ret < 0) {

                /* We didn't match any BAT entry or don't have BATs */

                ret = get_segment(env, ctx, eaddr, rw, access_type);

            }

            break;

        case POWERPC_MMU_SOFT_4xx:

        case POWERPC_MMU_SOFT_4xx_Z:

            ret = mmu40x_get_physical_address(env, ctx, eaddr,

                                              rw, access_type);

            break;

        case POWERPC_MMU_601:

            /* XXX: TODO */

            cpu_abort(env, "601 MMU model not implemented\n");

            return -1;

        case POWERPC_MMU_BOOKE:

            ret = mmubooke_get_physical_address(env, ctx, eaddr,

                                                rw, access_type);

            break;

        case POWERPC_MMU_BOOKE_FSL:

            /* XXX: TODO */

            cpu_abort(env, "BookE FSL MMU model not implemented\n");

            return -1;

        case POWERPC_MMU_REAL_4xx:

            cpu_abort(env, "PowerPC 401 does not do any translation\n");

            return -1;

        default:

            cpu_abort(env, "Unknown or invalid MMU model\n");

            return -1;

        }

    }

#if 0

    if (loglevel != 0) {

        fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",

                __func__, eaddr, ret, ctx->raddr);

    }

#endif



    return ret;

}

int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,

                          int rw, int access_type, int check_BATs)

{

    int ret;

#if 0

    if (loglevel != 0) {

        fprintf(logfile, "%s\n", __func__);

    }

#endif

    if ((access_type == ACCESS_CODE && msr_ir == 0) ||

        (access_type != ACCESS_CODE && msr_dr == 0)) {

        

        ret = check_physical(env, ctx, eaddr, rw);

    } else {

        ret = -1;

        switch (env->mmu_model) {

        case POWERPC_MMU_32B:

        case POWERPC_MMU_SOFT_6xx:

        case POWERPC_MMU_SOFT_74xx:

            

            if (check_BATs)

                ret = get_bat(env, ctx, eaddr, rw, access_type);

            

#if defined(TARGET_PPC64)

        case POWERPC_MMU_64B:

        case POWERPC_MMU_64BRIDGE:

#endif

            if (ret < 0) {

                

                ret = get_segment(env, ctx, eaddr, rw, access_type);

            }

            break;

        case POWERPC_MMU_SOFT_4xx:

        case POWERPC_MMU_SOFT_4xx_Z:

            ret = mmu40x_get_physical_address(env, ctx, eaddr,

                                              rw, access_type);

            break;

        case POWERPC_MMU_601:

            

            cpu_abort(env, "601 MMU model not implemented\n");

            return -1;

        case POWERPC_MMU_BOOKE:

            ret = mmubooke_get_physical_address(env, ctx, eaddr,

                                                rw, access_type);

            break;

        case POWERPC_MMU_BOOKE_FSL:

            

            cpu_abort(env, "BookE FSL MMU model not implemented\n");

            return -1;

        case POWERPC_MMU_REAL_4xx:

            cpu_abort(env, "PowerPC 401 does not do any translation\n");

            return -1;

        default:

            cpu_abort(env, "Unknown or invalid MMU model\n");

            return -1;

        }

    }

#if 0

    if (loglevel != 0) {

        fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",

                __func__, eaddr, ret, ctx->raddr);

    }

#endif



    return ret;

}

#endif #endif         case POWERPC_MMU_64BRIDGE:         case POWERPC_MMU_64BRIDGE:             break;
int FUNC_0 (CPUState *VAR_0, mmu_ctx_t *VAR_1, target_ulong VAR_2,

                          int VAR_3, int VAR_4, int VAR_5)

{

    int VAR_6;

#if 0

    if (loglevel != 0) {

        fprintf(logfile, "%s\n", __func__);

    }

#endif

    if ((VAR_4 == ACCESS_CODE && msr_ir == 0) ||

        (VAR_4 != ACCESS_CODE && msr_dr == 0)) {

        

        VAR_6 = check_physical(VAR_0, VAR_1, VAR_2, VAR_3);

    } else {

        VAR_6 = -1;

        switch (VAR_0->mmu_model) {

        case POWERPC_MMU_32B:

        case POWERPC_MMU_SOFT_6xx:

        case POWERPC_MMU_SOFT_74xx:

            

            if (VAR_5)

                VAR_6 = get_bat(VAR_0, VAR_1, VAR_2, VAR_3, VAR_4);

            

#if defined(TARGET_PPC64)

        case POWERPC_MMU_64B:

        case POWERPC_MMU_64BRIDGE:

#endif

            if (VAR_6 < 0) {

                

                VAR_6 = get_segment(VAR_0, VAR_1, VAR_2, VAR_3, VAR_4);

            }

            break;

        case POWERPC_MMU_SOFT_4xx:

        case POWERPC_MMU_SOFT_4xx_Z:

            VAR_6 = mmu40x_get_physical_address(VAR_0, VAR_1, VAR_2,

                                              VAR_3, VAR_4);

            break;

        case POWERPC_MMU_601:

            

            cpu_abort(VAR_0, "601 MMU model not implemented\n");

            return -1;

        case POWERPC_MMU_BOOKE:

            VAR_6 = mmubooke_get_physical_address(VAR_0, VAR_1, VAR_2,

                                                VAR_3, VAR_4);

            break;

        case POWERPC_MMU_BOOKE_FSL:

            

            cpu_abort(VAR_0, "BookE FSL MMU model not implemented\n");

            return -1;

        case POWERPC_MMU_REAL_4xx:

            cpu_abort(VAR_0, "PowerPC 401 does not do any translation\n");

            return -1;

        default:

            cpu_abort(VAR_0, "Unknown or invalid MMU model\n");

            return -1;

        }

    }

#if 0

    if (loglevel != 0) {

        fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",

                __func__, VAR_2, VAR_6, VAR_1->raddr);

    }

#endif



    return VAR_6;

}

int FUNC_0 (CPUState *VAR_0, mmu_ctx_t *VAR_1, target_ulong VAR_2,
int VAR_3, int VAR_4, int VAR_5)
{ int VAR_6; #if 0
if (loglevel != 0) { fprintf(logfile, "%s\n", __func__); } #endif
if ((VAR_4 == ACCESS_CODE && msr_ir == 0) ||
(VAR_4 != ACCESS_CODE && msr_dr == 0)) { VAR_6 = check_physical(VAR_0, VAR_1, VAR_2, VAR_3); } else { VAR_6 = -1; switch (VAR_0->mmu_model) { case POWERPC_MMU_32B:
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
if (VAR_5)
VAR_6 = get_bat(VAR_0, VAR_1, VAR_2, VAR_3, VAR_4); #if defined(TARGET_PPC64)
case POWERPC_MMU_64B:
case POWERPC_MMU_64BRIDGE:
#endif
if (VAR_6 < 0) { VAR_6 = get_segment(VAR_0, VAR_1, VAR_2, VAR_3, VAR_4); } break; case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
VAR_6 = mmu40x_get_physical_address(VAR_0, VAR_1, VAR_2,
VAR_3, VAR_4); break; case POWERPC_MMU_601:
cpu_abort(VAR_0, "601 MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE:
VAR_6 = mmubooke_get_physical_address(VAR_0, VAR_1, VAR_2,
VAR_3, VAR_4); break; case POWERPC_MMU_BOOKE_FSL:
cpu_abort(VAR_0, "BookE FSL MMU model not implemented\n"); return -1; case POWERPC_MMU_REAL_4xx:
cpu_abort(VAR_0, "PowerPC 401 does not do any translation\n"); return -1; default:
cpu_abort(VAR_0, "Unknown or invalid MMU model\n"); return -1; } } #if 0
if (loglevel != 0) { fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
__func__, VAR_2, VAR_6, VAR_1->raddr); } #endif
return VAR_6; }