void cpu_reset(CPUX86State *env)
{
    int i;
    memset(env, 0, offsetof(CPUX86State, breakpoints));
    tlb_flush(env, 1);
    env->old_exception = -1;
    /* init to reset state */
#ifdef CONFIG_SOFTMMU
    env->hflags |= HF_SOFTMMU_MASK;
#endif
    env->hflags2 |= HF2_GIF_MASK;
    cpu_x86_update_cr0(env, 0x60000010);
    env->a20_mask = ~0x0;
    env->smbase = 0x30000;
    env->idt.limit = 0xffff;
    env->gdt.limit = 0xffff;
    env->ldt.limit = 0xffff;
    env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
    env->tr.limit = 0xffff;
    env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
    cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK);
    cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    env->eip = 0xfff0;
    env->regs[R_EDX] = env->cpuid_version;
    env->eflags = 0x2;
    /* FPU init */
    for(i = 0;i < 8; i++)
        env->fptags[i] = 1;
    env->fpuc = 0x37f;
    env->mxcsr = 0x1f80;
    memset(env->dr, 0, sizeof(env->dr));
    env->dr[6] = DR6_FIXED_1;
    env->dr[7] = DR7_FIXED_1;
    cpu_breakpoint_remove_all(env, BP_CPU);
    cpu_watchpoint_remove_all(env, BP_CPU);
void cpu_reset(CPUX86State *env)
{
    int i;
    memset(env, 0, offsetof(CPUX86State, breakpoints));
    tlb_flush(env, 1);
    env->old_exception = -1;
    
#ifdef CONFIG_SOFTMMU
    env->hflags |= HF_SOFTMMU_MASK;
#endif
    env->hflags2 |= HF2_GIF_MASK;
    cpu_x86_update_cr0(env, 0x60000010);
    env->a20_mask = ~0x0;
    env->smbase = 0x30000;
    env->idt.limit = 0xffff;
    env->gdt.limit = 0xffff;
    env->ldt.limit = 0xffff;
    env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
    env->tr.limit = 0xffff;
    env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
    cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK);
    cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    env->eip = 0xfff0;
    env->regs[R_EDX] = env->cpuid_version;
    env->eflags = 0x2;
    
    for(i = 0;i < 8; i++)
        env->fptags[i] = 1;
    env->fpuc = 0x37f;
    env->mxcsr = 0x1f80;
    memset(env->dr, 0, sizeof(env->dr));
    env->dr[6] = DR6_FIXED_1;
    env->dr[7] = DR7_FIXED_1;
    cpu_breakpoint_remove_all(env, BP_CPU);
    cpu_watchpoint_remove_all(env, BP_CPU);
void FUNC_0(CPUX86State *VAR_0)
{
    int VAR_1;
    memset(VAR_0, 0, offsetof(CPUX86State, breakpoints));
    tlb_flush(VAR_0, 1);
    VAR_0->old_exception = -1;
    
#ifdef CONFIG_SOFTMMU
    VAR_0->hflags |= HF_SOFTMMU_MASK;
#endif
    VAR_0->hflags2 |= HF2_GIF_MASK;
    cpu_x86_update_cr0(VAR_0, 0x60000010);
    VAR_0->a20_mask = ~0x0;
    VAR_0->smbase = 0x30000;
    VAR_0->idt.limit = 0xffff;
    VAR_0->gdt.limit = 0xffff;
    VAR_0->ldt.limit = 0xffff;
    VAR_0->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
    VAR_0->tr.limit = 0xffff;
    VAR_0->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
    cpu_x86_load_seg_cache(VAR_0, R_CS, 0xf000, 0xffff0000, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK);
    cpu_x86_load_seg_cache(VAR_0, R_DS, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    cpu_x86_load_seg_cache(VAR_0, R_ES, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    cpu_x86_load_seg_cache(VAR_0, R_SS, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    cpu_x86_load_seg_cache(VAR_0, R_FS, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    cpu_x86_load_seg_cache(VAR_0, R_GS, 0, 0, 0xffff,
                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
    VAR_0->eip = 0xfff0;
    VAR_0->regs[R_EDX] = VAR_0->cpuid_version;
    VAR_0->eflags = 0x2;
    
    for(VAR_1 = 0;VAR_1 < 8; VAR_1++)
        VAR_0->fptags[VAR_1] = 1;
    VAR_0->fpuc = 0x37f;
    VAR_0->mxcsr = 0x1f80;
    memset(VAR_0->dr, 0, sizeof(VAR_0->dr));
    VAR_0->dr[6] = DR6_FIXED_1;
    VAR_0->dr[7] = DR7_FIXED_1;
    cpu_breakpoint_remove_all(VAR_0, BP_CPU);
    cpu_watchpoint_remove_all(VAR_0, BP_CPU);
void FUNC_0(CPUX86State *VAR_0)
{ int VAR_1; memset(VAR_0, 0, offsetof(CPUX86State, breakpoints)); tlb_flush(VAR_0, 1); VAR_0->old_exception = -1; #ifdef CONFIG_SOFTMMU
VAR_0->hflags |= HF_SOFTMMU_MASK; #endif
VAR_0->hflags2 |= HF2_GIF_MASK; cpu_x86_update_cr0(VAR_0, 0x60000010); VAR_0->a20_mask = ~0x0; VAR_0->smbase = 0x30000; VAR_0->idt.limit = 0xffff; VAR_0->gdt.limit = 0xffff; VAR_0->ldt.limit = 0xffff; VAR_0->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); VAR_0->tr.limit = 0xffff; VAR_0->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); cpu_x86_load_seg_cache(VAR_0, R_CS, 0xf000, 0xffff0000, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK); cpu_x86_load_seg_cache(VAR_0, R_DS, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); cpu_x86_load_seg_cache(VAR_0, R_ES, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); cpu_x86_load_seg_cache(VAR_0, R_SS, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); cpu_x86_load_seg_cache(VAR_0, R_FS, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); cpu_x86_load_seg_cache(VAR_0, R_GS, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); VAR_0->eip = 0xfff0; VAR_0->regs[R_EDX] = VAR_0->cpuid_version; VAR_0->eflags = 0x2; for(VAR_1 = 0;VAR_1 < 8; VAR_1++) VAR_0->fptags[VAR_1] = 1; VAR_0->fpuc = 0x37f; VAR_0->mxcsr = 0x1f80; memset(VAR_0->dr, 0, sizeof(VAR_0->dr)); VAR_0->dr[6] = DR6_FIXED_1; VAR_0->dr[7] = DR7_FIXED_1; cpu_breakpoint_remove_all(VAR_0, BP_CPU); cpu_watchpoint_remove_all(VAR_0, BP_CPU);