static int nvme_start_ctrl(NvmeCtrl *n)

{

    uint32_t page_bits = NVME_CC_MPS(n->bar.cc) + 12;

    uint32_t page_size = 1 << page_bits;



    if (n->cq[0] || n->sq[0] || !n->bar.asq || !n->bar.acq ||

            n->bar.asq & (page_size - 1) || n->bar.acq & (page_size - 1) ||

            NVME_CC_MPS(n->bar.cc) < NVME_CAP_MPSMIN(n->bar.cap) ||

            NVME_CC_MPS(n->bar.cc) > NVME_CAP_MPSMAX(n->bar.cap) ||

            NVME_CC_IOCQES(n->bar.cc) < NVME_CTRL_CQES_MIN(n->id_ctrl.cqes) ||

            NVME_CC_IOCQES(n->bar.cc) > NVME_CTRL_CQES_MAX(n->id_ctrl.cqes) ||

            NVME_CC_IOSQES(n->bar.cc) < NVME_CTRL_SQES_MIN(n->id_ctrl.sqes) ||

            NVME_CC_IOSQES(n->bar.cc) > NVME_CTRL_SQES_MAX(n->id_ctrl.sqes) ||

            !NVME_AQA_ASQS(n->bar.aqa) || NVME_AQA_ASQS(n->bar.aqa) > 4095 ||

            !NVME_AQA_ACQS(n->bar.aqa) || NVME_AQA_ACQS(n->bar.aqa) > 4095) {

        return -1;

    }



    n->page_bits = page_bits;

    n->page_size = page_size;

    n->max_prp_ents = n->page_size / sizeof(uint64_t);

    n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc);

    n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc);

    nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0,

        NVME_AQA_ACQS(n->bar.aqa) + 1, 1);

    nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0,

        NVME_AQA_ASQS(n->bar.aqa) + 1);



    return 0;

}

static int nvme_start_ctrl(NvmeCtrl *n)

{

    uint32_t page_bits = NVME_CC_MPS(n->bar.cc) + 12;

    uint32_t page_size = 1 << page_bits;



    if (n->cq[0] || n->sq[0] || !n->bar.asq || !n->bar.acq ||

            n->bar.asq & (page_size - 1) || n->bar.acq & (page_size - 1) ||

            NVME_CC_MPS(n->bar.cc) < NVME_CAP_MPSMIN(n->bar.cap) ||

            NVME_CC_MPS(n->bar.cc) > NVME_CAP_MPSMAX(n->bar.cap) ||

            NVME_CC_IOCQES(n->bar.cc) < NVME_CTRL_CQES_MIN(n->id_ctrl.cqes) ||

            NVME_CC_IOCQES(n->bar.cc) > NVME_CTRL_CQES_MAX(n->id_ctrl.cqes) ||

            NVME_CC_IOSQES(n->bar.cc) < NVME_CTRL_SQES_MIN(n->id_ctrl.sqes) ||

            NVME_CC_IOSQES(n->bar.cc) > NVME_CTRL_SQES_MAX(n->id_ctrl.sqes) ||

            !NVME_AQA_ASQS(n->bar.aqa) || NVME_AQA_ASQS(n->bar.aqa) > 4095 ||

            !NVME_AQA_ACQS(n->bar.aqa) || NVME_AQA_ACQS(n->bar.aqa) > 4095) {

        return -1;

    }



    n->page_bits = page_bits;

    n->page_size = page_size;

    n->max_prp_ents = n->page_size / sizeof(uint64_t);

    n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc);

    n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc);

    nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0,

        NVME_AQA_ACQS(n->bar.aqa) + 1, 1);

    nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0,

        NVME_AQA_ASQS(n->bar.aqa) + 1);



    return 0;

}

static int FUNC_0(NvmeCtrl *VAR_0)

{

    uint32_t page_bits = NVME_CC_MPS(VAR_0->bar.cc) + 12;

    uint32_t page_size = 1 << page_bits;



    if (VAR_0->cq[0] || VAR_0->sq[0] || !VAR_0->bar.asq || !VAR_0->bar.acq ||

            VAR_0->bar.asq & (page_size - 1) || VAR_0->bar.acq & (page_size - 1) ||

            NVME_CC_MPS(VAR_0->bar.cc) < NVME_CAP_MPSMIN(VAR_0->bar.cap) ||

            NVME_CC_MPS(VAR_0->bar.cc) > NVME_CAP_MPSMAX(VAR_0->bar.cap) ||

            NVME_CC_IOCQES(VAR_0->bar.cc) < NVME_CTRL_CQES_MIN(VAR_0->id_ctrl.cqes) ||

            NVME_CC_IOCQES(VAR_0->bar.cc) > NVME_CTRL_CQES_MAX(VAR_0->id_ctrl.cqes) ||

            NVME_CC_IOSQES(VAR_0->bar.cc) < NVME_CTRL_SQES_MIN(VAR_0->id_ctrl.sqes) ||

            NVME_CC_IOSQES(VAR_0->bar.cc) > NVME_CTRL_SQES_MAX(VAR_0->id_ctrl.sqes) ||

            !NVME_AQA_ASQS(VAR_0->bar.aqa) || NVME_AQA_ASQS(VAR_0->bar.aqa) > 4095 ||

            !NVME_AQA_ACQS(VAR_0->bar.aqa) || NVME_AQA_ACQS(VAR_0->bar.aqa) > 4095) {

        return -1;

    }



    VAR_0->page_bits = page_bits;

    VAR_0->page_size = page_size;

    VAR_0->max_prp_ents = VAR_0->page_size / sizeof(uint64_t);

    VAR_0->cqe_size = 1 << NVME_CC_IOCQES(VAR_0->bar.cc);

    VAR_0->sqe_size = 1 << NVME_CC_IOSQES(VAR_0->bar.cc);

    nvme_init_cq(&VAR_0->admin_cq, VAR_0, VAR_0->bar.acq, 0, 0,

        NVME_AQA_ACQS(VAR_0->bar.aqa) + 1, 1);

    nvme_init_sq(&VAR_0->admin_sq, VAR_0, VAR_0->bar.asq, 0, 0,

        NVME_AQA_ASQS(VAR_0->bar.aqa) + 1);



    return 0;

}

static int FUNC_0(NvmeCtrl *VAR_0)
{ uint32_t page_bits = NVME_CC_MPS(VAR_0->bar.cc) + 12; uint32_t page_size = 1 << page_bits; if (VAR_0->cq[0] || VAR_0->sq[0] || !VAR_0->bar.asq || !VAR_0->bar.acq ||
VAR_0->bar.asq & (page_size - 1) || VAR_0->bar.acq & (page_size - 1) ||
NVME_CC_MPS(VAR_0->bar.cc) < NVME_CAP_MPSMIN(VAR_0->bar.cap) ||
NVME_CC_MPS(VAR_0->bar.cc) > NVME_CAP_MPSMAX(VAR_0->bar.cap) ||
NVME_CC_IOCQES(VAR_0->bar.cc) < NVME_CTRL_CQES_MIN(VAR_0->id_ctrl.cqes) ||
NVME_CC_IOCQES(VAR_0->bar.cc) > NVME_CTRL_CQES_MAX(VAR_0->id_ctrl.cqes) ||
NVME_CC_IOSQES(VAR_0->bar.cc) < NVME_CTRL_SQES_MIN(VAR_0->id_ctrl.sqes) ||
NVME_CC_IOSQES(VAR_0->bar.cc) > NVME_CTRL_SQES_MAX(VAR_0->id_ctrl.sqes) ||
!NVME_AQA_ASQS(VAR_0->bar.aqa) || NVME_AQA_ASQS(VAR_0->bar.aqa) > 4095 ||
!NVME_AQA_ACQS(VAR_0->bar.aqa) || NVME_AQA_ACQS(VAR_0->bar.aqa) > 4095) { return -1; } VAR_0->page_bits = page_bits; VAR_0->page_size = page_size; VAR_0->max_prp_ents = VAR_0->page_size / sizeof(uint64_t); VAR_0->cqe_size = 1 << NVME_CC_IOCQES(VAR_0->bar.cc); VAR_0->sqe_size = 1 << NVME_CC_IOSQES(VAR_0->bar.cc); nvme_init_cq(&VAR_0->admin_cq, VAR_0, VAR_0->bar.acq, 0, 0,
NVME_AQA_ACQS(VAR_0->bar.aqa) + 1, 1); nvme_init_sq(&VAR_0->admin_sq, VAR_0, VAR_0->bar.asq, 0, 0,
NVME_AQA_ASQS(VAR_0->bar.aqa) + 1); return 0; }