void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,

                         int flags)

{

    MIPSCPU *cpu = MIPS_CPU(cs);

    CPUMIPSState *env = &cpu->env;

    int i;



    cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx

                " LO=0x" TARGET_FMT_lx " ds %04x "

                TARGET_FMT_lx " " TARGET_FMT_ld "\n",

                env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],

                env->hflags, env->btarget, env->bcond);

    for (i = 0; i < 32; i++) {

        if ((i & 3) == 0)

            cpu_fprintf(f, "GPR%02d:", i);

        cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.gpr[i]);

        if ((i & 3) == 3)

            cpu_fprintf(f, "\n");

    }



    cpu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x" TARGET_FMT_lx "\n",

                env->CP0_Status, env->CP0_Cause, env->CP0_EPC);

    cpu_fprintf(f, "    Config0 0x%08x Config1 0x%08x LLAddr 0x%016"

                PRIx64 "\n",

                env->CP0_Config0, env->CP0_Config1, env->lladdr);

    cpu_fprintf(f, "    Config2 0x%08x Config3 0x%08x\n",

                env->CP0_Config2, env->CP0_Config3);

    cpu_fprintf(f, "    Config4 0x%08x Config5 0x%08x\n",

                env->CP0_Config4, env->CP0_Config5);

    if (env->hflags & MIPS_HFLAG_FPU)

        fpu_dump_state(env, f, cpu_fprintf, flags);

#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)

    cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);

#endif

}

void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,

                         int flags)

{

    MIPSCPU *cpu = MIPS_CPU(cs);

    CPUMIPSState *env = &cpu->env;

    int i;



    cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx

                " LO=0x" TARGET_FMT_lx " ds %04x "

                TARGET_FMT_lx " " TARGET_FMT_ld "\n",

                env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],

                env->hflags, env->btarget, env->bcond);

    for (i = 0; i < 32; i++) {

        if ((i & 3) == 0)

            cpu_fprintf(f, "GPR%02d:", i);

        cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.gpr[i]);

        if ((i & 3) == 3)

            cpu_fprintf(f, "\n");

    }



    cpu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x" TARGET_FMT_lx "\n",

                env->CP0_Status, env->CP0_Cause, env->CP0_EPC);

    cpu_fprintf(f, "    Config0 0x%08x Config1 0x%08x LLAddr 0x%016"

                PRIx64 "\n",

                env->CP0_Config0, env->CP0_Config1, env->lladdr);

    cpu_fprintf(f, "    Config2 0x%08x Config3 0x%08x\n",

                env->CP0_Config2, env->CP0_Config3);

    cpu_fprintf(f, "    Config4 0x%08x Config5 0x%08x\n",

                env->CP0_Config4, env->CP0_Config5);

    if (env->hflags & MIPS_HFLAG_FPU)

        fpu_dump_state(env, f, cpu_fprintf, flags);

#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)

    cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);

#endif

}

#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)     int i;     for (i = 0; i < 32; i++) { #endif #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)     cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags); #endif
void FUNC_0(CPUState *VAR_0, FILE *VAR_1, fprintf_function VAR_2,

                         int VAR_3)

{

    MIPSCPU *cpu = MIPS_CPU(VAR_0);

    CPUMIPSState *env = &cpu->env;

    int VAR_4;



    VAR_2(VAR_1, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx

                " LO=0x" TARGET_FMT_lx " ds %04x "

                TARGET_FMT_lx " " TARGET_FMT_ld "\n",

                env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],

                env->hflags, env->btarget, env->bcond);

    for (VAR_4 = 0; VAR_4 < 32; VAR_4++) {

        if ((VAR_4 & 3) == 0)

            VAR_2(VAR_1, "GPR%02d:", VAR_4);

        VAR_2(VAR_1, " %s " TARGET_FMT_lx, regnames[VAR_4], env->active_tc.gpr[VAR_4]);

        if ((VAR_4 & 3) == 3)

            VAR_2(VAR_1, "\n");

    }



    VAR_2(VAR_1, "CP0 Status  0x%08x Cause   0x%08x EPC    0x" TARGET_FMT_lx "\n",

                env->CP0_Status, env->CP0_Cause, env->CP0_EPC);

    VAR_2(VAR_1, "    Config0 0x%08x Config1 0x%08x LLAddr 0x%016"

                PRIx64 "\n",

                env->CP0_Config0, env->CP0_Config1, env->lladdr);

    VAR_2(VAR_1, "    Config2 0x%08x Config3 0x%08x\n",

                env->CP0_Config2, env->CP0_Config3);

    VAR_2(VAR_1, "    Config4 0x%08x Config5 0x%08x\n",

                env->CP0_Config4, env->CP0_Config5);

    if (env->hflags & MIPS_HFLAG_FPU)

        fpu_dump_state(env, VAR_1, VAR_2, VAR_3);

#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)

    cpu_mips_check_sign_extensions(env, VAR_1, VAR_2, VAR_3);

#endif

}

void FUNC_0(CPUState *VAR_0, FILE *VAR_1, fprintf_function VAR_2,
int VAR_3)
{ MIPSCPU *cpu = MIPS_CPU(VAR_0); CPUMIPSState *env = &cpu->env; int VAR_4; VAR_2(VAR_1, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx " ds %04x "
TARGET_FMT_lx " " TARGET_FMT_ld "\n",
env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
env->hflags, env->btarget, env->bcond); for (VAR_4 = 0; VAR_4 < 32; VAR_4++) { if ((VAR_4 & 3) == 0)
VAR_2(VAR_1, "GPR%02d:", VAR_4); VAR_2(VAR_1, " %s " TARGET_FMT_lx, regnames[VAR_4], env->active_tc.gpr[VAR_4]); if ((VAR_4 & 3) == 3)
VAR_2(VAR_1, "\n"); } VAR_2(VAR_1, "CP0 Status  0x%08x Cause   0x%08x EPC    0x" TARGET_FMT_lx "\n",
env->CP0_Status, env->CP0_Cause, env->CP0_EPC); VAR_2(VAR_1, "    Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
PRIx64 "\n",
env->CP0_Config0, env->CP0_Config1, env->lladdr); VAR_2(VAR_1, "    Config2 0x%08x Config3 0x%08x\n",
env->CP0_Config2, env->CP0_Config3); VAR_2(VAR_1, "    Config4 0x%08x Config5 0x%08x\n",
env->CP0_Config4, env->CP0_Config5); if (env->hflags & MIPS_HFLAG_FPU)
fpu_dump_state(env, VAR_1, VAR_2, VAR_3); #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
cpu_mips_check_sign_extensions(env, VAR_1, VAR_2, VAR_3); #endif
}