static void lm32_uclinux_init(MachineState *machine)

{

    const char *cpu_model = machine->cpu_model;

    const char *kernel_filename = machine->kernel_filename;

    const char *kernel_cmdline = machine->kernel_cmdline;

    const char *initrd_filename = machine->initrd_filename;

    LM32CPU *cpu;

    CPULM32State *env;

    DriveInfo *dinfo;

    MemoryRegion *address_space_mem =  get_system_memory();

    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);

    qemu_irq irq[32];

    HWSetup *hw;

    ResetInfo *reset_info;

    int i;



    /* memory map */

    hwaddr flash_base   = 0x04000000;

    size_t flash_sector_size        = 256 * 1024;

    size_t flash_size               = 32 * 1024 * 1024;

    hwaddr ram_base     = 0x08000000;

    size_t ram_size                 = 64 * 1024 * 1024;

    hwaddr uart0_base   = 0x80000000;

    hwaddr timer0_base  = 0x80002000;

    hwaddr timer1_base  = 0x80010000;

    hwaddr timer2_base  = 0x80012000;

    int uart0_irq                   = 0;

    int timer0_irq                  = 1;

    int timer1_irq                  = 20;

    int timer2_irq                  = 21;

    hwaddr hwsetup_base = 0x0bffe000;

    hwaddr cmdline_base = 0x0bfff000;

    hwaddr initrd_base  = 0x08400000;

    size_t initrd_max               = 0x01000000;



    reset_info = g_malloc0(sizeof(ResetInfo));



    if (cpu_model == NULL) {

        cpu_model = "lm32-full";

    }

    cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));

    if (cpu == NULL) {

        fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);

        exit(1);

    }



    env = &cpu->env;

    reset_info->cpu = cpu;



    reset_info->flash_base = flash_base;



    memory_region_allocate_system_memory(phys_ram, NULL,

                                         "lm32_uclinux.sdram", ram_size);

    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);



    dinfo = drive_get(IF_PFLASH, 0, 0);

    /* Spansion S29NS128P */

    pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,

                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,

                          flash_sector_size, flash_size / flash_sector_size,

                          1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);



    /* create irq lines */

    env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));

    for (i = 0; i < 32; i++) {

        irq[i] = qdev_get_gpio_in(env->pic_state, i);

    }



    lm32_uart_create(uart0_base, irq[uart0_irq], serial_hds[0]);

    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);

    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);

    sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);



    /* make sure juart isn't the first chardev */

    env->juart_state = lm32_juart_init(serial_hds[1]);



    reset_info->bootstrap_pc = flash_base;



    if (kernel_filename) {

        uint64_t entry;

        int kernel_size;



        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,

                               1, EM_LATTICEMICO32, 0, 0);

        reset_info->bootstrap_pc = entry;



        if (kernel_size < 0) {

            kernel_size = load_image_targphys(kernel_filename, ram_base,

                                              ram_size);

            reset_info->bootstrap_pc = ram_base;

        }



        if (kernel_size < 0) {

            fprintf(stderr, "qemu: could not load kernel '%s'\n",

                    kernel_filename);

            exit(1);

        }

    }



    /* generate a rom with the hardware description */

    hw = hwsetup_init();

    hwsetup_add_cpu(hw, "LM32", 75000000);

    hwsetup_add_flash(hw, "flash", flash_base, flash_size);

    hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);

    hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);

    hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);

    hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);

    hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);

    hwsetup_add_trailer(hw);

    hwsetup_create_rom(hw, hwsetup_base);

    hwsetup_free(hw);



    reset_info->hwsetup_base = hwsetup_base;



    if (kernel_cmdline && strlen(kernel_cmdline)) {

        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,

                kernel_cmdline);

        reset_info->cmdline_base = cmdline_base;

    }



    if (initrd_filename) {

        size_t initrd_size;

        initrd_size = load_image_targphys(initrd_filename, initrd_base,

                initrd_max);

        reset_info->initrd_base = initrd_base;

        reset_info->initrd_size = initrd_size;

    }



    qemu_register_reset(main_cpu_reset, reset_info);

}

static void lm32_uclinux_init(MachineState *machine)

{

    const char *cpu_model = machine->cpu_model;

    const char *kernel_filename = machine->kernel_filename;

    const char *kernel_cmdline = machine->kernel_cmdline;

    const char *initrd_filename = machine->initrd_filename;

    LM32CPU *cpu;

    CPULM32State *env;

    DriveInfo *dinfo;

    MemoryRegion *address_space_mem =  get_system_memory();

    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);

    qemu_irq irq[32];

    HWSetup *hw;

    ResetInfo *reset_info;

    int i;



    

    hwaddr flash_base   = 0x04000000;

    size_t flash_sector_size        = 256 * 1024;

    size_t flash_size               = 32 * 1024 * 1024;

    hwaddr ram_base     = 0x08000000;

    size_t ram_size                 = 64 * 1024 * 1024;

    hwaddr uart0_base   = 0x80000000;

    hwaddr timer0_base  = 0x80002000;

    hwaddr timer1_base  = 0x80010000;

    hwaddr timer2_base  = 0x80012000;

    int uart0_irq                   = 0;

    int timer0_irq                  = 1;

    int timer1_irq                  = 20;

    int timer2_irq                  = 21;

    hwaddr hwsetup_base = 0x0bffe000;

    hwaddr cmdline_base = 0x0bfff000;

    hwaddr initrd_base  = 0x08400000;

    size_t initrd_max               = 0x01000000;



    reset_info = g_malloc0(sizeof(ResetInfo));



    if (cpu_model == NULL) {

        cpu_model = "lm32-full";

    }

    cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));

    if (cpu == NULL) {

        fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);

        exit(1);

    }



    env = &cpu->env;

    reset_info->cpu = cpu;



    reset_info->flash_base = flash_base;



    memory_region_allocate_system_memory(phys_ram, NULL,

                                         "lm32_uclinux.sdram", ram_size);

    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);



    dinfo = drive_get(IF_PFLASH, 0, 0);

    

    pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,

                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,

                          flash_sector_size, flash_size / flash_sector_size,

                          1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);



    

    env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));

    for (i = 0; i < 32; i++) {

        irq[i] = qdev_get_gpio_in(env->pic_state, i);

    }



    lm32_uart_create(uart0_base, irq[uart0_irq], serial_hds[0]);

    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);

    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);

    sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);



    

    env->juart_state = lm32_juart_init(serial_hds[1]);



    reset_info->bootstrap_pc = flash_base;



    if (kernel_filename) {

        uint64_t entry;

        int kernel_size;



        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,

                               1, EM_LATTICEMICO32, 0, 0);

        reset_info->bootstrap_pc = entry;



        if (kernel_size < 0) {

            kernel_size = load_image_targphys(kernel_filename, ram_base,

                                              ram_size);

            reset_info->bootstrap_pc = ram_base;

        }



        if (kernel_size < 0) {

            fprintf(stderr, "qemu: could not load kernel '%s'\n",

                    kernel_filename);

            exit(1);

        }

    }



    

    hw = hwsetup_init();

    hwsetup_add_cpu(hw, "LM32", 75000000);

    hwsetup_add_flash(hw, "flash", flash_base, flash_size);

    hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);

    hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);

    hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);

    hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);

    hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);

    hwsetup_add_trailer(hw);

    hwsetup_create_rom(hw, hwsetup_base);

    hwsetup_free(hw);



    reset_info->hwsetup_base = hwsetup_base;



    if (kernel_cmdline && strlen(kernel_cmdline)) {

        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,

                kernel_cmdline);

        reset_info->cmdline_base = cmdline_base;

    }



    if (initrd_filename) {

        size_t initrd_size;

        initrd_size = load_image_targphys(initrd_filename, initrd_base,

                initrd_max);

        reset_info->initrd_base = initrd_base;

        reset_info->initrd_size = initrd_size;

    }



    qemu_register_reset(main_cpu_reset, reset_info);

}

        exit(1);             exit(1);         exit(1);         exit(1);         exit(1);         exit(1);         exit(1);         exit(1);     if (cpu == NULL) {         fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);         exit(1);     if (cpu == NULL) {         fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);         exit(1);     if (cpu == NULL) {         fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);         exit(1);         exit(1);         exit(1);     if (cpu == NULL) {         exit(1);     if (cpu == NULL) {         exit(1);             exit(1);     if (cpu == NULL) {         exit(1);     if (cpu == NULL) {         exit(1);         exit(1);             exit(1);             exit(1);             exit(1);             exit(1);     if (cpu == NULL) {         exit(1);     if (cpu == NULL) {         exit(1);             exit(1);         exit(1);     if (cpu == NULL) {         exit(1);     if (cpu == NULL) {         exit(1);     if (cpu == NULL) {         exit(1);     if (cpu == NULL) {         exit(1);     if (cpu == NULL) {         exit(1);     if (cpu == NULL) {         exit(1);         exit(1);         exit(1);
static void FUNC_0(MachineState *VAR_0)

{

    const char *VAR_1 = VAR_0->VAR_1;

    const char *VAR_2 = VAR_0->VAR_2;

    const char *VAR_3 = VAR_0->VAR_3;

    const char *VAR_4 = VAR_0->VAR_4;

    LM32CPU *cpu;

    CPULM32State *env;

    DriveInfo *dinfo;

    MemoryRegion *address_space_mem =  get_system_memory();

    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);

    qemu_irq irq[32];

    HWSetup *hw;

    ResetInfo *reset_info;

    int VAR_5;



    

    hwaddr flash_base   = 0x04000000;

    size_t flash_sector_size        = 256 * 1024;

    size_t flash_size               = 32 * 1024 * 1024;

    hwaddr ram_base     = 0x08000000;

    size_t ram_size                 = 64 * 1024 * 1024;

    hwaddr uart0_base   = 0x80000000;

    hwaddr timer0_base  = 0x80002000;

    hwaddr timer1_base  = 0x80010000;

    hwaddr timer2_base  = 0x80012000;

    int VAR_6                   = 0;

    int VAR_7                  = 1;

    int VAR_8                  = 20;

    int VAR_9                  = 21;

    hwaddr hwsetup_base = 0x0bffe000;

    hwaddr cmdline_base = 0x0bfff000;

    hwaddr initrd_base  = 0x08400000;

    size_t initrd_max               = 0x01000000;



    reset_info = g_malloc0(sizeof(ResetInfo));



    if (VAR_1 == NULL) {

        VAR_1 = "lm32-full";

    }

    cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, VAR_1));

    if (cpu == NULL) {

        fprintf(stderr, "qemu: unable to find CPU '%s'\n", VAR_1);

        exit(1);

    }



    env = &cpu->env;

    reset_info->cpu = cpu;



    reset_info->flash_base = flash_base;



    memory_region_allocate_system_memory(phys_ram, NULL,

                                         "lm32_uclinux.sdram", ram_size);

    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);



    dinfo = drive_get(IF_PFLASH, 0, 0);

    

    pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,

                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,

                          flash_sector_size, flash_size / flash_sector_size,

                          1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);



    

    env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));

    for (VAR_5 = 0; VAR_5 < 32; VAR_5++) {

        irq[VAR_5] = qdev_get_gpio_in(env->pic_state, VAR_5);

    }



    lm32_uart_create(uart0_base, irq[VAR_6], serial_hds[0]);

    sysbus_create_simple("lm32-timer", timer0_base, irq[VAR_7]);

    sysbus_create_simple("lm32-timer", timer1_base, irq[VAR_8]);

    sysbus_create_simple("lm32-timer", timer2_base, irq[VAR_9]);



    

    env->juart_state = lm32_juart_init(serial_hds[1]);



    reset_info->bootstrap_pc = flash_base;



    if (VAR_2) {

        uint64_t entry;

        int VAR_10;



        VAR_10 = load_elf(VAR_2, NULL, NULL, &entry, NULL, NULL,

                               1, EM_LATTICEMICO32, 0, 0);

        reset_info->bootstrap_pc = entry;



        if (VAR_10 < 0) {

            VAR_10 = load_image_targphys(VAR_2, ram_base,

                                              ram_size);

            reset_info->bootstrap_pc = ram_base;

        }



        if (VAR_10 < 0) {

            fprintf(stderr, "qemu: could not load kernel '%s'\n",

                    VAR_2);

            exit(1);

        }

    }



    

    hw = hwsetup_init();

    hwsetup_add_cpu(hw, "LM32", 75000000);

    hwsetup_add_flash(hw, "flash", flash_base, flash_size);

    hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);

    hwsetup_add_timer(hw, "timer0", timer0_base, VAR_7);

    hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, VAR_8);

    hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, VAR_9);

    hwsetup_add_uart(hw, "uart", uart0_base, VAR_6);

    hwsetup_add_trailer(hw);

    hwsetup_create_rom(hw, hwsetup_base);

    hwsetup_free(hw);



    reset_info->hwsetup_base = hwsetup_base;



    if (VAR_3 && strlen(VAR_3)) {

        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,

                VAR_3);

        reset_info->cmdline_base = cmdline_base;

    }



    if (VAR_4) {

        size_t initrd_size;

        initrd_size = load_image_targphys(VAR_4, initrd_base,

                initrd_max);

        reset_info->initrd_base = initrd_base;

        reset_info->initrd_size = initrd_size;

    }



    qemu_register_reset(main_cpu_reset, reset_info);

}

static void FUNC_0(MachineState *VAR_0)
{ const char *VAR_1 = VAR_0->VAR_1; const char *VAR_2 = VAR_0->VAR_2; const char *VAR_3 = VAR_0->VAR_3; const char *VAR_4 = VAR_0->VAR_4; LM32CPU *cpu; CPULM32State *env; DriveInfo *dinfo; MemoryRegion *address_space_mem =  get_system_memory(); MemoryRegion *phys_ram = g_new(MemoryRegion, 1); qemu_irq irq[32]; HWSetup *hw; ResetInfo *reset_info; int VAR_5; hwaddr flash_base   = 0x04000000; size_t flash_sector_size        = 256 * 1024; size_t flash_size               = 32 * 1024 * 1024; hwaddr ram_base     = 0x08000000; size_t ram_size                 = 64 * 1024 * 1024; hwaddr uart0_base   = 0x80000000; hwaddr timer0_base  = 0x80002000; hwaddr timer1_base  = 0x80010000; hwaddr timer2_base  = 0x80012000; int VAR_6                   = 0; int VAR_7                  = 1; int VAR_8                  = 20; int VAR_9                  = 21; hwaddr hwsetup_base = 0x0bffe000; hwaddr cmdline_base = 0x0bfff000; hwaddr initrd_base  = 0x08400000; size_t initrd_max               = 0x01000000; reset_info = g_malloc0(sizeof(ResetInfo)); if (VAR_1 == NULL) { VAR_1 = "lm32-full"; } cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, VAR_1)); if (cpu == NULL) { fprintf(stderr, "qemu: unable to find CPU '%s'\n", VAR_1); exit(1); } env = &cpu->env; reset_info->cpu = cpu; reset_info->flash_base = flash_base; memory_region_allocate_system_memory(phys_ram, NULL,
"lm32_uclinux.sdram", ram_size); memory_region_add_subregion(address_space_mem, ram_base, phys_ram); dinfo = drive_get(IF_PFLASH, 0, 0); pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
flash_sector_size, flash_size / flash_sector_size,
1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0)); for (VAR_5 = 0; VAR_5 < 32; VAR_5++) { irq[VAR_5] = qdev_get_gpio_in(env->pic_state, VAR_5); } lm32_uart_create(uart0_base, irq[VAR_6], serial_hds[0]); sysbus_create_simple("lm32-timer", timer0_base, irq[VAR_7]); sysbus_create_simple("lm32-timer", timer1_base, irq[VAR_8]); sysbus_create_simple("lm32-timer", timer2_base, irq[VAR_9]); env->juart_state = lm32_juart_init(serial_hds[1]); reset_info->bootstrap_pc = flash_base; if (VAR_2) { uint64_t entry; int VAR_10; VAR_10 = load_elf(VAR_2, NULL, NULL, &entry, NULL, NULL,
1, EM_LATTICEMICO32, 0, 0); reset_info->bootstrap_pc = entry; if (VAR_10 < 0) { VAR_10 = load_image_targphys(VAR_2, ram_base,
ram_size); reset_info->bootstrap_pc = ram_base; } if (VAR_10 < 0) { fprintf(stderr, "qemu: could not load kernel '%s'\n",
VAR_2); exit(1); } } hw = hwsetup_init(); hwsetup_add_cpu(hw, "LM32", 75000000); hwsetup_add_flash(hw, "flash", flash_base, flash_size); hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size); hwsetup_add_timer(hw, "timer0", timer0_base, VAR_7); hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, VAR_8); hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, VAR_9); hwsetup_add_uart(hw, "uart", uart0_base, VAR_6); hwsetup_add_trailer(hw); hwsetup_create_rom(hw, hwsetup_base); hwsetup_free(hw); reset_info->hwsetup_base = hwsetup_base; if (VAR_3 && strlen(VAR_3)) { pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
VAR_3); reset_info->cmdline_base = cmdline_base; } if (VAR_4) { size_t initrd_size; initrd_size = load_image_targphys(VAR_4, initrd_base,
initrd_max); reset_info->initrd_base = initrd_base; reset_info->initrd_size = initrd_size; } qemu_register_reset(main_cpu_reset, reset_info); }