static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,

                                int rw, int tlb_error)

{

    CPUState *cs = CPU(mips_env_get_cpu(env));

    int exception = 0, error_code = 0;



    switch (tlb_error) {

    default:

    case TLBRET_BADADDR:

        /* Reference to kernel address from user mode or supervisor mode */

        /* Reference to supervisor address from user mode */

        if (rw == MMU_DATA_STORE) {

            exception = EXCP_AdES;

        } else {

            exception = EXCP_AdEL;

        }

        break;

    case TLBRET_NOMATCH:

        /* No TLB match for a mapped address */

        if (rw == MMU_DATA_STORE) {

            exception = EXCP_TLBS;

        } else {

            exception = EXCP_TLBL;

        }

        error_code = 1;

        break;

    case TLBRET_INVALID:

        /* TLB match with no valid bit */

        if (rw == MMU_DATA_STORE) {

            exception = EXCP_TLBS;

        } else {

            exception = EXCP_TLBL;

        }

        break;

    case TLBRET_DIRTY:

        /* TLB match but 'D' bit is cleared */

        exception = EXCP_LTLBL;

        break;

    case TLBRET_XI:

        /* Execute-Inhibit Exception */

        if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {

            exception = EXCP_TLBXI;

        } else {

            exception = EXCP_TLBL;

        }

        break;

    case TLBRET_RI:

        /* Read-Inhibit Exception */

        if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {

            exception = EXCP_TLBRI;

        } else {

            exception = EXCP_TLBL;

        }

        break;

    }

    /* Raise exception */

    env->CP0_BadVAddr = address;

    env->CP0_Context = (env->CP0_Context & ~0x007fffff) |

                       ((address >> 9) & 0x007ffff0);

    env->CP0_EntryHi =

        (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));

#if defined(TARGET_MIPS64)

    env->CP0_EntryHi &= env->SEGMask;

    env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |

                        ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |

                        ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);

#endif

    cs->exception_index = exception;

    env->error_code = error_code;

}

static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,

                                int rw, int tlb_error)

{

    CPUState *cs = CPU(mips_env_get_cpu(env));

    int exception = 0, error_code = 0;



    switch (tlb_error) {

    default:

    case TLBRET_BADADDR:

        

        

        if (rw == MMU_DATA_STORE) {

            exception = EXCP_AdES;

        } else {

            exception = EXCP_AdEL;

        }

        break;

    case TLBRET_NOMATCH:

        

        if (rw == MMU_DATA_STORE) {

            exception = EXCP_TLBS;

        } else {

            exception = EXCP_TLBL;

        }

        error_code = 1;

        break;

    case TLBRET_INVALID:

        

        if (rw == MMU_DATA_STORE) {

            exception = EXCP_TLBS;

        } else {

            exception = EXCP_TLBL;

        }

        break;

    case TLBRET_DIRTY:

        

        exception = EXCP_LTLBL;

        break;

    case TLBRET_XI:

        

        if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {

            exception = EXCP_TLBXI;

        } else {

            exception = EXCP_TLBL;

        }

        break;

    case TLBRET_RI:

        

        if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {

            exception = EXCP_TLBRI;

        } else {

            exception = EXCP_TLBL;

        }

        break;

    }

    

    env->CP0_BadVAddr = address;

    env->CP0_Context = (env->CP0_Context & ~0x007fffff) |

                       ((address >> 9) & 0x007ffff0);

    env->CP0_EntryHi =

        (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));

#if defined(TARGET_MIPS64)

    env->CP0_EntryHi &= env->SEGMask;

    env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |

                        ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |

                        ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);

#endif

    cs->exception_index = exception;

    env->error_code = error_code;

}

static void FUNC_0(CPUMIPSState *VAR_0, target_ulong VAR_1,

                                int VAR_2, int VAR_3)

{

    CPUState *cs = CPU(mips_env_get_cpu(VAR_0));

    int VAR_4 = 0, VAR_5 = 0;



    switch (VAR_3) {

    default:

    case TLBRET_BADADDR:

        

        

        if (VAR_2 == MMU_DATA_STORE) {

            VAR_4 = EXCP_AdES;

        } else {

            VAR_4 = EXCP_AdEL;

        }

        break;

    case TLBRET_NOMATCH:

        

        if (VAR_2 == MMU_DATA_STORE) {

            VAR_4 = EXCP_TLBS;

        } else {

            VAR_4 = EXCP_TLBL;

        }

        VAR_5 = 1;

        break;

    case TLBRET_INVALID:

        

        if (VAR_2 == MMU_DATA_STORE) {

            VAR_4 = EXCP_TLBS;

        } else {

            VAR_4 = EXCP_TLBL;

        }

        break;

    case TLBRET_DIRTY:

        

        VAR_4 = EXCP_LTLBL;

        break;

    case TLBRET_XI:

        

        if (VAR_0->CP0_PageGrain & (1 << CP0PG_IEC)) {

            VAR_4 = EXCP_TLBXI;

        } else {

            VAR_4 = EXCP_TLBL;

        }

        break;

    case TLBRET_RI:

        

        if (VAR_0->CP0_PageGrain & (1 << CP0PG_IEC)) {

            VAR_4 = EXCP_TLBRI;

        } else {

            VAR_4 = EXCP_TLBL;

        }

        break;

    }

    

    VAR_0->CP0_BadVAddr = VAR_1;

    VAR_0->CP0_Context = (VAR_0->CP0_Context & ~0x007fffff) |

                       ((VAR_1 >> 9) & 0x007ffff0);

    VAR_0->CP0_EntryHi =

        (VAR_0->CP0_EntryHi & 0xFF) | (VAR_1 & (TARGET_PAGE_MASK << 1));

#if defined(TARGET_MIPS64)

    VAR_0->CP0_EntryHi &= VAR_0->SEGMask;

    VAR_0->CP0_XContext = (VAR_0->CP0_XContext & ((~0ULL) << (VAR_0->SEGBITS - 7))) |

                        ((VAR_1 & 0xC00000000000ULL) >> (55 - VAR_0->SEGBITS)) |

                        ((VAR_1 & ((1ULL << VAR_0->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);

#endif

    cs->exception_index = VAR_4;

    VAR_0->VAR_5 = VAR_5;

}

static void FUNC_0(CPUMIPSState *VAR_0, target_ulong VAR_1,
int VAR_2, int VAR_3)
{ CPUState *cs = CPU(mips_env_get_cpu(VAR_0)); int VAR_4 = 0, VAR_5 = 0; switch (VAR_3) { default:
case TLBRET_BADADDR:
if (VAR_2 == MMU_DATA_STORE) { VAR_4 = EXCP_AdES; } else { VAR_4 = EXCP_AdEL; } break; case TLBRET_NOMATCH:
if (VAR_2 == MMU_DATA_STORE) { VAR_4 = EXCP_TLBS; } else { VAR_4 = EXCP_TLBL; } VAR_5 = 1; break; case TLBRET_INVALID:
if (VAR_2 == MMU_DATA_STORE) { VAR_4 = EXCP_TLBS; } else { VAR_4 = EXCP_TLBL; } break; case TLBRET_DIRTY:
VAR_4 = EXCP_LTLBL; break; case TLBRET_XI:
if (VAR_0->CP0_PageGrain & (1 << CP0PG_IEC)) { VAR_4 = EXCP_TLBXI; } else { VAR_4 = EXCP_TLBL; } break; case TLBRET_RI:
if (VAR_0->CP0_PageGrain & (1 << CP0PG_IEC)) { VAR_4 = EXCP_TLBRI; } else { VAR_4 = EXCP_TLBL; } break; } VAR_0->CP0_BadVAddr = VAR_1; VAR_0->CP0_Context = (VAR_0->CP0_Context & ~0x007fffff) |
((VAR_1 >> 9) & 0x007ffff0); VAR_0->CP0_EntryHi =
(VAR_0->CP0_EntryHi & 0xFF) | (VAR_1 & (TARGET_PAGE_MASK << 1)); #if defined(TARGET_MIPS64)
VAR_0->CP0_EntryHi &= VAR_0->SEGMask; VAR_0->CP0_XContext = (VAR_0->CP0_XContext & ((~0ULL) << (VAR_0->SEGBITS - 7))) |
((VAR_1 & 0xC00000000000ULL) >> (55 - VAR_0->SEGBITS)) |
((VAR_1 & ((1ULL << VAR_0->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); #endif
cs->exception_index = VAR_4; VAR_0->VAR_5 = VAR_5; }