void gic_update(GICState *s)

{

    int best_irq;

    int best_prio;

    int irq;

    int level;

    int cpu;

    int cm;



    for (cpu = 0; cpu < NUM_CPU(s); cpu++) {

        cm = 1 << cpu;

        s->current_pending[cpu] = 1023;

        if (!s->enabled || !s->cpu_enabled[cpu]) {

            qemu_irq_lower(s->parent_irq[cpu]);

            return;

        }

        best_prio = 0x100;

        best_irq = 1023;

        for (irq = 0; irq < s->num_irq; irq++) {

            if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) &&

                (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) {

                if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {

                    best_prio = GIC_GET_PRIORITY(irq, cpu);

                    best_irq = irq;

                }

            }

        }

        level = 0;

        if (best_prio < s->priority_mask[cpu]) {

            s->current_pending[cpu] = best_irq;

            if (best_prio < s->running_priority[cpu]) {

                DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu);

                level = 1;

            }

        }

        qemu_set_irq(s->parent_irq[cpu], level);

    }

}

void gic_update(GICState *s)

{

    int best_irq;

    int best_prio;

    int irq;

    int level;

    int cpu;

    int cm;



    for (cpu = 0; cpu < NUM_CPU(s); cpu++) {

        cm = 1 << cpu;

        s->current_pending[cpu] = 1023;

        if (!s->enabled || !s->cpu_enabled[cpu]) {

            qemu_irq_lower(s->parent_irq[cpu]);

            return;

        }

        best_prio = 0x100;

        best_irq = 1023;

        for (irq = 0; irq < s->num_irq; irq++) {

            if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) &&

                (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) {

                if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {

                    best_prio = GIC_GET_PRIORITY(irq, cpu);

                    best_irq = irq;

                }

            }

        }

        level = 0;

        if (best_prio < s->priority_mask[cpu]) {

            s->current_pending[cpu] = best_irq;

            if (best_prio < s->running_priority[cpu]) {

                DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu);

                level = 1;

            }

        }

        qemu_set_irq(s->parent_irq[cpu], level);

    }

}

void FUNC_0(GICState *VAR_0)

{

    int VAR_1;

    int VAR_2;

    int VAR_3;

    int VAR_4;

    int VAR_5;

    int VAR_6;



    for (VAR_5 = 0; VAR_5 < NUM_CPU(VAR_0); VAR_5++) {

        VAR_6 = 1 << VAR_5;

        VAR_0->current_pending[VAR_5] = 1023;

        if (!VAR_0->enabled || !VAR_0->cpu_enabled[VAR_5]) {

            qemu_irq_lower(VAR_0->parent_irq[VAR_5]);

            return;

        }

        VAR_2 = 0x100;

        VAR_1 = 1023;

        for (VAR_3 = 0; VAR_3 < VAR_0->num_irq; VAR_3++) {

            if (GIC_TEST_ENABLED(VAR_3, VAR_6) && gic_test_pending(VAR_0, VAR_3, VAR_6) &&

                (VAR_3 < GIC_INTERNAL || GIC_TARGET(VAR_3) & VAR_6)) {

                if (GIC_GET_PRIORITY(VAR_3, VAR_5) < VAR_2) {

                    VAR_2 = GIC_GET_PRIORITY(VAR_3, VAR_5);

                    VAR_1 = VAR_3;

                }

            }

        }

        VAR_4 = 0;

        if (VAR_2 < VAR_0->priority_mask[VAR_5]) {

            VAR_0->current_pending[VAR_5] = VAR_1;

            if (VAR_2 < VAR_0->running_priority[VAR_5]) {

                DPRINTF("Raised pending IRQ %d (VAR_5 %d)\n", VAR_1, VAR_5);

                VAR_4 = 1;

            }

        }

        qemu_set_irq(VAR_0->parent_irq[VAR_5], VAR_4);

    }

}

void FUNC_0(GICState *VAR_0)
{ int VAR_1; int VAR_2; int VAR_3; int VAR_4; int VAR_5; int VAR_6; for (VAR_5 = 0; VAR_5 < NUM_CPU(VAR_0); VAR_5++) { VAR_6 = 1 << VAR_5; VAR_0->current_pending[VAR_5] = 1023; if (!VAR_0->enabled || !VAR_0->cpu_enabled[VAR_5]) { qemu_irq_lower(VAR_0->parent_irq[VAR_5]); return; } VAR_2 = 0x100; VAR_1 = 1023; for (VAR_3 = 0; VAR_3 < VAR_0->num_irq; VAR_3++) { if (GIC_TEST_ENABLED(VAR_3, VAR_6) && gic_test_pending(VAR_0, VAR_3, VAR_6) &&
(VAR_3 < GIC_INTERNAL || GIC_TARGET(VAR_3) & VAR_6)) { if (GIC_GET_PRIORITY(VAR_3, VAR_5) < VAR_2) { VAR_2 = GIC_GET_PRIORITY(VAR_3, VAR_5); VAR_1 = VAR_3; } } } VAR_4 = 0; if (VAR_2 < VAR_0->priority_mask[VAR_5]) { VAR_0->current_pending[VAR_5] = VAR_1; if (VAR_2 < VAR_0->running_priority[VAR_5]) { DPRINTF("Raised pending IRQ %d (VAR_5 %d)\n", VAR_1, VAR_5); VAR_4 = 1; } } qemu_set_irq(VAR_0->parent_irq[VAR_5], VAR_4); } }