static void pci_device_reset(PCIDevice *dev)

{

    int r;



    dev->irq_state = 0;

    pci_update_irq_status(dev);

    /* Clear all writeable bits */

    pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,

                                 pci_get_word(dev->wmask + PCI_COMMAND));

    dev->config[PCI_CACHE_LINE_SIZE] = 0x0;

    dev->config[PCI_INTERRUPT_LINE] = 0x0;

    for (r = 0; r < PCI_NUM_REGIONS; ++r) {

        PCIIORegion *region = &dev->io_regions[r];

        if (!region->size) {

            continue;

        }



        if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&

            region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {

            pci_set_quad(dev->config + pci_bar(dev, r), region->type);

        } else {

            pci_set_long(dev->config + pci_bar(dev, r), region->type);

        }

    }

    pci_update_mappings(dev);

}

static void pci_device_reset(PCIDevice *dev)

{

    int r;



    dev->irq_state = 0;

    pci_update_irq_status(dev);

    

    pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,

                                 pci_get_word(dev->wmask + PCI_COMMAND));

    dev->config[PCI_CACHE_LINE_SIZE] = 0x0;

    dev->config[PCI_INTERRUPT_LINE] = 0x0;

    for (r = 0; r < PCI_NUM_REGIONS; ++r) {

        PCIIORegion *region = &dev->io_regions[r];

        if (!region->size) {

            continue;

        }



        if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&

            region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {

            pci_set_quad(dev->config + pci_bar(dev, r), region->type);

        } else {

            pci_set_long(dev->config + pci_bar(dev, r), region->type);

        }

    }

    pci_update_mappings(dev);

}

static void FUNC_0(PCIDevice *VAR_0)

{

    int VAR_1;



    VAR_0->irq_state = 0;

    pci_update_irq_status(VAR_0);

    

    pci_word_test_and_clear_mask(VAR_0->config + PCI_COMMAND,

                                 pci_get_word(VAR_0->wmask + PCI_COMMAND));

    VAR_0->config[PCI_CACHE_LINE_SIZE] = 0x0;

    VAR_0->config[PCI_INTERRUPT_LINE] = 0x0;

    for (VAR_1 = 0; VAR_1 < PCI_NUM_REGIONS; ++VAR_1) {

        PCIIORegion *region = &VAR_0->io_regions[VAR_1];

        if (!region->size) {

            continue;

        }



        if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&

            region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {

            pci_set_quad(VAR_0->config + pci_bar(VAR_0, VAR_1), region->type);

        } else {

            pci_set_long(VAR_0->config + pci_bar(VAR_0, VAR_1), region->type);

        }

    }

    pci_update_mappings(VAR_0);

}

static void FUNC_0(PCIDevice *VAR_0)
{ int VAR_1; VAR_0->irq_state = 0; pci_update_irq_status(VAR_0); pci_word_test_and_clear_mask(VAR_0->config + PCI_COMMAND,
pci_get_word(VAR_0->wmask + PCI_COMMAND)); VAR_0->config[PCI_CACHE_LINE_SIZE] = 0x0; VAR_0->config[PCI_INTERRUPT_LINE] = 0x0; for (VAR_1 = 0; VAR_1 < PCI_NUM_REGIONS; ++VAR_1) { PCIIORegion *region = &VAR_0->io_regions[VAR_1]; if (!region->size) { continue; } if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { pci_set_quad(VAR_0->config + pci_bar(VAR_0, VAR_1), region->type); } else { pci_set_long(VAR_0->config + pci_bar(VAR_0, VAR_1), region->type); } } pci_update_mappings(VAR_0); }