void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64)

{

    int i, fpus, fptag, nb_xmm_regs;

    floatx80 tmp;

    target_ulong addr;



    /* The operand must be 16 byte aligned */

    if (ptr & 0xf) {

        raise_exception(env, EXCP0D_GPF);

    }



    env->fpuc = cpu_lduw_data(env, ptr);

    fpus = cpu_lduw_data(env, ptr + 2);

    fptag = cpu_lduw_data(env, ptr + 4);

    env->fpstt = (fpus >> 11) & 7;

    env->fpus = fpus & ~0x3800;

    fptag ^= 0xff;

    for (i = 0; i < 8; i++) {

        env->fptags[i] = ((fptag >> i) & 1);

    }



    addr = ptr + 0x20;

    for (i = 0; i < 8; i++) {

        tmp = helper_fldt(env, addr);

        ST(i) = tmp;

        addr += 16;

    }



    if (env->cr[4] & CR4_OSFXSR_MASK) {

        /* XXX: finish it */

        env->mxcsr = cpu_ldl_data(env, ptr + 0x18);

        /* cpu_ldl_data(env, ptr + 0x1c); */

        if (env->hflags & HF_CS64_MASK) {

            nb_xmm_regs = 16;

        } else {

            nb_xmm_regs = 8;

        }

        addr = ptr + 0xa0;

        /* Fast FXRESTORE leaves out the XMM registers */

        if (!(env->efer & MSR_EFER_FFXSR)

            || (env->hflags & HF_CPL_MASK)

            || !(env->hflags & HF_LMA_MASK)) {

            for (i = 0; i < nb_xmm_regs; i++) {

                env->xmm_regs[i].XMM_Q(0) = cpu_ldq_data(env, addr);

                env->xmm_regs[i].XMM_Q(1) = cpu_ldq_data(env, addr + 8);

                addr += 16;

            }

        }

    }

}

void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64)

{

    int i, fpus, fptag, nb_xmm_regs;

    floatx80 tmp;

    target_ulong addr;



    

    if (ptr & 0xf) {

        raise_exception(env, EXCP0D_GPF);

    }



    env->fpuc = cpu_lduw_data(env, ptr);

    fpus = cpu_lduw_data(env, ptr + 2);

    fptag = cpu_lduw_data(env, ptr + 4);

    env->fpstt = (fpus >> 11) & 7;

    env->fpus = fpus & ~0x3800;

    fptag ^= 0xff;

    for (i = 0; i < 8; i++) {

        env->fptags[i] = ((fptag >> i) & 1);

    }



    addr = ptr + 0x20;

    for (i = 0; i < 8; i++) {

        tmp = helper_fldt(env, addr);

        ST(i) = tmp;

        addr += 16;

    }



    if (env->cr[4] & CR4_OSFXSR_MASK) {

        

        env->mxcsr = cpu_ldl_data(env, ptr + 0x18);

        

        if (env->hflags & HF_CS64_MASK) {

            nb_xmm_regs = 16;

        } else {

            nb_xmm_regs = 8;

        }

        addr = ptr + 0xa0;

        

        if (!(env->efer & MSR_EFER_FFXSR)

            || (env->hflags & HF_CPL_MASK)

            || !(env->hflags & HF_LMA_MASK)) {

            for (i = 0; i < nb_xmm_regs; i++) {

                env->xmm_regs[i].XMM_Q(0) = cpu_ldq_data(env, addr);

                env->xmm_regs[i].XMM_Q(1) = cpu_ldq_data(env, addr + 8);

                addr += 16;

            }

        }

    }

}

        env->mxcsr = cpu_ldl_data(env, ptr + 0x18);
void FUNC_0(CPUX86State *VAR_0, target_ulong VAR_1, int VAR_2)

{

    int VAR_3, VAR_4, VAR_5, VAR_6;

    floatx80 tmp;

    target_ulong addr;



    

    if (VAR_1 & 0xf) {

        raise_exception(VAR_0, EXCP0D_GPF);

    }



    VAR_0->fpuc = cpu_lduw_data(VAR_0, VAR_1);

    VAR_4 = cpu_lduw_data(VAR_0, VAR_1 + 2);

    VAR_5 = cpu_lduw_data(VAR_0, VAR_1 + 4);

    VAR_0->fpstt = (VAR_4 >> 11) & 7;

    VAR_0->VAR_4 = VAR_4 & ~0x3800;

    VAR_5 ^= 0xff;

    for (VAR_3 = 0; VAR_3 < 8; VAR_3++) {

        VAR_0->fptags[VAR_3] = ((VAR_5 >> VAR_3) & 1);

    }



    addr = VAR_1 + 0x20;

    for (VAR_3 = 0; VAR_3 < 8; VAR_3++) {

        tmp = helper_fldt(VAR_0, addr);

        ST(VAR_3) = tmp;

        addr += 16;

    }



    if (VAR_0->cr[4] & CR4_OSFXSR_MASK) {

        

        VAR_0->mxcsr = cpu_ldl_data(VAR_0, VAR_1 + 0x18);

        

        if (VAR_0->hflags & HF_CS64_MASK) {

            VAR_6 = 16;

        } else {

            VAR_6 = 8;

        }

        addr = VAR_1 + 0xa0;

        

        if (!(VAR_0->efer & MSR_EFER_FFXSR)

            || (VAR_0->hflags & HF_CPL_MASK)

            || !(VAR_0->hflags & HF_LMA_MASK)) {

            for (VAR_3 = 0; VAR_3 < VAR_6; VAR_3++) {

                VAR_0->xmm_regs[VAR_3].XMM_Q(0) = cpu_ldq_data(VAR_0, addr);

                VAR_0->xmm_regs[VAR_3].XMM_Q(1) = cpu_ldq_data(VAR_0, addr + 8);

                addr += 16;

            }

        }

    }

}

void FUNC_0(CPUX86State *VAR_0, target_ulong VAR_1, int VAR_2)
{ int VAR_3, VAR_4, VAR_5, VAR_6; floatx80 tmp; target_ulong addr; if (VAR_1 & 0xf) { raise_exception(VAR_0, EXCP0D_GPF); } VAR_0->fpuc = cpu_lduw_data(VAR_0, VAR_1); VAR_4 = cpu_lduw_data(VAR_0, VAR_1 + 2); VAR_5 = cpu_lduw_data(VAR_0, VAR_1 + 4); VAR_0->fpstt = (VAR_4 >> 11) & 7; VAR_0->VAR_4 = VAR_4 & ~0x3800; VAR_5 ^= 0xff; for (VAR_3 = 0; VAR_3 < 8; VAR_3++) { VAR_0->fptags[VAR_3] = ((VAR_5 >> VAR_3) & 1); } addr = VAR_1 + 0x20; for (VAR_3 = 0; VAR_3 < 8; VAR_3++) { tmp = helper_fldt(VAR_0, addr); ST(VAR_3) = tmp; addr += 16; } if (VAR_0->cr[4] & CR4_OSFXSR_MASK) { VAR_0->mxcsr = cpu_ldl_data(VAR_0, VAR_1 + 0x18); if (VAR_0->hflags & HF_CS64_MASK) { VAR_6 = 16; } else { VAR_6 = 8; } addr = VAR_1 + 0xa0; if (!(VAR_0->efer & MSR_EFER_FFXSR)
|| (VAR_0->hflags & HF_CPL_MASK)
|| !(VAR_0->hflags & HF_LMA_MASK)) { for (VAR_3 = 0; VAR_3 < VAR_6; VAR_3++) { VAR_0->xmm_regs[VAR_3].XMM_Q(0) = cpu_ldq_data(VAR_0, addr); VAR_0->xmm_regs[VAR_3].XMM_Q(1) = cpu_ldq_data(VAR_0, addr + 8); addr += 16; } } } }