static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
{
    struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
    uint32_t ret;
    int bank;
    offset -= s->base;
    if (offset >= 0x200)
        return 0;
    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        return s->dir[bank];
    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        return s->rising[bank];
    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        return s->falling[bank];
    case GAFR_L:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2];
    case GAFR_U:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2 + 1];
    case GPLR:		/* GPIO Pin-Level registers */
        ret = (s->olevel[bank] & s->dir[bank]) |
                (s->ilevel[bank] & ~s->dir[bank]);
        if (s->read_notify)
            s->read_notify(s->opaque);
        return ret;
    case GEDR:		/* GPIO Edge Detect Status registers */
        return s->status[bank];
    default:
        cpu_abort(cpu_single_env,
                "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }
    return 0;
}
static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
{
    struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
    uint32_t ret;
    int bank;
    offset -= s->base;
    if (offset >= 0x200)
        return 0;
    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		
        return s->dir[bank];
    case GRER:		
        return s->rising[bank];
    case GFER:		
        return s->falling[bank];
    case GAFR_L:	
        return s->gafr[bank * 2];
    case GAFR_U:	
        return s->gafr[bank * 2 + 1];
    case GPLR:		
        ret = (s->olevel[bank] & s->dir[bank]) |
                (s->ilevel[bank] & ~s->dir[bank]);
        if (s->read_notify)
            s->read_notify(s->opaque);
        return ret;
    case GEDR:		
        return s->status[bank];
    default:
        cpu_abort(cpu_single_env,
                "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }
    return 0;
}
static uint32_t FUNC_0(void *opaque, target_phys_addr_t offset)
{
    struct pxa2xx_gpio_info_s *VAR_0 = (struct pxa2xx_gpio_info_s *) opaque;
    uint32_t ret;
    int VAR_1;
    offset -= VAR_0->base;
    if (offset >= 0x200)
        return 0;
    VAR_1 = pxa2xx_gpio_regs[offset].VAR_1;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		
        return VAR_0->dir[VAR_1];
    case GRER:		
        return VAR_0->rising[VAR_1];
    case GFER:		
        return VAR_0->falling[VAR_1];
    case GAFR_L:	
        return VAR_0->gafr[VAR_1 * 2];
    case GAFR_U:	
        return VAR_0->gafr[VAR_1 * 2 + 1];
    case GPLR:		
        ret = (VAR_0->olevel[VAR_1] & VAR_0->dir[VAR_1]) |
                (VAR_0->ilevel[VAR_1] & ~VAR_0->dir[VAR_1]);
        if (VAR_0->read_notify)
            VAR_0->read_notify(VAR_0->opaque);
        return ret;
    case GEDR:		
        return VAR_0->status[VAR_1];
    default:
        cpu_abort(cpu_single_env,
                "%VAR_0: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }
    return 0;
}
static uint32_t FUNC_0(void *opaque, target_phys_addr_t offset)
{ struct pxa2xx_gpio_info_s *VAR_0 = (struct pxa2xx_gpio_info_s *) opaque; uint32_t ret; int VAR_1; offset -= VAR_0->base; if (offset >= 0x200)
return 0; VAR_1 = pxa2xx_gpio_regs[offset].VAR_1; switch (pxa2xx_gpio_regs[offset].reg) { case GPDR:
return VAR_0->dir[VAR_1]; case GRER:
return VAR_0->rising[VAR_1]; case GFER:
return VAR_0->falling[VAR_1]; case GAFR_L:
return VAR_0->gafr[VAR_1 * 2]; case GAFR_U:
return VAR_0->gafr[VAR_1 * 2 + 1]; case GPLR:
ret = (VAR_0->olevel[VAR_1] & VAR_0->dir[VAR_1]) |
(VAR_0->ilevel[VAR_1] & ~VAR_0->dir[VAR_1]); if (VAR_0->read_notify)
VAR_0->read_notify(VAR_0->opaque); return ret; case GEDR:
return VAR_0->status[VAR_1]; default:
cpu_abort(cpu_single_env,
"%VAR_0: Bad offset " REG_FMT "\n", __FUNCTION__, offset); } return 0; }