static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState *s,

                                        XenPTReg *cfg_entry, uint32_t *val,

                                        uint32_t dev_value, uint32_t valid_mask)

{

    XenPTRegInfo *reg = cfg_entry->reg;

    XenPTRegion *base = NULL;

    PCIDevice *d = (PCIDevice *)&s->dev;

    uint32_t writable_mask = 0;

    uint32_t throughable_mask = get_throughable_mask(s, reg, valid_mask);

    pcibus_t r_size = 0;

    uint32_t bar_ro_mask = 0;



    r_size = d->io_regions[PCI_ROM_SLOT].size;

    base = &s->bases[PCI_ROM_SLOT];

    /* align memory type resource size */

    r_size = xen_pt_get_emul_size(base->bar_flag, r_size);



    /* set emulate mask and read-only mask */

    bar_ro_mask = (reg->ro_mask | (r_size - 1)) & ~PCI_ROM_ADDRESS_ENABLE;



    /* modify emulate register */

    writable_mask = ~bar_ro_mask & valid_mask;

    cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);



    /* create value for writing to I/O device register */

    *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);



    return 0;

}

static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState *s,

                                        XenPTReg *cfg_entry, uint32_t *val,

                                        uint32_t dev_value, uint32_t valid_mask)

{

    XenPTRegInfo *reg = cfg_entry->reg;

    XenPTRegion *base = NULL;

    PCIDevice *d = (PCIDevice *)&s->dev;

    uint32_t writable_mask = 0;

    uint32_t throughable_mask = get_throughable_mask(s, reg, valid_mask);

    pcibus_t r_size = 0;

    uint32_t bar_ro_mask = 0;



    r_size = d->io_regions[PCI_ROM_SLOT].size;

    base = &s->bases[PCI_ROM_SLOT];

    

    r_size = xen_pt_get_emul_size(base->bar_flag, r_size);



    

    bar_ro_mask = (reg->ro_mask | (r_size - 1)) & ~PCI_ROM_ADDRESS_ENABLE;



    

    writable_mask = ~bar_ro_mask & valid_mask;

    cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);



    

    *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);



    return 0;

}

static int FUNC_0(XenPCIPassthroughState *VAR_0,

                                        XenPTReg *VAR_1, uint32_t *VAR_2,

                                        uint32_t VAR_3, uint32_t VAR_4)

{

    XenPTRegInfo *reg = VAR_1->reg;

    XenPTRegion *base = NULL;

    PCIDevice *d = (PCIDevice *)&VAR_0->dev;

    uint32_t writable_mask = 0;

    uint32_t throughable_mask = get_throughable_mask(VAR_0, reg, VAR_4);

    pcibus_t r_size = 0;

    uint32_t bar_ro_mask = 0;



    r_size = d->io_regions[PCI_ROM_SLOT].size;

    base = &VAR_0->bases[PCI_ROM_SLOT];

    

    r_size = xen_pt_get_emul_size(base->bar_flag, r_size);



    

    bar_ro_mask = (reg->ro_mask | (r_size - 1)) & ~PCI_ROM_ADDRESS_ENABLE;



    

    writable_mask = ~bar_ro_mask & VAR_4;

    VAR_1->data = XEN_PT_MERGE_VALUE(*VAR_2, VAR_1->data, writable_mask);



    

    *VAR_2 = XEN_PT_MERGE_VALUE(*VAR_2, VAR_3, throughable_mask);



    return 0;

}

static int FUNC_0(XenPCIPassthroughState *VAR_0,
XenPTReg *VAR_1, uint32_t *VAR_2,
uint32_t VAR_3, uint32_t VAR_4)
{ XenPTRegInfo *reg = VAR_1->reg; XenPTRegion *base = NULL; PCIDevice *d = (PCIDevice *)&VAR_0->dev; uint32_t writable_mask = 0; uint32_t throughable_mask = get_throughable_mask(VAR_0, reg, VAR_4); pcibus_t r_size = 0; uint32_t bar_ro_mask = 0; r_size = d->io_regions[PCI_ROM_SLOT].size; base = &VAR_0->bases[PCI_ROM_SLOT]; r_size = xen_pt_get_emul_size(base->bar_flag, r_size); bar_ro_mask = (reg->ro_mask | (r_size - 1)) & ~PCI_ROM_ADDRESS_ENABLE; writable_mask = ~bar_ro_mask & VAR_4; VAR_1->data = XEN_PT_MERGE_VALUE(*VAR_2, VAR_1->data, writable_mask); *VAR_2 = XEN_PT_MERGE_VALUE(*VAR_2, VAR_3, throughable_mask); return 0; }