static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)

{

    PIIX4PMState *s = opaque;

    int ret, i;

    uint16_t temp;



    ret = pci_device_load(&s->dev, f);

    if (ret < 0) {

        return ret;

    }

    qemu_get_be16s(f, &s->ar.pm1.evt.sts);

    qemu_get_be16s(f, &s->ar.pm1.evt.en);

    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);



    ret = vmstate_load_state(f, &vmstate_apm, opaque, 1);

    if (ret) {

        return ret;

    }



    qemu_get_timer(f, s->ar.tmr.timer);

    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);



    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);

    for (i = 0; i < 3; i++) {

        qemu_get_be16s(f, &temp);

    }



    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);

    for (i = 0; i < 3; i++) {

        qemu_get_be16s(f, &temp);

    }



    ret = vmstate_load_state(f, &vmstate_pci_status, opaque, 1);

    return ret;

}

static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)

{

    PIIX4PMState *s = opaque;

    int ret, i;

    uint16_t temp;



    ret = pci_device_load(&s->dev, f);

    if (ret < 0) {

        return ret;

    }

    qemu_get_be16s(f, &s->ar.pm1.evt.sts);

    qemu_get_be16s(f, &s->ar.pm1.evt.en);

    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);



    ret = vmstate_load_state(f, &vmstate_apm, opaque, 1);

    if (ret) {

        return ret;

    }



    qemu_get_timer(f, s->ar.tmr.timer);

    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);



    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);

    for (i = 0; i < 3; i++) {

        qemu_get_be16s(f, &temp);

    }



    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);

    for (i = 0; i < 3; i++) {

        qemu_get_be16s(f, &temp);

    }



    ret = vmstate_load_state(f, &vmstate_pci_status, opaque, 1);

    return ret;

}

    ret = vmstate_load_state(f, &vmstate_apm, opaque, 1);     ret = vmstate_load_state(f, &vmstate_pci_status, opaque, 1);
static int FUNC_0(QEMUFile *VAR_0, void *VAR_1, int VAR_2)

{

    PIIX4PMState *s = VAR_1;

    int VAR_3, VAR_4;

    uint16_t temp;



    VAR_3 = pci_device_load(&s->dev, VAR_0);

    if (VAR_3 < 0) {

        return VAR_3;

    }

    qemu_get_be16s(VAR_0, &s->ar.pm1.evt.sts);

    qemu_get_be16s(VAR_0, &s->ar.pm1.evt.en);

    qemu_get_be16s(VAR_0, &s->ar.pm1.cnt.cnt);



    VAR_3 = vmstate_load_state(VAR_0, &vmstate_apm, VAR_1, 1);

    if (VAR_3) {

        return VAR_3;

    }



    qemu_get_timer(VAR_0, s->ar.tmr.timer);

    qemu_get_sbe64s(VAR_0, &s->ar.tmr.overflow_time);



    qemu_get_be16s(VAR_0, (uint16_t *)s->ar.gpe.sts);

    for (VAR_4 = 0; VAR_4 < 3; VAR_4++) {

        qemu_get_be16s(VAR_0, &temp);

    }



    qemu_get_be16s(VAR_0, (uint16_t *)s->ar.gpe.en);

    for (VAR_4 = 0; VAR_4 < 3; VAR_4++) {

        qemu_get_be16s(VAR_0, &temp);

    }



    VAR_3 = vmstate_load_state(VAR_0, &vmstate_pci_status, VAR_1, 1);

    return VAR_3;

}

static int FUNC_0(QEMUFile *VAR_0, void *VAR_1, int VAR_2)
{ PIIX4PMState *s = VAR_1; int VAR_3, VAR_4; uint16_t temp; VAR_3 = pci_device_load(&s->dev, VAR_0); if (VAR_3 < 0) { return VAR_3; } qemu_get_be16s(VAR_0, &s->ar.pm1.evt.sts); qemu_get_be16s(VAR_0, &s->ar.pm1.evt.en); qemu_get_be16s(VAR_0, &s->ar.pm1.cnt.cnt); VAR_3 = vmstate_load_state(VAR_0, &vmstate_apm, VAR_1, 1); if (VAR_3) { return VAR_3; } qemu_get_timer(VAR_0, s->ar.tmr.timer); qemu_get_sbe64s(VAR_0, &s->ar.tmr.overflow_time); qemu_get_be16s(VAR_0, (uint16_t *)s->ar.gpe.sts); for (VAR_4 = 0; VAR_4 < 3; VAR_4++) { qemu_get_be16s(VAR_0, &temp); } qemu_get_be16s(VAR_0, (uint16_t *)s->ar.gpe.en); for (VAR_4 = 0; VAR_4 < 3; VAR_4++) { qemu_get_be16s(VAR_0, &temp); } VAR_3 = vmstate_load_state(VAR_0, &vmstate_pci_status, VAR_1, 1); return VAR_3; }