static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)

{

    switch (offset) {

    case 0x00: /* Control */

        s->cpu_enabled[cpu] = (value & 1);

        DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis");

        break;

    case 0x04: /* Priority mask */

        s->priority_mask[cpu] = (value & 0xff);

        break;

    case 0x08: /* Binary Point */

        /* ??? Not implemented.  */

        break;

    case 0x10: /* End Of Interrupt */

        return gic_complete_irq(s, cpu, value & 0x3ff);

    default:

        hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);

        return;

    }

    gic_update(s);

}

static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)

{

    switch (offset) {

    case 0x00: 

        s->cpu_enabled[cpu] = (value & 1);

        DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis");

        break;

    case 0x04: 

        s->priority_mask[cpu] = (value & 0xff);

        break;

    case 0x08: 

        

        break;

    case 0x10: 

        return gic_complete_irq(s, cpu, value & 0x3ff);

    default:

        hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);

        return;

    }

    gic_update(s);

}

        DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis");
static void FUNC_0(gic_state *VAR_0, int VAR_1, int VAR_2, uint32_t VAR_3)

{

    switch (VAR_2) {

    case 0x00: 

        VAR_0->cpu_enabled[VAR_1] = (VAR_3 & 1);

        DPRINTF("CPU %d %sabled\n", VAR_1, VAR_0->cpu_enabled ? "En" : "Dis");

        break;

    case 0x04: 

        VAR_0->priority_mask[VAR_1] = (VAR_3 & 0xff);

        break;

    case 0x08: 

        

        break;

    case 0x10: 

        return gic_complete_irq(VAR_0, VAR_1, VAR_3 & 0x3ff);

    default:

        hw_error("FUNC_0: Bad VAR_2 %x\n", (int)VAR_2);

        return;

    }

    gic_update(VAR_0);

}

static void FUNC_0(gic_state *VAR_0, int VAR_1, int VAR_2, uint32_t VAR_3)
{ switch (VAR_2) { case 0x00:
VAR_0->cpu_enabled[VAR_1] = (VAR_3 & 1); DPRINTF("CPU %d %sabled\n", VAR_1, VAR_0->cpu_enabled ? "En" : "Dis"); break; case 0x04:
VAR_0->priority_mask[VAR_1] = (VAR_3 & 0xff); break; case 0x08:
break; case 0x10:
return gic_complete_irq(VAR_0, VAR_1, VAR_3 & 0x3ff); default:
hw_error("FUNC_0: Bad VAR_2 %x\n", (int)VAR_2); return; } gic_update(VAR_0); }