static void apic_init_ipi(APICState *s)

{

    int i;



    s->tpr = 0;

    s->spurious_vec = 0xff;

    s->log_dest = 0;

    s->dest_mode = 0xf;

    memset(s->isr, 0, sizeof(s->isr));

    memset(s->tmr, 0, sizeof(s->tmr));

    memset(s->irr, 0, sizeof(s->irr));

    for(i = 0; i < APIC_LVT_NB; i++)

        s->lvt[i] = 1 << 16; /* mask LVT */

    s->esr = 0;

    memset(s->icr, 0, sizeof(s->icr));

    s->divide_conf = 0;

    s->count_shift = 0;

    s->initial_count = 0;

    s->initial_count_load_time = 0;

    s->next_time = 0;



    cpu_reset(s->cpu_env);



    s->cpu_env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP);

}

static void apic_init_ipi(APICState *s)

{

    int i;



    s->tpr = 0;

    s->spurious_vec = 0xff;

    s->log_dest = 0;

    s->dest_mode = 0xf;

    memset(s->isr, 0, sizeof(s->isr));

    memset(s->tmr, 0, sizeof(s->tmr));

    memset(s->irr, 0, sizeof(s->irr));

    for(i = 0; i < APIC_LVT_NB; i++)

        s->lvt[i] = 1 << 16; 

    s->esr = 0;

    memset(s->icr, 0, sizeof(s->icr));

    s->divide_conf = 0;

    s->count_shift = 0;

    s->initial_count = 0;

    s->initial_count_load_time = 0;

    s->next_time = 0;



    cpu_reset(s->cpu_env);



    s->cpu_env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP);

}

static void FUNC_0(APICState *VAR_0)

{

    int VAR_1;



    VAR_0->tpr = 0;

    VAR_0->spurious_vec = 0xff;

    VAR_0->log_dest = 0;

    VAR_0->dest_mode = 0xf;

    memset(VAR_0->isr, 0, sizeof(VAR_0->isr));

    memset(VAR_0->tmr, 0, sizeof(VAR_0->tmr));

    memset(VAR_0->irr, 0, sizeof(VAR_0->irr));

    for(VAR_1 = 0; VAR_1 < APIC_LVT_NB; VAR_1++)

        VAR_0->lvt[VAR_1] = 1 << 16; 

    VAR_0->esr = 0;

    memset(VAR_0->icr, 0, sizeof(VAR_0->icr));

    VAR_0->divide_conf = 0;

    VAR_0->count_shift = 0;

    VAR_0->initial_count = 0;

    VAR_0->initial_count_load_time = 0;

    VAR_0->next_time = 0;



    cpu_reset(VAR_0->cpu_env);



    VAR_0->cpu_env->halted = !(VAR_0->apicbase & MSR_IA32_APICBASE_BSP);

}

static void FUNC_0(APICState *VAR_0)
{ int VAR_1; VAR_0->tpr = 0; VAR_0->spurious_vec = 0xff; VAR_0->log_dest = 0; VAR_0->dest_mode = 0xf; memset(VAR_0->isr, 0, sizeof(VAR_0->isr)); memset(VAR_0->tmr, 0, sizeof(VAR_0->tmr)); memset(VAR_0->irr, 0, sizeof(VAR_0->irr)); for(VAR_1 = 0; VAR_1 < APIC_LVT_NB; VAR_1++) VAR_0->lvt[VAR_1] = 1 << 16; VAR_0->esr = 0; memset(VAR_0->icr, 0, sizeof(VAR_0->icr)); VAR_0->divide_conf = 0; VAR_0->count_shift = 0; VAR_0->initial_count = 0; VAR_0->initial_count_load_time = 0; VAR_0->next_time = 0; cpu_reset(VAR_0->cpu_env); VAR_0->cpu_env->halted = !(VAR_0->apicbase & MSR_IA32_APICBASE_BSP); }