void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)

{

    trace_esp_mem_writeb(saddr, s->wregs[saddr], val);

    switch (saddr) {

    case ESP_TCHI:

        s->tchi_written = true;

        /* fall through */

    case ESP_TCLO:

    case ESP_TCMID:

        s->rregs[ESP_RSTAT] &= ~STAT_TC;

        break;

    case ESP_FIFO:

        if (s->do_cmd) {

            if (s->cmdlen < TI_BUFSZ) {

                s->cmdbuf[s->cmdlen++] = val & 0xff;

            } else {

                trace_esp_error_fifo_overrun();

            }

        } else if (s->ti_size == TI_BUFSZ - 1) {

            trace_esp_error_fifo_overrun();

        } else {

            s->ti_size++;

            s->ti_buf[s->ti_wptr++] = val & 0xff;

        }

        break;

    case ESP_CMD:

        s->rregs[saddr] = val;

        if (val & CMD_DMA) {

            s->dma = 1;

            /* Reload DMA counter.  */

            s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];

            s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];

            s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI];

        } else {

            s->dma = 0;

        }

        switch(val & CMD_CMD) {

        case CMD_NOP:

            trace_esp_mem_writeb_cmd_nop(val);

            break;

        case CMD_FLUSH:

            trace_esp_mem_writeb_cmd_flush(val);

            //s->ti_size = 0;

            s->rregs[ESP_RINTR] = INTR_FC;

            s->rregs[ESP_RSEQ] = 0;

            s->rregs[ESP_RFLAGS] = 0;

            break;

        case CMD_RESET:

            trace_esp_mem_writeb_cmd_reset(val);

            esp_soft_reset(s);

            break;

        case CMD_BUSRESET:

            trace_esp_mem_writeb_cmd_bus_reset(val);

            s->rregs[ESP_RINTR] = INTR_RST;

            if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {

                esp_raise_irq(s);

            }

            break;

        case CMD_TI:

            handle_ti(s);

            break;

        case CMD_ICCS:

            trace_esp_mem_writeb_cmd_iccs(val);

            write_response(s);

            s->rregs[ESP_RINTR] = INTR_FC;

            s->rregs[ESP_RSTAT] |= STAT_MI;

            break;

        case CMD_MSGACC:

            trace_esp_mem_writeb_cmd_msgacc(val);

            s->rregs[ESP_RINTR] = INTR_DC;

            s->rregs[ESP_RSEQ] = 0;

            s->rregs[ESP_RFLAGS] = 0;

            esp_raise_irq(s);

            break;

        case CMD_PAD:

            trace_esp_mem_writeb_cmd_pad(val);

            s->rregs[ESP_RSTAT] = STAT_TC;

            s->rregs[ESP_RINTR] = INTR_FC;

            s->rregs[ESP_RSEQ] = 0;

            break;

        case CMD_SATN:

            trace_esp_mem_writeb_cmd_satn(val);

            break;

        case CMD_RSTATN:

            trace_esp_mem_writeb_cmd_rstatn(val);

            break;

        case CMD_SEL:

            trace_esp_mem_writeb_cmd_sel(val);

            handle_s_without_atn(s);

            break;

        case CMD_SELATN:

            trace_esp_mem_writeb_cmd_selatn(val);

            handle_satn(s);

            break;

        case CMD_SELATNS:

            trace_esp_mem_writeb_cmd_selatns(val);

            handle_satn_stop(s);

            break;

        case CMD_ENSEL:

            trace_esp_mem_writeb_cmd_ensel(val);

            s->rregs[ESP_RINTR] = 0;

            break;

        case CMD_DISSEL:

            trace_esp_mem_writeb_cmd_dissel(val);

            s->rregs[ESP_RINTR] = 0;

            esp_raise_irq(s);

            break;

        default:

            trace_esp_error_unhandled_command(val);

            break;

        }

        break;

    case ESP_WBUSID ... ESP_WSYNO:

        break;

    case ESP_CFG1:

    case ESP_CFG2: case ESP_CFG3:

    case ESP_RES3: case ESP_RES4:

        s->rregs[saddr] = val;

        break;

    case ESP_WCCF ... ESP_WTEST:

        break;

    default:

        trace_esp_error_invalid_write(val, saddr);

        return;

    }

    s->wregs[saddr] = val;

}

void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)

{

    trace_esp_mem_writeb(saddr, s->wregs[saddr], val);

    switch (saddr) {

    case ESP_TCHI:

        s->tchi_written = true;

        

    case ESP_TCLO:

    case ESP_TCMID:

        s->rregs[ESP_RSTAT] &= ~STAT_TC;

        break;

    case ESP_FIFO:

        if (s->do_cmd) {

            if (s->cmdlen < TI_BUFSZ) {

                s->cmdbuf[s->cmdlen++] = val & 0xff;

            } else {

                trace_esp_error_fifo_overrun();

            }

        } else if (s->ti_size == TI_BUFSZ - 1) {

            trace_esp_error_fifo_overrun();

        } else {

            s->ti_size++;

            s->ti_buf[s->ti_wptr++] = val & 0xff;

        }

        break;

    case ESP_CMD:

        s->rregs[saddr] = val;

        if (val & CMD_DMA) {

            s->dma = 1;

            

            s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];

            s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];

            s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI];

        } else {

            s->dma = 0;

        }

        switch(val & CMD_CMD) {

        case CMD_NOP:

            trace_esp_mem_writeb_cmd_nop(val);

            break;

        case CMD_FLUSH:

            trace_esp_mem_writeb_cmd_flush(val);

            

            s->rregs[ESP_RINTR] = INTR_FC;

            s->rregs[ESP_RSEQ] = 0;

            s->rregs[ESP_RFLAGS] = 0;

            break;

        case CMD_RESET:

            trace_esp_mem_writeb_cmd_reset(val);

            esp_soft_reset(s);

            break;

        case CMD_BUSRESET:

            trace_esp_mem_writeb_cmd_bus_reset(val);

            s->rregs[ESP_RINTR] = INTR_RST;

            if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {

                esp_raise_irq(s);

            }

            break;

        case CMD_TI:

            handle_ti(s);

            break;

        case CMD_ICCS:

            trace_esp_mem_writeb_cmd_iccs(val);

            write_response(s);

            s->rregs[ESP_RINTR] = INTR_FC;

            s->rregs[ESP_RSTAT] |= STAT_MI;

            break;

        case CMD_MSGACC:

            trace_esp_mem_writeb_cmd_msgacc(val);

            s->rregs[ESP_RINTR] = INTR_DC;

            s->rregs[ESP_RSEQ] = 0;

            s->rregs[ESP_RFLAGS] = 0;

            esp_raise_irq(s);

            break;

        case CMD_PAD:

            trace_esp_mem_writeb_cmd_pad(val);

            s->rregs[ESP_RSTAT] = STAT_TC;

            s->rregs[ESP_RINTR] = INTR_FC;

            s->rregs[ESP_RSEQ] = 0;

            break;

        case CMD_SATN:

            trace_esp_mem_writeb_cmd_satn(val);

            break;

        case CMD_RSTATN:

            trace_esp_mem_writeb_cmd_rstatn(val);

            break;

        case CMD_SEL:

            trace_esp_mem_writeb_cmd_sel(val);

            handle_s_without_atn(s);

            break;

        case CMD_SELATN:

            trace_esp_mem_writeb_cmd_selatn(val);

            handle_satn(s);

            break;

        case CMD_SELATNS:

            trace_esp_mem_writeb_cmd_selatns(val);

            handle_satn_stop(s);

            break;

        case CMD_ENSEL:

            trace_esp_mem_writeb_cmd_ensel(val);

            s->rregs[ESP_RINTR] = 0;

            break;

        case CMD_DISSEL:

            trace_esp_mem_writeb_cmd_dissel(val);

            s->rregs[ESP_RINTR] = 0;

            esp_raise_irq(s);

            break;

        default:

            trace_esp_error_unhandled_command(val);

            break;

        }

        break;

    case ESP_WBUSID ... ESP_WSYNO:

        break;

    case ESP_CFG1:

    case ESP_CFG2: case ESP_CFG3:

    case ESP_RES3: case ESP_RES4:

        s->rregs[saddr] = val;

        break;

    case ESP_WCCF ... ESP_WTEST:

        break;

    default:

        trace_esp_error_invalid_write(val, saddr);

        return;

    }

    s->wregs[saddr] = val;

}

void FUNC_0(ESPState *VAR_0, uint32_t VAR_1, uint64_t VAR_2)

{

    trace_esp_mem_writeb(VAR_1, VAR_0->wregs[VAR_1], VAR_2);

    switch (VAR_1) {

    case ESP_TCHI:

        VAR_0->tchi_written = true;

        

    case ESP_TCLO:

    case ESP_TCMID:

        VAR_0->rregs[ESP_RSTAT] &= ~STAT_TC;

        break;

    case ESP_FIFO:

        if (VAR_0->do_cmd) {

            if (VAR_0->cmdlen < TI_BUFSZ) {

                VAR_0->cmdbuf[VAR_0->cmdlen++] = VAR_2 & 0xff;

            } else {

                trace_esp_error_fifo_overrun();

            }

        } else if (VAR_0->ti_size == TI_BUFSZ - 1) {

            trace_esp_error_fifo_overrun();

        } else {

            VAR_0->ti_size++;

            VAR_0->ti_buf[VAR_0->ti_wptr++] = VAR_2 & 0xff;

        }

        break;

    case ESP_CMD:

        VAR_0->rregs[VAR_1] = VAR_2;

        if (VAR_2 & CMD_DMA) {

            VAR_0->dma = 1;

            

            VAR_0->rregs[ESP_TCLO] = VAR_0->wregs[ESP_TCLO];

            VAR_0->rregs[ESP_TCMID] = VAR_0->wregs[ESP_TCMID];

            VAR_0->rregs[ESP_TCHI] = VAR_0->wregs[ESP_TCHI];

        } else {

            VAR_0->dma = 0;

        }

        switch(VAR_2 & CMD_CMD) {

        case CMD_NOP:

            trace_esp_mem_writeb_cmd_nop(VAR_2);

            break;

        case CMD_FLUSH:

            trace_esp_mem_writeb_cmd_flush(VAR_2);

            

            VAR_0->rregs[ESP_RINTR] = INTR_FC;

            VAR_0->rregs[ESP_RSEQ] = 0;

            VAR_0->rregs[ESP_RFLAGS] = 0;

            break;

        case CMD_RESET:

            trace_esp_mem_writeb_cmd_reset(VAR_2);

            esp_soft_reset(VAR_0);

            break;

        case CMD_BUSRESET:

            trace_esp_mem_writeb_cmd_bus_reset(VAR_2);

            VAR_0->rregs[ESP_RINTR] = INTR_RST;

            if (!(VAR_0->wregs[ESP_CFG1] & CFG1_RESREPT)) {

                esp_raise_irq(VAR_0);

            }

            break;

        case CMD_TI:

            handle_ti(VAR_0);

            break;

        case CMD_ICCS:

            trace_esp_mem_writeb_cmd_iccs(VAR_2);

            write_response(VAR_0);

            VAR_0->rregs[ESP_RINTR] = INTR_FC;

            VAR_0->rregs[ESP_RSTAT] |= STAT_MI;

            break;

        case CMD_MSGACC:

            trace_esp_mem_writeb_cmd_msgacc(VAR_2);

            VAR_0->rregs[ESP_RINTR] = INTR_DC;

            VAR_0->rregs[ESP_RSEQ] = 0;

            VAR_0->rregs[ESP_RFLAGS] = 0;

            esp_raise_irq(VAR_0);

            break;

        case CMD_PAD:

            trace_esp_mem_writeb_cmd_pad(VAR_2);

            VAR_0->rregs[ESP_RSTAT] = STAT_TC;

            VAR_0->rregs[ESP_RINTR] = INTR_FC;

            VAR_0->rregs[ESP_RSEQ] = 0;

            break;

        case CMD_SATN:

            trace_esp_mem_writeb_cmd_satn(VAR_2);

            break;

        case CMD_RSTATN:

            trace_esp_mem_writeb_cmd_rstatn(VAR_2);

            break;

        case CMD_SEL:

            trace_esp_mem_writeb_cmd_sel(VAR_2);

            handle_s_without_atn(VAR_0);

            break;

        case CMD_SELATN:

            trace_esp_mem_writeb_cmd_selatn(VAR_2);

            handle_satn(VAR_0);

            break;

        case CMD_SELATNS:

            trace_esp_mem_writeb_cmd_selatns(VAR_2);

            handle_satn_stop(VAR_0);

            break;

        case CMD_ENSEL:

            trace_esp_mem_writeb_cmd_ensel(VAR_2);

            VAR_0->rregs[ESP_RINTR] = 0;

            break;

        case CMD_DISSEL:

            trace_esp_mem_writeb_cmd_dissel(VAR_2);

            VAR_0->rregs[ESP_RINTR] = 0;

            esp_raise_irq(VAR_0);

            break;

        default:

            trace_esp_error_unhandled_command(VAR_2);

            break;

        }

        break;

    case ESP_WBUSID ... ESP_WSYNO:

        break;

    case ESP_CFG1:

    case ESP_CFG2: case ESP_CFG3:

    case ESP_RES3: case ESP_RES4:

        VAR_0->rregs[VAR_1] = VAR_2;

        break;

    case ESP_WCCF ... ESP_WTEST:

        break;

    default:

        trace_esp_error_invalid_write(VAR_2, VAR_1);

        return;

    }

    VAR_0->wregs[VAR_1] = VAR_2;

}

void FUNC_0(ESPState *VAR_0, uint32_t VAR_1, uint64_t VAR_2)
{ trace_esp_mem_writeb(VAR_1, VAR_0->wregs[VAR_1], VAR_2); switch (VAR_1) { case ESP_TCHI:
VAR_0->tchi_written = true; case ESP_TCLO:
case ESP_TCMID:
VAR_0->rregs[ESP_RSTAT] &= ~STAT_TC; break; case ESP_FIFO:
if (VAR_0->do_cmd) { if (VAR_0->cmdlen < TI_BUFSZ) { VAR_0->cmdbuf[VAR_0->cmdlen++] = VAR_2 & 0xff; } else { trace_esp_error_fifo_overrun(); } } else if (VAR_0->ti_size == TI_BUFSZ - 1) { trace_esp_error_fifo_overrun(); } else { VAR_0->ti_size++; VAR_0->ti_buf[VAR_0->ti_wptr++] = VAR_2 & 0xff; } break; case ESP_CMD:
VAR_0->rregs[VAR_1] = VAR_2; if (VAR_2 & CMD_DMA) { VAR_0->dma = 1; VAR_0->rregs[ESP_TCLO] = VAR_0->wregs[ESP_TCLO]; VAR_0->rregs[ESP_TCMID] = VAR_0->wregs[ESP_TCMID]; VAR_0->rregs[ESP_TCHI] = VAR_0->wregs[ESP_TCHI]; } else { VAR_0->dma = 0; } switch(VAR_2 & CMD_CMD) { case CMD_NOP:
trace_esp_mem_writeb_cmd_nop(VAR_2); break; case CMD_FLUSH:
trace_esp_mem_writeb_cmd_flush(VAR_2); VAR_0->rregs[ESP_RINTR] = INTR_FC; VAR_0->rregs[ESP_RSEQ] = 0; VAR_0->rregs[ESP_RFLAGS] = 0; break; case CMD_RESET:
trace_esp_mem_writeb_cmd_reset(VAR_2); esp_soft_reset(VAR_0); break; case CMD_BUSRESET:
trace_esp_mem_writeb_cmd_bus_reset(VAR_2); VAR_0->rregs[ESP_RINTR] = INTR_RST; if (!(VAR_0->wregs[ESP_CFG1] & CFG1_RESREPT)) { esp_raise_irq(VAR_0); } break; case CMD_TI:
handle_ti(VAR_0); break; case CMD_ICCS:
trace_esp_mem_writeb_cmd_iccs(VAR_2); write_response(VAR_0); VAR_0->rregs[ESP_RINTR] = INTR_FC; VAR_0->rregs[ESP_RSTAT] |= STAT_MI; break; case CMD_MSGACC:
trace_esp_mem_writeb_cmd_msgacc(VAR_2); VAR_0->rregs[ESP_RINTR] = INTR_DC; VAR_0->rregs[ESP_RSEQ] = 0; VAR_0->rregs[ESP_RFLAGS] = 0; esp_raise_irq(VAR_0); break; case CMD_PAD:
trace_esp_mem_writeb_cmd_pad(VAR_2); VAR_0->rregs[ESP_RSTAT] = STAT_TC; VAR_0->rregs[ESP_RINTR] = INTR_FC; VAR_0->rregs[ESP_RSEQ] = 0; break; case CMD_SATN:
trace_esp_mem_writeb_cmd_satn(VAR_2); break; case CMD_RSTATN:
trace_esp_mem_writeb_cmd_rstatn(VAR_2); break; case CMD_SEL:
trace_esp_mem_writeb_cmd_sel(VAR_2); handle_s_without_atn(VAR_0); break; case CMD_SELATN:
trace_esp_mem_writeb_cmd_selatn(VAR_2); handle_satn(VAR_0); break; case CMD_SELATNS:
trace_esp_mem_writeb_cmd_selatns(VAR_2); handle_satn_stop(VAR_0); break; case CMD_ENSEL:
trace_esp_mem_writeb_cmd_ensel(VAR_2); VAR_0->rregs[ESP_RINTR] = 0; break; case CMD_DISSEL:
trace_esp_mem_writeb_cmd_dissel(VAR_2); VAR_0->rregs[ESP_RINTR] = 0; esp_raise_irq(VAR_0); break; default:
trace_esp_error_unhandled_command(VAR_2); break; } break; case ESP_WBUSID ... ESP_WSYNO:
break; case ESP_CFG1:
case ESP_CFG2: case ESP_CFG3:
case ESP_RES3: case ESP_RES4:
VAR_0->rregs[VAR_1] = VAR_2; break; case ESP_WCCF ... ESP_WTEST:
break; default:
trace_esp_error_invalid_write(VAR_2, VAR_1); return; } VAR_0->wregs[VAR_1] = VAR_2; }