static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,

                               uint64_t value)

{

    ARMCPU *cpu = arm_env_get_cpu(env);



    /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */

    tlb_flush(CPU(cpu), 1);

    env->cp15.c2_control = value;

}

static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,

                               uint64_t value)

{

    ARMCPU *cpu = arm_env_get_cpu(env);



    

    tlb_flush(CPU(cpu), 1);

    env->cp15.c2_control = value;

}

static void FUNC_0(CPUARMState *VAR_0, const ARMCPRegInfo *VAR_1,

                               uint64_t VAR_2)

{

    ARMCPU *cpu = arm_env_get_cpu(VAR_0);



    

    tlb_flush(CPU(cpu), 1);

    VAR_0->cp15.c2_control = VAR_2;

}

static void FUNC_0(CPUARMState *VAR_0, const ARMCPRegInfo *VAR_1,
uint64_t VAR_2)
{ ARMCPU *cpu = arm_env_get_cpu(VAR_0); tlb_flush(CPU(cpu), 1); VAR_0->cp15.c2_control = VAR_2; }