int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type,

                     uint8_t port)

{

    /* PCIe cap v1 init */

    int pos;

    uint8_t *exp_cap;



    assert(pci_is_express(dev));



    pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_SIZEOF);

    if (pos < 0) {

        return pos;

    }

    dev->exp.exp_cap = pos;

    exp_cap = dev->config + pos;



    pcie_cap_v1_fill(exp_cap, port, type, PCI_EXP_FLAGS_VER1);



    return pos;

}

int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type,

                     uint8_t port)

{

    

    int pos;

    uint8_t *exp_cap;



    assert(pci_is_express(dev));



    pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_SIZEOF);

    if (pos < 0) {

        return pos;

    }

    dev->exp.exp_cap = pos;

    exp_cap = dev->config + pos;



    pcie_cap_v1_fill(exp_cap, port, type, PCI_EXP_FLAGS_VER1);



    return pos;

}

    uint8_t *exp_cap;     exp_cap = dev->config + pos;     pcie_cap_v1_fill(exp_cap, port, type, PCI_EXP_FLAGS_VER1);
int FUNC_0(PCIDevice *VAR_0, uint8_t VAR_1, uint8_t VAR_2,

                     uint8_t VAR_3)

{

    

    int VAR_4;

    uint8_t *exp_cap;



    assert(pci_is_express(VAR_0));



    VAR_4 = pci_add_capability(VAR_0, PCI_CAP_ID_EXP, VAR_1, PCI_EXP_VER1_SIZEOF);

    if (VAR_4 < 0) {

        return VAR_4;

    }

    VAR_0->exp.exp_cap = VAR_4;

    exp_cap = VAR_0->config + VAR_4;



    pcie_cap_v1_fill(exp_cap, VAR_3, VAR_2, PCI_EXP_FLAGS_VER1);



    return VAR_4;

}

int FUNC_0(PCIDevice *VAR_0, uint8_t VAR_1, uint8_t VAR_2,
uint8_t VAR_3)
{ int VAR_4; uint8_t *exp_cap; assert(pci_is_express(VAR_0)); VAR_4 = pci_add_capability(VAR_0, PCI_CAP_ID_EXP, VAR_1, PCI_EXP_VER1_SIZEOF); if (VAR_4 < 0) { return VAR_4; } VAR_0->exp.exp_cap = VAR_4; exp_cap = VAR_0->config + VAR_4; pcie_cap_v1_fill(exp_cap, VAR_3, VAR_2, PCI_EXP_FLAGS_VER1); return VAR_4; }