static void setup_vm_cmd(IVState *s, const char *cmd, bool msix)

{

    uint64_t barsize;



    s->qtest = qtest_start(cmd);

    s->pcibus = qpci_init_pc(NULL);

    s->dev = get_device(s->pcibus);



    s->reg_base = qpci_iomap(s->dev, 0, &barsize);

    g_assert_nonnull(s->reg_base);

    g_assert_cmpuint(barsize, ==, 256);



    if (msix) {

        qpci_msix_enable(s->dev);

    }



    s->mem_base = qpci_iomap(s->dev, 2, &barsize);

    g_assert_nonnull(s->mem_base);

    g_assert_cmpuint(barsize, ==, TMPSHMSIZE);



    qpci_device_enable(s->dev);

}

static void setup_vm_cmd(IVState *s, const char *cmd, bool msix)

{

    uint64_t barsize;



    s->qtest = qtest_start(cmd);

    s->pcibus = qpci_init_pc(NULL);

    s->dev = get_device(s->pcibus);



    s->reg_base = qpci_iomap(s->dev, 0, &barsize);

    g_assert_nonnull(s->reg_base);

    g_assert_cmpuint(barsize, ==, 256);



    if (msix) {

        qpci_msix_enable(s->dev);

    }



    s->mem_base = qpci_iomap(s->dev, 2, &barsize);

    g_assert_nonnull(s->mem_base);

    g_assert_cmpuint(barsize, ==, TMPSHMSIZE);



    qpci_device_enable(s->dev);

}

    s->reg_base = qpci_iomap(s->dev, 0, &barsize);     g_assert_nonnull(s->reg_base);     s->mem_base = qpci_iomap(s->dev, 2, &barsize);     g_assert_nonnull(s->mem_base);
static void FUNC_0(IVState *VAR_0, const char *VAR_1, bool VAR_2)

{

    uint64_t barsize;



    VAR_0->qtest = qtest_start(VAR_1);

    VAR_0->pcibus = qpci_init_pc(NULL);

    VAR_0->dev = get_device(VAR_0->pcibus);



    VAR_0->reg_base = qpci_iomap(VAR_0->dev, 0, &barsize);

    g_assert_nonnull(VAR_0->reg_base);

    g_assert_cmpuint(barsize, ==, 256);



    if (VAR_2) {

        qpci_msix_enable(VAR_0->dev);

    }



    VAR_0->mem_base = qpci_iomap(VAR_0->dev, 2, &barsize);

    g_assert_nonnull(VAR_0->mem_base);

    g_assert_cmpuint(barsize, ==, TMPSHMSIZE);



    qpci_device_enable(VAR_0->dev);

}

static void FUNC_0(IVState *VAR_0, const char *VAR_1, bool VAR_2)
{ uint64_t barsize; VAR_0->qtest = qtest_start(VAR_1); VAR_0->pcibus = qpci_init_pc(NULL); VAR_0->dev = get_device(VAR_0->pcibus); VAR_0->reg_base = qpci_iomap(VAR_0->dev, 0, &barsize); g_assert_nonnull(VAR_0->reg_base); g_assert_cmpuint(barsize, ==, 256); if (VAR_2) { qpci_msix_enable(VAR_0->dev); } VAR_0->mem_base = qpci_iomap(VAR_0->dev, 2, &barsize); g_assert_nonnull(VAR_0->mem_base); g_assert_cmpuint(barsize, ==, TMPSHMSIZE); qpci_device_enable(VAR_0->dev); }