static void uart_write(void *opaque, hwaddr addr,

                       uint64_t value, unsigned size)

{

    LM32UartState *s = opaque;

    unsigned char ch = value;



    trace_lm32_uart_memory_write(addr, value);



    addr >>= 2;

    switch (addr) {

    case R_RXTX:

        if (s->chr) {



            qemu_chr_fe_write_all(s->chr, &ch, 1);

        }

        break;

    case R_IER:

    case R_LCR:

    case R_MCR:

    case R_DIV:

        s->regs[addr] = value;

        break;

    case R_IIR:

    case R_LSR:

    case R_MSR:

        error_report("lm32_uart: write access to read only register 0x"

                TARGET_FMT_plx, addr << 2);

        break;

    default:

        error_report("lm32_uart: write access to unknown register 0x"

                TARGET_FMT_plx, addr << 2);

        break;

    }

    uart_update_irq(s);

}
static void uart_write(void *opaque, hwaddr addr,

                       uint64_t value, unsigned size)

{

    LM32UartState *s = opaque;

    unsigned char ch = value;



    trace_lm32_uart_memory_write(addr, value);



    addr >>= 2;

    switch (addr) {

    case R_RXTX:

        if (s->chr) {



            qemu_chr_fe_write_all(s->chr, &ch, 1);

        }

        break;

    case R_IER:

    case R_LCR:

    case R_MCR:

    case R_DIV:

        s->regs[addr] = value;

        break;

    case R_IIR:

    case R_LSR:

    case R_MSR:

        error_report("lm32_uart: write access to read only register 0x"

                TARGET_FMT_plx, addr << 2);

        break;

    default:

        error_report("lm32_uart: write access to unknown register 0x"

                TARGET_FMT_plx, addr << 2);

        break;

    }

    uart_update_irq(s);

}
static void FUNC_0(void *VAR_0, hwaddr VAR_1,

                       uint64_t VAR_2, unsigned VAR_3)

{

    LM32UartState *s = VAR_0;

    unsigned char VAR_4 = VAR_2;



    trace_lm32_uart_memory_write(VAR_1, VAR_2);



    VAR_1 >>= 2;

    switch (VAR_1) {

    case R_RXTX:

        if (s->chr) {



            qemu_chr_fe_write_all(s->chr, &VAR_4, 1);

        }

        break;

    case R_IER:

    case R_LCR:

    case R_MCR:

    case R_DIV:

        s->regs[VAR_1] = VAR_2;

        break;

    case R_IIR:

    case R_LSR:

    case R_MSR:

        error_report("lm32_uart: write access to read only register 0x"

                TARGET_FMT_plx, VAR_1 << 2);

        break;

    default:

        error_report("lm32_uart: write access to unknown register 0x"

                TARGET_FMT_plx, VAR_1 << 2);

        break;

    }

    uart_update_irq(s);

}
static void FUNC_0(void *VAR_0, hwaddr VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ LM32UartState *s = VAR_0; unsigned char VAR_4 = VAR_2; trace_lm32_uart_memory_write(VAR_1, VAR_2); VAR_1 >>= 2; switch (VAR_1) { case R_RXTX:
if (s->chr) { qemu_chr_fe_write_all(s->chr, &VAR_4, 1); } break; case R_IER:
case R_LCR:
case R_MCR:
case R_DIV:
s->regs[VAR_1] = VAR_2; break; case R_IIR:
case R_LSR:
case R_MSR:
error_report("lm32_uart: write access to read only register 0x"
TARGET_FMT_plx, VAR_1 << 2); break; default:
error_report("lm32_uart: write access to unknown register 0x"
TARGET_FMT_plx, VAR_1 << 2); break; } uart_update_irq(s); }