static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,

                                uint64_t value, unsigned size)

{

    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;



    if (size != 4) {

        return omap_badwidth_write32(opaque, addr, value);

    }



    switch (offset) {

    case 0x00:	/* TVR */

        s->timer.reset_val = value & 0x00ffffff;

        break;



    case 0x04:	/* TCR */

        OMAP_RO_REG(addr);

        break;



    case 0x08:	/* CR */

        s->timer.ar = (value >> 3) & 1;

        s->timer.it_ena = (value >> 2) & 1;

        if (s->timer.st != (value & 1) || (value & 2)) {

            omap_timer_sync(&s->timer);

            s->timer.enable = value & 1;

            s->timer.st = value & 1;

            omap_timer_update(&s->timer);

        }

        break;



    default:

        OMAP_BAD_REG(addr);

    }

}

static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,

                                uint64_t value, unsigned size)

{

    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;



    if (size != 4) {

        return omap_badwidth_write32(opaque, addr, value);

    }



    switch (offset) {

    case 0x00:	

        s->timer.reset_val = value & 0x00ffffff;

        break;



    case 0x04:	

        OMAP_RO_REG(addr);

        break;



    case 0x08:	

        s->timer.ar = (value >> 3) & 1;

        s->timer.it_ena = (value >> 2) & 1;

        if (s->timer.st != (value & 1) || (value & 2)) {

            omap_timer_sync(&s->timer);

            s->timer.enable = value & 1;

            s->timer.st = value & 1;

            omap_timer_update(&s->timer);

        }

        break;



    default:

        OMAP_BAD_REG(addr);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                                uint64_t VAR_2, unsigned VAR_3)

{

    struct omap_32khz_timer_s *VAR_4 = (struct omap_32khz_timer_s *) VAR_0;

    int VAR_5 = VAR_1 & OMAP_MPUI_REG_MASK;



    if (VAR_3 != 4) {

        return omap_badwidth_write32(VAR_0, VAR_1, VAR_2);

    }



    switch (VAR_5) {

    case 0x00:	

        VAR_4->timer.reset_val = VAR_2 & 0x00ffffff;

        break;



    case 0x04:	

        OMAP_RO_REG(VAR_1);

        break;



    case 0x08:	

        VAR_4->timer.ar = (VAR_2 >> 3) & 1;

        VAR_4->timer.it_ena = (VAR_2 >> 2) & 1;

        if (VAR_4->timer.st != (VAR_2 & 1) || (VAR_2 & 2)) {

            omap_timer_sync(&VAR_4->timer);

            VAR_4->timer.enable = VAR_2 & 1;

            VAR_4->timer.st = VAR_2 & 1;

            omap_timer_update(&VAR_4->timer);

        }

        break;



    default:

        OMAP_BAD_REG(VAR_1);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ struct omap_32khz_timer_s *VAR_4 = (struct omap_32khz_timer_s *) VAR_0; int VAR_5 = VAR_1 & OMAP_MPUI_REG_MASK; if (VAR_3 != 4) { return omap_badwidth_write32(VAR_0, VAR_1, VAR_2); } switch (VAR_5) { case 0x00:
VAR_4->timer.reset_val = VAR_2 & 0x00ffffff; break; case 0x04:
OMAP_RO_REG(VAR_1); break; case 0x08:
VAR_4->timer.ar = (VAR_2 >> 3) & 1; VAR_4->timer.it_ena = (VAR_2 >> 2) & 1; if (VAR_4->timer.st != (VAR_2 & 1) || (VAR_2 & 2)) { omap_timer_sync(&VAR_4->timer); VAR_4->timer.enable = VAR_2 & 1; VAR_4->timer.st = VAR_2 & 1; omap_timer_update(&VAR_4->timer); } break; default:
OMAP_BAD_REG(VAR_1); } }