static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,

                          DisplayState *ds, const char *cpu_model)



{

    CPUState *env, *envs[MAX_CPUS];

    unsigned int i;

    void *iommu, *espdma, *ledma, *main_esp;

    const sparc_def_t *def;

    qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,

        *espdma_irq, *ledma_irq;



    /* init CPUs */

    sparc_find_by_name(cpu_model, &def);

    if (def == NULL) {

        fprintf(stderr, "Unable to find Sparc CPU definition\n");

        exit(1);

    }



    for(i = 0; i < smp_cpus; i++) {

        env = cpu_init();

        cpu_sparc_register(env, def);

        envs[i] = env;

        if (i == 0) {

            qemu_register_reset(main_cpu_reset, env);

        } else {

            qemu_register_reset(secondary_cpu_reset, env);

            env->halted = 1;

        }

        register_savevm("cpu", i, 3, cpu_save, cpu_load, env);

        cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);

    }



    for (i = smp_cpus; i < MAX_CPUS; i++)

        cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);



    /* allocate RAM */

    cpu_register_physical_memory(0, ram_size, 0);



    iommu = iommu_init(hwdef->iommu_base);

    slavio_intctl = slavio_intctl_init(hwdef->intctl_base,

                                       hwdef->intctl_base + 0x10000ULL,

                                       &hwdef->intbit_to_level[0],

                                       &slavio_irq, &slavio_cpu_irq,

                                       cpu_irqs,

                                       hwdef->clock_irq);



    espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],

                              iommu, &espdma_irq);

    ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,

                             slavio_irq[hwdef->le_irq], iommu, &ledma_irq);



    if (graphic_depth != 8 && graphic_depth != 24) {

        fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);

        exit (1);

    }

    tcx_init(ds, hwdef->tcx_base, phys_ram_base + ram_size, ram_size,

             hwdef->vram_size, graphic_width, graphic_height, graphic_depth);



    if (nd_table[0].model == NULL

        || strcmp(nd_table[0].model, "lance") == 0) {

        lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq);

    } else if (strcmp(nd_table[0].model, "?") == 0) {

        fprintf(stderr, "qemu: Supported NICs: lance\n");

        exit (1);

    } else {

        fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);

        exit (1);

    }



    nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,

                        hwdef->nvram_size, 8);

    for (i = 0; i < MAX_CPUS; i++) {

        slavio_timer_init(hwdef->counter_base +

                          (target_phys_addr_t)(i * TARGET_PAGE_SIZE),

                           slavio_cpu_irq[i], 0);

    }

    slavio_timer_init(hwdef->counter_base + 0x10000ULL,

                      slavio_irq[hwdef->clock1_irq], 2);

    slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]);

    // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device

    // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device

    slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],

                       serial_hds[1], serial_hds[0]);

    fdctrl_init(slavio_irq[hwdef->fd_irq], 0, 1, hwdef->fd_base, fd_table);

    main_esp = esp_init(bs_table, hwdef->esp_base, espdma, *espdma_irq);



    for (i = 0; i < MAX_DISKS; i++) {

        if (bs_table[i]) {

            esp_scsi_attach(main_esp, bs_table[i], i);

        }

    }



    slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base,

                                   slavio_irq[hwdef->me_irq]);

    if (hwdef->cs_base != (target_phys_addr_t)-1)

        cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);

}

static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,

                          DisplayState *ds, const char *cpu_model)



{

    CPUState *env, *envs[MAX_CPUS];

    unsigned int i;

    void *iommu, *espdma, *ledma, *main_esp;

    const sparc_def_t *def;

    qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,

        *espdma_irq, *ledma_irq;



    

    sparc_find_by_name(cpu_model, &def);

    if (def == NULL) {

        fprintf(stderr, "Unable to find Sparc CPU definition\n");

        exit(1);

    }



    for(i = 0; i < smp_cpus; i++) {

        env = cpu_init();

        cpu_sparc_register(env, def);

        envs[i] = env;

        if (i == 0) {

            qemu_register_reset(main_cpu_reset, env);

        } else {

            qemu_register_reset(secondary_cpu_reset, env);

            env->halted = 1;

        }

        register_savevm("cpu", i, 3, cpu_save, cpu_load, env);

        cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);

    }



    for (i = smp_cpus; i < MAX_CPUS; i++)

        cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);



    

    cpu_register_physical_memory(0, ram_size, 0);



    iommu = iommu_init(hwdef->iommu_base);

    slavio_intctl = slavio_intctl_init(hwdef->intctl_base,

                                       hwdef->intctl_base + 0x10000ULL,

                                       &hwdef->intbit_to_level[0],

                                       &slavio_irq, &slavio_cpu_irq,

                                       cpu_irqs,

                                       hwdef->clock_irq);



    espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],

                              iommu, &espdma_irq);

    ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,

                             slavio_irq[hwdef->le_irq], iommu, &ledma_irq);



    if (graphic_depth != 8 && graphic_depth != 24) {

        fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);

        exit (1);

    }

    tcx_init(ds, hwdef->tcx_base, phys_ram_base + ram_size, ram_size,

             hwdef->vram_size, graphic_width, graphic_height, graphic_depth);



    if (nd_table[0].model == NULL

        || strcmp(nd_table[0].model, "lance") == 0) {

        lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq);

    } else if (strcmp(nd_table[0].model, "?") == 0) {

        fprintf(stderr, "qemu: Supported NICs: lance\n");

        exit (1);

    } else {

        fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);

        exit (1);

    }



    nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,

                        hwdef->nvram_size, 8);

    for (i = 0; i < MAX_CPUS; i++) {

        slavio_timer_init(hwdef->counter_base +

                          (target_phys_addr_t)(i * TARGET_PAGE_SIZE),

                           slavio_cpu_irq[i], 0);

    }

    slavio_timer_init(hwdef->counter_base + 0x10000ULL,

                      slavio_irq[hwdef->clock1_irq], 2);

    slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]);

    

    

    slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],

                       serial_hds[1], serial_hds[0]);

    fdctrl_init(slavio_irq[hwdef->fd_irq], 0, 1, hwdef->fd_base, fd_table);

    main_esp = esp_init(bs_table, hwdef->esp_base, espdma, *espdma_irq);



    for (i = 0; i < MAX_DISKS; i++) {

        if (bs_table[i]) {

            esp_scsi_attach(main_esp, bs_table[i], i);

        }

    }



    slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base,

                                   slavio_irq[hwdef->me_irq]);

    if (hwdef->cs_base != (target_phys_addr_t)-1)

        cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);

}

static void FUNC_0(const struct VAR_0 *VAR_0, int VAR_1,

                          DisplayState *VAR_2, const char *VAR_3)



{

    CPUState *env, *envs[MAX_CPUS];

    unsigned int VAR_4;

    void *VAR_5, *VAR_6, *VAR_7, *VAR_8;

    const sparc_def_t *VAR_9;

    qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,

        *espdma_irq, *ledma_irq;



    

    sparc_find_by_name(VAR_3, &VAR_9);

    if (VAR_9 == NULL) {

        fprintf(stderr, "Unable to find Sparc CPU definition\n");

        exit(1);

    }



    for(VAR_4 = 0; VAR_4 < smp_cpus; VAR_4++) {

        env = cpu_init();

        cpu_sparc_register(env, VAR_9);

        envs[VAR_4] = env;

        if (VAR_4 == 0) {

            qemu_register_reset(main_cpu_reset, env);

        } else {

            qemu_register_reset(secondary_cpu_reset, env);

            env->halted = 1;

        }

        register_savevm("cpu", VAR_4, 3, cpu_save, cpu_load, env);

        cpu_irqs[VAR_4] = qemu_allocate_irqs(cpu_set_irq, envs[VAR_4], MAX_PILS);

    }



    for (VAR_4 = smp_cpus; VAR_4 < MAX_CPUS; VAR_4++)

        cpu_irqs[VAR_4] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);



    

    cpu_register_physical_memory(0, VAR_1, 0);



    VAR_5 = iommu_init(VAR_0->iommu_base);

    slavio_intctl = slavio_intctl_init(VAR_0->intctl_base,

                                       VAR_0->intctl_base + 0x10000ULL,

                                       &VAR_0->intbit_to_level[0],

                                       &slavio_irq, &slavio_cpu_irq,

                                       cpu_irqs,

                                       VAR_0->clock_irq);



    VAR_6 = sparc32_dma_init(VAR_0->dma_base, slavio_irq[VAR_0->esp_irq],

                              VAR_5, &espdma_irq);

    VAR_7 = sparc32_dma_init(VAR_0->dma_base + 16ULL,

                             slavio_irq[VAR_0->le_irq], VAR_5, &ledma_irq);



    if (graphic_depth != 8 && graphic_depth != 24) {

        fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);

        exit (1);

    }

    tcx_init(VAR_2, VAR_0->tcx_base, phys_ram_base + VAR_1, VAR_1,

             VAR_0->vram_size, graphic_width, graphic_height, graphic_depth);



    if (nd_table[0].model == NULL

        || strcmp(nd_table[0].model, "lance") == 0) {

        lance_init(&nd_table[0], VAR_0->le_base, VAR_7, *ledma_irq);

    } else if (strcmp(nd_table[0].model, "?") == 0) {

        fprintf(stderr, "qemu: Supported NICs: lance\n");

        exit (1);

    } else {

        fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);

        exit (1);

    }



    nvram = m48t59_init(slavio_irq[0], VAR_0->nvram_base, 0,

                        VAR_0->nvram_size, 8);

    for (VAR_4 = 0; VAR_4 < MAX_CPUS; VAR_4++) {

        slavio_timer_init(VAR_0->counter_base +

                          (target_phys_addr_t)(VAR_4 * TARGET_PAGE_SIZE),

                           slavio_cpu_irq[VAR_4], 0);

    }

    slavio_timer_init(VAR_0->counter_base + 0x10000ULL,

                      slavio_irq[VAR_0->clock1_irq], 2);

    slavio_serial_ms_kbd_init(VAR_0->ms_kb_base, slavio_irq[VAR_0->ms_kb_irq]);

    

    

    slavio_serial_init(VAR_0->serial_base, slavio_irq[VAR_0->ser_irq],

                       serial_hds[1], serial_hds[0]);

    fdctrl_init(slavio_irq[VAR_0->fd_irq], 0, 1, VAR_0->fd_base, fd_table);

    VAR_8 = esp_init(bs_table, VAR_0->esp_base, VAR_6, *espdma_irq);



    for (VAR_4 = 0; VAR_4 < MAX_DISKS; VAR_4++) {

        if (bs_table[VAR_4]) {

            esp_scsi_attach(VAR_8, bs_table[VAR_4], VAR_4);

        }

    }



    slavio_misc = slavio_misc_init(VAR_0->slavio_base, VAR_0->power_base,

                                   slavio_irq[VAR_0->me_irq]);

    if (VAR_0->cs_base != (target_phys_addr_t)-1)

        cs_init(VAR_0->cs_base, VAR_0->cs_irq, slavio_intctl);

}

static void FUNC_0(const struct VAR_0 *VAR_0, int VAR_1,
DisplayState *VAR_2, const char *VAR_3)
{ CPUState *env, *envs[MAX_CPUS]; unsigned int VAR_4; void *VAR_5, *VAR_6, *VAR_7, *VAR_8; const sparc_def_t *VAR_9; qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
*espdma_irq, *ledma_irq; sparc_find_by_name(VAR_3, &VAR_9); if (VAR_9 == NULL) { fprintf(stderr, "Unable to find Sparc CPU definition\n"); exit(1); } for(VAR_4 = 0; VAR_4 < smp_cpus; VAR_4++) { env = cpu_init(); cpu_sparc_register(env, VAR_9); envs[VAR_4] = env; if (VAR_4 == 0) { qemu_register_reset(main_cpu_reset, env); } else { qemu_register_reset(secondary_cpu_reset, env); env->halted = 1; } register_savevm("cpu", VAR_4, 3, cpu_save, cpu_load, env); cpu_irqs[VAR_4] = qemu_allocate_irqs(cpu_set_irq, envs[VAR_4], MAX_PILS); } for (VAR_4 = smp_cpus; VAR_4 < MAX_CPUS; VAR_4++) cpu_irqs[VAR_4] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); cpu_register_physical_memory(0, VAR_1, 0); VAR_5 = iommu_init(VAR_0->iommu_base); slavio_intctl = slavio_intctl_init(VAR_0->intctl_base,
VAR_0->intctl_base + 0x10000ULL,
&VAR_0->intbit_to_level[0],
&slavio_irq, &slavio_cpu_irq,
cpu_irqs,
VAR_0->clock_irq); VAR_6 = sparc32_dma_init(VAR_0->dma_base, slavio_irq[VAR_0->esp_irq],
VAR_5, &espdma_irq); VAR_7 = sparc32_dma_init(VAR_0->dma_base + 16ULL,
slavio_irq[VAR_0->le_irq], VAR_5, &ledma_irq); if (graphic_depth != 8 && graphic_depth != 24) { fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); exit (1); } tcx_init(VAR_2, VAR_0->tcx_base, phys_ram_base + VAR_1, VAR_1,
VAR_0->vram_size, graphic_width, graphic_height, graphic_depth); if (nd_table[0].model == NULL
|| strcmp(nd_table[0].model, "lance") == 0) { lance_init(&nd_table[0], VAR_0->le_base, VAR_7, *ledma_irq); } else if (strcmp(nd_table[0].model, "?") == 0) { fprintf(stderr, "qemu: Supported NICs: lance\n"); exit (1); } else { fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); exit (1); } nvram = m48t59_init(slavio_irq[0], VAR_0->nvram_base, 0,
VAR_0->nvram_size, 8); for (VAR_4 = 0; VAR_4 < MAX_CPUS; VAR_4++) { slavio_timer_init(VAR_0->counter_base +
(target_phys_addr_t)(VAR_4 * TARGET_PAGE_SIZE),
slavio_cpu_irq[VAR_4], 0); } slavio_timer_init(VAR_0->counter_base + 0x10000ULL,
slavio_irq[VAR_0->clock1_irq], 2); slavio_serial_ms_kbd_init(VAR_0->ms_kb_base, slavio_irq[VAR_0->ms_kb_irq]); slavio_serial_init(VAR_0->serial_base, slavio_irq[VAR_0->ser_irq],
serial_hds[1], serial_hds[0]); fdctrl_init(slavio_irq[VAR_0->fd_irq], 0, 1, VAR_0->fd_base, fd_table); VAR_8 = esp_init(bs_table, VAR_0->esp_base, VAR_6, *espdma_irq); for (VAR_4 = 0; VAR_4 < MAX_DISKS; VAR_4++) { if (bs_table[VAR_4]) { esp_scsi_attach(VAR_8, bs_table[VAR_4], VAR_4); } } slavio_misc = slavio_misc_init(VAR_0->slavio_base, VAR_0->power_base,
slavio_irq[VAR_0->me_irq]); if (VAR_0->cs_base != (target_phys_addr_t)-1)
cs_init(VAR_0->cs_base, VAR_0->cs_irq, slavio_intctl); }