static void grlib_apbuart_write(void *opaque, hwaddr addr,

                                uint64_t value, unsigned size)

{

    UART          *uart = opaque;

    unsigned char  c    = 0;



    addr &= 0xff;



    /* Unit registers */

    switch (addr) {

    case DATA_OFFSET:

    case DATA_OFFSET + 3:       /* When only one byte write */

        /* Transmit when character device available and transmitter enabled */

        if ((uart->chr) && (uart->control & UART_TRANSMIT_ENABLE)) {

            c = value & 0xFF;

            qemu_chr_fe_write(uart->chr, &c, 1);

            /* Generate interrupt */

            if (uart->control & UART_TRANSMIT_INTERRUPT) {

                qemu_irq_pulse(uart->irq);

            }

        }

        return;



    case STATUS_OFFSET:

        /* Read Only */

        return;



    case CONTROL_OFFSET:

        uart->control = value;

        return;



    case SCALER_OFFSET:

        /* Not supported */

        return;



    default:

        break;

    }



    trace_grlib_apbuart_writel_unknown(addr, value);

}

static void grlib_apbuart_write(void *opaque, hwaddr addr,

                                uint64_t value, unsigned size)

{

    UART          *uart = opaque;

    unsigned char  c    = 0;



    addr &= 0xff;



    

    switch (addr) {

    case DATA_OFFSET:

    case DATA_OFFSET + 3:       

        

        if ((uart->chr) && (uart->control & UART_TRANSMIT_ENABLE)) {

            c = value & 0xFF;

            qemu_chr_fe_write(uart->chr, &c, 1);

            

            if (uart->control & UART_TRANSMIT_INTERRUPT) {

                qemu_irq_pulse(uart->irq);

            }

        }

        return;



    case STATUS_OFFSET:

        

        return;



    case CONTROL_OFFSET:

        uart->control = value;

        return;



    case SCALER_OFFSET:

        

        return;



    default:

        break;

    }



    trace_grlib_apbuart_writel_unknown(addr, value);

}

            qemu_chr_fe_write(uart->chr, &c, 1);
static void FUNC_0(void *VAR_0, hwaddr VAR_1,

                                uint64_t VAR_2, unsigned VAR_3)

{

    UART          *uart = VAR_0;

    unsigned char  VAR_4    = 0;



    VAR_1 &= 0xff;



    

    switch (VAR_1) {

    case DATA_OFFSET:

    case DATA_OFFSET + 3:       

        

        if ((uart->chr) && (uart->control & UART_TRANSMIT_ENABLE)) {

            VAR_4 = VAR_2 & 0xFF;

            qemu_chr_fe_write(uart->chr, &VAR_4, 1);

            

            if (uart->control & UART_TRANSMIT_INTERRUPT) {

                qemu_irq_pulse(uart->irq);

            }

        }

        return;



    case STATUS_OFFSET:

        

        return;



    case CONTROL_OFFSET:

        uart->control = VAR_2;

        return;



    case SCALER_OFFSET:

        

        return;



    default:

        break;

    }



    trace_grlib_apbuart_writel_unknown(VAR_1, VAR_2);

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ UART          *uart = VAR_0; unsigned char  VAR_4    = 0; VAR_1 &= 0xff; switch (VAR_1) { case DATA_OFFSET:
case DATA_OFFSET + 3:
if ((uart->chr) && (uart->control & UART_TRANSMIT_ENABLE)) { VAR_4 = VAR_2 & 0xFF; qemu_chr_fe_write(uart->chr, &VAR_4, 1); if (uart->control & UART_TRANSMIT_INTERRUPT) { qemu_irq_pulse(uart->irq); } } return; case STATUS_OFFSET:
return; case CONTROL_OFFSET:
uart->control = VAR_2; return; case SCALER_OFFSET:
return; default:
break; } trace_grlib_apbuart_writel_unknown(VAR_1, VAR_2); }