void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)

{

    int memory_map_mode, plane, write_mode, b, func_select, mask;

    uint32_t write_mask, bit_mask, set_mask;



#ifdef DEBUG_VGA_MEM

    printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);

#endif

    /* convert to VGA memory offset */

    memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;

    addr &= 0x1ffff;

    switch(memory_map_mode) {

    case 0:

        break;

    case 1:

        if (addr >= 0x10000)

            return;

        addr += s->bank_offset;

        break;

    case 2:

        addr -= 0x10000;

        if (addr >= 0x8000)

            return;

        break;

    default:

    case 3:

        addr -= 0x18000;

        if (addr >= 0x8000)

            return;

        break;

    }



    if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {

        /* chain 4 mode : simplest access */

        plane = addr & 3;

        mask = (1 << plane);

        if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {

            assert(addr < s->vram_size);

            s->vram_ptr[addr] = val;

#ifdef DEBUG_VGA_MEM

            printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);

#endif

            s->plane_updated |= mask; /* only used to detect font change */

            memory_region_set_dirty(&s->vram, addr, 1);

        }

    } else if (s->gr[VGA_GFX_MODE] & 0x10) {

        /* odd/even mode (aka text mode mapping) */

        plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);

        mask = (1 << plane);

        if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {

            addr = ((addr & ~1) << 1) | plane;

            if (addr >= s->vram_size) {

                return;

            }

            s->vram_ptr[addr] = val;

#ifdef DEBUG_VGA_MEM

            printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);

#endif

            s->plane_updated |= mask; /* only used to detect font change */

            memory_region_set_dirty(&s->vram, addr, 1);

        }

    } else {

        /* standard VGA latched access */

        write_mode = s->gr[VGA_GFX_MODE] & 3;

        switch(write_mode) {

        default:

        case 0:

            /* rotate */

            b = s->gr[VGA_GFX_DATA_ROTATE] & 7;

            val = ((val >> b) | (val << (8 - b))) & 0xff;

            val |= val << 8;

            val |= val << 16;



            /* apply set/reset mask */

            set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];

            val = (val & ~set_mask) |

                (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);

            bit_mask = s->gr[VGA_GFX_BIT_MASK];

            break;

        case 1:

            val = s->latch;

            goto do_write;

        case 2:

            val = mask16[val & 0x0f];

            bit_mask = s->gr[VGA_GFX_BIT_MASK];

            break;

        case 3:

            /* rotate */

            b = s->gr[VGA_GFX_DATA_ROTATE] & 7;

            val = (val >> b) | (val << (8 - b));



            bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;

            val = mask16[s->gr[VGA_GFX_SR_VALUE]];

            break;

        }



        /* apply logical operation */

        func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;

        switch(func_select) {

        case 0:

        default:

            /* nothing to do */

            break;

        case 1:

            /* and */

            val &= s->latch;

            break;

        case 2:

            /* or */

            val |= s->latch;

            break;

        case 3:

            /* xor */

            val ^= s->latch;

            break;

        }



        /* apply bit mask */

        bit_mask |= bit_mask << 8;

        bit_mask |= bit_mask << 16;

        val = (val & bit_mask) | (s->latch & ~bit_mask);



    do_write:

        /* mask data according to sr[2] */

        mask = s->sr[VGA_SEQ_PLANE_WRITE];

        s->plane_updated |= mask; /* only used to detect font change */

        write_mask = mask16[mask];

        if (addr * sizeof(uint32_t) >= s->vram_size) {

            return;

        }

        ((uint32_t *)s->vram_ptr)[addr] =

            (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |

            (val & write_mask);

#ifdef DEBUG_VGA_MEM

        printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",

               addr * 4, write_mask, val);

#endif

        memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));

    }

}

void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)

{

    int memory_map_mode, plane, write_mode, b, func_select, mask;

    uint32_t write_mask, bit_mask, set_mask;



#ifdef DEBUG_VGA_MEM

    printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);

#endif

    

    memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;

    addr &= 0x1ffff;

    switch(memory_map_mode) {

    case 0:

        break;

    case 1:

        if (addr >= 0x10000)

            return;

        addr += s->bank_offset;

        break;

    case 2:

        addr -= 0x10000;

        if (addr >= 0x8000)

            return;

        break;

    default:

    case 3:

        addr -= 0x18000;

        if (addr >= 0x8000)

            return;

        break;

    }



    if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {

        

        plane = addr & 3;

        mask = (1 << plane);

        if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {

            assert(addr < s->vram_size);

            s->vram_ptr[addr] = val;

#ifdef DEBUG_VGA_MEM

            printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);

#endif

            s->plane_updated |= mask; 

            memory_region_set_dirty(&s->vram, addr, 1);

        }

    } else if (s->gr[VGA_GFX_MODE] & 0x10) {

        

        plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);

        mask = (1 << plane);

        if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {

            addr = ((addr & ~1) << 1) | plane;

            if (addr >= s->vram_size) {

                return;

            }

            s->vram_ptr[addr] = val;

#ifdef DEBUG_VGA_MEM

            printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);

#endif

            s->plane_updated |= mask; 

            memory_region_set_dirty(&s->vram, addr, 1);

        }

    } else {

        

        write_mode = s->gr[VGA_GFX_MODE] & 3;

        switch(write_mode) {

        default:

        case 0:

            

            b = s->gr[VGA_GFX_DATA_ROTATE] & 7;

            val = ((val >> b) | (val << (8 - b))) & 0xff;

            val |= val << 8;

            val |= val << 16;



            

            set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];

            val = (val & ~set_mask) |

                (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);

            bit_mask = s->gr[VGA_GFX_BIT_MASK];

            break;

        case 1:

            val = s->latch;

            goto do_write;

        case 2:

            val = mask16[val & 0x0f];

            bit_mask = s->gr[VGA_GFX_BIT_MASK];

            break;

        case 3:

            

            b = s->gr[VGA_GFX_DATA_ROTATE] & 7;

            val = (val >> b) | (val << (8 - b));



            bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;

            val = mask16[s->gr[VGA_GFX_SR_VALUE]];

            break;

        }



        

        func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;

        switch(func_select) {

        case 0:

        default:

            

            break;

        case 1:

            

            val &= s->latch;

            break;

        case 2:

            

            val |= s->latch;

            break;

        case 3:

            

            val ^= s->latch;

            break;

        }



        

        bit_mask |= bit_mask << 8;

        bit_mask |= bit_mask << 16;

        val = (val & bit_mask) | (s->latch & ~bit_mask);



    do_write:

        

        mask = s->sr[VGA_SEQ_PLANE_WRITE];

        s->plane_updated |= mask; 

        write_mask = mask16[mask];

        if (addr * sizeof(uint32_t) >= s->vram_size) {

            return;

        }

        ((uint32_t *)s->vram_ptr)[addr] =

            (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |

            (val & write_mask);

#ifdef DEBUG_VGA_MEM

        printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",

               addr * 4, write_mask, val);

#endif

        memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));

    }

}

    if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {     if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {         if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {         if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {         mask = s->sr[VGA_SEQ_PLANE_WRITE];
void FUNC_0(VGACommonState *VAR_0, hwaddr VAR_1, uint32_t VAR_2)

{

    int VAR_3, VAR_4, VAR_5, VAR_6, VAR_7, VAR_8;

    uint32_t write_mask, bit_mask, set_mask;



#ifdef DEBUG_VGA_MEM

    printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", VAR_1, VAR_2);

#endif

    

    VAR_3 = (VAR_0->gr[VGA_GFX_MISC] >> 2) & 3;

    VAR_1 &= 0x1ffff;

    switch(VAR_3) {

    case 0:

        break;

    case 1:

        if (VAR_1 >= 0x10000)

            return;

        VAR_1 += VAR_0->bank_offset;

        break;

    case 2:

        VAR_1 -= 0x10000;

        if (VAR_1 >= 0x8000)

            return;

        break;

    default:

    case 3:

        VAR_1 -= 0x18000;

        if (VAR_1 >= 0x8000)

            return;

        break;

    }



    if (VAR_0->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {

        

        VAR_4 = VAR_1 & 3;

        VAR_8 = (1 << VAR_4);

        if (VAR_0->sr[VGA_SEQ_PLANE_WRITE] & VAR_8) {

            assert(VAR_1 < VAR_0->vram_size);

            VAR_0->vram_ptr[VAR_1] = VAR_2;

#ifdef DEBUG_VGA_MEM

            printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", VAR_1);

#endif

            VAR_0->plane_updated |= VAR_8; 

            memory_region_set_dirty(&VAR_0->vram, VAR_1, 1);

        }

    } else if (VAR_0->gr[VGA_GFX_MODE] & 0x10) {

        

        VAR_4 = (VAR_0->gr[VGA_GFX_PLANE_READ] & 2) | (VAR_1 & 1);

        VAR_8 = (1 << VAR_4);

        if (VAR_0->sr[VGA_SEQ_PLANE_WRITE] & VAR_8) {

            VAR_1 = ((VAR_1 & ~1) << 1) | VAR_4;

            if (VAR_1 >= VAR_0->vram_size) {

                return;

            }

            VAR_0->vram_ptr[VAR_1] = VAR_2;

#ifdef DEBUG_VGA_MEM

            printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", VAR_1);

#endif

            VAR_0->plane_updated |= VAR_8; 

            memory_region_set_dirty(&VAR_0->vram, VAR_1, 1);

        }

    } else {

        

        VAR_5 = VAR_0->gr[VGA_GFX_MODE] & 3;

        switch(VAR_5) {

        default:

        case 0:

            

            VAR_6 = VAR_0->gr[VGA_GFX_DATA_ROTATE] & 7;

            VAR_2 = ((VAR_2 >> VAR_6) | (VAR_2 << (8 - VAR_6))) & 0xff;

            VAR_2 |= VAR_2 << 8;

            VAR_2 |= VAR_2 << 16;



            

            set_mask = mask16[VAR_0->gr[VGA_GFX_SR_ENABLE]];

            VAR_2 = (VAR_2 & ~set_mask) |

                (mask16[VAR_0->gr[VGA_GFX_SR_VALUE]] & set_mask);

            bit_mask = VAR_0->gr[VGA_GFX_BIT_MASK];

            break;

        case 1:

            VAR_2 = VAR_0->latch;

            goto do_write;

        case 2:

            VAR_2 = mask16[VAR_2 & 0x0f];

            bit_mask = VAR_0->gr[VGA_GFX_BIT_MASK];

            break;

        case 3:

            

            VAR_6 = VAR_0->gr[VGA_GFX_DATA_ROTATE] & 7;

            VAR_2 = (VAR_2 >> VAR_6) | (VAR_2 << (8 - VAR_6));



            bit_mask = VAR_0->gr[VGA_GFX_BIT_MASK] & VAR_2;

            VAR_2 = mask16[VAR_0->gr[VGA_GFX_SR_VALUE]];

            break;

        }



        

        VAR_7 = VAR_0->gr[VGA_GFX_DATA_ROTATE] >> 3;

        switch(VAR_7) {

        case 0:

        default:

            

            break;

        case 1:

            

            VAR_2 &= VAR_0->latch;

            break;

        case 2:

            

            VAR_2 |= VAR_0->latch;

            break;

        case 3:

            

            VAR_2 ^= VAR_0->latch;

            break;

        }



        

        bit_mask |= bit_mask << 8;

        bit_mask |= bit_mask << 16;

        VAR_2 = (VAR_2 & bit_mask) | (VAR_0->latch & ~bit_mask);



    do_write:

        

        VAR_8 = VAR_0->sr[VGA_SEQ_PLANE_WRITE];

        VAR_0->plane_updated |= VAR_8; 

        write_mask = mask16[VAR_8];

        if (VAR_1 * sizeof(uint32_t) >= VAR_0->vram_size) {

            return;

        }

        ((uint32_t *)VAR_0->vram_ptr)[VAR_1] =

            (((uint32_t *)VAR_0->vram_ptr)[VAR_1] & ~write_mask) |

            (VAR_2 & write_mask);

#ifdef DEBUG_VGA_MEM

        printf("vga: latch: [0x" TARGET_FMT_plx "] VAR_8=0x%08x VAR_2=0x%08x\n",

               VAR_1 * 4, write_mask, VAR_2);

#endif

        memory_region_set_dirty(&VAR_0->vram, VAR_1 << 2, sizeof(uint32_t));

    }

}

void FUNC_0(VGACommonState *VAR_0, hwaddr VAR_1, uint32_t VAR_2)
{ int VAR_3, VAR_4, VAR_5, VAR_6, VAR_7, VAR_8; uint32_t write_mask, bit_mask, set_mask; #ifdef DEBUG_VGA_MEM
printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", VAR_1, VAR_2); #endif
VAR_3 = (VAR_0->gr[VGA_GFX_MISC] >> 2) & 3; VAR_1 &= 0x1ffff; switch(VAR_3) { case 0:
break; case 1:
if (VAR_1 >= 0x10000)
return; VAR_1 += VAR_0->bank_offset; break; case 2:
VAR_1 -= 0x10000; if (VAR_1 >= 0x8000)
return; break; default:
case 3:
VAR_1 -= 0x18000; if (VAR_1 >= 0x8000)
return; break; } if (VAR_0->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) { VAR_4 = VAR_1 & 3; VAR_8 = (1 << VAR_4); if (VAR_0->sr[VGA_SEQ_PLANE_WRITE] & VAR_8) { assert(VAR_1 < VAR_0->vram_size); VAR_0->vram_ptr[VAR_1] = VAR_2; #ifdef DEBUG_VGA_MEM
printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", VAR_1); #endif
VAR_0->plane_updated |= VAR_8; memory_region_set_dirty(&VAR_0->vram, VAR_1, 1); } } else if (VAR_0->gr[VGA_GFX_MODE] & 0x10) { VAR_4 = (VAR_0->gr[VGA_GFX_PLANE_READ] & 2) | (VAR_1 & 1); VAR_8 = (1 << VAR_4); if (VAR_0->sr[VGA_SEQ_PLANE_WRITE] & VAR_8) { VAR_1 = ((VAR_1 & ~1) << 1) | VAR_4; if (VAR_1 >= VAR_0->vram_size) { return; } VAR_0->vram_ptr[VAR_1] = VAR_2; #ifdef DEBUG_VGA_MEM
printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", VAR_1); #endif
VAR_0->plane_updated |= VAR_8; memory_region_set_dirty(&VAR_0->vram, VAR_1, 1); } } else { VAR_5 = VAR_0->gr[VGA_GFX_MODE] & 3; switch(VAR_5) { default:
case 0:
VAR_6 = VAR_0->gr[VGA_GFX_DATA_ROTATE] & 7; VAR_2 = ((VAR_2 >> VAR_6) | (VAR_2 << (8 - VAR_6))) & 0xff; VAR_2 |= VAR_2 << 8; VAR_2 |= VAR_2 << 16; set_mask = mask16[VAR_0->gr[VGA_GFX_SR_ENABLE]]; VAR_2 = (VAR_2 & ~set_mask) |
(mask16[VAR_0->gr[VGA_GFX_SR_VALUE]] & set_mask); bit_mask = VAR_0->gr[VGA_GFX_BIT_MASK]; break; case 1:
VAR_2 = VAR_0->latch; goto do_write; case 2:
VAR_2 = mask16[VAR_2 & 0x0f]; bit_mask = VAR_0->gr[VGA_GFX_BIT_MASK]; break; case 3:
VAR_6 = VAR_0->gr[VGA_GFX_DATA_ROTATE] & 7; VAR_2 = (VAR_2 >> VAR_6) | (VAR_2 << (8 - VAR_6)); bit_mask = VAR_0->gr[VGA_GFX_BIT_MASK] & VAR_2; VAR_2 = mask16[VAR_0->gr[VGA_GFX_SR_VALUE]]; break; } VAR_7 = VAR_0->gr[VGA_GFX_DATA_ROTATE] >> 3; switch(VAR_7) { case 0:
default:
break; case 1:
VAR_2 &= VAR_0->latch; break; case 2:
VAR_2 |= VAR_0->latch; break; case 3:
VAR_2 ^= VAR_0->latch; break; } bit_mask |= bit_mask << 8; bit_mask |= bit_mask << 16; VAR_2 = (VAR_2 & bit_mask) | (VAR_0->latch & ~bit_mask); do_write:
VAR_8 = VAR_0->sr[VGA_SEQ_PLANE_WRITE]; VAR_0->plane_updated |= VAR_8; write_mask = mask16[VAR_8]; if (VAR_1 * sizeof(uint32_t) >= VAR_0->vram_size) { return; } ((uint32_t *)VAR_0->vram_ptr)[VAR_1] =
(((uint32_t *)VAR_0->vram_ptr)[VAR_1] & ~write_mask) |
(VAR_2 & write_mask); #ifdef DEBUG_VGA_MEM
printf("vga: latch: [0x" TARGET_FMT_plx "] VAR_8=0x%08x VAR_2=0x%08x\n",
VAR_1 * 4, write_mask, VAR_2); #endif
memory_region_set_dirty(&VAR_0->vram, VAR_1 << 2, sizeof(uint32_t)); } }