static void port92_write(void *opaque, hwaddr addr, uint64_t val,

                         unsigned size)

{

    Port92State *s = opaque;

    int oldval = s->outport;



    DPRINTF("port92: write 0x%02" PRIx64 "\n", val);

    s->outport = val;

    qemu_set_irq(*s->a20_out, (val >> 1) & 1);

    if ((val & 1) && !(oldval & 1)) {

        qemu_system_reset_request();

    }

}

static void port92_write(void *opaque, hwaddr addr, uint64_t val,

                         unsigned size)

{

    Port92State *s = opaque;

    int oldval = s->outport;



    DPRINTF("port92: write 0x%02" PRIx64 "\n", val);

    s->outport = val;

    qemu_set_irq(*s->a20_out, (val >> 1) & 1);

    if ((val & 1) && !(oldval & 1)) {

        qemu_system_reset_request();

    }

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1, uint64_t VAR_2,

                         unsigned VAR_3)

{

    Port92State *s = VAR_0;

    int VAR_4 = s->outport;



    DPRINTF("port92: write 0x%02" PRIx64 "\n", VAR_2);

    s->outport = VAR_2;

    qemu_set_irq(*s->a20_out, (VAR_2 >> 1) & 1);

    if ((VAR_2 & 1) && !(VAR_4 & 1)) {

        qemu_system_reset_request();

    }

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1, uint64_t VAR_2,
unsigned VAR_3)
{ Port92State *s = VAR_0; int VAR_4 = s->outport; DPRINTF("port92: write 0x%02" PRIx64 "\n", VAR_2); s->outport = VAR_2; qemu_set_irq(*s->a20_out, (VAR_2 >> 1) & 1); if ((VAR_2 & 1) && !(VAR_4 & 1)) { qemu_system_reset_request(); } }