static void ppc_core99_init (int ram_size, int vga_ram_size,

                             const char *boot_device, DisplayState *ds,

                             const char **fd_filename, int snapshot,

                             const char *kernel_filename,

                             const char *kernel_cmdline,

                             const char *initrd_filename,

                             const char *cpu_model)

{

    CPUState *env = NULL, *envs[MAX_CPUS];

    char buf[1024];

    qemu_irq *pic, **openpic_irqs;

    int unin_memory;

    int linux_boot, i;

    unsigned long bios_offset, vga_bios_offset;

    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;

    PCIBus *pci_bus;

    nvram_t nvram;

#if 0

    MacIONVRAMState *nvr;

    int nvram_mem_index;

#endif

    m48t59_t *m48t59;

    int vga_bios_size, bios_size;

    qemu_irq *dummy_irq;

    int pic_mem_index, dbdma_mem_index, cuda_mem_index;

    int ide_mem_index[2];

    int ppc_boot_device = boot_device[0];



    linux_boot = (kernel_filename != NULL);



    /* init CPUs */

    if (cpu_model == NULL)

        cpu_model = "default";

    for (i = 0; i < smp_cpus; i++) {

        env = cpu_init(cpu_model);

        if (!env) {

            fprintf(stderr, "Unable to find PowerPC CPU definition\n");

            exit(1);

        }

        /* Set time-base frequency to 100 Mhz */

        cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);

#if 0

        env->osi_call = vga_osi_call;

#endif

        qemu_register_reset(&cpu_ppc_reset, env);

        register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);

        envs[i] = env;

    }

    if (env->nip < 0xFFF80000) {

        /* Special test for PowerPC 601:

         * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.

         * But the NVRAM is located at 0xFFF04000...

         */

        cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n");

    }



    /* allocate RAM */

    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);



    /* allocate and load BIOS */

    bios_offset = ram_size + vga_ram_size;

    if (bios_name == NULL)

        bios_name = BIOS_FILENAME;

    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);

    bios_size = load_image(buf, phys_ram_base + bios_offset);

    if (bios_size < 0 || bios_size > BIOS_SIZE) {

        cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);

        exit(1);

    }

    bios_size = (bios_size + 0xfff) & ~0xfff;

    if (bios_size > 0x00080000) {

        /* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */

        cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n");

    }

    cpu_register_physical_memory((uint32_t)(-bios_size),

                                 bios_size, bios_offset | IO_MEM_ROM);



    /* allocate and load VGA BIOS */

    vga_bios_offset = bios_offset + bios_size;

    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);

    vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);

    if (vga_bios_size < 0) {

        /* if no bios is present, we can still work */

        fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);

        vga_bios_size = 0;

    } else {

        /* set a specific header (XXX: find real Apple format for NDRV

           drivers) */

        phys_ram_base[vga_bios_offset] = 'N';

        phys_ram_base[vga_bios_offset + 1] = 'D';

        phys_ram_base[vga_bios_offset + 2] = 'R';

        phys_ram_base[vga_bios_offset + 3] = 'V';

        cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),

                     vga_bios_size);

        vga_bios_size += 8;

    }

    vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;



    if (linux_boot) {

        kernel_base = KERNEL_LOAD_ADDR;

        /* now we can load the kernel */

        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);

        if (kernel_size < 0) {

            cpu_abort(env, "qemu: could not load kernel '%s'\n",

                      kernel_filename);

            exit(1);

        }

        /* load initrd */

        if (initrd_filename) {

            initrd_base = INITRD_LOAD_ADDR;

            initrd_size = load_image(initrd_filename,

                                     phys_ram_base + initrd_base);

            if (initrd_size < 0) {

                cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",

                          initrd_filename);

                exit(1);

            }

        } else {

            initrd_base = 0;

            initrd_size = 0;

        }

        ppc_boot_device = 'm';

    } else {

        kernel_base = 0;

        kernel_size = 0;

        initrd_base = 0;

        initrd_size = 0;

    }



    isa_mem_base = 0x80000000;



    /* Register 8 MB of ISA IO space */

    isa_mmio_init(0xf2000000, 0x00800000);



    /* UniN init */

    unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);

    cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);



    openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));

    openpic_irqs[0] =

        qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);

    for (i = 0; i < smp_cpus; i++) {

        /* Mac99 IRQ connection between OpenPIC outputs pins

         * and PowerPC input pins

         */

        switch (PPC_INPUT(env)) {

        case PPC_FLAGS_INPUT_6xx:

            openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);

            openpic_irqs[i][OPENPIC_OUTPUT_INT] =

                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];

            openpic_irqs[i][OPENPIC_OUTPUT_CINT] =

                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];

            openpic_irqs[i][OPENPIC_OUTPUT_MCK] =

                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];

            /* Not connected ? */

            openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;

            /* Check this */

            openpic_irqs[i][OPENPIC_OUTPUT_RESET] =

                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];

            break;

#if defined(TARGET_PPC64)

        case PPC_FLAGS_INPUT_970:

            openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);

            openpic_irqs[i][OPENPIC_OUTPUT_INT] =

                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];

            openpic_irqs[i][OPENPIC_OUTPUT_CINT] =

                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];

            openpic_irqs[i][OPENPIC_OUTPUT_MCK] =

                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];

            /* Not connected ? */

            openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;

            /* Check this */

            openpic_irqs[i][OPENPIC_OUTPUT_RESET] =

                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];

            break;

#endif /* defined(TARGET_PPC64) */

        default:

            cpu_abort(env, "Bus model not supported on mac99 machine\n");

            exit(1);

        }

    }

    pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);

    pci_bus = pci_pmac_init(pic);

    /* init basic PC hardware */

    pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,

                 ram_size, vga_ram_size,

                 vga_bios_offset, vga_bios_size);

    

    /* XXX: suppress that */

    dummy_irq = i8259_init(NULL);



    /* XXX: use Mac Serial port */

    serial_init(0x3f8, dummy_irq[4], serial_hds[0]);

    for(i = 0; i < nb_nics; i++) {

        if (!nd_table[i].model)

            nd_table[i].model = "ne2k_pci";

        pci_nic_init(pci_bus, &nd_table[i], -1);

    }

#if 1

    ide_mem_index[0] = pmac_ide_init(&bs_table[0], pic[0x13]);

    ide_mem_index[1] = pmac_ide_init(&bs_table[2], pic[0x14]);

#else

    pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);

#endif

    /* cuda also initialize ADB */

    cuda_init(&cuda_mem_index, pic[0x19]);

    

    adb_kbd_init(&adb_bus);

    adb_mouse_init(&adb_bus);



    dbdma_init(&dbdma_mem_index);



    macio_init(pci_bus, 0x0022, 0, pic_mem_index, dbdma_mem_index,

               cuda_mem_index, NULL, 2, ide_mem_index);



    if (usb_enabled) {

        usb_ohci_init_pci(pci_bus, 3, -1);

    }



    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)

        graphic_depth = 15;

#if 0 /* XXX: this is ugly but needed for now, or OHW won't boot */

    /* The NewWorld NVRAM is not located in the MacIO device */

    nvr = macio_nvram_init(&nvram_mem_index, 0x2000);

    pmac_format_nvram_partition(nvr, 0x2000);

    macio_nvram_map(nvr, 0xFFF04000);

    nvram.opaque = nvr;

    nvram.read_fn = &macio_nvram_read;

    nvram.write_fn = &macio_nvram_write;

#else

    m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);

    nvram.opaque = m48t59;

    nvram.read_fn = &m48t59_read;

    nvram.write_fn = &m48t59_write;

#endif

    PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "MAC99", ram_size,

                         ppc_boot_device, kernel_base, kernel_size,

                         kernel_cmdline,

                         initrd_base, initrd_size,

                         /* XXX: need an option to load a NVRAM image */

                         0,

                         graphic_width, graphic_height, graphic_depth);

    /* No PCI init: the BIOS will do it */



    /* Special port to get debug messages from Open-Firmware */

    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);

 }

static void ppc_core99_init (int ram_size, int vga_ram_size,

                             const char *boot_device, DisplayState *ds,

                             const char **fd_filename, int snapshot,

                             const char *kernel_filename,

                             const char *kernel_cmdline,

                             const char *initrd_filename,

                             const char *cpu_model)

{

    CPUState *env = NULL, *envs[MAX_CPUS];

    char buf[1024];

    qemu_irq *pic, **openpic_irqs;

    int unin_memory;

    int linux_boot, i;

    unsigned long bios_offset, vga_bios_offset;

    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;

    PCIBus *pci_bus;

    nvram_t nvram;

#if 0

    MacIONVRAMState *nvr;

    int nvram_mem_index;

#endif

    m48t59_t *m48t59;

    int vga_bios_size, bios_size;

    qemu_irq *dummy_irq;

    int pic_mem_index, dbdma_mem_index, cuda_mem_index;

    int ide_mem_index[2];

    int ppc_boot_device = boot_device[0];



    linux_boot = (kernel_filename != NULL);



    

    if (cpu_model == NULL)

        cpu_model = "default";

    for (i = 0; i < smp_cpus; i++) {

        env = cpu_init(cpu_model);

        if (!env) {

            fprintf(stderr, "Unable to find PowerPC CPU definition\n");

            exit(1);

        }

        

        cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);

#if 0

        env->osi_call = vga_osi_call;

#endif

        qemu_register_reset(&cpu_ppc_reset, env);

        register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);

        envs[i] = env;

    }

    if (env->nip < 0xFFF80000) {

        







        cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n");

    }



    

    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);



    

    bios_offset = ram_size + vga_ram_size;

    if (bios_name == NULL)

        bios_name = BIOS_FILENAME;

    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);

    bios_size = load_image(buf, phys_ram_base + bios_offset);

    if (bios_size < 0 || bios_size > BIOS_SIZE) {

        cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);

        exit(1);

    }

    bios_size = (bios_size + 0xfff) & ~0xfff;

    if (bios_size > 0x00080000) {

        

        cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n");

    }

    cpu_register_physical_memory((uint32_t)(-bios_size),

                                 bios_size, bios_offset | IO_MEM_ROM);



    

    vga_bios_offset = bios_offset + bios_size;

    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);

    vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);

    if (vga_bios_size < 0) {

        

        fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);

        vga_bios_size = 0;

    } else {

        



        phys_ram_base[vga_bios_offset] = 'N';

        phys_ram_base[vga_bios_offset + 1] = 'D';

        phys_ram_base[vga_bios_offset + 2] = 'R';

        phys_ram_base[vga_bios_offset + 3] = 'V';

        cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),

                     vga_bios_size);

        vga_bios_size += 8;

    }

    vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;



    if (linux_boot) {

        kernel_base = KERNEL_LOAD_ADDR;

        

        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);

        if (kernel_size < 0) {

            cpu_abort(env, "qemu: could not load kernel '%s'\n",

                      kernel_filename);

            exit(1);

        }

        

        if (initrd_filename) {

            initrd_base = INITRD_LOAD_ADDR;

            initrd_size = load_image(initrd_filename,

                                     phys_ram_base + initrd_base);

            if (initrd_size < 0) {

                cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",

                          initrd_filename);

                exit(1);

            }

        } else {

            initrd_base = 0;

            initrd_size = 0;

        }

        ppc_boot_device = 'm';

    } else {

        kernel_base = 0;

        kernel_size = 0;

        initrd_base = 0;

        initrd_size = 0;

    }



    isa_mem_base = 0x80000000;



    

    isa_mmio_init(0xf2000000, 0x00800000);



    

    unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);

    cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);



    openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));

    openpic_irqs[0] =

        qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);

    for (i = 0; i < smp_cpus; i++) {

        





        switch (PPC_INPUT(env)) {

        case PPC_FLAGS_INPUT_6xx:

            openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);

            openpic_irqs[i][OPENPIC_OUTPUT_INT] =

                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];

            openpic_irqs[i][OPENPIC_OUTPUT_CINT] =

                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];

            openpic_irqs[i][OPENPIC_OUTPUT_MCK] =

                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];

            

            openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;

            

            openpic_irqs[i][OPENPIC_OUTPUT_RESET] =

                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];

            break;

#if defined(TARGET_PPC64)

        case PPC_FLAGS_INPUT_970:

            openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);

            openpic_irqs[i][OPENPIC_OUTPUT_INT] =

                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];

            openpic_irqs[i][OPENPIC_OUTPUT_CINT] =

                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];

            openpic_irqs[i][OPENPIC_OUTPUT_MCK] =

                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];

            

            openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;

            

            openpic_irqs[i][OPENPIC_OUTPUT_RESET] =

                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];

            break;

#endif 

        default:

            cpu_abort(env, "Bus model not supported on mac99 machine\n");

            exit(1);

        }

    }

    pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);

    pci_bus = pci_pmac_init(pic);

    

    pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,

                 ram_size, vga_ram_size,

                 vga_bios_offset, vga_bios_size);

    

    

    dummy_irq = i8259_init(NULL);



    

    serial_init(0x3f8, dummy_irq[4], serial_hds[0]);

    for(i = 0; i < nb_nics; i++) {

        if (!nd_table[i].model)

            nd_table[i].model = "ne2k_pci";

        pci_nic_init(pci_bus, &nd_table[i], -1);

    }

#if 1

    ide_mem_index[0] = pmac_ide_init(&bs_table[0], pic[0x13]);

    ide_mem_index[1] = pmac_ide_init(&bs_table[2], pic[0x14]);

#else

    pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);

#endif

    

    cuda_init(&cuda_mem_index, pic[0x19]);

    

    adb_kbd_init(&adb_bus);

    adb_mouse_init(&adb_bus);



    dbdma_init(&dbdma_mem_index);



    macio_init(pci_bus, 0x0022, 0, pic_mem_index, dbdma_mem_index,

               cuda_mem_index, NULL, 2, ide_mem_index);



    if (usb_enabled) {

        usb_ohci_init_pci(pci_bus, 3, -1);

    }



    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)

        graphic_depth = 15;

#if 0 

    

    nvr = macio_nvram_init(&nvram_mem_index, 0x2000);

    pmac_format_nvram_partition(nvr, 0x2000);

    macio_nvram_map(nvr, 0xFFF04000);

    nvram.opaque = nvr;

    nvram.read_fn = &macio_nvram_read;

    nvram.write_fn = &macio_nvram_write;

#else

    m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);

    nvram.opaque = m48t59;

    nvram.read_fn = &m48t59_read;

    nvram.write_fn = &m48t59_write;

#endif

    PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "MAC99", ram_size,

                         ppc_boot_device, kernel_base, kernel_size,

                         kernel_cmdline,

                         initrd_base, initrd_size,

                         

                         0,

                         graphic_width, graphic_height, graphic_depth);

    



    

    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);

 }

static void FUNC_0 (int VAR_0, int VAR_1,

                             const char *VAR_2, DisplayState *VAR_3,

                             const char **VAR_4, int VAR_5,

                             const char *VAR_6,

                             const char *VAR_7,

                             const char *VAR_8,

                             const char *VAR_9)

{

    CPUState *env = NULL, *envs[MAX_CPUS];

    char VAR_10[1024];

    qemu_irq *pic, **openpic_irqs;

    int VAR_11;

    int VAR_12, VAR_13;

    unsigned long VAR_14, VAR_15;

    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;

    PCIBus *pci_bus;

    nvram_t nvram;

#if 0

    MacIONVRAMState *nvr;

    int nvram_mem_index;

#endif

    m48t59_t *m48t59;

    int VAR_16, VAR_17;

    qemu_irq *dummy_irq;

    int VAR_18, VAR_19, VAR_20;

    int VAR_21[2];

    int VAR_22 = VAR_2[0];



    VAR_12 = (VAR_6 != NULL);



    

    if (VAR_9 == NULL)

        VAR_9 = "default";

    for (VAR_13 = 0; VAR_13 < smp_cpus; VAR_13++) {

        env = cpu_init(VAR_9);

        if (!env) {

            fprintf(stderr, "Unable to find PowerPC CPU definition\n");

            exit(1);

        }

        

        cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);

#if 0

        env->osi_call = vga_osi_call;

#endif

        qemu_register_reset(&cpu_ppc_reset, env);

        register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);

        envs[VAR_13] = env;

    }

    if (env->nip < 0xFFF80000) {

        







        cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n");

    }



    

    cpu_register_physical_memory(0, VAR_0, IO_MEM_RAM);



    

    VAR_14 = VAR_0 + VAR_1;

    if (bios_name == NULL)

        bios_name = BIOS_FILENAME;

    snprintf(VAR_10, sizeof(VAR_10), "%s/%s", bios_dir, bios_name);

    VAR_17 = load_image(VAR_10, phys_ram_base + VAR_14);

    if (VAR_17 < 0 || VAR_17 > BIOS_SIZE) {

        cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", VAR_10);

        exit(1);

    }

    VAR_17 = (VAR_17 + 0xfff) & ~0xfff;

    if (VAR_17 > 0x00080000) {

        

        cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n");

    }

    cpu_register_physical_memory((uint32_t)(-VAR_17),

                                 VAR_17, VAR_14 | IO_MEM_ROM);



    

    VAR_15 = VAR_14 + VAR_17;

    snprintf(VAR_10, sizeof(VAR_10), "%s/%s", bios_dir, VGABIOS_FILENAME);

    VAR_16 = load_image(VAR_10, phys_ram_base + VAR_15 + 8);

    if (VAR_16 < 0) {

        

        fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", VAR_10);

        VAR_16 = 0;

    } else {

        



        phys_ram_base[VAR_15] = 'N';

        phys_ram_base[VAR_15 + 1] = 'D';

        phys_ram_base[VAR_15 + 2] = 'R';

        phys_ram_base[VAR_15 + 3] = 'V';

        cpu_to_be32w((uint32_t *)(phys_ram_base + VAR_15 + 4),

                     VAR_16);

        VAR_16 += 8;

    }

    VAR_16 = (VAR_16 + 0xfff) & ~0xfff;



    if (VAR_12) {

        kernel_base = KERNEL_LOAD_ADDR;

        

        kernel_size = load_image(VAR_6, phys_ram_base + kernel_base);

        if (kernel_size < 0) {

            cpu_abort(env, "qemu: could not load kernel '%s'\n",

                      VAR_6);

            exit(1);

        }

        

        if (VAR_8) {

            initrd_base = INITRD_LOAD_ADDR;

            initrd_size = load_image(VAR_8,

                                     phys_ram_base + initrd_base);

            if (initrd_size < 0) {

                cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",

                          VAR_8);

                exit(1);

            }

        } else {

            initrd_base = 0;

            initrd_size = 0;

        }

        VAR_22 = 'm';

    } else {

        kernel_base = 0;

        kernel_size = 0;

        initrd_base = 0;

        initrd_size = 0;

    }



    isa_mem_base = 0x80000000;



    

    isa_mmio_init(0xf2000000, 0x00800000);



    

    VAR_11 = cpu_register_io_memory(0, unin_read, unin_write, NULL);

    cpu_register_physical_memory(0xf8000000, 0x00001000, VAR_11);



    openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));

    openpic_irqs[0] =

        qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);

    for (VAR_13 = 0; VAR_13 < smp_cpus; VAR_13++) {

        





        switch (PPC_INPUT(env)) {

        case PPC_FLAGS_INPUT_6xx:

            openpic_irqs[VAR_13] = openpic_irqs[0] + (VAR_13 * OPENPIC_OUTPUT_NB);

            openpic_irqs[VAR_13][OPENPIC_OUTPUT_INT] =

                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];

            openpic_irqs[VAR_13][OPENPIC_OUTPUT_CINT] =

                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];

            openpic_irqs[VAR_13][OPENPIC_OUTPUT_MCK] =

                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];

            

            openpic_irqs[VAR_13][OPENPIC_OUTPUT_DEBUG] = NULL;

            

            openpic_irqs[VAR_13][OPENPIC_OUTPUT_RESET] =

                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];

            break;

#if defined(TARGET_PPC64)

        case PPC_FLAGS_INPUT_970:

            openpic_irqs[VAR_13] = openpic_irqs[0] + (VAR_13 * OPENPIC_OUTPUT_NB);

            openpic_irqs[VAR_13][OPENPIC_OUTPUT_INT] =

                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];

            openpic_irqs[VAR_13][OPENPIC_OUTPUT_CINT] =

                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];

            openpic_irqs[VAR_13][OPENPIC_OUTPUT_MCK] =

                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];

            

            openpic_irqs[VAR_13][OPENPIC_OUTPUT_DEBUG] = NULL;

            

            openpic_irqs[VAR_13][OPENPIC_OUTPUT_RESET] =

                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];

            break;

#endif 

        default:

            cpu_abort(env, "Bus model not supported on mac99 machine\n");

            exit(1);

        }

    }

    pic = openpic_init(NULL, &VAR_18, smp_cpus, openpic_irqs, NULL);

    pci_bus = pci_pmac_init(pic);

    

    pci_vga_init(pci_bus, VAR_3, phys_ram_base + VAR_0,

                 VAR_0, VAR_1,

                 VAR_15, VAR_16);

    

    

    dummy_irq = i8259_init(NULL);



    

    serial_init(0x3f8, dummy_irq[4], serial_hds[0]);

    for(VAR_13 = 0; VAR_13 < nb_nics; VAR_13++) {

        if (!nd_table[VAR_13].model)

            nd_table[VAR_13].model = "ne2k_pci";

        pci_nic_init(pci_bus, &nd_table[VAR_13], -1);

    }

#if 1

    VAR_21[0] = pmac_ide_init(&bs_table[0], pic[0x13]);

    VAR_21[1] = pmac_ide_init(&bs_table[2], pic[0x14]);

#else

    pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);

#endif

    

    cuda_init(&VAR_20, pic[0x19]);

    

    adb_kbd_init(&adb_bus);

    adb_mouse_init(&adb_bus);



    dbdma_init(&VAR_19);



    macio_init(pci_bus, 0x0022, 0, VAR_18, VAR_19,

               VAR_20, NULL, 2, VAR_21);



    if (usb_enabled) {

        usb_ohci_init_pci(pci_bus, 3, -1);

    }



    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)

        graphic_depth = 15;

#if 0 

    

    nvr = macio_nvram_init(&nvram_mem_index, 0x2000);

    pmac_format_nvram_partition(nvr, 0x2000);

    macio_nvram_map(nvr, 0xFFF04000);

    nvram.opaque = nvr;

    nvram.read_fn = &macio_nvram_read;

    nvram.write_fn = &macio_nvram_write;

#else

    m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);

    nvram.opaque = m48t59;

    nvram.read_fn = &m48t59_read;

    nvram.write_fn = &m48t59_write;

#endif

    PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "MAC99", VAR_0,

                         VAR_22, kernel_base, kernel_size,

                         VAR_7,

                         initrd_base, initrd_size,

                         

                         0,

                         graphic_width, graphic_height, graphic_depth);

    



    

    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);

 }

static void FUNC_0 (int VAR_0, int VAR_1,
const char *VAR_2, DisplayState *VAR_3,
const char **VAR_4, int VAR_5,
const char *VAR_6,
const char *VAR_7,
const char *VAR_8,
const char *VAR_9)
{ CPUState *env = NULL, *envs[MAX_CPUS]; char VAR_10[1024]; qemu_irq *pic, **openpic_irqs; int VAR_11; int VAR_12, VAR_13; unsigned long VAR_14, VAR_15; uint32_t kernel_base, kernel_size, initrd_base, initrd_size; PCIBus *pci_bus; nvram_t nvram; #if 0
MacIONVRAMState *nvr; int nvram_mem_index; #endif
m48t59_t *m48t59; int VAR_16, VAR_17; qemu_irq *dummy_irq; int VAR_18, VAR_19, VAR_20; int VAR_21[2]; int VAR_22 = VAR_2[0]; VAR_12 = (VAR_6 != NULL); if (VAR_9 == NULL)
VAR_9 = "default"; for (VAR_13 = 0; VAR_13 < smp_cpus; VAR_13++) { env = cpu_init(VAR_9); if (!env) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); #if 0
env->osi_call = vga_osi_call; #endif
qemu_register_reset(&cpu_ppc_reset, env); register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); envs[VAR_13] = env; } if (env->nip < 0xFFF80000) { cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n"); } cpu_register_physical_memory(0, VAR_0, IO_MEM_RAM); VAR_14 = VAR_0 + VAR_1; if (bios_name == NULL)
bios_name = BIOS_FILENAME; snprintf(VAR_10, sizeof(VAR_10), "%s/%s", bios_dir, bios_name); VAR_17 = load_image(VAR_10, phys_ram_base + VAR_14); if (VAR_17 < 0 || VAR_17 > BIOS_SIZE) { cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", VAR_10); exit(1); } VAR_17 = (VAR_17 + 0xfff) & ~0xfff; if (VAR_17 > 0x00080000) { cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n"); } cpu_register_physical_memory((uint32_t)(-VAR_17),
VAR_17, VAR_14 | IO_MEM_ROM); VAR_15 = VAR_14 + VAR_17; snprintf(VAR_10, sizeof(VAR_10), "%s/%s", bios_dir, VGABIOS_FILENAME); VAR_16 = load_image(VAR_10, phys_ram_base + VAR_15 + 8); if (VAR_16 < 0) { fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", VAR_10); VAR_16 = 0; } else { phys_ram_base[VAR_15] = 'N'; phys_ram_base[VAR_15 + 1] = 'D'; phys_ram_base[VAR_15 + 2] = 'R'; phys_ram_base[VAR_15 + 3] = 'V'; cpu_to_be32w((uint32_t *)(phys_ram_base + VAR_15 + 4),
VAR_16); VAR_16 += 8; } VAR_16 = (VAR_16 + 0xfff) & ~0xfff; if (VAR_12) { kernel_base = KERNEL_LOAD_ADDR; kernel_size = load_image(VAR_6, phys_ram_base + kernel_base); if (kernel_size < 0) { cpu_abort(env, "qemu: could not load kernel '%s'\n",
VAR_6); exit(1); } if (VAR_8) { initrd_base = INITRD_LOAD_ADDR; initrd_size = load_image(VAR_8,
phys_ram_base + initrd_base); if (initrd_size < 0) { cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
VAR_8); exit(1); } } else { initrd_base = 0; initrd_size = 0; } VAR_22 = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; } isa_mem_base = 0x80000000; isa_mmio_init(0xf2000000, 0x00800000); VAR_11 = cpu_register_io_memory(0, unin_read, unin_write, NULL); cpu_register_physical_memory(0xf8000000, 0x00001000, VAR_11); openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); openpic_irqs[0] =
qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); for (VAR_13 = 0; VAR_13 < smp_cpus; VAR_13++) { switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_6xx:
openpic_irqs[VAR_13] = openpic_irqs[0] + (VAR_13 * OPENPIC_OUTPUT_NB); openpic_irqs[VAR_13][OPENPIC_OUTPUT_INT] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[VAR_13][OPENPIC_OUTPUT_CINT] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[VAR_13][OPENPIC_OUTPUT_MCK] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; openpic_irqs[VAR_13][OPENPIC_OUTPUT_DEBUG] = NULL; openpic_irqs[VAR_13][OPENPIC_OUTPUT_RESET] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; break; #if defined(TARGET_PPC64)
case PPC_FLAGS_INPUT_970:
openpic_irqs[VAR_13] = openpic_irqs[0] + (VAR_13 * OPENPIC_OUTPUT_NB); openpic_irqs[VAR_13][OPENPIC_OUTPUT_INT] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[VAR_13][OPENPIC_OUTPUT_CINT] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[VAR_13][OPENPIC_OUTPUT_MCK] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; openpic_irqs[VAR_13][OPENPIC_OUTPUT_DEBUG] = NULL; openpic_irqs[VAR_13][OPENPIC_OUTPUT_RESET] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; break; #endif
default:
cpu_abort(env, "Bus model not supported on mac99 machine\n"); exit(1); } } pic = openpic_init(NULL, &VAR_18, smp_cpus, openpic_irqs, NULL); pci_bus = pci_pmac_init(pic); pci_vga_init(pci_bus, VAR_3, phys_ram_base + VAR_0,
VAR_0, VAR_1,
VAR_15, VAR_16); dummy_irq = i8259_init(NULL); serial_init(0x3f8, dummy_irq[4], serial_hds[0]); for(VAR_13 = 0; VAR_13 < nb_nics; VAR_13++) { if (!nd_table[VAR_13].model)
nd_table[VAR_13].model = "ne2k_pci"; pci_nic_init(pci_bus, &nd_table[VAR_13], -1); } #if 1
VAR_21[0] = pmac_ide_init(&bs_table[0], pic[0x13]); VAR_21[1] = pmac_ide_init(&bs_table[2], pic[0x14]); #else
pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); #endif
cuda_init(&VAR_20, pic[0x19]); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); dbdma_init(&VAR_19); macio_init(pci_bus, 0x0022, 0, VAR_18, VAR_19,
VAR_20, NULL, 2, VAR_21); if (usb_enabled) { usb_ohci_init_pci(pci_bus, 3, -1); } if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
graphic_depth = 15; #if 0
nvr = macio_nvram_init(&nvram_mem_index, 0x2000); pmac_format_nvram_partition(nvr, 0x2000); macio_nvram_map(nvr, 0xFFF04000); nvram.opaque = nvr; nvram.read_fn = &macio_nvram_read; nvram.write_fn = &macio_nvram_write; #else
m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59); nvram.opaque = m48t59; nvram.read_fn = &m48t59_read; nvram.write_fn = &m48t59_write; #endif
PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "MAC99", VAR_0,
VAR_22, kernel_base, kernel_size,
VAR_7,
initrd_base, initrd_size,
0,
graphic_width, graphic_height, graphic_depth); register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); }