minimac2_write(void *opaque, target_phys_addr_t addr, uint64_t value,

               unsigned size)

{

    MilkymistMinimac2State *s = opaque;



    trace_milkymist_minimac2_memory_read(addr, value);



    addr >>= 2;

    switch (addr) {

    case R_MDIO:

    {

        /* MDIO_DI is read only */

        int mdio_di = (s->regs[R_MDIO] & MDIO_DI);

        s->regs[R_MDIO] = value;

        if (mdio_di) {

            s->regs[R_MDIO] |= mdio_di;

        } else {

            s->regs[R_MDIO] &= ~mdio_di;

        }



        minimac2_update_mdio(s);

    } break;

    case R_TXCOUNT:

        s->regs[addr] = value;

        if (value > 0) {

            minimac2_tx(s);

        }

        break;

    case R_STATE0:

    case R_STATE1:

        s->regs[addr] = value;

        update_rx_interrupt(s);

        break;

    case R_SETUP:

    case R_COUNT0:

    case R_COUNT1:

        s->regs[addr] = value;

        break;



    default:

        error_report("milkymist_minimac2: write access to unknown register 0x"

                TARGET_FMT_plx, addr << 2);

        break;

    }

}

minimac2_write(void *opaque, target_phys_addr_t addr, uint64_t value,

               unsigned size)

{

    MilkymistMinimac2State *s = opaque;



    trace_milkymist_minimac2_memory_read(addr, value);



    addr >>= 2;

    switch (addr) {

    case R_MDIO:

    {

        

        int mdio_di = (s->regs[R_MDIO] & MDIO_DI);

        s->regs[R_MDIO] = value;

        if (mdio_di) {

            s->regs[R_MDIO] |= mdio_di;

        } else {

            s->regs[R_MDIO] &= ~mdio_di;

        }



        minimac2_update_mdio(s);

    } break;

    case R_TXCOUNT:

        s->regs[addr] = value;

        if (value > 0) {

            minimac2_tx(s);

        }

        break;

    case R_STATE0:

    case R_STATE1:

        s->regs[addr] = value;

        update_rx_interrupt(s);

        break;

    case R_SETUP:

    case R_COUNT0:

    case R_COUNT1:

        s->regs[addr] = value;

        break;



    default:

        error_report("milkymist_minimac2: write access to unknown register 0x"

                TARGET_FMT_plx, addr << 2);

        break;

    }

}

FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint64_t VAR_2,

               unsigned VAR_3)

{

    MilkymistMinimac2State *s = VAR_0;



    trace_milkymist_minimac2_memory_read(VAR_1, VAR_2);



    VAR_1 >>= 2;

    switch (VAR_1) {

    case R_MDIO:

    {

        

        int VAR_4 = (s->regs[R_MDIO] & MDIO_DI);

        s->regs[R_MDIO] = VAR_2;

        if (VAR_4) {

            s->regs[R_MDIO] |= VAR_4;

        } else {

            s->regs[R_MDIO] &= ~VAR_4;

        }



        minimac2_update_mdio(s);

    } break;

    case R_TXCOUNT:

        s->regs[VAR_1] = VAR_2;

        if (VAR_2 > 0) {

            minimac2_tx(s);

        }

        break;

    case R_STATE0:

    case R_STATE1:

        s->regs[VAR_1] = VAR_2;

        update_rx_interrupt(s);

        break;

    case R_SETUP:

    case R_COUNT0:

    case R_COUNT1:

        s->regs[VAR_1] = VAR_2;

        break;



    default:

        error_report("milkymist_minimac2: write access to unknown register 0x"

                TARGET_FMT_plx, VAR_1 << 2);

        break;

    }

}

FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint64_t VAR_2,
unsigned VAR_3)
{ MilkymistMinimac2State *s = VAR_0; trace_milkymist_minimac2_memory_read(VAR_1, VAR_2); VAR_1 >>= 2; switch (VAR_1) { case R_MDIO:
{ int VAR_4 = (s->regs[R_MDIO] & MDIO_DI); s->regs[R_MDIO] = VAR_2; if (VAR_4) { s->regs[R_MDIO] |= VAR_4; } else { s->regs[R_MDIO] &= ~VAR_4; } minimac2_update_mdio(s); } break; case R_TXCOUNT:
s->regs[VAR_1] = VAR_2; if (VAR_2 > 0) { minimac2_tx(s); } break; case R_STATE0:
case R_STATE1:
s->regs[VAR_1] = VAR_2; update_rx_interrupt(s); break; case R_SETUP:
case R_COUNT0:
case R_COUNT1:
s->regs[VAR_1] = VAR_2; break; default:
error_report("milkymist_minimac2: write access to unknown register 0x"
TARGET_FMT_plx, VAR_1 << 2); break; } }