static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,

                                unsigned size)

{

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;

    int offset = addr;

    int bank_no, line_no;

    struct omap_intr_handler_bank_s *bank = NULL;



    if ((offset & 0xf80) == 0x80) {

        bank_no = (offset & 0x60) >> 5;

        if (bank_no < s->nbanks) {

            offset &= ~0x60;

            bank = &s->bank[bank_no];

        }

    }



    switch (offset) {

    case 0x00:	/* INTC_REVISION */

        return 0x21;



    case 0x10:	/* INTC_SYSCONFIG */

        return (s->autoidle >> 2) & 1;



    case 0x14:	/* INTC_SYSSTATUS */

        return 1;						/* RESETDONE */



    case 0x40:	/* INTC_SIR_IRQ */

        return s->sir_intr[0];



    case 0x44:	/* INTC_SIR_FIQ */

        return s->sir_intr[1];



    case 0x48:	/* INTC_CONTROL */

        return (!s->mask) << 2;					/* GLOBALMASK */



    case 0x4c:	/* INTC_PROTECTION */

        return 0;



    case 0x50:	/* INTC_IDLE */

        return s->autoidle & 3;



    /* Per-bank registers */

    case 0x80:	/* INTC_ITR */

        return bank->inputs;



    case 0x84:	/* INTC_MIR */

        return bank->mask;



    case 0x88:	/* INTC_MIR_CLEAR */

    case 0x8c:	/* INTC_MIR_SET */

        return 0;



    case 0x90:	/* INTC_ISR_SET */

        return bank->swi;



    case 0x94:	/* INTC_ISR_CLEAR */

        return 0;



    case 0x98:	/* INTC_PENDING_IRQ */

        return bank->irqs & ~bank->mask & ~bank->fiq;



    case 0x9c:	/* INTC_PENDING_FIQ */

        return bank->irqs & ~bank->mask & bank->fiq;



    /* Per-line registers */

    case 0x100 ... 0x300:	/* INTC_ILR */

        bank_no = (offset - 0x100) >> 7;

        if (bank_no > s->nbanks)

            break;

        bank = &s->bank[bank_no];

        line_no = (offset & 0x7f) >> 2;

        return (bank->priority[line_no] << 2) |

                ((bank->fiq >> line_no) & 1);

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,

                                unsigned size)

{

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;

    int offset = addr;

    int bank_no, line_no;

    struct omap_intr_handler_bank_s *bank = NULL;



    if ((offset & 0xf80) == 0x80) {

        bank_no = (offset & 0x60) >> 5;

        if (bank_no < s->nbanks) {

            offset &= ~0x60;

            bank = &s->bank[bank_no];

        }

    }



    switch (offset) {

    case 0x00:	

        return 0x21;



    case 0x10:	

        return (s->autoidle >> 2) & 1;



    case 0x14:	

        return 1;						



    case 0x40:	

        return s->sir_intr[0];



    case 0x44:	

        return s->sir_intr[1];



    case 0x48:	

        return (!s->mask) << 2;					



    case 0x4c:	

        return 0;



    case 0x50:	

        return s->autoidle & 3;



    

    case 0x80:	

        return bank->inputs;



    case 0x84:	

        return bank->mask;



    case 0x88:	

    case 0x8c:	

        return 0;



    case 0x90:	

        return bank->swi;



    case 0x94:	

        return 0;



    case 0x98:	

        return bank->irqs & ~bank->mask & ~bank->fiq;



    case 0x9c:	

        return bank->irqs & ~bank->mask & bank->fiq;



    

    case 0x100 ... 0x300:	

        bank_no = (offset - 0x100) >> 7;

        if (bank_no > s->nbanks)

            break;

        bank = &s->bank[bank_no];

        line_no = (offset & 0x7f) >> 2;

        return (bank->priority[line_no] << 2) |

                ((bank->fiq >> line_no) & 1);

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static uint64_t FUNC_0(void *opaque, target_phys_addr_t addr,

                                unsigned size)

{

    struct omap_intr_handler_s *VAR_0 = (struct omap_intr_handler_s *) opaque;

    int VAR_1 = addr;

    int VAR_2, VAR_3;

    struct omap_intr_handler_bank_s *VAR_4 = NULL;



    if ((VAR_1 & 0xf80) == 0x80) {

        VAR_2 = (VAR_1 & 0x60) >> 5;

        if (VAR_2 < VAR_0->nbanks) {

            VAR_1 &= ~0x60;

            VAR_4 = &VAR_0->VAR_4[VAR_2];

        }

    }



    switch (VAR_1) {

    case 0x00:	

        return 0x21;



    case 0x10:	

        return (VAR_0->autoidle >> 2) & 1;



    case 0x14:	

        return 1;						



    case 0x40:	

        return VAR_0->sir_intr[0];



    case 0x44:	

        return VAR_0->sir_intr[1];



    case 0x48:	

        return (!VAR_0->mask) << 2;					



    case 0x4c:	

        return 0;



    case 0x50:	

        return VAR_0->autoidle & 3;



    

    case 0x80:	

        return VAR_4->inputs;



    case 0x84:	

        return VAR_4->mask;



    case 0x88:	

    case 0x8c:	

        return 0;



    case 0x90:	

        return VAR_4->swi;



    case 0x94:	

        return 0;



    case 0x98:	

        return VAR_4->irqs & ~VAR_4->mask & ~VAR_4->fiq;



    case 0x9c:	

        return VAR_4->irqs & ~VAR_4->mask & VAR_4->fiq;



    

    case 0x100 ... 0x300:	

        VAR_2 = (VAR_1 - 0x100) >> 7;

        if (VAR_2 > VAR_0->nbanks)

            break;

        VAR_4 = &VAR_0->VAR_4[VAR_2];

        VAR_3 = (VAR_1 & 0x7f) >> 2;

        return (VAR_4->priority[VAR_3] << 2) |

                ((VAR_4->fiq >> VAR_3) & 1);

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static uint64_t FUNC_0(void *opaque, target_phys_addr_t addr,
unsigned size)
{ struct omap_intr_handler_s *VAR_0 = (struct omap_intr_handler_s *) opaque; int VAR_1 = addr; int VAR_2, VAR_3; struct omap_intr_handler_bank_s *VAR_4 = NULL; if ((VAR_1 & 0xf80) == 0x80) { VAR_2 = (VAR_1 & 0x60) >> 5; if (VAR_2 < VAR_0->nbanks) { VAR_1 &= ~0x60; VAR_4 = &VAR_0->VAR_4[VAR_2]; } } switch (VAR_1) { case 0x00:
return 0x21; case 0x10:
return (VAR_0->autoidle >> 2) & 1; case 0x14:
return 1; case 0x40:
return VAR_0->sir_intr[0]; case 0x44:
return VAR_0->sir_intr[1]; case 0x48:
return (!VAR_0->mask) << 2; case 0x4c:
return 0; case 0x50:
return VAR_0->autoidle & 3; case 0x80:
return VAR_4->inputs; case 0x84:
return VAR_4->mask; case 0x88:
case 0x8c:
return 0; case 0x90:
return VAR_4->swi; case 0x94:
return 0; case 0x98:
return VAR_4->irqs & ~VAR_4->mask & ~VAR_4->fiq; case 0x9c:
return VAR_4->irqs & ~VAR_4->mask & VAR_4->fiq; case 0x100 ... 0x300:
VAR_2 = (VAR_1 - 0x100) >> 7; if (VAR_2 > VAR_0->nbanks)
break; VAR_4 = &VAR_0->VAR_4[VAR_2]; VAR_3 = (VAR_1 & 0x7f) >> 2; return (VAR_4->priority[VAR_3] << 2) |
((VAR_4->fiq >> VAR_3) & 1); } OMAP_BAD_REG(addr); return 0; }