static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,

                             uint64_t value, unsigned size)

{

    mpcore_priv_state *s = (mpcore_priv_state *)opaque;

    /* SCU */

    switch (offset) {

    case 0: /* Control register.  */

        s->scu_control = value & 1;

        break;

    case 0x0c: /* Invalidate all.  */

        /* This is a no-op as cache is not emulated.  */

        break;

    default:

        hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);

    }

}

static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,

                             uint64_t value, unsigned size)

{

    mpcore_priv_state *s = (mpcore_priv_state *)opaque;

    

    switch (offset) {

    case 0: 

        s->scu_control = value & 1;

        break;

    case 0x0c: 

        

        break;

    default:

        hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                             uint64_t VAR_2, unsigned VAR_3)

{

    mpcore_priv_state *s = (mpcore_priv_state *)VAR_0;

    

    switch (VAR_1) {

    case 0: 

        s->scu_control = VAR_2 & 1;

        break;

    case 0x0c: 

        

        break;

    default:

        hw_error("mpcore_priv_read: Bad VAR_1 %x\n", (int)VAR_1);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ mpcore_priv_state *s = (mpcore_priv_state *)VAR_0; switch (VAR_1) { case 0:
s->scu_control = VAR_2 & 1; break; case 0x0c:
break; default:
hw_error("mpcore_priv_read: Bad VAR_1 %x\n", (int)VAR_1); } }