static void gen_check_sr(DisasContext *dc, uint32_t sr)

{

    if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {

        if (sregnames[sr].name) {

            qemu_log("SR %s is not configured\n", sregnames[sr].name);

        } else {

            qemu_log("SR %d is not implemented\n", sr);

        }

        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);

    }

}

static void gen_check_sr(DisasContext *dc, uint32_t sr)

{

    if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {

        if (sregnames[sr].name) {

            qemu_log("SR %s is not configured\n", sregnames[sr].name);

        } else {

            qemu_log("SR %d is not implemented\n", sr);

        }

        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);

    }

}

static void gen_check_sr(DisasContext *dc, uint32_t sr)
static void FUNC_0(DisasContext *VAR_0, uint32_t VAR_1)

{

    if (!xtensa_option_bits_enabled(VAR_0->config, sregnames[VAR_1].opt_bits)) {

        if (sregnames[VAR_1].name) {

            qemu_log("SR %s is not configured\n", sregnames[VAR_1].name);

        } else {

            qemu_log("SR %d is not implemented\n", VAR_1);

        }

        gen_exception_cause(VAR_0, ILLEGAL_INSTRUCTION_CAUSE);

    }

}

static void FUNC_0(DisasContext *VAR_0, uint32_t VAR_1)
{ if (!xtensa_option_bits_enabled(VAR_0->config, sregnames[VAR_1].opt_bits)) { if (sregnames[VAR_1].name) { qemu_log("SR %s is not configured\n", sregnames[VAR_1].name); } else { qemu_log("SR %d is not implemented\n", VAR_1); } gen_exception_cause(VAR_0, ILLEGAL_INSTRUCTION_CAUSE); } }