static void gen_ldx(DisasContext *dc, uint32_t code, uint32_t flags)

{

    I_TYPE(instr, code);



    TCGv addr = tcg_temp_new();

    TCGv data;



    /*

     * WARNING: Loads into R_ZERO are ignored, but we must generate the

     *          memory access itself to emulate the CPU precisely. Load

     *          from a protected page to R_ZERO will cause SIGSEGV on

     *          the Nios2 CPU.

     */

    if (likely(instr.b != R_ZERO)) {

        data = dc->cpu_R[instr.b];

    } else {

        data = tcg_temp_new();

    }



    tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16s);

    tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags);



    if (unlikely(instr.b == R_ZERO)) {

        tcg_temp_free(data);

    }



    tcg_temp_free(addr);

}

static void gen_ldx(DisasContext *dc, uint32_t code, uint32_t flags)

{

    I_TYPE(instr, code);



    TCGv addr = tcg_temp_new();

    TCGv data;



    











    if (likely(instr.b != R_ZERO)) {

        data = dc->cpu_R[instr.b];

    } else {

        data = tcg_temp_new();

    }



    tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16s);

    tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags);



    if (unlikely(instr.b == R_ZERO)) {

        tcg_temp_free(data);

    }



    tcg_temp_free(addr);

}

    tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16s);     tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16s);
static void FUNC_0(DisasContext *VAR_0, uint32_t VAR_1, uint32_t VAR_2)

{

    I_TYPE(instr, VAR_1);



    TCGv addr = tcg_temp_new();

    TCGv data;



    











    if (likely(instr.b != R_ZERO)) {

        data = VAR_0->cpu_R[instr.b];

    } else {

        data = tcg_temp_new();

    }



    tcg_gen_addi_tl(addr, load_gpr(VAR_0, instr.a), instr.imm16s);

    tcg_gen_qemu_ld_tl(data, addr, VAR_0->mem_idx, VAR_2);



    if (unlikely(instr.b == R_ZERO)) {

        tcg_temp_free(data);

    }



    tcg_temp_free(addr);

}

static void FUNC_0(DisasContext *VAR_0, uint32_t VAR_1, uint32_t VAR_2)
{ I_TYPE(instr, VAR_1); TCGv addr = tcg_temp_new(); TCGv data; if (likely(instr.b != R_ZERO)) { data = VAR_0->cpu_R[instr.b]; } else { data = tcg_temp_new(); } tcg_gen_addi_tl(addr, load_gpr(VAR_0, instr.a), instr.imm16s); tcg_gen_qemu_ld_tl(data, addr, VAR_0->mem_idx, VAR_2); if (unlikely(instr.b == R_ZERO)) { tcg_temp_free(data); } tcg_temp_free(addr); }