static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,

    unsigned size)

{

    switch (offset) {

    case 0xc:

        n->bar.intms |= data & 0xffffffff;

        n->bar.intmc = n->bar.intms;

        break;

    case 0x10:

        n->bar.intms &= ~(data & 0xffffffff);

        n->bar.intmc = n->bar.intms;

        break;

    case 0x14:

        /* Windows first sends data, then sends enable bit */

        if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) &&

            !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc))

        {

            n->bar.cc = data;

        }



        if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) {

            n->bar.cc = data;

            if (nvme_start_ctrl(n)) {

                n->bar.csts = NVME_CSTS_FAILED;

            } else {

                n->bar.csts = NVME_CSTS_READY;

            }

        } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) {

            nvme_clear_ctrl(n);

            n->bar.csts &= ~NVME_CSTS_READY;

        }

        if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) {

                nvme_clear_ctrl(n);

                n->bar.cc = data;

                n->bar.csts |= NVME_CSTS_SHST_COMPLETE;

        } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) {

                n->bar.csts &= ~NVME_CSTS_SHST_COMPLETE;

                n->bar.cc = data;

        }

        break;

    case 0x24:

        n->bar.aqa = data & 0xffffffff;

        break;

    case 0x28:

        n->bar.asq = data;

        break;

    case 0x2c:

        n->bar.asq |= data << 32;

        break;

    case 0x30:

        n->bar.acq = data;

        break;

    case 0x34:

        n->bar.acq |= data << 32;

        break;

    default:

        break;

    }

}

static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,

    unsigned size)

{

    switch (offset) {

    case 0xc:

        n->bar.intms |= data & 0xffffffff;

        n->bar.intmc = n->bar.intms;

        break;

    case 0x10:

        n->bar.intms &= ~(data & 0xffffffff);

        n->bar.intmc = n->bar.intms;

        break;

    case 0x14:

        

        if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) &&

            !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc))

        {

            n->bar.cc = data;

        }



        if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) {

            n->bar.cc = data;

            if (nvme_start_ctrl(n)) {

                n->bar.csts = NVME_CSTS_FAILED;

            } else {

                n->bar.csts = NVME_CSTS_READY;

            }

        } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) {

            nvme_clear_ctrl(n);

            n->bar.csts &= ~NVME_CSTS_READY;

        }

        if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) {

                nvme_clear_ctrl(n);

                n->bar.cc = data;

                n->bar.csts |= NVME_CSTS_SHST_COMPLETE;

        } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) {

                n->bar.csts &= ~NVME_CSTS_SHST_COMPLETE;

                n->bar.cc = data;

        }

        break;

    case 0x24:

        n->bar.aqa = data & 0xffffffff;

        break;

    case 0x28:

        n->bar.asq = data;

        break;

    case 0x2c:

        n->bar.asq |= data << 32;

        break;

    case 0x30:

        n->bar.acq = data;

        break;

    case 0x34:

        n->bar.acq |= data << 32;

        break;

    default:

        break;

    }

}

    case 0xc:     case 0x10:     case 0x14:             if (nvme_start_ctrl(n)) {                 nvme_clear_ctrl(n);                 n->bar.cc = data;                 n->bar.csts |= NVME_CSTS_SHST_COMPLETE;                 n->bar.csts &= ~NVME_CSTS_SHST_COMPLETE;                 n->bar.cc = data;     case 0x24:     case 0x28:     case 0x2c:     case 0x30:     case 0x34:
static void FUNC_0(NvmeCtrl *VAR_0, hwaddr VAR_1, uint64_t VAR_2,

    unsigned VAR_3)

{

    switch (VAR_1) {

    case 0xc:

        VAR_0->bar.intms |= VAR_2 & 0xffffffff;

        VAR_0->bar.intmc = VAR_0->bar.intms;

        break;

    case 0x10:

        VAR_0->bar.intms &= ~(VAR_2 & 0xffffffff);

        VAR_0->bar.intmc = VAR_0->bar.intms;

        break;

    case 0x14:

        

        if (!NVME_CC_EN(VAR_2) && !NVME_CC_EN(VAR_0->bar.cc) &&

            !NVME_CC_SHN(VAR_2) && !NVME_CC_SHN(VAR_0->bar.cc))

        {

            VAR_0->bar.cc = VAR_2;

        }



        if (NVME_CC_EN(VAR_2) && !NVME_CC_EN(VAR_0->bar.cc)) {

            VAR_0->bar.cc = VAR_2;

            if (nvme_start_ctrl(VAR_0)) {

                VAR_0->bar.csts = NVME_CSTS_FAILED;

            } else {

                VAR_0->bar.csts = NVME_CSTS_READY;

            }

        } else if (!NVME_CC_EN(VAR_2) && NVME_CC_EN(VAR_0->bar.cc)) {

            nvme_clear_ctrl(VAR_0);

            VAR_0->bar.csts &= ~NVME_CSTS_READY;

        }

        if (NVME_CC_SHN(VAR_2) && !(NVME_CC_SHN(VAR_0->bar.cc))) {

                nvme_clear_ctrl(VAR_0);

                VAR_0->bar.cc = VAR_2;

                VAR_0->bar.csts |= NVME_CSTS_SHST_COMPLETE;

        } else if (!NVME_CC_SHN(VAR_2) && NVME_CC_SHN(VAR_0->bar.cc)) {

                VAR_0->bar.csts &= ~NVME_CSTS_SHST_COMPLETE;

                VAR_0->bar.cc = VAR_2;

        }

        break;

    case 0x24:

        VAR_0->bar.aqa = VAR_2 & 0xffffffff;

        break;

    case 0x28:

        VAR_0->bar.asq = VAR_2;

        break;

    case 0x2c:

        VAR_0->bar.asq |= VAR_2 << 32;

        break;

    case 0x30:

        VAR_0->bar.acq = VAR_2;

        break;

    case 0x34:

        VAR_0->bar.acq |= VAR_2 << 32;

        break;

    default:

        break;

    }

}

static void FUNC_0(NvmeCtrl *VAR_0, hwaddr VAR_1, uint64_t VAR_2,
unsigned VAR_3)
{ switch (VAR_1) { case 0xc:
VAR_0->bar.intms |= VAR_2 & 0xffffffff; VAR_0->bar.intmc = VAR_0->bar.intms; break; case 0x10:
VAR_0->bar.intms &= ~(VAR_2 & 0xffffffff); VAR_0->bar.intmc = VAR_0->bar.intms; break; case 0x14:
if (!NVME_CC_EN(VAR_2) && !NVME_CC_EN(VAR_0->bar.cc) &&
!NVME_CC_SHN(VAR_2) && !NVME_CC_SHN(VAR_0->bar.cc))
{ VAR_0->bar.cc = VAR_2; } if (NVME_CC_EN(VAR_2) && !NVME_CC_EN(VAR_0->bar.cc)) { VAR_0->bar.cc = VAR_2; if (nvme_start_ctrl(VAR_0)) { VAR_0->bar.csts = NVME_CSTS_FAILED; } else { VAR_0->bar.csts = NVME_CSTS_READY; } } else if (!NVME_CC_EN(VAR_2) && NVME_CC_EN(VAR_0->bar.cc)) { nvme_clear_ctrl(VAR_0); VAR_0->bar.csts &= ~NVME_CSTS_READY; } if (NVME_CC_SHN(VAR_2) && !(NVME_CC_SHN(VAR_0->bar.cc))) { nvme_clear_ctrl(VAR_0); VAR_0->bar.cc = VAR_2; VAR_0->bar.csts |= NVME_CSTS_SHST_COMPLETE; } else if (!NVME_CC_SHN(VAR_2) && NVME_CC_SHN(VAR_0->bar.cc)) { VAR_0->bar.csts &= ~NVME_CSTS_SHST_COMPLETE; VAR_0->bar.cc = VAR_2; } break; case 0x24:
VAR_0->bar.aqa = VAR_2 & 0xffffffff; break; case 0x28:
VAR_0->bar.asq = VAR_2; break; case 0x2c:
VAR_0->bar.asq |= VAR_2 << 32; break; case 0x30:
VAR_0->bar.acq = VAR_2; break; case 0x34:
VAR_0->bar.acq |= VAR_2 << 32; break; default:
break; } }