static int kvm_get_msrs(CPUState *env)

{

    struct {

        struct kvm_msrs info;

        struct kvm_msr_entry entries[100];

    } msr_data;

    struct kvm_msr_entry *msrs = msr_data.entries;

    int ret, i, n;



    n = 0;

    msrs[n++].index = MSR_IA32_SYSENTER_CS;

    msrs[n++].index = MSR_IA32_SYSENTER_ESP;

    msrs[n++].index = MSR_IA32_SYSENTER_EIP;

    if (kvm_has_msr_star(env)) {

        msrs[n++].index = MSR_STAR;

    }

    if (kvm_has_msr_hsave_pa(env)) {

        msrs[n++].index = MSR_VM_HSAVE_PA;

    }

    msrs[n++].index = MSR_IA32_TSC;

#ifdef TARGET_X86_64

    if (lm_capable_kernel) {

        msrs[n++].index = MSR_CSTAR;

        msrs[n++].index = MSR_KERNELGSBASE;

        msrs[n++].index = MSR_FMASK;

        msrs[n++].index = MSR_LSTAR;

    }

#endif

    msrs[n++].index = MSR_KVM_SYSTEM_TIME;

    msrs[n++].index = MSR_KVM_WALL_CLOCK;

#ifdef KVM_CAP_ASYNC_PF

    msrs[n++].index = MSR_KVM_ASYNC_PF_EN;

#endif



#ifdef KVM_CAP_MCE

    if (env->mcg_cap) {

        msrs[n++].index = MSR_MCG_STATUS;

        msrs[n++].index = MSR_MCG_CTL;

        for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {

            msrs[n++].index = MSR_MC0_CTL + i;

        }

    }

#endif



    msr_data.info.nmsrs = n;

    ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);

    if (ret < 0) {

        return ret;

    }



    for (i = 0; i < ret; i++) {

        switch (msrs[i].index) {

        case MSR_IA32_SYSENTER_CS:

            env->sysenter_cs = msrs[i].data;

            break;

        case MSR_IA32_SYSENTER_ESP:

            env->sysenter_esp = msrs[i].data;

            break;

        case MSR_IA32_SYSENTER_EIP:

            env->sysenter_eip = msrs[i].data;

            break;

        case MSR_STAR:

            env->star = msrs[i].data;

            break;

#ifdef TARGET_X86_64

        case MSR_CSTAR:

            env->cstar = msrs[i].data;

            break;

        case MSR_KERNELGSBASE:

            env->kernelgsbase = msrs[i].data;

            break;

        case MSR_FMASK:

            env->fmask = msrs[i].data;

            break;

        case MSR_LSTAR:

            env->lstar = msrs[i].data;

            break;

#endif

        case MSR_IA32_TSC:

            env->tsc = msrs[i].data;

            break;

        case MSR_VM_HSAVE_PA:

            env->vm_hsave = msrs[i].data;

            break;

        case MSR_KVM_SYSTEM_TIME:

            env->system_time_msr = msrs[i].data;

            break;

        case MSR_KVM_WALL_CLOCK:

            env->wall_clock_msr = msrs[i].data;

            break;

#ifdef KVM_CAP_MCE

        case MSR_MCG_STATUS:

            env->mcg_status = msrs[i].data;

            break;

        case MSR_MCG_CTL:

            env->mcg_ctl = msrs[i].data;

            break;

#endif

        default:

#ifdef KVM_CAP_MCE

            if (msrs[i].index >= MSR_MC0_CTL &&

                msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {

                env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;

            }

#endif

            break;

#ifdef KVM_CAP_ASYNC_PF

        case MSR_KVM_ASYNC_PF_EN:

            env->async_pf_en_msr = msrs[i].data;

            break;

#endif

        }

    }



    return 0;

}

static int kvm_get_msrs(CPUState *env)

{

    struct {

        struct kvm_msrs info;

        struct kvm_msr_entry entries[100];

    } msr_data;

    struct kvm_msr_entry *msrs = msr_data.entries;

    int ret, i, n;



    n = 0;

    msrs[n++].index = MSR_IA32_SYSENTER_CS;

    msrs[n++].index = MSR_IA32_SYSENTER_ESP;

    msrs[n++].index = MSR_IA32_SYSENTER_EIP;

    if (kvm_has_msr_star(env)) {

        msrs[n++].index = MSR_STAR;

    }

    if (kvm_has_msr_hsave_pa(env)) {

        msrs[n++].index = MSR_VM_HSAVE_PA;

    }

    msrs[n++].index = MSR_IA32_TSC;

#ifdef TARGET_X86_64

    if (lm_capable_kernel) {

        msrs[n++].index = MSR_CSTAR;

        msrs[n++].index = MSR_KERNELGSBASE;

        msrs[n++].index = MSR_FMASK;

        msrs[n++].index = MSR_LSTAR;

    }

#endif

    msrs[n++].index = MSR_KVM_SYSTEM_TIME;

    msrs[n++].index = MSR_KVM_WALL_CLOCK;

#ifdef KVM_CAP_ASYNC_PF

    msrs[n++].index = MSR_KVM_ASYNC_PF_EN;

#endif



#ifdef KVM_CAP_MCE

    if (env->mcg_cap) {

        msrs[n++].index = MSR_MCG_STATUS;

        msrs[n++].index = MSR_MCG_CTL;

        for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {

            msrs[n++].index = MSR_MC0_CTL + i;

        }

    }

#endif



    msr_data.info.nmsrs = n;

    ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);

    if (ret < 0) {

        return ret;

    }



    for (i = 0; i < ret; i++) {

        switch (msrs[i].index) {

        case MSR_IA32_SYSENTER_CS:

            env->sysenter_cs = msrs[i].data;

            break;

        case MSR_IA32_SYSENTER_ESP:

            env->sysenter_esp = msrs[i].data;

            break;

        case MSR_IA32_SYSENTER_EIP:

            env->sysenter_eip = msrs[i].data;

            break;

        case MSR_STAR:

            env->star = msrs[i].data;

            break;

#ifdef TARGET_X86_64

        case MSR_CSTAR:

            env->cstar = msrs[i].data;

            break;

        case MSR_KERNELGSBASE:

            env->kernelgsbase = msrs[i].data;

            break;

        case MSR_FMASK:

            env->fmask = msrs[i].data;

            break;

        case MSR_LSTAR:

            env->lstar = msrs[i].data;

            break;

#endif

        case MSR_IA32_TSC:

            env->tsc = msrs[i].data;

            break;

        case MSR_VM_HSAVE_PA:

            env->vm_hsave = msrs[i].data;

            break;

        case MSR_KVM_SYSTEM_TIME:

            env->system_time_msr = msrs[i].data;

            break;

        case MSR_KVM_WALL_CLOCK:

            env->wall_clock_msr = msrs[i].data;

            break;

#ifdef KVM_CAP_MCE

        case MSR_MCG_STATUS:

            env->mcg_status = msrs[i].data;

            break;

        case MSR_MCG_CTL:

            env->mcg_ctl = msrs[i].data;

            break;

#endif

        default:

#ifdef KVM_CAP_MCE

            if (msrs[i].index >= MSR_MC0_CTL &&

                msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {

                env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;

            }

#endif

            break;

#ifdef KVM_CAP_ASYNC_PF

        case MSR_KVM_ASYNC_PF_EN:

            env->async_pf_en_msr = msrs[i].data;

            break;

#endif

        }

    }



    return 0;

}

static int FUNC_0(CPUState *VAR_0)

{

    struct {

        struct kvm_msrs info;

        struct kvm_msr_entry entries[100];

    } VAR_1;

    struct kvm_msr_entry *VAR_2 = VAR_1.entries;

    int VAR_3, VAR_4, VAR_5;



    VAR_5 = 0;

    VAR_2[VAR_5++].index = MSR_IA32_SYSENTER_CS;

    VAR_2[VAR_5++].index = MSR_IA32_SYSENTER_ESP;

    VAR_2[VAR_5++].index = MSR_IA32_SYSENTER_EIP;

    if (kvm_has_msr_star(VAR_0)) {

        VAR_2[VAR_5++].index = MSR_STAR;

    }

    if (kvm_has_msr_hsave_pa(VAR_0)) {

        VAR_2[VAR_5++].index = MSR_VM_HSAVE_PA;

    }

    VAR_2[VAR_5++].index = MSR_IA32_TSC;

#ifdef TARGET_X86_64

    if (lm_capable_kernel) {

        VAR_2[VAR_5++].index = MSR_CSTAR;

        VAR_2[VAR_5++].index = MSR_KERNELGSBASE;

        VAR_2[VAR_5++].index = MSR_FMASK;

        VAR_2[VAR_5++].index = MSR_LSTAR;

    }

#endif

    VAR_2[VAR_5++].index = MSR_KVM_SYSTEM_TIME;

    VAR_2[VAR_5++].index = MSR_KVM_WALL_CLOCK;

#ifdef KVM_CAP_ASYNC_PF

    VAR_2[VAR_5++].index = MSR_KVM_ASYNC_PF_EN;

#endif



#ifdef KVM_CAP_MCE

    if (VAR_0->mcg_cap) {

        VAR_2[VAR_5++].index = MSR_MCG_STATUS;

        VAR_2[VAR_5++].index = MSR_MCG_CTL;

        for (VAR_4 = 0; VAR_4 < (VAR_0->mcg_cap & 0xff) * 4; VAR_4++) {

            VAR_2[VAR_5++].index = MSR_MC0_CTL + VAR_4;

        }

    }

#endif



    VAR_1.info.nmsrs = VAR_5;

    VAR_3 = kvm_vcpu_ioctl(VAR_0, KVM_GET_MSRS, &VAR_1);

    if (VAR_3 < 0) {

        return VAR_3;

    }



    for (VAR_4 = 0; VAR_4 < VAR_3; VAR_4++) {

        switch (VAR_2[VAR_4].index) {

        case MSR_IA32_SYSENTER_CS:

            VAR_0->sysenter_cs = VAR_2[VAR_4].data;

            break;

        case MSR_IA32_SYSENTER_ESP:

            VAR_0->sysenter_esp = VAR_2[VAR_4].data;

            break;

        case MSR_IA32_SYSENTER_EIP:

            VAR_0->sysenter_eip = VAR_2[VAR_4].data;

            break;

        case MSR_STAR:

            VAR_0->star = VAR_2[VAR_4].data;

            break;

#ifdef TARGET_X86_64

        case MSR_CSTAR:

            VAR_0->cstar = VAR_2[VAR_4].data;

            break;

        case MSR_KERNELGSBASE:

            VAR_0->kernelgsbase = VAR_2[VAR_4].data;

            break;

        case MSR_FMASK:

            VAR_0->fmask = VAR_2[VAR_4].data;

            break;

        case MSR_LSTAR:

            VAR_0->lstar = VAR_2[VAR_4].data;

            break;

#endif

        case MSR_IA32_TSC:

            VAR_0->tsc = VAR_2[VAR_4].data;

            break;

        case MSR_VM_HSAVE_PA:

            VAR_0->vm_hsave = VAR_2[VAR_4].data;

            break;

        case MSR_KVM_SYSTEM_TIME:

            VAR_0->system_time_msr = VAR_2[VAR_4].data;

            break;

        case MSR_KVM_WALL_CLOCK:

            VAR_0->wall_clock_msr = VAR_2[VAR_4].data;

            break;

#ifdef KVM_CAP_MCE

        case MSR_MCG_STATUS:

            VAR_0->mcg_status = VAR_2[VAR_4].data;

            break;

        case MSR_MCG_CTL:

            VAR_0->mcg_ctl = VAR_2[VAR_4].data;

            break;

#endif

        default:

#ifdef KVM_CAP_MCE

            if (VAR_2[VAR_4].index >= MSR_MC0_CTL &&

                VAR_2[VAR_4].index < MSR_MC0_CTL + (VAR_0->mcg_cap & 0xff) * 4) {

                VAR_0->mce_banks[VAR_2[VAR_4].index - MSR_MC0_CTL] = VAR_2[VAR_4].data;

            }

#endif

            break;

#ifdef KVM_CAP_ASYNC_PF

        case MSR_KVM_ASYNC_PF_EN:

            VAR_0->async_pf_en_msr = VAR_2[VAR_4].data;

            break;

#endif

        }

    }



    return 0;

}

static int FUNC_0(CPUState *VAR_0)
{ struct { struct kvm_msrs info; struct kvm_msr_entry entries[100]; } VAR_1; struct kvm_msr_entry *VAR_2 = VAR_1.entries; int VAR_3, VAR_4, VAR_5; VAR_5 = 0; VAR_2[VAR_5++].index = MSR_IA32_SYSENTER_CS; VAR_2[VAR_5++].index = MSR_IA32_SYSENTER_ESP; VAR_2[VAR_5++].index = MSR_IA32_SYSENTER_EIP; if (kvm_has_msr_star(VAR_0)) { VAR_2[VAR_5++].index = MSR_STAR; } if (kvm_has_msr_hsave_pa(VAR_0)) { VAR_2[VAR_5++].index = MSR_VM_HSAVE_PA; } VAR_2[VAR_5++].index = MSR_IA32_TSC; #ifdef TARGET_X86_64
if (lm_capable_kernel) { VAR_2[VAR_5++].index = MSR_CSTAR; VAR_2[VAR_5++].index = MSR_KERNELGSBASE; VAR_2[VAR_5++].index = MSR_FMASK; VAR_2[VAR_5++].index = MSR_LSTAR; } #endif
VAR_2[VAR_5++].index = MSR_KVM_SYSTEM_TIME; VAR_2[VAR_5++].index = MSR_KVM_WALL_CLOCK; #ifdef KVM_CAP_ASYNC_PF
VAR_2[VAR_5++].index = MSR_KVM_ASYNC_PF_EN; #endif
#ifdef KVM_CAP_MCE
if (VAR_0->mcg_cap) { VAR_2[VAR_5++].index = MSR_MCG_STATUS; VAR_2[VAR_5++].index = MSR_MCG_CTL; for (VAR_4 = 0; VAR_4 < (VAR_0->mcg_cap & 0xff) * 4; VAR_4++) { VAR_2[VAR_5++].index = MSR_MC0_CTL + VAR_4; } } #endif
VAR_1.info.nmsrs = VAR_5; VAR_3 = kvm_vcpu_ioctl(VAR_0, KVM_GET_MSRS, &VAR_1); if (VAR_3 < 0) { return VAR_3; } for (VAR_4 = 0; VAR_4 < VAR_3; VAR_4++) { switch (VAR_2[VAR_4].index) { case MSR_IA32_SYSENTER_CS:
VAR_0->sysenter_cs = VAR_2[VAR_4].data; break; case MSR_IA32_SYSENTER_ESP:
VAR_0->sysenter_esp = VAR_2[VAR_4].data; break; case MSR_IA32_SYSENTER_EIP:
VAR_0->sysenter_eip = VAR_2[VAR_4].data; break; case MSR_STAR:
VAR_0->star = VAR_2[VAR_4].data; break; #ifdef TARGET_X86_64
case MSR_CSTAR:
VAR_0->cstar = VAR_2[VAR_4].data; break; case MSR_KERNELGSBASE:
VAR_0->kernelgsbase = VAR_2[VAR_4].data; break; case MSR_FMASK:
VAR_0->fmask = VAR_2[VAR_4].data; break; case MSR_LSTAR:
VAR_0->lstar = VAR_2[VAR_4].data; break; #endif
case MSR_IA32_TSC:
VAR_0->tsc = VAR_2[VAR_4].data; break; case MSR_VM_HSAVE_PA:
VAR_0->vm_hsave = VAR_2[VAR_4].data; break; case MSR_KVM_SYSTEM_TIME:
VAR_0->system_time_msr = VAR_2[VAR_4].data; break; case MSR_KVM_WALL_CLOCK:
VAR_0->wall_clock_msr = VAR_2[VAR_4].data; break; #ifdef KVM_CAP_MCE
case MSR_MCG_STATUS:
VAR_0->mcg_status = VAR_2[VAR_4].data; break; case MSR_MCG_CTL:
VAR_0->mcg_ctl = VAR_2[VAR_4].data; break; #endif
default:
#ifdef KVM_CAP_MCE
if (VAR_2[VAR_4].index >= MSR_MC0_CTL &&
VAR_2[VAR_4].index < MSR_MC0_CTL + (VAR_0->mcg_cap & 0xff) * 4) { VAR_0->mce_banks[VAR_2[VAR_4].index - MSR_MC0_CTL] = VAR_2[VAR_4].data; } #endif
break; #ifdef KVM_CAP_ASYNC_PF
case MSR_KVM_ASYNC_PF_EN:
VAR_0->async_pf_en_msr = VAR_2[VAR_4].data; break; #endif
} } return 0; }