static void apic_reset(void *opaque)

{

    APICState *s = opaque;

    int bsp = cpu_is_bsp(s->cpu_env);



    s->apicbase = 0xfee00000 |

        (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;



    apic_init_ipi(s);



    if (bsp) {

        /*

         * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization

         * time typically by BIOS, so PIC interrupt can be delivered to the

         * processor when local APIC is enabled.

         */

        s->lvt[APIC_LVT_LINT0] = 0x700;

    }

}

static void apic_reset(void *opaque)

{

    APICState *s = opaque;

    int bsp = cpu_is_bsp(s->cpu_env);



    s->apicbase = 0xfee00000 |

        (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;



    apic_init_ipi(s);



    if (bsp) {

        









        s->lvt[APIC_LVT_LINT0] = 0x700;

    }

}

static void FUNC_0(void *VAR_0)

{

    APICState *s = VAR_0;

    int VAR_1 = cpu_is_bsp(s->cpu_env);



    s->apicbase = 0xfee00000 |

        (VAR_1 ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;



    apic_init_ipi(s);



    if (VAR_1) {

        









        s->lvt[APIC_LVT_LINT0] = 0x700;

    }

}

static void FUNC_0(void *VAR_0)
{ APICState *s = VAR_0; int VAR_1 = cpu_is_bsp(s->cpu_env); s->apicbase = 0xfee00000 |
(VAR_1 ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; apic_init_ipi(s); if (VAR_1) { s->lvt[APIC_LVT_LINT0] = 0x700; } }