static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,

                                 uint64_t value, unsigned size)

{

    struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;



    if (size != 4) {

        return omap_badwidth_write32(opaque, addr, value);

    }



    switch (addr) {

    case 0x00:	/* CNTL_TIMER */

        omap_timer_sync(s);

        s->enable = (value >> 5) & 1;

        s->ptv = (value >> 2) & 7;

        s->ar = (value >> 1) & 1;

        s->st = value & 1;

        omap_timer_update(s);

        return;



    case 0x04:	/* LOAD_TIM */

        s->reset_val = value;

        return;



    case 0x08:	/* READ_TIM */

        OMAP_RO_REG(addr);

        break;



    default:

        OMAP_BAD_REG(addr);

    }

}

static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,

                                 uint64_t value, unsigned size)

{

    struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;



    if (size != 4) {

        return omap_badwidth_write32(opaque, addr, value);

    }



    switch (addr) {

    case 0x00:	

        omap_timer_sync(s);

        s->enable = (value >> 5) & 1;

        s->ptv = (value >> 2) & 7;

        s->ar = (value >> 1) & 1;

        s->st = value & 1;

        omap_timer_update(s);

        return;



    case 0x04:	

        s->reset_val = value;

        return;



    case 0x08:	

        OMAP_RO_REG(addr);

        break;



    default:

        OMAP_BAD_REG(addr);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                                 uint64_t VAR_2, unsigned VAR_3)

{

    struct omap_mpu_timer_s *VAR_4 = (struct omap_mpu_timer_s *) VAR_0;



    if (VAR_3 != 4) {

        return omap_badwidth_write32(VAR_0, VAR_1, VAR_2);

    }



    switch (VAR_1) {

    case 0x00:	

        omap_timer_sync(VAR_4);

        VAR_4->enable = (VAR_2 >> 5) & 1;

        VAR_4->ptv = (VAR_2 >> 2) & 7;

        VAR_4->ar = (VAR_2 >> 1) & 1;

        VAR_4->st = VAR_2 & 1;

        omap_timer_update(VAR_4);

        return;



    case 0x04:	

        VAR_4->reset_val = VAR_2;

        return;



    case 0x08:	

        OMAP_RO_REG(VAR_1);

        break;



    default:

        OMAP_BAD_REG(VAR_1);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ struct omap_mpu_timer_s *VAR_4 = (struct omap_mpu_timer_s *) VAR_0; if (VAR_3 != 4) { return omap_badwidth_write32(VAR_0, VAR_1, VAR_2); } switch (VAR_1) { case 0x00:
omap_timer_sync(VAR_4); VAR_4->enable = (VAR_2 >> 5) & 1; VAR_4->ptv = (VAR_2 >> 2) & 7; VAR_4->ar = (VAR_2 >> 1) & 1; VAR_4->st = VAR_2 & 1; omap_timer_update(VAR_4); return; case 0x04:
VAR_4->reset_val = VAR_2; return; case 0x08:
OMAP_RO_REG(VAR_1); break; default:
OMAP_BAD_REG(VAR_1); } }