Question: Analog transistor representations for simulating bacterial genetic circuit behavior.

In recent years, the field of systems biology has gained significant traction, attracting the interest of physicists and quantitative scientists who seek to apply their analytical skills to the complexity of biological systems. Two seminal texts, "An Introduction to Systems Biology: Design Principles of Biological Circuits" by Uri Alon and "Systems Biology: Properties of Reconstructed Networks" by Bernhard Ø. Palsson, have emerged as key resources for those looking to delve into this interdisciplinary area. These books offer a refreshing departure from traditional biology textbooks by emphasizing quantitative modeling over nomenclature and focusing on essential modeling concepts rather than exhaustive lists of components. They also make nontrivial quantitative predictions that have been verified through experimentation, providing a solid foundation for understanding biological circuits.

Alon's book is particularly accessible to physicists and scientists with a quantitative background, as it assumes no prior knowledge of biology and begins by explaining the fundamental functions of the cell and the degrees of freedom that enable its operation. The text then delves into detailed discussions of network motifs, which are circuit elements believed to be repeatedly utilized in biological systems. These motifs include autoregulation, feed-forward loops, positive-feedback loops, and kinetic proofreading. Alon also explores the concept of robustness in biological systems, using examples such as chemotaxis and developmental pattern formation to illustrate the general physical principles at work in biology. The book concludes with an epilogue on simplicity in biology, tying together the intricate biological details into a cohesive and inspiring overview of the field.

Palsson's "Systems Biology," on the other hand, takes a different approach by focusing on the techniques used for reconstructing detailed, predictive models of biological circuits. This text is particularly relevant given the recent advancements in genomics, which have made it possible to map out the metabolic networks of bacteria and simpler eukaryotes. Palsson's book is more technique-driven than principle-driven, providing a comprehensive guide to reconstructing circuit models for entire organisms.

Both texts are highly regarded and can be used in tandem to create an accessible course for beginners, offering a comprehensive introduction to systems biology. The inclusion of exercises ranging from elementary to advanced research topics further enhances their educational value, making them essential resources for anyone interested in the design principles of biological circuits and the emerging field of systems biology.

With current tools and technology, someone who has physical access to a chip can extract the detailed layout of the integrated circuit (IC). By using advanced visual imaging techniques, reverse engineering can reveal details that are meant to be kept secret, such as a secure protocol or novel implementation that offers a competitive advantage. A promising solution to defend against reverse engineering attacks is IC camouflaging. In this work, we propose a new camouflaging technique based on the threshold voltage of the transistors. We refer to these cells as threshold dependent camouflaged cells. Our work differs from current commercial solutions in that the latter use look-alike cells, with the assumption that it is difficult for the reverse engineer to identify the cell's functionality. Yet, if a structural distinction between cells exists, then these are still vulnerable, especially as reverse engineers use more advanced and precise techniques. On the other hand, the proposed threshold dependent standard cells are structurally identical regardless of the cells' functionality. Detailed circuit simulations of our proposed threshold dependent camouflaged cells demonstrate that they can be used to cost-effectively and robustly camouflage large netlists. Corner analysis of process, temperature, and supply voltage (PVT) variations show that our cells operate as expected over all PVT corners simulated.

The paper develops a neuromorphic system on a Spartan 6 field programmable gate array (FPGA) board to generate locomotion patterns (gaits) for three different legged robots (biped, quadruped, and hexapod). The neuromorphic system consists of a reconfigurable FPGA-based architecture for a 3G artificial neural network (spiking neural network), which acts as a Central Pattern Generator (CPG). The locomotion patterns, are then generated by the CPG through a general neural architecture, which parameters are offline estimated by means of grammatical evolution and Victor-Purpura distance-based fitness function. The neuromorphic system is fully validated on real biped, quadruped, and hexapod robots.

(ABSTRACT) Analogcircuit/IC design for high speed optical fiber communication is a fairly new research area in Dr. Ha's group. In the first project sponsored by ETRI (Electronics and Telecommunication Research Institute) we started to design the building blocks of receiver for next generation 400 Gb/s optical fiber communication. In this thesis research a transceiver architecture based on 4x100 Gb/s parallel communication is proposed. As part of the receiver, a transimpedance amplifier for 100 Gb/s optical communication is designed, analyzed and simulated. Simulation results demonstrate the excellent feasibility of proposed architecture. always dominated the high speed optical transceiver design because of their inherent properties of high mobility and low noise. But they are power hungry and bulky in size which made them less attractive for highly integrated circuit design. On the contrary, CMOS technology always drew attraction because of low cost, low power dissipation and high level of integration facility. But their notorious parasitic characteristic and inferior noise performance makes high speed transceiver design very challenging. The emergence of nano-scale CMOS offer highly scaled feature sized transistors with transition frequencies exceeding 200 GHz and can improve optical receiver performance significantly. Increasing bandwidth to meet the target data rate is the most challenging task of TIA design especially in CMOS technology. Several CMOS TIA architectures have been published recently [6]-[11] for 40 Gb/s data rate having bandwidth no more than 40 GHz. In contrast to existing works, the goal of this research is to step further and design a single channel stand-alone iii TIA compatible in serial 100 Gb/s data rate with enhanced bandwidth and optimized transimpedance gain, input referred noise and group delay variation. A 100 Gb/s transimpedance amplifier (TIA) for optical receiver front end is designed in this work. To achieve wide bandwidth and low group delay variation a differential TIA with active feedback network is proposed. Proposed design also combines regulated cascode front end, peaking inductors and capacitive degeneration to have wide band response. Simulation results show 70 GHz bandwidth, 42 dBΩ transimpedance gain and 2.8 ps of group delay variation for proposed architecture. Input referred noise current density is 26 pA/√ while the total power dissipation from 1.2V supply is 24mW. Performance of the proposed TIA is compared with other existing TIAs, and the proposed TIA shows significant improvement in bandwidth and group delay variation compared to other existing TIA architectures. iv To my parents v Acknowledgements First …

Miniaturization of devices has brought a lot of improvements in the healthcare delivery as a result of advancenments in Integrated circuit technologies. As a result, proper and effective way of analyzing various body conditions and diseases can be achieved. When the heart muscles repolarize and depolarize, it generates electrical impulses which could help the doctor or the health professional to diagnose various heart abnormalities. The aim of this project is to design and develop a miniaturized ECG system displayed on both PC and Tablet for preliminary diagnoses of the heart. This system utilizes a programmable single-chip microcontroller for analysing the biosignals to indicate the condition of the heart. The system is incomporated with alarm systems which prompt the doctor if there is any abnormality from a patient's heart. These abnormalities could be bradycardia or tachycardia. This system is built with a provision of enabling wireless transmission of ECG signals to a PC or TABLET through BLUETOOTH and ANDROID PLATFORM. The android application can be installed and tested on any smart phone or tablet and screen resolution can be adjusted later as per requirement. This helps the doctor to have visual description of the patient ECG without the need of mounted monitors. The experimental results show that device is clinically useful, compact, cost effective and user friendly.

The first successful FPGA implementation [1] of artificial neural networks (ANNs) was published a little over a decade ago. It is timely to review the progress that has been made in this research area. This brief survey provides a taxonomy for classifying FPGA implementations of ANNs. Different implementation techniques and design issues are discussed. Future research trends are also presented.

This work is motivated by the experimental design problem of optimizing the power output of nano-enhanced microbial fuel cells. Microbial fuel cells (MFCs) (Bond and Lovley, 2003; Fan et al., 2007; Park and Zeikus, 2003; Reguera, 2005) use micro-organisms to break down organic matter and generate electricity. For a particular MFC design, it is critical to optimize the biological energetics and the microbial/electrode interface of the system, which research has shown to depend strongly on the surface properties of the anodes (Park and Zeikus, 2003; Reguera, 2005). This motivates the design of nano-enhanced anodes, where nano-structures (e.g. carbon nano-wire) are grown on the anode surface to improve the MFC’s power output. Unfortunately, there is little understanding of the interaction between various possible nano-enhancements and MFC capabilities for different micro-organisms. Thus, optimizing anode design for a particular application is largely guess work. Our goal is to develop algorithms to aid this process. Bayesian optimization (Jones, 2001a; Brochu et al., 2009) has been widely used for experimental design problems where the goal is to optimize an unknown function f(·), that is costly to evaluate. In general, we are interested in finding the point x∗ ∈ X d ⊂ Rd such that: x∗ = argmax x∈X d f(x), (1)

MOTIVATION
Molecular biotechnology now makes it possible to build elaborate systems models, but the systems biology community needs information standards if models are to be shared, evaluated and developed cooperatively.

RESULTS
We summarize the Systems Biology Markup Language (SBML) Level 1, a free, open, XML-based format for representing biochemical reaction networks. SBML is a software-independent language for describing models common to research in many areas of computational biology, including cell signaling pathways, metabolic pathways, gene regulation, and others.

AVAILABILITY
The specification of SBML Level 1 is freely available from http://www.sbml.org/

Intrabody nanonetworks for nervous system monitoring are envisioned as a key application of the Internet of Nano-Things (IoNT) paradigm, with the aim of developing radically new medical diagnosis and treatment techniques. Indeed, very recently, bionic devices have been implanted inside a living human brain as innovative treatment for drug-resistant epilepsy. In this context, this paper proposes a systems-theoretic communication model to capture the actual behavior of biological neurons. Specifically, biological neurons exhibit physical extension due to their projections called dendrites, which propagate the electrochemical stimulation received via synapses to the soma. Experimental evidences show that the dendrites exhibit two main features: 1) the compartmentalization at the level of the dendritic branches of the neuronal processes and 2) the location-dependent preference for different frequencies. Stemming from these experimental evidences, we propose to model the dendritic tree as a spatiotemporal filter bank, where each filter models the behavior in both space and time of a dendritic branch. Each filter is fully characterized along with the overall neuronal response. Furthermore, sufficient conditions on the incoming stimulus for inducing a null-neuronal response are derived. The conducted theoretical analysis shows that: 1) the neuronal information is encoded in the stimulus temporal pattern, i.e., it is possible to select the neuron to affect by changing the stimulus frequency content; in this sense, the communication among neurons is frequency-selective and 2) the spatial distribution of the dendrites affects the neuronal response; in this sense, the communication among neurons is spatial-selective. The theoretical analysis is validated through a real neuron morphology.

Systems that extract structured information from natural language passages have been highly successful in specialized domains. The time is opportune for developing analogous applications for molecular biology and genomics. We present a system, GENIES, that extracts and structures information about cellular pathways from the biological literature in accordance with a knowledge model that we developed earlier. We implemented GENIES by modifying an existing medical natural language processing system, MedLEE, and performed a preliminary evaluation study. Our results demonstrate the value of the underlying techniques for the purpose of acquiring valuable knowledge from biological journals.

A 1.8V CMOS chopper four-quadrant analog multiplier, intending to serve as an autonomous IC block for low-frequency signal processing, is presented. Particular emphasis is laid upon achieving low output noise by means of chopper stabilization, while the multiplier's operation is based on the MOS Translinear Principle. The proposed design has been implemented and simulated in TSMC 0.18 µm CMOS process.


Question: Analog transistor representations for simulating bacterial genetic circuit behaviors.

This comprehensive resource delves into the dual realms of ultra low power electronics and bioelectronics, offering a pioneering, in-depth exploration of these interconnected disciplines. It elucidates the core theories and circuit designs essential for ultra low power electronic engineering, along with their practical implications in the biomedical sector. Moreover, it examines the energy-efficient paradigms found in biological systems, specifically cellular and neural mechanisms, and how they can stimulate groundbreaking low power designs in mixed-signal and radio frequency (RF) electronics. The book features a distinctive, holistic perspective on ultra low power analog and digital electronics, highlighting the strategic use of the energy-efficient subthreshold transistor operation in both domains. Sections dedicated to batteries, energy harvesting, and future energy trends equip readers with a comprehensive understanding of the critical interplay between energy consumption and generation across different scales. Enriched with practical insights and case studies from cutting-edge applications such as brain implants, cochlear implants, biomolecular sensing, cardiac devices, and bio-inspired technologies, this book is a valuable and engaging tool for both academic and professional engineers.

Toshiba's 5th generation BiCD/CD-0.13 is a new process platform for analog power applications based on 0.13µm CMOS technology. The process platform has six varieties of rated voltage, 5V, 6V, 18V, 25V, 40V, and 60V. 5 to 18V CD-0.13 process use P-type silicon substrate. 25 to 60V BiCD-0.13 process use N-Epi wafer with N+/P+ buried layer on P type silicon substrate. Each LDMOS recode ultra-low on-resistance compared with that of previous papers, and we will realize the highest performance analog power IC's using this technology.

Many modern neural simulators focus on the simulation of networks of spiking neurons on parallel hardware. Another important framework in computational neuroscience, rate-coded neural networks, is mostly difficult or impossible to implement using these simulators. We present here the ANNarchy (Artificial Neural Networks architect) neural simulator, which allows to easily define and simulate rate-coded and spiking networks, as well as combinations of both. The interface in Python has been designed to be close to the PyNN interface, while the definition of neuron and synapse models can be specified using an equation-oriented mathematical description similar to the Brian neural simulator. This information is used to generate C++ code that will efficiently perform the simulation on the chosen parallel hardware (multi-core system or graphical processing unit). Several numerical methods are available to transform ordinary differential equations into an efficient C++code. We compare the parallel performance of the simulator to existing solutions.

Power Dissipation of Digital circuits can be reduced by 15% 25% by using appropriate logic restructuring and also it can be reduced by 40% 60% by lowering switching activity. Here, Gate Diffusion Input Technique which is based on a Shannon expansion is analyzed for minimizing the power consumption and delay of static digital circuits. This technique as compare to other currently used logic design style, allows less power consumption and reduced propagation delay for low-power design of combinatorial digital circuits with minimum number of transistors. In this paper, basic building blocks of digital system and few combinational circuits are analyzed using GDI and other CMOS techniques. All circuits are designed at 180nm technology in CADENCE and simulate using VIRTUOSO SPECTRE simulator at 100 MHz frequency. Comparative analysis has been done among GDI and other parallel design styles for designing ripple adder, CLA adder and bit magnitude comparator. Simulation result shows GDI technique saves 53. 3%, 55. 6% and 75. 6% power in ripple adder, CLA adder and bit magnitude comparator respectively as compare to CMOS. Also delay is reduced with 25. 2%, 3. 4% and 6. 9% as compare to CMOS. Analysis conclude that GDI is revolutionary high speed and low power consumption technique.

This paper describes a bioamplifier that employs a voltage-controlled-pseudo-resistor to achieve tunable bandwidth and wide operating voltage range for biomedical applications. The versatile pseudo-resistor employed provides ultra-high resistance for ac coupling to cancel the dc offset from electrode–tissue interface. The voltage-controlled-pseudo-resistor consists of serial-connected PMOS transistors working at the subthreshold region and an auto-tuning circuit that makes sure the constant (time-invariant) control-voltage of the pseudo-resistor. This bandwidth-tunable bioamplifier is designed in a 0.18-μm standard CMOS process, achieving a gain of 40.2 dB with 10.35-μW power consumption. The designed chip was also used to develop the proof-of-concept prototype. An operation bandwidth of 9.5 kHz, inputreferred noise of 5.2 μVrms from 6.3 Hz to 9.5 kHz and 5.54 μVrms from 250 Hz to 9.5 kHz, and a tunable cutoff-frequency from 6.3–600 Hz were demonstrated to prove our design. & 2015 Elsevier Ltd. All rights reserved.

A voltage-to-time converter (VTC) is presented for use in a time-based analog-to-digital converter (ADC). The converter runs with a 5 GHz input clock to provide a maximum conversion rate of 5 GS/s. A novel architecture enables the VTC to provide an adjustable linear delay versus input voltage characteristic. The circuit is realized in a 90nm CMOS process. After calibration, the converter achieves better than 3.7 effective bits for input frequencies up to 1.75 GHz, making it suitable for use in a time-based ADC with up to 4-bit resolution.

In this paper, we describe three simple low-voltage CMOS analogs of the Wilson current mirror that function well at all current levels, ranging from weak inversion to strong inversion. Each of these current mirrors can operate on a low power-supply voltage of a diode drop plus two saturation voltages and features a wide output-voltage swing with a cascode-type incremental output impedance. Two of the circuits requires an input voltage of a diode drop plus a saturation voltage while the third one features a low input voltage of a saturation voltage. We present experimental results from versions of these three current mirrors that were fabricated in a 0.5-mum CMOS process through MOSIS, comparing them with CMOS implementations of the conventional Wilson and super-Wilson current mirrors.

1 School of Electrical Engineering and Computer Science, Ohio University, Athens, Ohio, United States of America, 2 Bioinformatics and Research Computing, Whitehead Institute, Cambridge, Massachusetts, United States of America, 3 Department of Biological Sciences and School of Computer Science, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States of America, 4 European Molecular Biology Laboratory, European Bioinformatics Institute, Wellcome Trust Genome Campus, Hinxton, Cambridge, United Kingdom, 5 School of Informatics and Computing, Indiana University, Bloomington, Indiana, United States of America, 6 School of Computer Science and Engineering, The University of New South Wales, Sydney, New South Wales, Australia, 7 The Genome Analysis Centre, Norwich Research Park, Norwich, United Kingdom

Intrabody nanonetworks for nervous system monitoring are envisioned as a key application of the Internet of Nano-Things (IoNT) paradigm, with the aim of developing radically new medical diagnosis and treatment techniques. Indeed, very recently, bionic devices have been implanted inside a living human brain as innovative treatment for drug-resistant epilepsy. In this context, this paper proposes a systems-theoretic communication model to capture the actual behavior of biological neurons. Specifically, biological neurons exhibit physical extension due to their projections called dendrites, which propagate the electrochemical stimulation received via synapses to the soma. Experimental evidences show that the dendrites exhibit two main features: 1) the compartmentalization at the level of the dendritic branches of the neuronal processes and 2) the location-dependent preference for different frequencies. Stemming from these experimental evidences, we propose to model the dendritic tree as a spatiotemporal filter bank, where each filter models the behavior in both space and time of a dendritic branch. Each filter is fully characterized along with the overall neuronal response. Furthermore, sufficient conditions on the incoming stimulus for inducing a null-neuronal response are derived. The conducted theoretical analysis shows that: 1) the neuronal information is encoded in the stimulus temporal pattern, i.e., it is possible to select the neuron to affect by changing the stimulus frequency content; in this sense, the communication among neurons is frequency-selective and 2) the spatial distribution of the dendrites affects the neuronal response; in this sense, the communication among neurons is spatial-selective. The theoretical analysis is validated through a real neuron morphology.

Memristive nanodevices can feature a compact multilevel nonvolatile memory function, but are prone to device variability. We propose a novel neural network-based computing paradigm, which exploits their specific physics, and which has virtual immunity to their variability. Memristive devices are used as synapses in a spiking neural network performing unsupervised learning. They learn using a simplified and customized “spike timing dependent plasticity” rule. In the network, neurons’ threshold is adjusted following a homeostasis-type rule. We perform system level simulations with an experimentally verified model of the memristive devices’ behavior. They show, on the textbook case of character recognition, that performance can compare with traditional supervised networks of similar complexity. They also show that the system can retain functionality with extreme variations of various memristive devices’ parameters (a relative standard dispersion of more than 50% is tolerated on all device parameters), thanks to the robustness of the scheme, its unsupervised nature, and the capability of homeostasis. Additionally the network can adjust to stimuli presented with different coding schemes, is particularly robust to read disturb effects and does not require unrealistic control on the devices’ conductance. These results open the way for a novel design approach for ultraadaptive electronic systems.

This paper presents logic style compariso ns based on different logic functions and claimed m odified Gate Diffusion Input logic (Mod-GDI) to be much more power-efficient than Gate Diffusion Input logic (GDI) and complementary CMOS logic design. However, DC and Tr ansient analysis performed on more efficient modifi ed Gate Diffusion Input logic (Mod-GDI) circuit realization s and a wider range of different logic cells, as we ll as the use of practical circuit arrangements reveal Mod-GDI to be superior to GDI and CMOS in the majority cases wit h respect to speed, area, power dissipation, and power-delay pro ducts. This manuscript shows that Mod-GDI is the logic style of preference for the realization of arbitrary combinational circuits, if low voltage, low power, and small power-delay products are of concern. All Simulations are perfor med through PSPICE based on 0.18 μm CMOS technology, and results show power characteristics of Mod-GDI technique of low power digital circuit design. Simulation results shows up to 45% reduction in power-delay product in Mod-GDI. Mod-GDI approach allows realization of a broad variety of multifaceted logic functions by means of only two transistors. T his technique is appropriate for designing of fast, low power circuits, using reduced number of transistor (as compared to CMOS techniques), while improving power characteris tics.


Question: Analog transistor representations for bacterial genetic circuit modeling.

This paper presents an innovative 75 dB, 251 /spl mu/W analog speech processor designed to maintain the critical attributes of performance, robustness, and programmability required for hearing-impaired individuals, while significantly lowering power consumption in comparison to digital signal processing (DSP) and analog-to-digital (A/D) conversion methods. A notable feature of this processor is its capability to output zero-crossing signals, which are essential for stimulation techniques that leverage phase information to enhance the overall performance of hearing devices. This analog bionic ear processor represents a significant advancement in the field, offering a more efficient and effective solution for those suffering from hearing loss.

This paper describes an ultralow-power neural recording amplifier. The amplifier appears to be the lowest power and most energy-efficient neural recording amplifier reported to date. We describe low-noise design techniques that help the neural amplifier achieve input-referred noise that is near the theoretical limit of any amplifier using a differential pair as an input stage. Since neural amplifiers must include differential input pairs in practice to allow robust rejection of common-mode and power supply noise, our design appears to be near the optimum allowed by theory. The bandwidth of the amplifier can be adjusted for recording either neural spikes or local field potentials (LFPs). When configured for recording neural spikes, the amplifier yielded a midband gain of 40.8 dB and a -3-dB bandwidth from 45 Hz to 5.32 kHz; the amplifier's input-referred noise was measured to be 3.06 muVrms while consuming 7.56 muW of power from a 2.8-V supply corresponding to a noise efficiency factor (NEF) of 2.67 with the theoretical limit being 2.02. When configured for recording LFPs, the amplifier achieved a midband gain of 40.9 dB and a -3-dB bandwidth from 392 mHz to 295 Hz; the input-referred noise was 1.66 muVrms while consuming 2.08 muW from a 2.8-V supply corresponding to an NEF of 3.21. The amplifier was fabricated in AMI's 0.5-mum CMOS process and occupies 0.16 mm2 of chip area. We obtained successful recordings of action potentials from the robust nucleus of the arcopallium (RA) of an anesthesized zebra finch brain with the amplifier. Our experimental measurements of the amplifier's performance including its noise were in good accord with theory and circuit simulations.

The first part of this paper explores the general issues in using Artificial Life techniques to program actual mobile robots. In particular it explores the difficulties inherent in transferring programs evolved in a simulated environment to run on an actual robot. It examines the dual evolution of organism morphology and nervous systems in biology. It proposes techniques to capture some of the search space pruning that dual evolution offers in the domain of robot programming. It explores the relationship between robot morphology and program structure, and techniques for capturing regularities across this mapping. The second part of the paper is much more specific. It proposes techniques which could allow realistic explorations concerning the evolution of programs to control physically embodied mobile robots. In particular we introduce a new abstraction for behavior-based robot programming which is specially tailored to be used with genetic programming techniques. To compete with hand coding techniques it will be necessary to automatically evolve programs that are one to two orders of magnitude more complex than those previously reported in any domain. Considerable extensions to previously reported approaches to genetic programming are necessary in order to achieve this goal.

A low cost pulse transceiver has been developed for measuring the electrical properties of materials. The transceiver generates an ultra wide band (UWB) pulse as well as samples the received pulse. The pulse generator has been designed using a silicon-germanium (SiGe) analog comparator which is a possible alternative to step recovery diodes. The pulse is received by an extended time sampling circuit. The sampling circuit presented is an alternative design that does not require the use of a broadband balun.

In this paper, we argue that model-based design and platform-based design are two views of the same thing. A platform is a set of designs. Model-based design is about using platforms with useful modeling properties to specify designs, and then synthesizing implementations from these specifications. A design language, such as SystemC or VHDL, defines a platform. Any valid expression in the language is an element of the set. Viewed from below, the language provides an abstraction of implementation capabilities. Viewed from above, the language provides a set of constraints together with benefits that flow from those constraints. It provides a conceptual framework within which a design is crafted. An actor-oriented platform lies above the program-level platforms that are widely used today. It orthogonalizes the actor definition language and the actor assembly language, enabling domain-polymorphic actor definitions, multiple models of computation, and hierarchical heterogeneity. Actor-oriented platforms offer compelling modeling properties. Synthesis into program-level descriptions is possible. We illustrate these concepts by describing a design framework built on Ptolemy II.

XOR and XNOR gate plays an important role in digital systems including arithmetic and encryption circuits. This paper proposes a combination of XOR-XNOR gate using 6-transistors for low power applications. Comparison between a best existing XOR-XNOR have been done by simulating the proposed and other design using 65nm CMOS technology in Cadence environment. The simulation results demonstrate the delay, power consumption and power-delay product (PDP) at different supply voltages ranging from 0.6V to 1.2V. The results show that the proposed design has lower power dissipation and has a full voltage swing.

This paper describes the analysis and design of saturated silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) switches for millimeter-wave applications. A switch optimization procedure is developed based on detailed theoretical analysis and is then used to design multiple switch variants. The switches utilize IBM's 90-nm 9HP technology, which features SiGe HBTs with peak f T/ fmax of 300/350 GHz. Using a reverse-saturated configuration, a single-pole double-throw switch with a measured insertion loss of 1.05 dB and isolation of 22 dB is achieved at 94 GHz after de-embedding pad losses. The switch draws 5.2 mA from a 1.1-V supply, limiting power consumption to less than 6 mW. The switching speed is analyzed and the simulated turn-on and turn-off times are found to be less than 200 ps. A technique is also introduced to significantly increase the power-handling capabilities of saturated SiGe switches up to an input-referred 1-dB compression point of 22 dBm. Finally, the impact of RF stress on this novel configuration is investigated and initial measurements over a 48-h period show little performance degradation. These results demonstrate that SiGe-based switches may provide significant benefits to millimeter-wave systems.

We present a fully differential two-stage Miller op-amp operating from a 0.5 V power supply. The input signal is applied to the bulk nodes of the input devices. A prototype was designed in a standard 0.18 /spl mu/m CMOS process using standard 0.5 V V/sub T/ devices. It has a measured 52 dB DC gain, a 2.5 MHz gain-bandwidth and consumes 110 /spl mu/W.

The paper describes a technique to design a phase invariant variable gain amplifier (VGA). Variable gain is achieved by varying the bias current in a BJT, while the phase variation is minimized by designing a local feedback network such that the applied base to emitter voltage has a bias-dependent phase variation which compensates the inherent phase variation of the transconductance. Two differential 28GHz VGA variants based on these principles achieve <;5° phase variation over 8dB and 18dB of gain control range, respectively, with phase invariance maintained over PVT. Implemented in GF 8HP BiCMOS technology, the VGAs achieve 18dB nominal gain, 4GHz bandwidth, and IP1dB > -13dBm while consuming 35mW.

In this paper, we present a novel level shifter circuit converting subthreshold signal levels to super-threshold signal levels at high-speed using ultra low-power and a small silicon area, making it well-suited for low-power applications such as wireless sensor networks and implantable medical devices. The proposed circuit introduces a new voltage level shifter topology employing a level-shifting capacitor contributing to increase the range of conversion voltages, while significantly reducing the conversion delay. Such a level-shifting capacitor is quickly charged, whenever the input signal detects a low-to-high transition, in order to boost internal voltage nodes, and quickly reach a high output voltage level. The proposed circuit achieves a shorter propagation delay and a smaller silicon area for a given operating frequency and power consumption compared to other circuit solutions. Measurement results are presented for the proposed circuit fabricated in a 0.18- $\mu \text {m}$  TSMC technology. The proposed circuit can convert a wide range of the input voltages from 330 mV to 1.8 V, and operate over a frequency range of 100 Hz to 100 MHz. It has a propagation delay of 29 ns and a power consumption of 61.5 nW for input signals 0.4 V, at a frequency of 500-kHz, outperforming previous designs.

This paper provides an overview of the recent circuit level and physical level substrate noise reduction techniques. Several of these techniques are compared for their advantages and disadvantages in "system-on-chip" applications.


Question: Analog transistor representations for bacterial genetic circuit simulations.

The genomic exploration for enhancing cellulosic biofuel production
In the quest for sustainable energy alternatives to fossil fuels, cellulosic biomass has emerged as a promising resource for biofuel generation. However, the practical realization of large-scale cellulosic biofuel production faces significant challenges, including land-use constraints and process inefficiencies. To overcome these obstacles and advance the field, the integration of genomic knowledge from various biological sources is essential. This includes the study of potential energy crops and microorganisms capable of efficiently degrading biomass. By harnessing genomic information from across the biosphere, researchers aim to optimize energy crop traits and enhance the capabilities of biomass-degrading microorganisms. This strategy is pivotal for improving the efficiency and scalability of biomass-to-biofuel conversion technologies, ultimately contributing to a more viable and sustainable future for cellulosic biofuel production.

Next generation wireless transmitters will rely on highly integrated silicon-based solutions to realize the cost and performance goals of the 4G market. This will require increased use of digital compensation techniques and innovative circuit approaches to maximize power and efficiency and minimize linearity degradation. This paper summarizes the circuit and system strategies being developed to meet these aggressive performance goals.

A 1.8V CMOS chopper four-quadrant analog multiplier, intending to serve as an autonomous IC block for low-frequency signal processing, is presented. Particular emphasis is laid upon achieving low output noise by means of chopper stabilization, while the multiplier's operation is based on the MOS Translinear Principle. The proposed design has been implemented and simulated in TSMC 0.18 µm CMOS process.

This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic preamplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor’s parameters in pre-amplifier’s gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers’ estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results. key words: dynamic amplifier, dynamic comparator, load capacitance, bypass current, calibration, and PVT variation

“Some Design Aspects of a Two-Stage Rail-to-Rail CMOS Op Amp' by Sander L. J. Gierkink, Peter J. Holzmann, Remco J. Wiegerink and Roelof F. Wassenaar, Analog Integrated Circuits and Signal Processing, Vol. 21, No. 2, Nov. 1999, pp 143-152. “Compact Low-Voltage Power-Efficient Operational Amplifier Cells for VLSI by Klaas-Jan de Langen and Johan H. Huijsing, IEEE Journal of Solid State Circuits, vol. 33, No. 10, Oct. 1998, pp. 1482–1496. “Design Aspects of a Rail-to-Rail CMOS Op Amp' by Glierkink et al., Mesa Research institute, ECT-97-36, pp. 23-28.

Neuromorphic algorithms, which are comprised of highly complex, large-scale networks of artificial neurons, are increasingly used for a variety of recognition, classification, search and vision tasks. However, their computational and energy requirements can be quite high, and hence their energy-efficient implementation is of great interest.
 We propose a new approach to design energy-efficient hardware implementations of large-scale neural networks (NNs) using approximate computing. Our work is motivated by the observations that (i) NNs are used in applications where less-than-perfect results are acceptable, and often inevitable, and (ii) they are highly resilient to inexactness in many (but not all) of their constituent computations. We make two key contributions. First, we propose a method to transform any given NN into an Approximate Neural Network (AxNN). This is performed by (i) adapting the backpropagation technique, which is commonly used to train these networks, to quantify the impact of approximating each neuron to the overall network quality (e.g., classification accuracy), and (ii) selectively approximating those neurons that impact network quality the least. Further, we make the key observation that training is a naturally error-healing process that can be used to mitigate the impact of approximations to neurons. Therefore, we incrementally retrain the network with the approximations in-place, reclaiming a significant portion of the quality ceded by approximations. As a second contribution, we propose a programmable and quality-configurable neuromorphic processing engine (qcNPE), which utilizes arrays of specialized processing elements that execute neuron computations with dynamically configurable accuracies and can be used to execute AxNNs from diverse applications. We evaluated the proposed approach by constructing AXNNs for 6 recognition applications (ranging in complexity from 12-47,818 neurons and 160-3,155,968 connections) and executing them on two different platforms--qcNPE implementation containing 272 processing elements in 45nm technology and a commodity Intel Xeon server. Our results demonstrate 1.14X-1.92X energy benefits for virtually no loss (< 0.5%) in output quality, and even higher improvements (upto 2.3X) when some loss (upto 7.5%) in output quality is acceptable.

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the timeconsuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster. & 2009 Elsevier B.V. All rights reserved.

In this paper we presented a new 13T full adder design based on hybrid --CMOS logic design style. Adders are one of the most basic building blocks in digital components present in the Arithmetic Logic Unit (ALU). The performance of an adder have a significant impact on the overall performance of a digital system. The new design is compared with some existing designs for power consumption, delay, PDP at various frequencies viz 10 MHz, 200 MHz and 1 GHz. the simulations are carried out on Cadence Virtuoso at 180nm CMOS technology and the simulation results are analyzed to verify the superiority of the proposed design over the existing designs. Maximum saving of power delay product is at low frequency by proposed circuit is 96.8% with respect to C-CMOS and significant improvement is observed at other frequencies also. The power consumption increases at a slow rate in comparison to other adders with increase in frequency.

In this paper, we present a novel level shifter circuit converting subthreshold signal levels to super-threshold signal levels at high-speed using ultra low-power and a small silicon area, making it well-suited for low-power applications such as wireless sensor networks and implantable medical devices. The proposed circuit introduces a new voltage level shifter topology employing a level-shifting capacitor contributing to increase the range of conversion voltages, while significantly reducing the conversion delay. Such a level-shifting capacitor is quickly charged, whenever the input signal detects a low-to-high transition, in order to boost internal voltage nodes, and quickly reach a high output voltage level. The proposed circuit achieves a shorter propagation delay and a smaller silicon area for a given operating frequency and power consumption compared to other circuit solutions. Measurement results are presented for the proposed circuit fabricated in a 0.18- $\mu \text {m}$  TSMC technology. The proposed circuit can convert a wide range of the input voltages from 330 mV to 1.8 V, and operate over a frequency range of 100 Hz to 100 MHz. It has a propagation delay of 29 ns and a power consumption of 61.5 nW for input signals 0.4 V, at a frequency of 500-kHz, outperforming previous designs.

This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemented to write assembly programs in this teaching tool. In addition to the microoperation simulation, the complete configuration can be run on Xilinx Spartan-3 FPGA board. Such implementation offers good code density, easy customization, easily developed software, small area, and high performance at low cost.

This work discusses two fundamental blocks of an in vivo MOS dosimeter, namely the radiation sensor and the VT-extractor circuit. It is shown that threshold extractor circuits based on an all-region MOSFET model are very appropriate for low power design. The accuracy of the extractor circuits allows using the PMOS transistors of the integrated circuit CD4007 as the radiation sensor in a dosimeter for radiotherapy applications.


Question: Analog transistor representations for simulating bacterial genetic circuitry.

A 10-nW 12-bit precise analog storage cell with sub-femtoamp leakage
Analog storage cells provide a compact, precise, and energy-efficient solution for temporary local memory, particularly beneficial in adaptive circuit applications. Their performance is primarily defined by the sampling precision and voltage droop achievable within a specified area and power budget. Prior implementations may have fallen short of optimal voltage droop due to unaccounted MOS leakage mechanisms. This paper presents an experimental characterization of the primary sources of MOS leakage in a standard 1.5-micron CMOS process, focusing on currents in the 1 femtoamp to 1 attoamp range. The findings uncover an accumulation-mode source-drain coupling mechanism that can overshadow diode leakage under certain bias conditions, potentially limiting previous designs. To circumvent this leakage issue, a straightforward guideline is proposed, leading to the development of an ultra-low leakage switch topology. A differential storage cell, incorporating this innovative switch, achieves an average leakage of 10 attoamps at room temperature, marking an 8-fold reduction compared to previous designs. The cell maintains one bit of voltage precision, equating to 700 microvolts on a 12-bit scale and 11.3 millivolts on an 8-bit scale, for durations of 3.3 and 54 minutes, respectively. This represents a 15-fold enhancement in hold time at these voltage precisions compared to the lowest leakage cell to date, in only 92% of the required area. As the leakage is independent of amplifier bias, the cell can operate on as little as 10 nanowatts of power. Preliminary measurements also suggest that the switch's leakage decreases quadratically with the reduction in process feature size.

This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemented to write assembly programs in this teaching tool. In addition to the microoperation simulation, the complete configuration can be run on Xilinx Spartan-3 FPGA board. Such implementation offers good code density, easy customization, easily developed software, small area, and high performance at low cost.

This paper presents a noninvasive wireless sensor platform for continuous health monitoring. The sensor system integrates a loop antenna, wireless sensor interface chip, and glucose sensor on a polymer substrate. The IC consists of power management, readout circuitry, wireless communication interface, LED driver, and energy storage capacitors in a 0.36-mm2 CMOS chip with no external components. The sensitivity of our glucose sensor is 0.18 μA·mm-2·mM-1. The system is wirelessly powered and achieves a measured glucose range of 0.05-1 mM with a sensitivity of 400 Hz/mM while consuming 3 μW from a regulated 1.2-V supply.

Sample preparation in digital microfluidics refers to the generation of droplets with target concentrations for onchip biochemical applications. In recent years, digital microfluidic biochips (DMFBs) have been adopted as a platform for sample preparation. However, there remain one major problem associated with sample preparation on a conventional DMFB. For conventional DMFBs, only a (1:1) mixing/splitting model can be used, leading to an increase in the number of fluidic operations required for sample preparation. To overcome the drawback, we adopt a next generation DMFB platform, referred to as micro-electrode-dot-array (MEDA), for sample preparation. We propose the first sample preparation method that exploits the MEDA-specific advantages of fine-grained control of droplet sizes and real-time droplet sensing. Experimental demonstration using a fabricated MEDA biochip and simulation results highlight the effectiveness of the proposed sample-preparation method.

Systems that extract structured information from natural language passages have been highly successful in specialized domains. The time is opportune for developing analogous applications for molecular biology and genomics. We present a system, GENIES, that extracts and structures information about cellular pathways from the biological literature in accordance with a knowledge model that we developed earlier. We implemented GENIES by modifying an existing medical natural language processing system, MedLEE, and performed a preliminary evaluation study. Our results demonstrate the value of the underlying techniques for the purpose of acquiring valuable knowledge from biological journals.

A 75 dB 251 /spl mu/W analog speech processor is described that preserves the performance, robustness, and programmability needed for deaf patients at a reduced power consumption compared to that of implementations with A/D and DSP. It also provides zero-crossing outputs for stimulation strategies that use phase information to improve performance.

This paper presents a wireless headstage with real-time spike detection and data compression for combined optogenetics and multichannel electrophysiological recording. The proposed headstage, which is intended to perform both optical stimulation and electrophysiological recordings simultaneously in freely moving transgenic rodents, is entirely built with commercial off-the-shelf components, and includes 32 recording channels and 32 optical stimulation channels. It can detect, compress and transmit full action potential waveforms over 32 channels in parallel and in real time using an embedded digital signal processor based on a low-power field programmable gate array and a Microblaze microprocessor softcore. Such a processor implements a complete digital spike detector featuring a novel adaptive threshold based on a Sigma-delta control loop, and a wavelet data compression module using a new dynamic coefficient re-quantization technique achieving large compression ratios with higher signal quality. Simultaneous optical stimulation and recording have been performed in-vivo using an optrode featuring 8 microelectrodes and 1 implantable fiber coupled to a 465-nm LED, in the somatosensory cortex and the Hippocampus of a transgenic mouse expressing ChannelRhodospin (Thy1::ChR2-YFP line 4) under anesthetized conditions. Experimental results show that the proposed headstage can trigger neuron activity while collecting, detecting and compressing single cell microvolt amplitude activity from multiple channels in parallel while achieving overall compression ratios above 500. This is the first reported high-channel count wireless optogenetic device providing simultaneous optical stimulation and recording. Measured characteristics show that the proposed headstage can achieve up to 100% of true positive detection rate for signal-to-noise ratio (SNR) down to 15 dB, while achieving up to 97.28% at SNR as low as 5 dB. The implemented prototype features a lifespan of up to 105 minutes, and uses a lightweight (2.8 g) and compact  $(17 \times 18 \times 10\ \text{mm}^{3})$ rigid-flex printed circuit board.

Many modern neural simulators focus on the simulation of networks of spiking neurons on parallel hardware. Another important framework in computational neuroscience, rate-coded neural networks, is mostly difficult or impossible to implement using these simulators. We present here the ANNarchy (Artificial Neural Networks architect) neural simulator, which allows to easily define and simulate rate-coded and spiking networks, as well as combinations of both. The interface in Python has been designed to be close to the PyNN interface, while the definition of neuron and synapse models can be specified using an equation-oriented mathematical description similar to the Brian neural simulator. This information is used to generate C++ code that will efficiently perform the simulation on the chosen parallel hardware (multi-core system or graphical processing unit). Several numerical methods are available to transform ordinary differential equations into an efficient C++code. We compare the parallel performance of the simulator to existing solutions.

PSO and DE algorithms and its variants are used for the optimization of a buffer-chain circuit and the results of all the algorithms are compared in this literature. By testing these algorithms on different mathematical benchmark functions the best parameter values of buffer chain circuit are obtained in such a way that it reduces the error between simulated output and optimized output, hence giving the best circuit performance. Evolutionary algorithms are better in performance and speed than the classical methods. 130nm CMOS technology has been used in this work. With the help of these parameter values the circuit simulator gives the values of power consumption, symmetry, rise time and fall time, which are almost closer to the desired specification of the buffer chain circuit.

This brief presents a capacitor digital-to-analog converter (DAC) based technique that is suitable for pre-emphasis-enabled multilevel wireline transmitter design in voltage mode. Detailed comparisons between the proposed technique and conventional direct-coupling-based as well as resistor-DAC-based multilevel transmitter design techniques are given, revealing potential benefits in terms of speed, linearity, implementation complexity, and also power consumption. A PAM-4 transmitter with 2-Tap feed-forward equalization adopting the proposed technique is implemented in 65-nm CMOS technology. It achieves a 25-Gb/s data rate and energy efficiency of 2 mW/Gb/s.

This brief delineates the design and realization of a 10-GS/s 4-bit digital-to-analog converter (DAC) for the cognitive ultrawideband (CUWB), an emerging solution for low interference and efficient spectrum utilization in communication networks. The DAC serves as the data converter for the adaptive waveform transmitter therein, largely to reduce its power dissipation and hardware complexity. For reasons of low power dissipation and low-cost CUWB application, the resolution of the DAC is 4 bits, its realization is in standard 65-nm CMOS, and the architecture is a single core. The binary current-steering DAC includes critical building blocks such as current sources and a novel deglitcher circuit. The current sources are designed for small area with high linearity based on our derived relationship between current-source output resistance and linearity parameters [integral nonlinearity (INL) and spurious-free dynamic range (SFDR)]. The deglitcher design includes high-speed source followers as high-speed low voltage swing buffers to improve the linearity by decreasing the output glitch energy. The DAC embodies an in situ hardware efficient (small integrated-circuit area and reduced input/output pinout) tester that generates 4 × 10-Gb/s test-data pattern to facilitate functional verification. The designed DAC achieves ≤ 0.16-least significant bit INL/differential nonlinearity and > 23-dBc SFDR over the Nyquist bandwidth up to 4.53 GHz, and features the most competitive figures-of-merit of all similar DACs reported to date.


Question: Defending against multi-target assaults in hash-based signature systems.

This paper explores the capabilities and limitations of quantum computing, a topic that has garnered significant interest due to recent breakthroughs [4, 16, 15] indicating that quantum computers may outperform classical probabilistic machines. Building upon Shor's discovery that both factoring and discrete logarithm problems can be solved in quantum polynomial time, a natural inquiry arises: Can all problems in NP be efficiently resolved within quantum polynomial time? We tackle this question by demonstrating that, relative to an oracle selected at random, the probability is 1 that NP cannot be solved by a quantum Turing machine in time o(2n/2). Furthermore, we show that, relative to a permutation oracle chosen at random, the probability is 1 that NP ∩ co-NP cannot be solved by a quantum Turing machine in time o(2n/3). These findings are significant as they establish a baseline for the computational boundaries of quantum machines. Grover's recent work [13], which illustrates how to accept the class NP relative to any oracle on a quantum computer in time O(2n/2), confirms the tightness of our first bound. This research will be featured in a special issue of the SIAM Journal on Computing dedicated to quantum computing. The authors are affiliated with IBM T. J. Watson Research Laboratory, Microsoft, nserc and fcar in Canada, Université de Montréal, and the University of California, Berkeley, and are supported by various grants and institutions.

Question: Enhancing Security in Blockchain through Quantum Key Distribution

Documents: Quantum Computing and Cryptography
Quantum computing presents a paradigm shift that challenges the security foundations of traditional cryptographic systems. This paper discusses the implications of quantum computing on cryptography, focusing on the vulnerabilities that arise when classical cryptographic algorithms are subjected to quantum computing attacks. We analyze the impact of Shor's algorithm on public-key cryptography, demonstrating that it can efficiently factor large numbers and compute discrete logarithms, tasks that are central to the security of widely used cryptosystems such as RSA and Diffie-Hellman. Moreover, we explore the resilience of symmetric-key cryptography in the face of quantum computing, finding that while quantum computers can accelerate the search for symmetric keys, the increased key size can mitigate this threat. We also introduce post-quantum cryptography, a field that aims to develop cryptographic algorithms that are secure against both classical and quantum computers. This includes lattice-based cryptography, code-based cryptography, and hash-based cryptography, which are considered promising candidates for post-quantum security. We conclude by

Security and performance are critical goals for distributed systems. The increased design complexity, incomplete expertise of developers, and limited functionality of existing testing tools often result in bugs and vulnerabilities that prevent implementations from achieving their design goals in practice. Many of these bugs, vulnerabilities, and misconfigurations manifest after the code has already been deployed making the debugging process difficult and costly. In this paper, we present Turret, a platform for automatically finding performance attacks in unmodified implementations of distributed systems. Turret does not require the user to provide any information about vulnerabilities and runs the implementation in the same operating system setup as the deployment, with an emulated network. Turret uses a new attack finding algorithm and several optimizations that allow it to find attacks in a matter of minutes. We ran Turret on 5 different distributed system implementations specifically designed to tolerate insider attacks, and found 30 performance attacks, 24 of which were not previously reported to the best of our knowledge.

Software cache-based side channel attacks present serious threats to modern computer systems. Using caches as a side channel, these attacks are able to derive secret keys used in cryptographic operations through legitimate activities. Among existing countermeasures, software solutions are typically application specific and incur substantial performance overhead. Recent hardware proposals including the Partition-Locked cache (PLcache) and Random-Permutation cache (RPcache) [23], although very effective in reducing performance overhead while enhancing the security level, may still be vulnerable to advanced cache attacks. In this paper, we propose three hardware-software approaches to defend against software cache-based attacks - they present different tradeoffs between hardware complexity and performance overhead. First, we propose to use preloading to secure the PLcache. Second, we leverage informing loads, which is a lightweight architectural support originally proposed to improve memory performance, to protect the RPcache. Third, we propose novel software permutation to replace the random permutation hardware in the RPcache. This way, regular caches can be protected with hardware support for informing loads. In our experiments, we analyze various processor models for their vulnerability to cache attacks and demonstrate that even to the processor model that is most vulnerable to cache attacks, our proposed software-hardware integrated schemes provide strong security protection.

The TLS Internet Standard features a mixed bag of cryptographic algorithms and constructions, letting clients and servers negotiate their use for each run of the handshake. Although many ciphersuites are now well-understood in isolation, their composition remains problematic, and yet it is critical to obtain practical security guarantees for TLS. We experimentally confirm that all mainstream implementations of TLS share key materials between different algorithms, some of them of dubious strength. We outline attacks in their handling of resumption and renegotiation, stressing the need to model multiple related instances of the handshake. We study the provable security of the TLS handshake, as it is implemented and deployed. To capture the details of the standard and its main extensions, we rely on miTLS, a verified reference implementation of the protocol. miTLS inter-operates with mainstream browsers and servers for many protocol versions, configurations, and ciphersuites; and it provides application-level, provable security for some. We propose new agile security definitions and assumptions for the signatures, key encapsulation mechanisms (KEM), and key derivation algorithms used by the TLS handshake. By necessity, our definitions are stronger than those expected with simple modern protocols. To validate our model of key encapsulation, we prove that both RSA and Diffie-Hellman ciphersuites satisfy our definition for the KEM. In particular, we formalize the use of PKCS#1v1.5 encryption in TLS, including recommended countermeasures against Bleichenbacher attacks, and build a 3,000-line EasyCrypt proof of the security of the resulting master secret KEM against replayable chosen-ciphertext attacks under the assumption that ciphertexts are hard to re-randomize. Based on our new agile definitions, we construct a modular proof of security for the miTLS reference implementation of the handshake, including ciphersuite negotiation, key exchange, renegotiation, and resumption, treated as a detailed 3,600-line executable model. We present our main definitions, constructions, and proofs for an abstract model of the protocol, featuring series of related runs of the handshake with different ciphersuites. We also describe its refinement to account for the whole reference implementation, based on automated verification tools.

We present a simple and efficient compiler for transforming secure multi-party computation (MPC) protocols that enjoy security only with an honest majority into MPC protocols that guarantee security with no honest majority, in the oblivious-transfer (OT) hybrid model. Our technique works by combining a secure protocol in the honest majority setting with a protocol achieving only security against semi-honest parties in the setting of no honest majority. Applying our compiler to variants of protocols from the literature, we get several applications for secure two-party computation and for MPC with no honest majority. These include: • Constant-rate two-party computation in the OT-hybrid model. We obtain a statistically UC-secure two-party protocol in the OT-hybrid model that can evaluate a general circuit C of size s and depth d with a total communication complexity of O(s)+ poly(k, d, log s) and O(d) rounds. The above result generalizes to a constant number of parties. • Extending OTs in the malicious model. We obtain a computationally efficient protocol for generating many string OTs from few string OTs with only a constant amortized communication overhead compared to the total length of the string OTs. • Black-box constructions for constant-round MPC with no honest majority. We obtain general computationally UC-secure MPC protocols in the OT-hybrid model that use only a constant number of rounds, and only make a black-box access to a pseudorandom generator. This gives the first constant-round protocols for three or more parties that only make a black-box use of cryptographic primitives (and avoid expensive zero-knowledge proofs).

In a data-driven society, individuals and companies encounter numerous situations where private information is an important resource. How can parties handle confidential data if they do not trust everyone involved? This text is the first to present a comprehensive treatment of unconditionally secure techniques for multiparty computation (MPC) and secret sharing. In a secure MPC, each party possesses some private data, whereas secret sharing provides a way for one party to spread information on a secret such that all parties together hold full information, yet no single party has all the information. The authors present basic feasibility results from the last thirty years, generalizations to arbitrary access structures using linear secret sharing, some recent techniques for efficiency improvements, and a general treatment of the theory of secret sharing, focusing on asymptotic results with interesting applications related to MPC.

Searchable encryption schemes allow users to perform keyword based searches on an encrypted database. Almost all existing such schemes only consider the scenario where a single user acts as both the data owner and the querier. However, most databases in practice do not just serve one user; instead, they support search and write operations by multiple users. In this paper, we systematically study searchable encryption in a practical multi-user setting. Our results include a set of security notions for multi-user searchable encryption as well as a construction which is provably secure under the newly introduced security notions.

Recent work by Krawczyk [12] and Menezes [16] has highlighted the importance of understanding well the guarantees and limitations of formal security models when using them to prove the security of protocols. In this paper we focus on security models for authenticated key exchange (AKE) protocols. We observe that there are several classes of attacks on AKE protocols that lie outside the scope of the Canetti-Krawczyk model. Some of these additional attacks have already been considered by Krawczyk [12]. In an attempt to bring these attacks within the scope of the security model we extend the Canetti-Krawczyk model for AKE security by providing significantly greater powers to the adversary. Our contribution is a more compact, integrated, and comprehensive formulation of the security model. We then introduce a new AKE protocol called NAXOS and prove that it is secure against these stronger

Empirical evidence suggests that hashing is an effective strategy for dimensionality reduction and practical nonparametric estimation. In this paper we provide exponential tail bounds for feature hashing and show that the interaction between random subspaces is negligible with high probability. We demonstrate the feasibility of this approach with experimental results for a new use case --- multitask learning with hundreds of thousands of tasks.

The Bitcoin cryptocurrency records its transactions in a public log called the blockchain. Its security rests critically on the distributed protocol that maintains the blockchain, run by participants called miners. Conventional wisdom asserts that the mining protocol is incentive-compatible and secure against colluding minority groups, that is, it incentivizes miners to follow the protocol as prescribed.
 We show that the Bitcoin mining protocol is not incentive-compatible. We present an attack with which colluding miners' revenue is larger than their fair share. The attack can have significant consequences for Bitcoin: Rational miners will prefer to join the attackers, and the colluding group will increase in size until it becomes a majority. At this point, the Bitcoin system ceases to be a decentralized currency.
 Unless certain assumptions are made, selfish mining may be feasible for any coalition size of colluding miners. We propose a practical modification to the Bitcoin protocol that protects Bitcoin in the general case. It prohibits selfish mining by a coalition that command less than 1/4 of the resources. This threshold is lower than the wrongly assumed 1/2 bound, but better than the current reality where a coalition of any size can compromise the system.

In ciphertext policy attribute-based encryption (CP-ABE), every secret key is associated with a set of attributes, and every ciphertext is associated with an access structure on attributes. Decryption is enabled if and only if the user's attribute set satisfies the ciphertext access structure. This provides fine-grained access control on shared data in many practical settings, e.g., secure database and IP multicast.
 In this paper, we study CP-ABE schemes in which access structures are AND gates on positive and negative attributes. Our basic scheme is proven to be chosen plaintext (CPA) secure under the decisional bilinear Diffie-Hellman (DBDH) assumption. We then apply the Canetti-Halevi-Katz technique to obtain a chosen ciphertext (CCA) secure extension using one-time signatures. The security proof is a reduction to the DBDH assumption and the strong existential unforgeability of the signature primitive.
 In addition, we introduce hierarchical attributes to optimize our basic scheme - reducing both ciphertext size and encryption/decryption time while maintaining CPA security. We conclude with a discussion of practical applications of CP-ABE.


Question: Defending against multi-target assaults in hash-based signature systems.

This paper offers a comprehensive analysis of Grover's quantum database searching algorithm, delivering a precise formula to determine the success probability after any given iteration. This insight enables us to calculate the optimal number of iterations required for a near-guaranteed success in finding the target element. Additionally, the paper explores the algorithm's performance in scenarios where the sought-after element is not unique, presenting a novel method to locate such elements even when the total number of occurrences is unknown. By integrating techniques from Shor's quantum factoring algorithm with Grover's approach, the paper introduces an innovative technique for approximate quantum counting, facilitating the estimation of the number of solutions. Moreover, it establishes a lower bound on the efficiency of any quantum database searching algorithm, demonstrating that Grover's method is almost twice as optimal as any potential alternative in terms of the number of queries needed.

**Question**: An Algorithm for Secure Sharing of Personal Data

**Documents**: A Secure and Efficient Anonymous Authentication Scheme for Cloud Storage Services
To ensure secure access to cloud storage services, we propose a secure and efficient anonymous authentication scheme. In our scheme, a user can anonymously authenticate himself to a cloud storage server, without revealing his identity to the server. The user's identity is only known to the trusted third party, which is responsible for managing the user's credentials. The scheme is based on elliptic curve cryptography, which provides high security with low computational overhead. The scheme also supports user revocation and traceability, which are important features for cloud storage services. The security of our scheme is formally analyzed using the well-known BAN logic, and the performance of our scheme is evaluated through simulations. The results show that our scheme is efficient and scalable for practical cloud storage services.

**Similar Documents**: We introduce a secure and efficient anonymous authentication protocol tailored for cloud storage services, designed to ensure user privacy while accessing data. In our scheme, users can authenticate themselves to the cloud storage server without disclosing their identities, with only the trusted third party having knowledge of the user's true identity, responsible for credential management. Utilizing elliptic curve cryptography, the scheme achieves robust security with minimal computational requirements. Notably, it incorporates user revocation and traceability, critical for cloud storage functionality. The security analysis of our scheme is conducted using BAN logic, a well-established formal method, and its performance is assessed through simulations, demonstrating efficiency and scalability suitable for real-world cloud storage applications.

Power analysis attacks are a serious treat for implementations of modern cryptographic algorithms. Masking is a particularly appealing countermeasure against such attacks since it increases the security to a well quantifiable level and can be implemented without modifying the underlying technology. Its main drawback is the performance overhead it implies. For example, due to prohibitive memory costs, the straightforward application of masking to the AES algorithm, with precomputed tables, is hardly practical. In this paper, we exploit both the increased size of state-of-the-art reconfigurable hardware devices and previous optimization techniques to minimize the memory occupation of software S-boxes, in order to provide an efficient FPGA implementation of the AES algorithm, masked against side-channel attacks. We describe two high throughput architectures, based on 32-bit and 128-bit datapaths that are suitable for Xilinx Virtex-5 devices. In this way, we demonstrate the possibility to efficiently combine technological advances with algorithmic optimizations in this context.

In this paper, we present a fast attack algorithm to find two-block collision of hash function MD5. The algorithm is based on the two-block collision differential path of MD5 that was presented by Wang et al. in the Conference EUROCRYPT 2005. We found that the derived conditions for the desired collision differential path were not sufficient to guarantee the path to hold and that some conditions could be modified to enlarge the collision set. By using technique of small range searching and omitting the computing steps to check the characteristics in the attack algorithm, we can speed up the attack of MD5 efficiently. Compared with the Advanced Message Modification technique presented by Wang et al., the small range searching technique can correct 4 more conditions for the first iteration differential and 3 more conditions for the second iteration differential, thus improving the probability and the complexity to find collisions. The whole attack on the MD5 can be accomplished within 5 hours using a PC with Pentium4 1.70GHz CPU.

New Cryptographic protocols which take full advantage of the unique properties of public key cryptosystems are now evolving. Several protocols for public key distribution and for digital signatures are briefly compared with each other and with the conventional alternative.

We analyze the concrete security and key sizes of theoretically sound lattice-based encryption schemes based on the “learning with errors” (LWE) problem. Our main contributions are: (1) a new lattice attack on LWE that combines basis reduction with an enumeration algorithm admitting a time/success tradeoff, which performs better than the simple distinguishing attack considered in prior analyses; (2) concrete parameters and security estimates for an LWE-based cryptosystem that is more compact and efficient than the well-known schemes from the literature. Our new key sizes are up to 10 times smaller than prior examples, while providing even stronger concrete security levels.

In this paper we explore the problem of creating vulnerability signatures. A vulnerability signature matches all exploits of a given vulnerability, even polymorphic or metamorphic variants. Our work departs from previous approaches by focusing on the semantics of the program and vulnerability exercised by a sample exploit instead of the semantics or syntax of the exploit itself. We show the semantics of a vulnerability define a language which contains all and only those inputs that exploit the vulnerability. A vulnerability signature is a representation (e.g., a regular expression) of the vulnerability language. Unlike exploit-based signatures whose error rate can only be empirically measured for known test cases, the quality of a vulnerability signature can be formally quantified for all possible inputs. We provide a formal definition of a vulnerability signature and investigate the computational complexity of creating and matching vulnerability signatures. We also systematically explore the design space of vulnerability signatures. We identify three central issues in vulnerability-signature creation: how a vulnerability signature represents the set of inputs that may exercise a vulnerability, the vulnerability coverage (i.e., number of vulnerable program paths) that is subject to our analysis during signature creation, and how a vulnerability signature is then created for a given representation and coverage. We propose new data-flow analysis and novel adoption of existing techniques such as constraint solving for automatically generating vulnerability signatures. We have built a prototype system to test our techniques. Our experiments show that we can automatically generate a vulnerability signature using a single exploit which is of much higher quality than previous exploit-based signatures. In addition, our techniques have several other security applications, and thus may be of independent interest

—A digital signature is an important public-key primitive that performs the function of conventional handwritten signatures for entity authentication, data integrity, and non-repudiation, especially within the electronic commerce environment. Currently, most conventional digital signature schemes are based on mathematical hard problems. These mathematical algorithms require computers to perform the heavy and complex computations to generate and verify the keys and signatures. In 1995, Naor and Shamir proposed a visual cryptography (VC) for binary images. VC has high security and requires simple computations. The purpose of this paper is to provide an alternative to the current digital signature technology. In this paper, we introduce a new digital signature scheme based on the concept of a non-expansion visual cryptography. A visual digital signature scheme is a method to enable visual verification of the authenticity of an image in an insecure environment without the need to perform any complex computations. Our proposed scheme generates visual shares and manipulates them using the simple Boolean operations OR rather than generating and computing large and long random integer values as in the conventional digital signature schemes currently in use.

We introduce a formal modeling in ASLan++ of the twofactor authentication protocol used by the Electrum Bitcoin wallet. This allows us to perform an automatic analysis of the wallet and show that it is secure for standard scenarios in Dolev Yao model [Dolev 1981]. The result could be derived thanks to some advanced features of the protocol analyzer such as the possibility to specify i) new intruder deduction rules with clauses and ii) non-deducibility constraints.

In an attribute-based encryption (ABE) scheme, a ciphertext is associated with an ℓ-bit public index ind and a message m, and a secret key is associated with a Boolean predicate P. The secret key allows decrypting the ciphertext and learning m if and only if P(ind) = 1. Moreover, the scheme should be secure against collusions of users, namely, given secret keys for polynomially many predicates, an adversary learns nothing about the message if none of the secret keys can individually decrypt the ciphertext.
 We present attribute-based encryption schemes for circuits of any arbitrary polynomial size, where the public parameters and the ciphertext grow linearly with the depth of the circuit. Our construction is secure under the standard learning with errors (LWE) assumption. Previous constructions of attribute-based encryption were for Boolean formulas, captured by the complexity class NC1.
 In the course of our construction, we present a new framework for constructing ABE schemes. As a by-product of our framework, we obtain ABE schemes for polynomial-size branching programs, corresponding to the complexity class LOGSPACE, under quantitatively better assumptions.

The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper presents the full implementations of all of the second round candidates in hardware with all of their variants. In order to determine their computational efficiency, an important aspect in NIST's round two evaluation criteria, this paper gives an area/speed comparison of each design both with and without a hardware interface, thereby giving an overall impression of their performance in resource constrained and resource abundant environments. The implementation results are provided for a Virtex-5 FPGA device. The efficiency of the architectures for the hash functions are compared in terms of throughput per unit area.

The one-time pad, the mother of all encryption schemes, is well known to be information-theoretically secure, in contrast to most encryption schemes used in practice, which are at most computationally secure. In this paper, we focus on another, completely different aspect in which the one-time pad is superior to normal encryption, and which surfaces only when the receiver (not only the eavesdropper) is considered potentially dishonest, as can be the case in a larger protocol context in which encryption is used as a sub-protocol. For example, such a dishonest receiver (who is, say, coerced by the eavesdropper) can in normal encryption verifiably leak the message to the eavesdropper by revealing the secret key. While this leakage feature can provably not be avoided completely, it is more limited if the one-time pad is used. We use the constructive cryptography framework to make these statements precise.


Question: Defending against multi-target assaults in hash-based signature systems.

Introducing XMSS: A Novel, Efficient Forward Secure Signature Scheme Grounded in Fundamental Security Assumptions

In this paper, we unveil XMSS, a groundbreaking hash-based signature scheme designed to be both forward secure and highly practical, with its security foundation rooted in the essential assumptions of a pseudorandom function family and second preimage resistance. XMSS stands out by significantly minimizing signature sizes, achieving a reduction of over 75% in comparison to the most secure existing hash-based signature schemes. This advancement not only enhances efficiency but also reinforces security, making XMSS a compelling choice for applications requiring robust cryptographic mechanisms.

Alessandro Cimatti 1, Edmund Clarke2, Enrico Giunchiglia3, Fausto Giunchiglia 4, Marco Pistore1, Marco Roveri 1, Roberto Sebastiani 4, and Armando Tacchella 3 1 ITC-IRST, Via Sommarive 18, 38050 Trento, Italy fcimatti,pistore,roverig@irst.itc.it 2 Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh (PA), USA emc@cs.cmu.edu 3 DIST – Università di Genova, Viale Causa 13, 16145 Genova, Italy fenrico,tacg@mrg.dist.unige.it 4 Università di Trento, Via Sommarive 14, 38050 Trento, Italy ffausto,rsebag@science.unitn.it

We present a novel approach to fully homomorphic encryption (FHE) that dramatically improves performance and bases security on weaker assumptions. A central conceptual contribution in our work is a new way of constructing leveled, fully homomorphic encryption schemes (capable of evaluating arbitrary polynomial-size circuits of a-priori bounded depth), without Gentry’s bootstrapping procedure.
 Specifically, we offer a choice of FHE schemes based on the learning with error (LWE) or Ring LWE (RLWE) problems that have 2 λ security against known attacks. We construct the following.
 (1) A leveled FHE scheme that can evaluate depth-L arithmetic circuits (composed of fan-in 2 gates) using O(λ. L3) per-gate computation, quasilinear in the security parameter. Security is based on RLWE for an approximation factor exponential in L. This construction does not use the bootstrapping procedure.
 (2) A leveled FHE scheme that can evaluate depth-L arithmetic circuits (composed of fan-in 2 gates) using O(λ2) per-gate computation, which is independent of L. Security is based on RLWE for quasipolynomial factors. This construction uses bootstrapping as an optimization.
 We obtain similar results for LWE, but with worse performance. All previous (leveled) FHE schemes required a per-gate computation of Ω(λ3.5), and all of them relied on subexponential hardness assumptions.
 We introduce a number of further optimizations to our scheme based on the Ring LWE assumption. As an example, for circuits of large width (e.g., where a constant fraction of levels have width Ω(λ)), we can reduce the per-gate computation of the bootstrapped version to O(λ), independent of L, by batching the bootstrapping operation. At the core of our construction is a new approach for managing the noise in lattice-based ciphertexts, significantly extending the techniques of Brakerski and Vaikuntanathan [2011b].

We study the setting in which a user stores encrypted documents (e.g. e-mails) on an untrusted server. In order to retrieve documents satisfying a certain search criterion, the user gives the server a capability that allows the server to identify exactly those documents. Work in this area has largely focused on search criteria consisting of a single keyword. If the user is actually interested in documents containing each of several keywords (conjunctive keyword search) the user must either give the server capabilities for each of the keywords individually and rely on an intersection calculation (by either the server or the user) to determine the correct set of documents, or alternatively, the user may store additional information on the server to facilitate such searches. Neither solution is desirable; the former enables the server to learn which documents match each individual keyword of the conjunctive search and the latter results in exponential storage if the user allows for searches on every set of keywords. We define a security model for conjunctive keyword search over encrypted data and present the first schemes for conducting such searches securely. We propose first a scheme for which the communication cost is linear in the number of documents, but that cost can be incurred “offline” before the conjunctive query is asked. The security of this scheme relies on the Decisional Diffie-Hellman (DDH) assumption. We propose a second scheme whose communication cost is on the order of the number of keyword fields and whose security relies on a new hardness assumption.

Software based side-channel attacks allow an unprivileged spy process to extract secret information from a victim (cryptosystem) process by exploiting some indirect leakage of “side-channel” information. It has been realized that some components of modern computer microarchitectures leak certain side-channel information and can create unforeseen security risks. An example of such MicroArchitectural Side-Channel Analysis is the Cache Attack — a group of attacks that exploit information leaks from cache latencies [4, 7, 13, 15, 17]. Public awareness of Cache Attack vulnerabilities lead software writers of OpenSSL (version 0.9.8a and subsequent versions) to incorporate countermeasures for preventing these attacks. In this paper, we present a new and yet unforeseen side channel attack that is enabled by the recently published Simple Branch Prediction Analysis (SBPA) which is another type of MicroArchitectural Analysis, cf. [2, 3]. We show that modular inversion — a critical primitive in public key cryptography — is a natural target of SBPA attacks because it typically uses the Binary Extended Euclidean algorithm whose nature is an input-centric sequence of conditional branches. Our results show that SBPA can be used to extract secret parameters during the execution of the Binary Extended Euclidean algorithm. This poses a new potential risk to crypto-applications such as OpenSSL, which already employs Cache Attack countermeasures. Thus, it is necessary to develop new software mitigation techniques for BPA and incorporate them with cache analysis countermeasures in security applications. To mitigate this new risk in full generality, we apply a security-aware algorithm design methodology and propose some changes to the CRT-RSA algorithm flow. These changes either avoid some of the steps that require modular inversion, or remove the critical information leak from this procedure. In addition, we also show by example that, independently of the required changes in the algorithms, careful software analysis is also required in order to assure that the software implementation does not inadvertently introduce branches that may expose the application to SBPA attacks. These offer several simple ways for modifying OpenSSL in order to mitigate Branch Prediction Attacks.

Bitcoin is a decentralized payment system that relies on Proof-of-Work (PoW) to verify payments. Nowadays, Bitcoin is increasingly used in a number of fast payment scenarios, where the time between the exchange of currency and goods is short (in the order of few seconds). While the Bitcoin payment verification scheme is designed to prevent double-spending, our results show that the system requires tens of minutes to verify a transaction and is therefore inappropriate for fast payments. An example of this use of Bitcoin was recently reported in the media: Bitcoins were used as a form of \emph{fast} payment in a local fast-food restaurant. Until now, the security of fast Bitcoin payments has not been studied. In this paper, we analyze the security of using Bitcoin for fast payments. We show that, unless appropriate detection techniques are integrated in the current Bitcoin implementation, double-spending attacks on fast payments succeed with overwhelming probability and can be mounted at low cost. We further show that the measures recommended by Bitcoin developers for the use of Bitcoin in fast payments are not always effective in detecting double-spending; we show that if those recommendations are integrated in future Bitcoin implementations, double-spending attacks on Bitcoin will still be possible. Finally, we propose and implement a modification to the existing Bitcoin implementation that ensures the detection of double-spending attacks against fast payments.

This paper describes the first identity-based broadcast encryption scheme (IBBE) with constant size ciphertexts and private keys. In our scheme, the public key is of size linear in the maximal size m of the set of receivers, which is smaller than the number of possible users (identities) in the system. Compared with a recent broadcast encryption system introduced by Boneh, Gentry and Waters (BGW), our system has comparable properties, but with a better efficiency: the public key is shorter than in BGW. Moreover, the total number of possible users in the system does not have to be fixed in the setup.

Bitcoin, the arguably most popular cryptocurrency to date, allows users to perform transactions using freely chosen pseudonymous addresses. Previous research, however, suggests that these pseudonyms can easily be linked, implying a lower level of privacy than originally expected. To obfuscate the links between pseudonyms, different mixing methods have been proposed. One of the first approaches is the CoinJoin concept, where multiple users merge their transactions into one larger transaction. In theory, CoinJoin can be used to mix and transact bitcoins simultaneously, in one step. Yet, it is expected that differing bitcoin amounts would allow an attacker to derive the original single transactions. Solutions based on CoinJoin therefore prescribe the use of fixed bitcoin amounts and cannot be used to perform arbitrary transactions.In this paper, we define a model for CoinJoin transactions and metrics that allow conclusions about the provided anonymity. We generate and analyze CoinJoin transactions and show that with differing, representative amounts they generally do not provide any significant anonymity gains. As a solution to this problem, we present an output splitting approach that introduces sufficient ambiguity to effectively prevent linking in CoinJoin transactions. Furthermore, we discuss how this approach could be used in Bitcoin today.

We present SABER (Survivability Architecture: Block, Evade, React), a proposed survivability architecture that blocks, evades and reacts to a variety of attacks by using several security and survivability mechanisms in an automated and coordinated fashion. Contrary to the ad hoc manner in which contemporary survivable systems are built-using isolated, independent security mechanisms such as firewalls, intrusion detection systems and software sandboxes-SABER integrates several different technologies in an attempt to provide a unified framework for responding to the wide range of attacks malicious insiders and outsiders can launch.
 This coordinated multi-layer approach will be capable of defending against attacks targeted at various levels of the network stack, such as congestion-based DoS attacks, software-based DoS or code-injection attacks, and others. Our fundamental insight is that while multiple lines of defense are useful, most conventional, uncoordinated approaches fail to exploit the full range of available responses to incidents. By coordinating the response, the ability to survive successful security breaches increases substantially.
 We discuss the key components of SABER, how they will be integrated together, and how we can leverage on the promising results of the individual components to improve survivability in a variety of coordinated attack scenarios. SABER is currently in the prototyping stages, with several interesting open research topics.

Existing strong controlled physical unclonable function (PUF) designs are built to resist modeling attacks and they deal with noisy PUF responses by exploiting error correction logic. These designs are burdened by the costs of the error correction logic and information shown to leak through the associated helper data for assisting error corrections; leaving the design vulnerable to fault attacks or reliability-based attacks. We present a hybrid PUF–finite state machine (PUF-FSM) construction to realize a controlled strong PUF. The PUF-FSM design removes the need for error correction logic and related computation, storage of the helper data and loading it on-chip by only employing error-free responses judiciously determined on demand in the absence of the underlying PUF—an Arbiter PUF—with a large challenge response pair space. The PUF-FSM demonstrates improved security, especially to reliability-based attacks and is able to support a range of applications from authentication to more advanced cryptographic applications built upon shared keys. We experimentally validate the practicability of the PUF-FSM.

The stream cipher ChaCha20 and the MAC function Poly1305 have been published as IETF RFC 7539. Since then, the industry is starting to use it more often. For example, it has been implemented by Google in their Chrome browser for TLS and also support has been added to OpenSSL, as well as OpenSSH. It is often claimed, that the algorithms are designed to be resistant to side-channel attacks. However, this is only true, if the only observable side-channel is the timing behavior. In this paper, we show that ChaCha20 is susceptible to power and EM side-channel analysis, which also translates to an attack on Poly1305, if used together with ChaCha20 for key generation. As a first countermeasure, we analyze the effectiveness of randomly shuffling the operations of the ChaCha round function.