Question: A Bit from Here, A Bit from There: Cross-Project Code Utilization on GitHub

This study delves into the impact of gender and tenure diversity on the dynamics of teams within the Open Source Software (OSS) community, specifically on GitHub, the largest public OSS repository. Software development, especially in the OSS realm, thrives on collaboration, often involving teams that are geographically dispersed, fluid in composition, and open in nature, more so than their commercial counterparts. This openness fosters a level of diversity within OSS teams, which we explore in this paper. Previous studies have linked diversity, particularly in non-digital, offline environments, to team outcomes, typically with positive implications. However, the question remains: how does diversity manifest and affect OSS teams? Drawing on a vast dataset from GitHub, complemented by survey responses, we analyzed the relationship between gender and tenure diversity and two critical team outcomes: productivity and turnover. Through regression modeling, we discovered that both gender and tenure diversity are positively and significantly associated with productivity. These factors, combined, explain a significant portion of the variability in productivity observed across OSS teams on GitHub. Our findings offer valuable insights for decision-makers at all levels, potentially enhancing recruitment strategies and improving team performance in the OSS ecosystem.

This article proposes in depth comparative study of the most popular, used and analyzed Trust and Reputation System (TRS) according to the trust and reputation literature and in terms of specific trustworthiness criteria. This survey is realized relying on a selection of trustworthiness criteria that analyze and evaluate the maturity and effectiveness of TRS. These criteria describe the utility, the usability, the performance and the effectiveness of the TRS. We also provide a summary table of the compared TRS within a detailed and granular selection of trust and reputation aspects.

Understanding the behavior of source code written in an unfamiliar programming language is difficult. One way to aid understanding of difficult code is to add corresponding pseudo-code, which describes in detail the workings of the code in a natural language such as English. In spite of its usefulness, most source code does not have corresponding pseudo-code because it is tedious to create. This paper demonstrates a tool Pseudogen that makes it possible to automatically generate pseudo-code from source code using statistical machine translation (SMT). Pseudogen currently supports generation of English or Japanese pseudo-code from Python source code, and the SMT framework makes it easy for users to create new generators for their preferred source code/pseudo-code pairs.

We explore contextual and dispositional correlates of the motivation to contribute to open source initiatives. We examine how the context of the open source project, and the personal values of contributors, are related to the types of motivations for contributing. A web-based survey was administered to 300 contributors in two prominent open source contexts: software and content. As hypothesized, software contributors placed a greater emphasis on reputation-gaining and self-development motivations, compared with content contributors, who placed a greater emphasis on altruistic motives. Furthermore, the hypothesized relationships were found between contributors’ personal values and their motivations for contributing. 2007 Elsevier Ltd. All rights reserved.

This paper proposes a new approach called DREX (Developer Recommendation with k-nearest-neighbor search and Expertise ranking) to developer recommendation for bug resolution based on K-Nearest-Neighbor search with bug similarity and expertise ranking with various metrics, including simple frequency and social network metrics. We collect Mozilla Fire fox open bug repository as the experimental data set and compare different ranking metrics on the performance of recommending capable developers for bugs. Our experimental results demonstrate that, when recommending 10 developers for each one of the 250 testing bugs, DREX has produced better performance than traditional methods with multi-labeled text categorization. The best performance obtained by two metrics as Out-Degree and Frequency, is with recall as 0.6 on average. Moreover, other social network metrics such as Degree and Page Rank have produced comparable performance on developer recommendation as Frequency when used for developer expertise ranking.

Vulnerability prediction models (VPM) are believed to hold promise for providing software engineers guidance on where to prioritize precious verification resources to search for vulnerabilities. However, while Microsoft product teams have adopted defect prediction models, they have not adopted vulnerability prediction models (VPMs). The goal of this research is to measure whether vulnerability prediction models built using standard recommendations perform well enough to provide actionable results for engineering resource allocation. We define 'actionable' in terms of the inspection effort required to evaluate model results. We replicated a VPM for two releases of the Windows Operating System, varying model granularity and statistical learners. We reproduced binary-level prediction precision (~0.75) and recall (~0.2). However, binaries often exceed 1 million lines of code, too large to practically inspect, and engineers expressed preference for source file level predictions. Our source file level models yield precision below 0.5 and recall below 0.2. We suggest that VPMs must be refined to achieve actionable performance, possibly through security-specific metrics.

We have developed an efficient way to determine the syntactic similarity of files and have applied it to every document on the World Wide Web. Using this mechanism, we built a clustering of all the documents that are syntactically similar. Possible applications include a “Lost and Found” service, filtering the results of Web searches, updating widely distributed web-pages, and identifying violations of intellectual property rights.

ÐThis paper is an attempt to understand the processes by which software ages. We define code to be aged or decayed if its structure makes it unnecessarily difficult to understand or change and we measure the extent of decay by counting the number of faults in code in a period of time. Using change management data from a very large, long-lived software system, we explore the extent to which measurements from the change history are successful in predicting the distribution over modules of these incidences of faults. In general, process measures based on the change history are more useful in predicting fault rates than product metrics of the code: For instance, the number of times code has been changed is a better indication of how many faults it will contain than is its length. We also compare the fault rates of code of various ages, finding that if a module is, on the average, a year older than an otherwise similar module, the older module will have roughly a third fewer faults. Our most successful model measures the fault potential of a module as the sum of contributions from all of the times the module has been changed, with large, recent changes receiving the most weight. Index TermsÐFault potential, code decay, change management data, metrics, statistical analysis, generalized linear models.

Open-source software, usually created by volunteer programmers dispersed worldwide, now competes with that developed by software firms. This achievement is particularly impressive as open-source programmers rarely meet. They rely heavily on electronic media, which preclude the benefits of face-to-face contact that programmers enjoy within firms. In this paper, we describe findings that address this paradox based on observation, interviews and quantitative analyses of two open-source projects. The findings suggest that spontaneous work coordinated afterward is effective, rational organizational culture helps achieve agreement among members and communications media moderately support spontaneous work. These findings can imply a new model of dispersed collaboration.

Context. Software testing is the process of finding faults in software while executing it. The results of the testing are used to find and correct faults. Software defect prediction estimates where faults are likely to occur in source code. The results from the defect prediction can be used to optimize testing and ultimately improve software quality. Machine learning, that concerns computer programs learning from data, is used to build prediction models which then can be used to classify data. Objectives. In this study we, in collaboration with Ericsson, investigated whether software metrics from source code files combined with metrics from their respective tests predicts faults with better prediction performance compared to using only metrics from the source code files. Methods. A literature review was conducted to identify inputs for an experiment. The experiment was applied on one repository from Ericsson to identify the best performing set of metrics. Results. The prediction performance results of three metric sets are presented and compared with each other. Wilcoxon’s signed rank tests are performed on four different performance measures for each metric set and each machine learning algorithm to demonstrate significant differences of the results. Conclusions. We conclude that metrics from tests can be used to predict faults. However, the combination of source code metrics and test metrics do not outperform using only source code metrics. Moreover, we conclude that models built with metrics from the test metric set with minimal information of the source code can in fact predict faults in the source code.

It is difficult to develop style-preserving source-to-source transformation engines for C and C++. The main reason is not the complexity of those languages, but the use of the C pre-processor (cpp), especially ifdefs and macros. This has for example hindered the development of refactoring tools for C and C++. In this paper we propose to combine multiple techniques and heuristics to parse C/C++ source files as-is, while still having only a few modifications to the original grammars of C and C++. We rely on the fact that in most C and C++ software, programmers follow a limited number of conventions on the use of cpp which makes it possible to disambiguate different situations by just looking at the context, names, or indentation of cpp constructs. We have implemented a parser, Yacfe, based on these techniques and evaluated it on 16 large open source projects. Yacfe can on average parse 96% of those projects correctly. As a side effect, we also found mistakes in code that was not compiled because it was protected by particular ifdefs, but that was still analyzed by Yacfe. Using Yacfe on new projects may require adapting some of our techniques. We found that as conventions and idioms are shared by many projects, the adaptation time is on average less than 2 hours for a new project.


Question: A bit from here, a bit from there: Cross-project code reuse in GitHub repositories.

Introducing CCFinderX: An Advanced Multilingual Code Clone Detection System for Large-Scale Source Code Repositories

A code clone refers to a segment of code that is either identical or substantially similar to another within source files. Given that code clones are often associated with reduced software maintainability, a plethora of techniques and tools for code clone detection have been devised. This paper presents a novel clone detection approach, characterized by the transformation of input source text and a meticulous token-by-token comparison. To implement this approach, complemented by various optimization techniques, we have developed CCFinderX, a sophisticated tool designed to identify code clones in a wide array of programming languages, including but not limited to C, C++, Java, COBOL, and numerous others.

In addition, a set of metrics for quantifying the characteristics of code clones has been formulated. To assess the effectiveness of CCFinderX and its associated metrics, we conducted a series of case studies applying the tool to the source code of prominent systems such as JDK, FreeBSD, NetBSD, Linux, and a multitude of other software projects. The outcomes revealed that CCFinderX not only efficiently detected code clones but also that the developed metrics effectively captured the distinctive features of these systems. Moreover, we conducted a comparative analysis against existing clone detection techniques, further highlighting the superior performance of our proposed method.

Index Terms: Code clone, duplicate code, CASE tool, metrics, software maintenance.

The extraction of a code fragment into a separate method is one of the most widely performed refactoring activities, since it allows the decomposition of large and complex methods and can be used in combination with other code transformations for fixing a variety of design problems. Despite the significance of Extract Method refactoring towards code quality improvement, there is limited support for the identification of code fragments with distinct functionality that could be extracted into new methods. The goal of our approach is to automatically identify Extract Method refactoring opportunities which are related with the complete computation of a given variable (complete computation slice) and the statements affecting the state of a given object (object state slice). Moreover, a set of rules regarding the preservation of existing odule decomposition dependences is proposed that exclude refactoring opportunities corresponding to slices whose extraction could possibly cause a change in program behavior. The proposed approach has been evaluated regarding its ability to capture slices of code implementing a distinct functionality, its ability to resolve existing design flaws, its impact on the cohesion of the decomposed and extracted methods, and its ability to preserve program behavior. Moreover, precision and recall have been computed employing the refactoring depe opportunities found by in

Open-source software, usually created by volunteer programmers dispersed worldwide, now competes with that developed by software firms. This achievement is particularly impressive as open-source programmers rarely meet. They rely heavily on electronic media, which preclude the benefits of face-to-face contact that programmers enjoy within firms. In this paper, we describe findings that address this paradox based on observation, interviews and quantitative analyses of two open-source projects. The findings suggest that spontaneous work coordinated afterward is effective, rational organizational culture helps achieve agreement among members and communications media moderately support spontaneous work. These findings can imply a new model of dispersed collaboration.

Two important questions concerning the coordination of development effort are which bugs to fix first and how long it takes to fix them. In this paper we investigate empirically the relationships between bug report attributes and the time to fix. The objective is to compute prediction models that can be used to recommend whether a new bug should and will be fixed fast or will take more time for resolution. We examine in detail if attributes of a bug report can be used to build such a recommender system. We use decision tree analysis to compute and 10-fold cross validation to test prediction models. We explore prediction models in a series of empirical studies with bug report data of six systems of the three open source projects Eclipse, Mozilla, and Gnome. Results show that our models perform significantly better than random classification. For example, fast fixed Eclipse Platform bugs were classified correctly with a precision of 0.654 and a recall of 0.692. We also show that the inclusion of postsubmission bug report data of up to one month can further improve prediction models.

Surveying a suite of algorithms that offer a solution to managing large document archives.

We present a technique for automatically generating features for data-driven program analyses. Recently data-driven approaches for building a program analysis have been developed, which mine existing codebases and automatically learn heuristics for finding a cost-effective abstraction for a given analysis task. Such approaches reduce the burden of the analysis designers, but they do not remove it completely; they still leave the nontrivial task of designing so called features to the hands of the designers. Our technique aims at automating this feature design process. The idea is to use programs as features after reducing and abstracting them. Our technique goes through selected program-query pairs in codebases, and it reduces and abstracts the program in each pair to a few lines of code, while ensuring that the analysis behaves similarly for the original and the new programs with respect to the query. Each reduced program serves as a boolean feature for program-query pairs. This feature evaluates to true for a given program-query pair when (as a program) it is included in the program part of the pair. We have implemented our approach for three real-world static analyses. The experimental results show that these analyses with automatically-generated features are cost-effective and consistently perform well on a wide range of programs.

With the thriving of the mobile app markets, third-party libraries are pervasively integrated in the Android applications. Third-party libraries provide functionality such as advertisements, location services, and social networking services, making multi-functional app development much more productive. However, the spread of vulnerable or harmful third-party libraries may also hurt the entire mobile ecosystem, leading to various security problems. The Android platform suffers severely from such problems due to the way its ecosystem is constructed and maintained. Therefore, third-party Android library identification has emerged as an important problem which is the basis of many security applications such as repackaging detection and malware analysis. According to our investigation, existing work on Android library detection still requires improvement in many aspects, including accuracy and obfuscation resilience. In response to these limitations, we propose a novel approach to identifying third-party Android libraries. Our method utilizes the internal code dependencies of an Android app to detect and classify library candidates. Different from most previous methods which classify detected library candidates based on similarity comparison, our method is based on feature hashing and can better handle code whose package and method names are obfuscated. Based on this approach, we have developed a prototypical tool called LibD and evaluated it with an update-to-date and large-scale dataset. Our experimental results on 1,427,395 apps show that compared to existing tools, LibD can better handle multi-package third-party libraries in the presence of name-based obfuscation, leading to significantly improved precision without the loss of scalability.

How can designers of programming interfaces, interactive tools, and rich social environments enable more people to be more creative more often?

Software engineering is a knowledge-intensive activity that presents many information navigation challenges. Information spaces in software engineering include the source code and change history of the software, discussion lists and forums, issue databases, component technologies and their learning resources, and the development environment. The technical nature, size, and dynamicity of these information spaces motivate the development of a special class of applications to support developers: recommendation systems in software engineering (RSSEs), which are software applications that provide information items estimated to be valuable for a software engineering task in a given context. In this introduction, we review the characteristics of information spaces in software engineering, describe the unique aspects of RSSEs, present an overview of the issues and considerations involved in creating, evaluating, and using RSSEs, and present a general outlook on the current state of research and development in the field of recommendation systems for highly technical domains.

Bug repository systems have become an integral component of software development activities. Ideally, each bug report should help developers to find and fix a software fault. However, there is a subset of reported bugs that is not (easily) reproducible, on which developers spend considerable amounts of time and effort. We present an empirical analysis of non-reproducible bug reports to characterize their rate, nature, and root causes. We mine one industrial and five open-source bug repositories, resulting in 32K non-reproducible bug reports. We (1) compare properties of non-reproducible reports with their counterparts such as active time and number of authors, (2) investigate their life-cycle patterns, and (3) examine 120 Fixed non-reproducible reports. In addition, we qualitatively classify a set of randomly selected non-reproducible bug reports (1,643) into six common categories. Our results show that, on average, non-reproducible bug reports pertain to 17% of all bug reports, remain active three months longer than their counterparts, can be mainly (45%) classified as "Interbug Dependencies'', and 66% of Fixed non-reproducible reports were indeed reproduced and fixed.

Program authorship attribution—identifying a programmer based on stylistic characteristics of code—has practical implications for detecting software theft, digital forensics, and malware analysis. Authorship attribution is challenging in these domains where usually only binary code is available; existing source code-based approaches to attribution have left unclear whether and to what extent programmer style survives the compilation process. Casting authorship attribution as a machine learning problem, we present a novel program representation and techniques that automatically detect the stylistic features of binary code. We apply these techniques to two attribution problems: identifying the precise author of a program, and finding stylistic similarities between programs by unknown authors. Our experiments provide strong evidence that programmer style is preserved in program binaries.


Question: A Bit from Here, A Bit from There: Cross-Project Code Reuse on GitHub

In recent years, a plethora of methodologies and software tools for identifying code clones in software development have emerged. This paper offers a comprehensive qualitative comparison and assessment of the cutting-edge techniques and tools for code clone detection, consolidating extensive information into a structured conceptual framework. The paper initiates with foundational concepts, delineates a generic process for clone detection, and presents an overarching taxonomy of contemporary techniques and tools. The classification, comparison, and evaluation of these tools and techniques are undertaken from two distinct perspectives. Firstly, approaches are categorized and contrasted based on various facets, each encompassing a set of potentially overlapping attributes. Secondly, a qualitative evaluation is conducted on the classified techniques and tools, utilizing a taxonomy of editing scenarios crafted to emulate the creation of Type-1, Type-2, Type-3, and Type-4 clones. Additionally, illustrative examples are provided to guide the selection of the most suitable clone detection tool or technique, given a specific set of objectives and constraints. The primary deliverables of this study include: (1) a framework for categorizing clone detection techniques and tools, coupled with a classification of current clone detectors based on this schema, and (2) a taxonomy of editing scenarios leading to various clone types, alongside a qualitative evaluation of current clone detectors grounded in this taxonomy.

Two important questions concerning the coordination of development effort are which bugs to fix first and how long it takes to fix them. In this paper we investigate empirically the relationships between bug report attributes and the time to fix. The objective is to compute prediction models that can be used to recommend whether a new bug should and will be fixed fast or will take more time for resolution. We examine in detail if attributes of a bug report can be used to build such a recommender system. We use decision tree analysis to compute and 10-fold cross validation to test prediction models. We explore prediction models in a series of empirical studies with bug report data of six systems of the three open source projects Eclipse, Mozilla, and Gnome. Results show that our models perform significantly better than random classification. For example, fast fixed Eclipse Platform bugs were classified correctly with a precision of 0.654 and a recall of 0.692. We also show that the inclusion of postsubmission bug report data of up to one month can further improve prediction models.

Editor: Peter Anderson Rochester Institute of Technology 1 Lomb Memorial Dr. Rochester, NY 14623 pga@cs.rit.edu Each technique receives similar coverage, including a description of its new and prerequisite vocabulary, its model, the bug assumptlons that underlie its effectiveness, typical applications, examples (almost all based on standard IRS tax forms), caveats and limitations, automation and tools for the technique, a self-evaluation quiz, and exercises. Common threads in the presentation show the role

The traditional modular structure defined by the package hierarchy suffers from the dominant decomposition problem and it is widely accepted that alternative forms of modularization are necessary to increase developer’s productivity. In this paper, we propose an alternative form to understand and assess package modularity based on co-change clusters, which are highly inter-related classes considering cochange relations. We evaluate how co-change clusters relate to the package decomposition of four real-world systems. The results show that the projection of co-change clusters to packages follows different patterns in each system. Therefore, we claim that modular views based on co-change clusters can improve developers’ understanding on how well-modularized are their systems, considering that modularity is the ability to confine changes and evolve components in parallel.

The use of object-oriented design patterns in game development is being evaluated in this paper. Games’ quick evolution, demands great flexibility, code reusability and low maintenance costs. Games usually differentiate between versions, in respect of changes of the same type (additional animation, terrains etc). Consequently, the application of design patterns in them can be beneficial regarding maintainability. In order to investigate the benefits of using design patterns, a qualitative and a quantitative evaluation of open source projects is being performed. For the quantitative evaluation, the projects are being analyzed by reverse engineering techniques and software metrics are calculated. 2006 Elsevier B.V. All rights reserved.

Descriptive names are a vital part of readable, and hence maintainable, code. Recent progress on automatically suggesting names for local variables tantalizes with the prospect of replicating that success with method and class names. However, suggesting names for methods and classes is much more difficult. This is because good method and class names need to be functionally descriptive, but suggesting such names requires that the model goes beyond local context. We introduce a neural probabilistic language model for source code that is specifically designed for the method naming problem. Our model learns which names are semantically similar by assigning them to locations, called embeddings, in a high-dimensional continuous space, in such a way that names with similar embeddings tend to be used in similar contexts. These embeddings seem to contain semantic information about tokens, even though they are learned only from statistical co-occurrences of tokens. Furthermore, we introduce a variant of our model that is, to our knowledge, the first that can propose neologisms, names that have not appeared in the training corpus. We obtain state of the art results on the method, class, and even the simpler variable naming tasks. More broadly, the continuous embeddings that are learned by our model have the potential for wide application within software engineering.

In the context of open source development or software evolution, developers often face test suites which have been developed with no apparent rationale and which may need to be augmented or refined to ensure sufficient dependability, or even reduced to meet tight deadlines. We refer to this process as the re-engineering of test suites. It is important to provide both methodological and tool support to help people understand the limitations of test suites and their possible redundancies, so as to be able to refine them in a cost effective manner. To address this problem in the case of black-box testing, we propose a methodology based on machine learning that has shown promising results on a case study.

Alessandro Cimatti 1, Edmund Clarke2, Enrico Giunchiglia3, Fausto Giunchiglia 4, Marco Pistore1, Marco Roveri 1, Roberto Sebastiani 4, and Armando Tacchella 3 1 ITC-IRST, Via Sommarive 18, 38050 Trento, Italy fcimatti,pistore,roverig@irst.itc.it 2 Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh (PA), USA emc@cs.cmu.edu 3 DIST – Università di Genova, Viale Causa 13, 16145 Genova, Italy fenrico,tacg@mrg.dist.unige.it 4 Università di Trento, Via Sommarive 14, 38050 Trento, Italy ffausto,rsebag@science.unitn.it

ÐThis paper is an attempt to understand the processes by which software ages. We define code to be aged or decayed if its structure makes it unnecessarily difficult to understand or change and we measure the extent of decay by counting the number of faults in code in a period of time. Using change management data from a very large, long-lived software system, we explore the extent to which measurements from the change history are successful in predicting the distribution over modules of these incidences of faults. In general, process measures based on the change history are more useful in predicting fault rates than product metrics of the code: For instance, the number of times code has been changed is a better indication of how many faults it will contain than is its length. We also compare the fault rates of code of various ages, finding that if a module is, on the average, a year older than an otherwise similar module, the older module will have roughly a third fewer faults. Our most successful model measures the fault potential of a module as the sum of contributions from all of the times the module has been changed, with large, recent changes receiving the most weight. Index TermsÐFault potential, code decay, change management data, metrics, statistical analysis, generalized linear models.

The concept of cryptocurrencies is built from forgotten ideas in research literature.

0950-5849/$ see front matter 2010 Elsevier B.V. A doi:10.1016/j.infsof.2010.12.001 ⇑ Address: School of Computing, Blekinge Institute 372 25, Sweden. E-mail addresses: kai.petersen@bth.se, kai.petersen URLs: http://www.bth.se/besq, http://www.ericsso Context: Software productivity measurement is essential in order to control and improve the performance of software development. For example, by identifying role models (e.g. projects, individuals, tasks) when comparing productivity data. The prediction is of relevance to determine whether corrective actions are needed, and to discover which alternative improvement action would yield the best results. Objective: In this study we identify studies for software productivity prediction and measurement. Based on the identified studies we first create a classification scheme and map the studies into the scheme (systematic map). Thereafter, a detailed analysis and synthesis of the studies is conducted. Method: As a research method for systematically identifying and aggregating the evidence of productivity measurement and prediction approaches systematic mapping and systematic review have been used. Results: In total 38 studies have been identified, resulting in a classification scheme for empirical research on software productivity. The mapping allowed to identify the rigor of the evidence with respect to the different productivity approaches. In the detailed analysis the results were tabulated and synthesized to provide recommendations to practitioners. Conclusion: Risks with simple ratio-based measurement approaches were shown. In response to the problems data envelopment analysis seems to be a strong approach to capture multivariate productivity measures, and allows to identify reference projects to which inefficient projects should be compared. Regarding simulation no general prediction model can be identified. Simulation and statistical process control are promising methods for software productivity prediction. Overall, further evidence is needed to make stronger claims and recommendations. In particular, the discussion of validity threats should become standard, and models need to be compared with each other. 2010 Elsevier B.V. All rights reserved.


Question: A 65 nm CMOS 4-element sub-34 mW/element 60 GHz phased-array transceiver design.

This paper presents the design and implementation of a 16-element phased-array transmitter for Q-band applications, specifically within the 40-45 GHz frequency range, utilizing 0.18-mum SiGe BiCMOS technology. The phased-array system is based on 4-bit RF phase shifters, achieving a consistent power gain of 12.5plusmn1.5 dB per channel at 42.5 GHz across all phase states. The 3-dB gain bandwidth spans from 40 to 45.6 GHz, with an input and output return loss of less than -10 dB in the 37.5-50 GHz range. The transmitter exhibits less than 8.8deg RMS phase error and less than 1.2 dB RMS gain error across all phase states at frequencies between 30 and 50 GHz. At 42.5 GHz, the maximum saturated output power per channel is -2.5plusmn1.5 dBm. The RMS gain variation and RMS phase mismatch across all 16 channels are less than 0.5 dB and less than 4.5deg, respectively. The chip operates on a 5 V supply voltage, consuming 720 mA, and has an overall size of 2.6times3.2 mm2. To the best of our knowledge, this is the first reported 16-element phased array implemented on a silicon chip using RF phase shifting architecture at these frequencies.

Question: A 65 nm CMOS 4-Element Sub-34 mW/Element 60 GHz Phased-Array Transceiver

Document: A 60 GHz 4-Element Phased-Array Transceiver in 65 nm CMOS with Low Power Consumption per Element

A 60 GHz 4-element phased-array transceiver has been developed using 65 nm CMOS technology, focusing on minimizing power consumption per element. The transceiver is designed to operate in the 60 GHz frequency band, a range increasingly popular for high-speed wireless communication systems. Each element of the phased-array consumes less than 34 mW, making it highly energy-efficient. The system architecture integrates transmit and receive paths, along with digital control logic for phase shifting and gain adjustment. The phased-array transceiver demonstrates a wide 3-dB gain bandwidth, ensuring stable operation across the 60 GHz band. Moreover, it achieves low phase error and gain variation, critical

A code-domain N-path RX is proposed based on PN-code modulated LO pulses for concurrent reception of two code-modulated signals. Additionally, a combination of Walsh-Function and PN sequence is proposed to translate in-band TX self-interference (SI) to out-of-band at N-path RX output enabling frequency filtering for high SI rejection. A 0.3 GHz–1.4 GHz 65-nm CMOS implementation has 35 dB gain for desired signals and concurrently receives two RX signals while rejecting mismatched spreading codes at RF input. Proposed TX SI mitigation approach results in 38.5 dB rejection for −11.8dBm 1.46 Mb/s QPSK modulated SI at RX input. The RX achieves 23.7dBm OP1dB for in-band SI, while consuming ∼35mW and occupies 0.31mm2.

This work proposes a broadband microstrip patch antenna array with H-shaped aperture-coupled stacked rectangular patches is implemented to low-cost and low-loss organic substrate for flip chip chip scale (FCCSP) package for millimeter-wave antenna in package (AiP) application. The proposed antenna array is built on a low-cost and low-loss multilayer organic substrate for flip chip chip scale (FCCSP) package. The return loss of < −10 dB bandwidth of the proposed antenna array is from 55 to 69 GHz, which covers the requirement of IEEE 802.11ad standard. The cross-polarization levels in both and planes are better than 30 dB. The front-to-back ratio of the antenna radiation pattern is better than 20 dB. The prospoed microstrip patch antenna can achieve a wide bandwidth, low cross-polarization levels, low backward radiation levels, and easy integration with radio frequency (RF) circuits. This work provides a cost-effective approach for fifth-generation mobile communications (5G), IEEE 802.11ad, such as smart phone, laptops, and wireless router.

In this paper microstrip antenna for 60 GHz on LTCC is presented. Special techniques are used to satisfy the antenna specification in wide bandwidth (7 GHz, from 57 GHz to 64 GHz) and high gain (15 dBi). An increase in bandwidth is achieved by using aperture the coupling and the multilayer structure. Gain is increased by using parasitic patches which increase the total antenna aperture. In paper was presented 60 GHz parasitic microstrip antenna with two layers of parasitic patches. High gain is obtained as the result of the optimization. However, presented return loss results can not be treated as wide bandwidth.

An 8-Gb/s 0.3-µm CMOS transceiver uses multilevel signaling (4-PAM) and transmit pre-shaping in combination with receive equalization to reduce ISI due to channel low-pass effects. High on-chip frequencies are avoided by multi-plexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear PLL with a loop bandwidth >30MHz, phase margin >48 and capture range of 20MHz without a frequency acquisition aid. The transmitted 8-Gbps data is successfully detected by the receiver after a 10-m coaxial cable. The 2mm x 2mm chip consumes 1.1W at 8Gbps with a 3-V supply.

In this paper, we present a methodology to enhance the operating range of a Miller frequency divider. Conventionally Miller frequency dividers are visualized as mixers. We present how injection locking portrait of Miller dividers helps us to understand the dynamics of Miller frequency dividers. Further, we discuss how to enhance the operating range while optimizing the divider between power dissipation and operating range. The Miller divider with the proposed methodology has been designed in a standard CMOS 65 nm (low leakage) process. Post layout simulation results show that Miller divider with optimization techniques presented in this paper can operate over the frequency range of 13 GHz for 0dBm input power at center frequency of 61.5 GHz.

An SPDT switch consisting of both nMOS and pMOS transistors is presented. Compared with conventional SPDT switches using only nMOS transistors under the same bias condition, the proposed switch exhibits better power-handling capability (PHC). The mechanism for the PHC improvement is explained. A prototype is implemented using a 0.18-um CMOS process. Measurement results show that, at 2.4 GHz, the insertion loss is 0.62 dB when the nMOS transistors are on and 0.91 dB when the pMOS transistors are on. For both modes, the measured return loss and isolation are better than 10 dB and 19 dB, respectively, up to 6 GHz. Under 1.8-V operation, the switch is able to handle a 26.1-dBm input power when the nMOS transistors are on and a 24.0-dBm input power when the pMOS transistors are on.

A 2 × 2 (four-element) multiple-input multiple-output (MIMO) patch antenna system is designed and fabricated for a 2.45-GHz ISM band operation. It uses complementary split-ring resonator (CSRR) loading on its ground plane for antenna miniaturization. This reduces the single-element antenna size by 76%. The total board size of the proposed MIMO antenna system, including the GND plane is 100 × 50 × 0.8 mm3, while the single-patch antenna element has a size of 14 × 18 mm2. The antenna is fabricated and tested. Measured results are in good agreement with simulations. A minimum measured isolation of 10 dB is obtained given the close interelement spacing of 0.17λ. The maximum measured gain for a single operating element is -0.8 dBi.

Phased array technology has been evolving steadily with advances in solid-state microwave integrated circuits, analysis and design tools, and reliable fabrication practices. With significant government investments, the technologies have matured to a point where phased arrays are widely used in military systems. Next-generation phased arrays will employ high levels of digitization, which enables a wide range of improvements in capability and performance. Digital arrays leverage the rapid commercial evolution of digital processor technology. The cost of phased arrays can be minimized by utilizing high-volume commercial microwave manufacturing and packaging techniques. Dramatic cost reductions are achieved by employing a tile array architecture, which greatly reduces the number of printed circuit boards and connectors in the array.

A new generation of high-frequency integrated circuits is presented, which is called substrate integrated circuits (SICs). Current state-of-the-art of circuit design and implementation platforms based on this new concept are reviewed and discussed in detail. Different possibilities and numerous advantages of the SICs are shown for microwave, millimeter-wave and optoelectronics applications. Practical examples are illustrated with theoretical and experimental results for substrate integrated waveguide (SIW), substrate integrated slab waveguide (SISW) and substrate integrated nonradiating dielectric (SINRD) guide circuits. Future research and development trends are also discussed with reference to low-cost innovative design of millimeter-wave and optoelectronic integrated circuits.

Millimeter-wave technology brings a new paradigm of wireless communication in various areas including mobile devices, automotive, IoT (Internet of Things), medical, military and many others. In this paper, we present our recently developed antenna in a package and system for 5G (Fifth-Generation) millimeter-wave applications. The antenna is configured to be an array to compensate path loss and maintain data link budget. The antenna is designed with a multi-layer laminate substrate and is integrated with a 5G mmW RFIC. 5G NR (New Radio) wireless connection is demonstrated with a RFIC transceiver at 28 GHz band. Interoperability test is conducted to ensure compatibility with the 3GPP standard. Finally, indoor and outdoor field test including beamforming and beamtracking are presented to show realistic system-level throughput performance.


Question: A 65 nm CMOS 4-element sub-34 mW per element 60 GHz phased-array transceiver implementation.

This paper explores the Distributed Active Transformer (DAT) structure as a novel technique for power combining and impedance transformation, contrasting its performance with conventional on-chip methods. The inherent power-efficiency constraints faced in the development of high-power fully integrated amplifiers using standard silicon process technologies are thoroughly examined. The DAT emerges as an efficient solution for impedance transformation and power combining, adeptly merging multiple low-voltage push-pull amplifiers through magnetic coupling. To substantiate the efficacy of this innovative approach, a 2.4-GHz fully integrated power amplifier has been realized using 0.35-μm CMOS transistors, achieving a remarkable 1.9 W output power, a power-added efficiency of 41%, and 50 Ω input and output matching, all while operating at a low 2 V supply voltage. The amplifier's performance underscores the DAT's potential in overcoming power-efficiency limitations in high-power amplifier designs. This research was made possible through the generous support of Intel Corporation, the Army Research Office, the Jet Propulsion Laboratory, Infinion, and the National Science Foundation, with additional assistance from Conexant Systems for chip fabrication and technical support from Agilent Technologies and Sonnet Software Inc. for CAD tools. The "Special Issue on Silicon-Based RF and Microwave Integrated Circuits" in the IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 1, part 2, provides a detailed account of this work.

Massive multiple input and multiple output (MIMO) has attracted significant interests in both academia and industry. It has been considered as one of most promising technologies for 5G wireless systems. The large-scale antenna array for base stations naturally becomes the key to deploy the Massive MIMO technologies. In this communication, we present a dual-polarized antenna array with 144 ports for Massive MIMO operating at 3.7 GHz. The proposed array consists of 18 low profile subarrays. Each subarray consists of four single units. Each single antenna unit consists of one vertically polarized port and one horizontally polarized port connected to power splitters, which serve as a feeding network. A stacked patch design is used to construct the single unit with the feeding network, which gives higher gain and lower mutual coupling within the size of a conversional dual-port patch antenna. Simulation results of the proposed single antenna unit, sub-array, and Massive MIMO array are verified by measurement.

Nowadays emerging industrial radar applications demand for high-resolution, high-precision and at the same time low-cost radar sensors. Recent advances in semiconductor technology allow highly integrated radar sensors at frequencies up to several hundred GHz in mass-production suitable and cost-effective SiGe bipolar technologies. In this contribution, a SiGe MMIC-based 240 GHz radar sensor with more than 60GHz bandwidth is presented. It consists of a MMIC chip including the high-frequency components and a digital control module with the PLL stabilisation, ramp generation, and data acquisition. The antenna is realized by on-chip patch antennas, which are focused by using an additional dielectric lens. The radar allows fast and highly linear frequency sweeps from 204 GHz to 265 GHz with an maximum output power of ≈ -1dBm EIRP (patch only). A phase noise of <;-65 dBc/Hz (>1 kHz offset) is achieved over the complete tuning range. Additionally range profile, jitter and imaging measurements are presented to demonstrate the achieved system performance.

In this paper, modified circuit topologies of a differential voltage-controlled oscillator (VCO) and a quadrature VCO (QVCO) in a standard bulk 90-nm CMOS process are presented for low dc power and low phase-noise applications. By utilizing current-reuse and transformer-feedback techniques, the proposed VCO and QVCO can be operated at reduced dc power consumption while maintaining extraordinary circuit performance in terms of low phase-noise and low amplitude/phase errors. The VCO circuit topology is investigated to obtain the design procedure. The VCO is further applied to the QVCO design with a bottom-series coupling technique. The coupling network between two differential VCOs and device size are properly designed based on our proposed design methodology to achieve low amplitude and phase errors. Moreover, the VCO and the QVCO are fully characterized with amplitude and phase errors via a four-port vector network analyzer. With a dc power of 3 mW, the VCO exhibits a frequency tuning range from 20.3 to 21.3 GHz, a phase noise of - 116.4 dBc/Hz at 1-MHz offset, a figure-of-merit (FOM) of -198 dBc/Hz, a phase error of 3.8° , and an amplitude error of 0.9 dB. With a dc power of 6 mW, the QVCO demonstrates a phase noise of -117.4 dBc/Hz, a FOM of -195.6 dBc/Hz, a phase error of 4° , and an amplitude error of 0.6 dB. The proposed VCO and QVCO can be compared with the previously reported state-of-the-art VCOs and QVCOs in silicon-based technologies.

This paper, for the first time, presents successful integration of a W-band antenna with an organically flip-chip packaged silicon-germanium (SiGe) low-noise amplifier (LNA). The successful integration requires an optimized flip-chip interconnect. The interconnect performance was optimized by modeling and characterizing the flip-chip transition on a low-loss liquid crystal polymer organic substrate. When the loss of coplanar waveguide (CPW) lines is included, an insertion loss of 0.6 dB per flip-chip-interconnect is measured. If the loss of CPW lines is de-embedded, 0.25 dB of insertion loss is observed. This kind of low-loss flip-chip interconnect is essential for good performance of W-band modules. The module, which we present in this paper, consists of an end-fire Yagi-Uda antenna integrated with an SiGe BiCMOS LNA. The module is 3 mm × 1.9 mm and consumes only 19.2 mW of dc power. We present passive and active E- and H-plane radiation pattern measurements at 87, 90, and 94 GHz. Passive and active antennas both showed a 10-dB bandwidth of 10 GHz. The peak gain of passive and active antennas was 5.2 dBi at 90 GHz and 21.2 dBi at 93 GHz, respectively. The measurements match well with the simulated results.

A focal-plane array (FPA) for room-temperature detection of 0.65-THz radiation has been fully integrated in a low-cost 0.25 mum CMOS process technology. The circuit architecture is based on the principle of distributed resistive self-mixing and facilitates broadband direct detection well beyond the cutoff frequency of the technology. The 3 timesZ 5 pixel array consists of differential on-chip patch antennas, NMOS direct detectors, and integrated 43-dB voltage amplifiers. At 0.65 THz the FPA achieves a responsivity (Rv) of 80 kV/W and a noise equivalent power (NEP) of 300 pW/ radic{Hz}. Active multi-pixel imaging of postal envelopes demonstrates the FPAs potential for future cost-effective terahertz imaging solutions.

This paper presents a tunable CMOS directional coupler that utilizes lumped-element L-C sections. The lumped-element approach used to build the directional coupler makes it possible to integrate the coupler onto a single monolithic microwave integrated circuit (MMIC), as it occupies a small area compared to printed designs. The directional coupler uses varactors and tunable active inductors (TAIs) to synthesize the series and shunt reactances, respectively, which allows extensive electronic control over the coupling coefficient, while insuring a low return loss and a very high isolation. Furthermore, using varactors and TAIs allows the directional coupler to be reconfigured for operation over a wide range of frequencies. Moreover, the symmetric configuration of the coupler allows it to switch from forward to backward operation by simply exchanging the bias voltages applied across the series varactors. The MMIC coupler was fabricated in a standard 0.13-mum CMOS process and operates from a 1.5-V supply. The circuit occupies 730 mum times 600 mum, and is capable of achieving tunable coupling coefficients from 1.4 to 7.1 dB, while maintaining an isolation higher than 41 dB. The MMIC coupler is also capable of operating at any center frequency over the 2.1-3.1-GHz frequency range with higher than 40-dB isolation. The coupler achieves a -4.1-dBm 1-dB compression point while operating from a 1.5-V supply.

The design of a massive multiple-input-multiple-output (mMIMO) antenna system based on patch antennas is presented in this paper. The array consists of 16 ports, each port consists of a 2×2 patch antenna array with different phase excitation at each element to tilt the beam toward different directions to provide lower correlation coefficient values. A fixed progressive phase feed network is designed to provide the beam tilts. The proposed antenna system is designed using a 3-layer FR4 substrate with total size of 33.33×33.33×0.16 cm3.

A novel transformer feedback featuring wideband input matching and noise cancellation is proposed and demonstrated in a wideband differential LNA for software-defined-radio (SDR) applications. Implemented in 0.13μm CMOS with an area of 0.32mm2, the LNA prototype measures a wideband input matching S11 of less than -10dB from 1.2GHz to 6.6GHz and minimum NF of 1.8dB while consuming 11mA at 1.2V supply.

High power, broad bandwidth, high linearity, and low noise are among the most important features in amplifier design. The broad-band spatial power-combining technique addresses all these issues by combining the output power of a large quantity of microwave monolithic integrated circuit (MMIC) amplifiers in a broad-band coaxial waveguide environment, while maintaining good linearity and improving phase noise of the MMIC amplifiers. A coaxial waveguide was used as the host of the combining circuits for broader bandwidth and better uniformity by equally distributing the input power to each element. A new compact coaxial combiner with much smaller size is investigated. Broad-band slotline to microstrip-line transition is integrated for better compatibility with commercial MMIC amplifiers. Thermal simulations are performed and an improved thermal management scheme over previous designs is employed to improve the heat sinking in high-power application. A high-power amplifier using the compact combiner design is built and demonstrated to have a bandwidth from 6 to 17 GHz with 44-W maximum output power. Linearity measurement has shown a high third-order intercept point of 52 dBm. Analysis shows the amplifier has the ability to extend spurious-free dynamic range by 2 3 times. The amplifier also has shown a residual phase floor close to 140 dBc at 10-kHz offset from the carrier with 5–6-dB reductions compared to a single MMIC amplifier it integrates.

A Ka-band planar three-way power divider which uses the coupled line instead of the transmission line is proposed to reduce chip size. The proposed planar topology, different from the conventional Wilkinson power divider, is analyzed and can provide not only compact but also dc block characteristics, which are very suitable for monolithic microwave integrated circuit applications. The divider implemented by a pHEMT process shows an insertion loss less than 5.1 dB and an output isolation better than 17 dB. A return loss less than 18 dB and a phase difference of 4.2deg at 30 GHz can be achieved. Finally, good agreements between the simulation and experimental results are shown.


Question: A 65 nm CMOS 4-element sub-34 mW per element 60 GHz phased-array transceiver implementation.

This paper delves into the design and modeling of CMOS transistors, integrated passive components, and circuit blocks for millimeter-wave (mm-wave) applications. An in-depth examination of the impact of parasitics on the high-frequency performance of 130-nm CMOS transistors is conducted, with an optimized device layout achieving a peak f/sub max/ of 135 GHz. A new metric, the inductive quality factor (Q/sub L/), is proposed for evaluating transmission lines, revealing that coplanar waveguide (CPW) lines exhibit superior Q/sub L/ compared to microstrip lines in a standard CMOS back-end process. The paper presents methodologies for precise modeling of both active and passive components at mm-wave frequencies. These techniques were applied to the design of two wideband mm-wave CMOS amplifiers operating at 40 GHz and 60 GHz. The 40-GHz amplifier boasts a peak |S/sub 21/| of 19 dB, an output P/sub 1dB/ of -0.9 dBm, an IIP3 of -7.4 dBm, and consumes 24 mA from a 1.5-V supply. The 60-GHz amplifier, on the other hand, achieves a peak |S/sub 21/| of 12 dB, an output P/sub 1dB/ of +2.0 dBm, an NF of 8.8 dB, and consumes 36 mA from a 1.5-V supply. Both amplifiers were successfully fabricated using a standard 130-nm 6-metal layer bulk-CMOS process, illustrating the capability of mainstream CMOS technologies to support sophisticated mm-wave circuit designs.

This paper describes the design of a reconfigurable reflectarray element using commercially available radio frequency micro-electromechanical system (RF MEMS) switches. The element consists of a microstrip patch on the top surface and a slot with an actuated variable length in the ground plane. RF MEMS switches are mounted on the slot to electronically vary the slot length by actuating the switches and thus obtaining the desired phase response. Waveguide measurements and high frequency structure simulator (HFSS) simulations are used to characterize the reflectarray element. The four MEMS switches element gives 10 independent states with a phase swing of 150 deg and a loss variation from 0.4 dB to 1.5 dB at 2 GHz (more switches can provide larger phase shift). The loss is mainly attributed to the dielectric loss and the conductor loss, which occur due to the relatively strong electric fields in the substrate region below the patch and the large currents on the top surface of the patch, respectively, close to the patch resonance. Detailed analysis is performed to characterize the effect of the switches by taking into consideration the switch model and wire bonding effects.

This paper presents an over-110-GHz-bandwidth 2:1 analog multiplexer (AMUX) for ultra-broadband digital-to-analog (D/A) conversion subsystems. The AMUX was designed and fabricated by using newly developed $\pmb{0.25-\mu \mathrm{m}}$ -emitter-width InP double heterojunction bipolar transistors (DHBTs), which have a peak $\pmb{f_{\mathrm{T}}}$ and $\pmb{ f\displaystyle \max}$ of 460 and 480 GHz, respectively. The AMUX IC consists of lumped building blocks, including data-input linear buffers, a clock-input limiting buffer, an AMUX core, and an output linear buffer. The measured 3-dB bandwidth for data and clock paths are both over 110 GHz. In addition, it measures and obtains time-domain large-signal sampling operations of up to 180 GS/s. A 224-Gb/s (112-GBaud) four-level pulse-amplitude modulation (PAM4) signal was successfully generated by using this AMUX. To the best of our knowledge, this AMUX IC has the broadest bandwidth and the fastest sampling rate compared with any other previously reported AMUXes.

This paper presents a time-to-digital converter (TDC) that operates with a 20–64 GHz input and underpins the phase digitization function in a millimeter-wave all-digital fractional-N frequency synthesizer. A self-calibrated inductor-less frequency divider using dynamic CML latches provides an eight-phase input to a 3-bit “coarse” TDC, which is interfaced to a 5-bit “fine” TDC through a sub-sampling coarse-fine interface circuit. A wide bandwidth low dropout (LDO) on-chip regulator is used to decrease the effect of supply noise on TDC performance. A synthesized digital engine implements calibration using statistical element selection with mean adaptation to alleviate TDC nonlinearity that results from random mismatches and PVT variations. The TDC is fabricated in 65-nm CMOS along with the divider and calibration circuits, and achieves 450-fs resolution. The measured DNL and INL of the TDC are 0.65 and 1.2 LSB, respectively. The TDC consumes 11 mA from 1-V supply voltage. The TDC features a figure-of-merit of 0.167 (0.47) pJ per conversion step without (with) the frequency divider. A single-shot experiment shows that the on-chip LDO reduces the effect of TDC noise by reducing the standard deviation from 0.856 to 0.167 LSB for constant input. The prototype occupies an active area of  $502\times 110~\mu \text{m}^{\mathbf {2}}$  excluding pads.

In this work the realization of a 77-GHz frequency-division multiple-access-based frequency-modulated continuous-wave multiple-input multiple-output radar with four transceiver channels in conjunction with a non-uniform linear antenna array is presented. The radar system, consisting of an RF-frontend utilizes transceiver chips with integrated inphase/quadrature-modulators to generate the frequency shifted transmit signals and a field programmable gate array-based baseband board, is used for test measurements to verify the system performance and to demonstrate the beamforming capability as well as the accuracy of the digital-beamforming method.

A 20-GHz phase-locked loop with 4.9 ps/sub pp//0.65 ps/sub rms/ jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-/spl mu/m CMOS operates from 17.6 to 19.4GHz and dissipates 480mW.

This paper presents a 0.9GHz-10GHz Ultra Wideband Low Noise Amplifier (LNA) designed for software-defined-radios (SDR). Capacitive cross coupling (CCC) is used at both input stage and cascade stage for wideband input impedance matching and small noise figure (NF). A combination of inductor peaking load and series inductor between the cascade stages of LNA is employed for a flat gain and enhanced input matching. This LNA is implemented in a standard 0.18µm CMOS technology. For 0.9GHz-10GHz ultra wideband applications, it achieves a maximum gain of 14dB, 3.5dB∼4.1dB NF and +1.8dBm IIP3. It consumes only7.6mW from a 1.8V power supply.

This paper compares the performance of shunt and series/shunt single-pole double-throw nMOS switches designed in a 0.13 mum SiGe BiCMOS process for X-band phased array transmit/receive modules. From 8.5 to 10.5 GHz, the worst case return loss, insertion loss, and isolation are 14.5, 1.89, and 20.5 dB, respectively, for the reflective shunt switch, and 22.2, 2.33, and 22.5 dB, respectively, for the absorptive series/shunt switch. Both switches exhibit an IIP3 of about 28 dBm and dissipate no dc power. The performance of these switches are comparable to other CMOS switches found in triple well technologies, on non-standard substrates, using special device structures, or using extra dc biases

This paper presents a new design concept of a beam steerable high gain phased array antenna based on WR28 waveguide at 29 GHz frequency for fifth generation (5G) full dimension multiple input multiple output (FD-MIMO) system. The 8×8 planar phased array is fed by a three dimensional beamformer to obtain volumetric beam scanning ranging from −60 to +60 degrees both in azimuth and elevation direction. Beamforming network (BFN) is designed using 16 set of 8×8 Butler matrix beamformer to get 64 beam states, which control the horizontal and vertical angle. This is a new concept to design waveguide based high power three-dimensional beamformer for volumetric multibeam in Ka band for 5G application. The maximum gain of phased array is 28.5 dBi that covers 28.9 GHz to 29.4 GHz frequency band.

The extensive growth of wireless communications industry is creating a big market opportunity. Wireless operators are currently searching for new solutions which would be implemented into the existing wireless communication networks to provide the broader bandwidth, the better quality and new value-added services. In the last decade, most commercial efforts were focused on the 1-10 GHz spectrum for voice and data applications for mobile phones and portable computers (Niknejad & Hashemi, 2008). Nowadays, the interest is growing in applications that use high rate wireless communications. Multigigabit-per-second communication requires a very large bandwidth. The Ultra-Wide Band (UWB) technology was basically used for this issue. However, this technology has some shortcomings including problems with interference and a limited data rate. Furthermore, the 3–5 GHz spectrum is relatively crowded with many interferers appearing in the WiFi bands (Niknejad & Hashemi, 2008). The use of millimeter wave frequency band is considered the most promising technology for broadband wireless. In 2001, the Federal Communications Commission (FCC) released a set of rules governing the use of spectrum between 57 and 66 GHz (Baldwin, 2007). Hence, a large bandwidth coupled with high allowable transmit power equals high possible data rates. Traditionally the implementation of 60 GHz radio technology required expensive technologies based on III-V compound semiconductors such as InP and GaAs (Smulders et al., 2007). The rapid progress of CMOS technology has enabled its application in millimeter wave applications. Currently, the transistors became small enough, consequently fast enough. As a result, the CMOS technology has become one of the most attractive choices in implementing 60 GHz radio due to its low cost and high level of integration (Doan et al., 2005). Despite the advantages of CMOS technology, the design of 60 GHz CMOS transceiver exhibits several challenges and difficulties that the designers must overcome. This chapter aims to explore the potential of the 60 GHz band in the use for emergent generation multi-gigabit wireless applications. The chapter presents a quick overview of the state-of-the-art of 60 GHz radio technology and its potentials to provide for high data rate and short range wireless communications. The chapter is organized as follows. Section 2 presents an overview about 60 GHz band. The advantages are presented to highlight the performance characteristics of this band. The opportunities of the physical layer of the IEEE

A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wireless RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed dithering. Other imperfections of analog circuits are compensated through digital means. The presented ideas enable the employment of fully-digital frequency synthesizers using sophisticated signal processing algorithms, realized in the most advanced deep-submicrometer digital CMOS processes which allow almost no analog extensions. They also promote costeffective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13m CMOS process together with a DSP, which acts as a digital baseband processor with a large number of digital gates in order to investigate noise coupling. The phase noise is112 dBc/Hz at 500-kHz offset. The close-in spurious tones are below 62 dBc, while the far-out spurs are below 80 dBc. The presented ideas have been incorporated in a commercial Bluetooth transceiver.


Question: A 65 nm CMOS 4-element sub-34 mW per element 60 GHz phased-array transceiver design.

This paper unveils a groundbreaking on-chip impedance matching and power combining technique, termed the distributed active transformer, designed for fully integrated CMOS power amplifiers. The method integrates multiple low-voltage push-pull amplifiers in series, enabling higher output power while ensuring a 50Ω match. It innovatively utilizes virtual ac grounds and magnetic couplings, eliminating the reliance on off-chip components like tuned bonding wires or external inductors. Notably, it reduces the sensitivity of the amplifier's performance to bonding wire inductance, enhancing design reproducibility. As a proof of concept, a 2.4-GHz, 2-W, 2-V fully integrated power amplifier, with 50Ω input and output matching, was fabricated using 0.35μm CMOS transistors. The amplifier boasts a power-added efficiency (PAE) of 41% at the specified power level and can generate 450mW using a 1-V supply. Harmonic suppression is remarkably high at 64dBc or better. This novel topology paves the way for the first truly fully integrated, watt-level, low-voltage CMOS power amplifier for gigahertz-range applications.

The approach highlights the potential for advanced CMOS integration in power amplifiers, particularly in the 65nm CMOS process technology, where size, power efficiency, and integration level are critical. While the initial focus is on a 2.4-GHz application, the principles and techniques outlined could be adapted for higher frequency bands, such as 60GHz, making it relevant to the design of phased-array transceivers with stringent power and size constraints. The distributed active transformer's ability to combine multiple amplifiers while maintaining high efficiency and matching could be pivotal in achieving sub-34mW per element power consumption in 60GHz phased-array transceivers, a significant engineering challenge in the realm of millimeter-wave communication systems.

In this paper microstrip antenna for 60 GHz on LTCC is presented. Special techniques are used to satisfy the antenna specification in wide bandwidth (7 GHz, from 57 GHz to 64 GHz) and high gain (15 dBi). An increase in bandwidth is achieved by using aperture the coupling and the multilayer structure. Gain is increased by using parasitic patches which increase the total antenna aperture. In paper was presented 60 GHz parasitic microstrip antenna with two layers of parasitic patches. High gain is obtained as the result of the optimization. However, presented return loss results can not be treated as wide bandwidth.

In this paper the evolution of silicon based automotive radar for the 76-81 GHz range is described. Starting with SiGe bare-die chips in 2009, today packaged MMICs are available for low-cost radar applications. Future SiGe BiCMOS technology will enable highly integrated single chip radars with superior performance at lower power consumption. This will pave the way for automotive radar safety for everyone and will be an important step towards autonomous driving.

This letter presents a novel topology of a 4 ×4 Butler matrix, which can realize relatively flexible phase differences at the output ports. The proposed Butler matrix employs couplers with arbitrary phase-differences to replace quadrature couplers in the conventional Butler matrix. By controlling the phase differences of the applied couplers, the progressive phase differences among output ports of the proposed Butler matrix can be relatively flexible. To facilitate the design, closed-form design equations are derived and presented. For verifying the design concept, a planar 4×4 Butler matrix with four unique progressive phase differences ( - 30°, + 150°, - 120°, and + 60°) is designed and fabricated. At the operating frequency, the amplitude imbalance is less than 0.75 dB, and the phase mismatch is within ±6°. The measured return loss is better than 16 dB, and the isolation is better than 18 dB. The bandwidth with 10 dB return loss is about 15%.

A fully integrated step-down switched-capacitor dc–dc converter ring with 123 phases has been designed that could achieve fast dynamic voltage scaling for the microprocessor of wearable devices. The symmetrical multiphase converter ring surrounds its load in the square and supplies power to the on-chip power grid that is easily accessible at any point of the chip edges. The frequency of the <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula>-controlled oscillator is adjusted through its supply voltage <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula>, which allows the unity-gain frequency to be designed higher than the switching frequency. The converter ring has been fabricated in a low-leakage 65-nm CMOS process. This converter achieves a response time of 3 ns, a reference tracking speed of 2.5 V/<inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>, and a minimum output ripple of 2.2 mV. The peak efficiency is 80% at the power density of 66.6 mW/mm2, and the maximum power density is 180 mW/mm2.

Developing next-generation cellular technology (5G) in the mm-wave bands will require low-cost phased-array transceivers [1]. Even with the benefit of beamforming, due to space constraints in the mobile form-factor, increasing TX output power while maintaining acceptable PA PAE, LNA NF, and overall transceiver power consumption is important to maximizing link budget allowable path loss and minimizing handset case temperature. Further, the phased-array transceiver will need to be able to support dual-polarization communication. An IF interface to the analog baseband is desired for low power consumption in the handset or user equipment (UE) active antenna and to enable use of arrays of transceivers for customer premises equipment (CPE) or basestation (BS) antenna arrays with a low-loss IF power-combining/splitting network implemented on an antenna backplane carrying multiple tiled antenna modules.

This paper presents a direct-conversion receiver for FCC-compliant ultra-wideband (UWB) Gaussian-shaped pulses that are transmitted in one of fourteen 500-MHz-wide channels within the 3.1-10.6-GHz band. The receiver is fabricated in 0.18-mum SiGe BiCMOS. The packaged chip consists of an unmatched wideband low-noise amplifier (LNA), filter, phase-splitter, 5-GHz ISM band switchable notch filter, 3.1-10.6-GHz local oscillator (LO) amplifiers, mixers, and baseband channel-select filters/buffers. The required quadrature single-ended LO signals are generated externally. The average conversion gain and input P1dB are 32 dB and -41 dBm, respectively. The unmatched LNA provides a system noise figure of 3.3 to 5 dB over the entire band. The chip draws 30 mA from 1.8 V. To verify the unmatched LNA's performance in a complete system, wireless testing of the front-end embedded in a full receiver at 100 Mbps reveals a 10-3 bit-error rate (BER) at -80 dBm sensitivity. The notch filter suppresses out-of-band interferers and reduces the effects of intermodulation products that appear in the baseband. BER improvements of an order of magnitude and greater are demonstrated with the filter

This paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak f/sub max/ of 135 GHz has been achieved with optimal device layout. The inductive quality factor (Q/sub L/) is proposed as a more representative metric for transmission lines, and for a standard CMOS back-end process, coplanar waveguide (CPW) lines are determined to possess a higher Q/sub L/ than microstrip lines. Techniques for accurate modeling of active and passive components at mm-wave frequencies are presented. The proposed methodology was used to design two wideband mm-wave CMOS amplifiers operating at 40 GHz and 60 GHz. The 40-GHz amplifier achieves a peak |S/sub 21/| = 19 dB, output P/sub 1dB/ = -0.9 dBm, IIP3 = -7.4 dBm, and consumes 24 mA from a 1.5-V supply. The 60-GHz amplifier achieves a peak |S/sub 21/| = 12 dB, output P/sub 1dB/ = +2.0 dBm, NF = 8.8 dB, and consumes 36 mA from a 1.5-V supply. The amplifiers were fabricated in a standard 130-nm 6-metal layer bulk-CMOS process, demonstrating that complex mm-wave circuits are possible in today's mainstream CMOS technologies.

An SPDT switch consisting of both nMOS and pMOS transistors is presented. Compared with conventional SPDT switches using only nMOS transistors under the same bias condition, the proposed switch exhibits better power-handling capability (PHC). The mechanism for the PHC improvement is explained. A prototype is implemented using a 0.18-um CMOS process. Measurement results show that, at 2.4 GHz, the insertion loss is 0.62 dB when the nMOS transistors are on and 0.91 dB when the pMOS transistors are on. For both modes, the measured return loss and isolation are better than 10 dB and 19 dB, respectively, up to 6 GHz. Under 1.8-V operation, the switch is able to handle a 26.1-dBm input power when the nMOS transistors are on and a 24.0-dBm input power when the pMOS transistors are on.

Multiple-Input and Multiple-Output (MIMO) arrays provide more degrees of freedom than conventional phased arrays. They require that every transmitting element of the array can be identified when received. One way to achieve this is to give every element its own unique frequency. Offset-transmitters may be used to introduce MIMO or Doppler Division Multiple Access (DDMA) into phased-arrays without an excessive increase in waveform-generating hardware. Our dual-channel demonstrator IC can obtain a phase accuracy better than 1 degree and an spurious level of better than -65dBc for a single on-chip channel. This work investigates at X-band the effects of the limited on-chip isolation of 35dB, when multiple offset outputs are generated on a single chip for both beam steering and DDMA. In case of beam steering, the requirements on channel-to-channel isolation are less strict, making it well within reach. In the case of DDMA, we recommend increasing the channel-to-channel isolation by implementing multiple chips, in which case independent signals can be generated.

In this work, a miniature ultra-wideband (UWB) power divider (PD) is proposed. By implementing the transmission lines of a two-stage Wilkinson PD using bridged T-coils, very compact size with no reduction in bandwidth can be achieved. Specifically, a proposed UWB two-way PD with a center frequency f0=5.5 GHz is implemented using the commercial GaAs pHEMT process. The circuit size without pads is only 1.45 mm × 0.84 mm, which is about 0.027λ0 × 0.016λ0 at f0. The fractional bandwidth for 15-dB input/output return loss and isolation is 110%, and the in-band insertion loss is within 1.3 ± 0.36 dB.


Question: A 65 nm CMOS 4-element sub-34 mW/element 60 GHz phased-array transceiver implementation.

This paper introduces a state-of-the-art SiGe BiCMOS 16-element phased-array transmitter designed for 60GHz communications, capitalizing on the recent advancements in multi-Gb/s links within the 60GHz band that have opened new avenues for wireless communications [1,2]. The directional nature of millimeter-wave (mm-Wave) propagation necessitates beam steering for effective longer-range non-line-of-sight (NLOS) links at these frequencies. The phased-array architecture is particularly appealing for an integrated 60GHz transmitter (Tx) due to its ability to achieve both beam steering and increased EIRP through spatial combining. Recent demonstrations in silicon include an all-RF 16-element 40-to-45GHz transmitter for satellite applications [3], a 6-element 60GHz transmitter incorporating IF-path phase-shift [4], and a bi-directional 4-element 60GHz transmitter/receiver with RF phase shifters [5]. The present work showcases a fully-integrated phased-array transmitter capable of supporting multi-Gb/s NLOS IEEE 802.15.3c links. Beyond beam steering, the integrated circuit (IC) boasts several key features: an on-chip power sensor at each element, 3 temperature sensors, LO leakage and I/Q phase and amplitude adjustment, front-end OP1dB programmability, and an integrated modulator for pi/2-BPSK/MSK signaling (common mode in 802.15.3c). The IC is a complex design, integrating 2240 NPNs, 323,000 FETs, and numerous transmission lines, all fabricated using the IBM 8HP 0.12µm SiGe BiCMOS process (fT = 200GHz).

Planar antennas are common components in sensing applications due to their low cost, low profile and simple integration with systems. They can be used commonly at frequencies as high as 77 GHz and above, for example in automotive sensing. Also, new ultra-wideband communication systems operating around 60 GHz will heavily rely on planar antennas due to their unique properties. One special advantage of planar elements is that they can easily form array structures combining very simple elements, like microstrip patches. Also phased and conformal arrays can be built. Due to all these characteristics, planar antennas are very good candidates for building front ends for mm-wave applications in radar, sensing or communications. For some applications, which are either established today or which will become commercial in a few years, general requirements can be given. In addition to automotive radar, this mainly applies to 60 GHz ultra-broadband wireless indoor communications. Microwave imaging at 94 GHz and above is still much under research, as well as other sensing applications in the millimeter-wave region above 100 GHz. Prominent frequency bands are in the 122 and 140 GHz range1. Typical antenna requirements are multi-beam or scanning capability, high gain up to 30..36 dBi and moderate to low sidelobes. In monopulse radar systems, the sidelobes may be included in the angle determination scheme, then the sidelobe level requirements are rather relaxed. Loss is generally an important issue. Comparing a planar approach to a commercially available dielectric lens, the planar antenna exhibits significantly higher losses, especially if the beamforming device is included. The antenna efficiency of 77 GHz planar array columns is roughly 50%. These losses are caused by dielectric losses and conductor losses. To attain reliable predictions of the losses in full-wave simulations, care has to be taken in the

This letter presents a low-cost, high-gain, and high-efficiency 4 × 4 circular patch array antenna for gigabyte point-to-point wireless services at E-band (81-86 GHz). The antenna structure consists of two layers. The feed network is placed at the bottom layer, while the circular patches are on the top layer. To increase the efficiency of the antenna array, substrate integrated waveguide (SIW) is used to feed the circular patches through longitudinal slots etched on the top metallic surface. Low-cost printed circuit board (PCB) process is used to fabricate the antenna prototype. Simulated and measured bandwidths of the antenna array are 7.2%, which covers the desired frequency range of 81-86 GHz. Measured gain of the 4 × 4 antenna array is 18.5 dBi, which is almost constant within the antenna bandwidth. Measured radiation efficiency of 90.3% is obtained.

An X-band Single-Chip monolithic microwave integrated circuit (MMIC) has been developed by using a European GaN HEMT technology. The very compact MMIC die occupying only an area of 3.0 mm × 3.0 mm, integrates a high power amplifier (HPA), a low-noise amplifier (LNA) and a robust asymmetrical absorptive/reflective SPDT switch. At the antenna RF pad in the frequency range from 8.6 to 11.2 GHz, nearly 8 W of output power and 22 dB of linear gain were measured when operated in transmit mode. When operated in receive mode, a noise figure of 2.5 dB with a gain of 15 dB were measured at the Rx RF pad in the same frequency range.

In this work the realization of a 77-GHz frequency-division multiple-access-based frequency-modulated continuous-wave multiple-input multiple-output radar with four transceiver channels in conjunction with a non-uniform linear antenna array is presented. The radar system, consisting of an RF-frontend utilizes transceiver chips with integrated inphase/quadrature-modulators to generate the frequency shifted transmit signals and a field programmable gate array-based baseband board, is used for test measurements to verify the system performance and to demonstrate the beamforming capability as well as the accuracy of the digital-beamforming method.

An 8-Gb/s 0.3-µm CMOS transceiver uses multilevel signaling (4-PAM) and transmit pre-shaping in combination with receive equalization to reduce ISI due to channel low-pass effects. High on-chip frequencies are avoided by multi-plexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear PLL with a loop bandwidth >30MHz, phase margin >48 and capture range of 20MHz without a frequency acquisition aid. The transmitted 8-Gbps data is successfully detected by the receiver after a 10-m coaxial cable. The 2mm x 2mm chip consumes 1.1W at 8Gbps with a 3-V supply.

A novel planar dual-band phased array, operational in the X/Ku-bands and with wide-angle scanning capability is presented. The design, development and experimental demonstration are described. A new single-layer crossed L-bar microstrip antenna is used for the array design. The antenna has low-profile architecture, measuring only 0.33λ×0.33λ, at the low frequency band of operation, with flexible resonance tuning capability offered by the use of a plate-through-hole and field-matching ring arrangement. A 49-element planar (7 × 7) array demonstrator has been built and its performance validated, exhibiting good agreement with full-wave simulations. The dual-band array supports a large frequency ratio of nearly 1.8:1, and also maintains good sub-band bandwidths. Wide-angle scanning up to a maximum of 60 ° and 50 ° are achieved at the low and high frequency bands of operation, respectively.

A slot array antenna is designed using ridge gap waveguide technology in two sub arrays. Each sub array is fed through a power divider which is designed on a separate ridge- groove gap waveguide. The coupling between two gap waveguides is conducted using coaxial transmission lines. The power divider of ridge-groove gap is fed using coaxial line that can provide a bandwidth of 22% at 14 GHz. The integrated antenna operates within the frequency range of 13.5-15.6 GHz with a gain of 13.9-15.5 dB. Design of the transmission line, power divider and sub-array antenna is presented.

The extensive growth of wireless communications industry is creating a big market opportunity. Wireless operators are currently searching for new solutions which would be implemented into the existing wireless communication networks to provide the broader bandwidth, the better quality and new value-added services. In the last decade, most commercial efforts were focused on the 1-10 GHz spectrum for voice and data applications for mobile phones and portable computers (Niknejad & Hashemi, 2008). Nowadays, the interest is growing in applications that use high rate wireless communications. Multigigabit-per-second communication requires a very large bandwidth. The Ultra-Wide Band (UWB) technology was basically used for this issue. However, this technology has some shortcomings including problems with interference and a limited data rate. Furthermore, the 3–5 GHz spectrum is relatively crowded with many interferers appearing in the WiFi bands (Niknejad & Hashemi, 2008). The use of millimeter wave frequency band is considered the most promising technology for broadband wireless. In 2001, the Federal Communications Commission (FCC) released a set of rules governing the use of spectrum between 57 and 66 GHz (Baldwin, 2007). Hence, a large bandwidth coupled with high allowable transmit power equals high possible data rates. Traditionally the implementation of 60 GHz radio technology required expensive technologies based on III-V compound semiconductors such as InP and GaAs (Smulders et al., 2007). The rapid progress of CMOS technology has enabled its application in millimeter wave applications. Currently, the transistors became small enough, consequently fast enough. As a result, the CMOS technology has become one of the most attractive choices in implementing 60 GHz radio due to its low cost and high level of integration (Doan et al., 2005). Despite the advantages of CMOS technology, the design of 60 GHz CMOS transceiver exhibits several challenges and difficulties that the designers must overcome. This chapter aims to explore the potential of the 60 GHz band in the use for emergent generation multi-gigabit wireless applications. The chapter presents a quick overview of the state-of-the-art of 60 GHz radio technology and its potentials to provide for high data rate and short range wireless communications. The chapter is organized as follows. Section 2 presents an overview about 60 GHz band. The advantages are presented to highlight the performance characteristics of this band. The opportunities of the physical layer of the IEEE

This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in the charge pump. The architecture maintains high signal integrity while each port consumes only 7.5 mW/Gb/s. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.

The general issue of this letter deals with the design of a phased array antenna for high-data-rate SATCOM. A final demonstrator antenna could be installed on an unmanned aerial vehicle (UAV) to communicate with a satellite in Ka-band. First, a compact reflection-type phase shifter is designed and realized. Second, the conception of a phased array antenna prototype is detailed. Third, a new calibration method is involved that can provide the bias voltage to be applied to each phase shifter in order to scan the beam in the desired direction.