Question: Design, execution, and evaluation of highly optimized algorithms for AES key recovery in access-driven cache-based side-channel assaults.

This paper highlights the susceptibility of cryptographic systems to timing attacks, particularly focusing on implementations of Diffie-Hellman, RSA, DSS, and other cryptographic protocols. By meticulously measuring the time taken to execute private key operations, attackers can potentially uncover fixed Diffie-Hellman exponents, factor RSA keys, and compromise other encryption mechanisms. This form of attack poses a significant threat to various systems, including cryptographic tokens, network-based cryptosystems, and any application where attackers can make precise timing measurements. The paper underscores the vulnerability of real-world systems and the potential for attackers to exploit these weaknesses with relatively low computational cost, often requiring just known ciphertext. To mitigate these risks, the paper proposes countermeasures specifically for RSA and Diffie-Hellman algorithms. It is suggested that some cryptosystems may require significant modifications to safeguard against timing attacks, while new protocols and algorithms should inherently include defenses against such attacks to ensure the integrity and security of cryptographic systems.

A new sort algorithm, called AlphaSort, demonstrates that commodity processors and disks can handle commercial batch workloads. Using commodity processors, memory, and arrays of SCSI disks, AlphaSort runs the industrystandard sort benchmark in seven seconds. This beats the best published record on a 32-CPU 32-disk Hypercube by 8:1. On another benchmark, AlphaSort sorted more than a gigabyte in one minute. AlphaSort is a cache-sensitive, memoryintensive sort algorithm. We argue that modern architectures require algorithm designers to re-examine their use of the memory hierarchy. AlphaSort uses clustered data structures to get good cache locality, file striping to get high disk bandwidth, QuickSort to generate runs, and replacement-selection to merge the runs. It uses shared memory multiprocessors to break the sort into subsort chores. Because startup times are becoming a significant part of the total time, we propose two new benchmarks: (1) MinuteSort: how much can you sort in one minute, and (2) PennySort: how much can you sort for one penny.

Recent breakthroughs in cryptanalysis of standard hash functions like SHA-1 and MD5 raise the need for alternatives. A credible alternative to for instance SHA-1 or the SHA-2 family of hash functions is Whirlpool. Whirlpool is a hash function that has been evaluated and approved by NESSIE and is standardized by ISO/IEC. To the best of our knowledge only one FPGA implementation of Whirlpool has been published to date. This implementation is designed for high throughput rates requiring a considerable amount of hardware resources. In this article we present a compact hardware implementation of the hash function Whirlpool. The proposed architecture uses an innovative state representation that makes it possible to reduce the required hardware resources remarkably. The complete implementation requires 1456 CLB-slices and, most notably, no block RAMs.

A wireless router is a networking device that enables a user to set up a wireless connection to the Internet. A router can offer a secure channel by cryptographic means which provides authenticity and confidentiality. Nowadays, almost all routers use a secure channel by default that is based on Wi-Fi Protected Access II (WPA2). This is a security protocol which is believed not to be susceptible to practical key recovery attacks. However, the passwords should have sufficient entropy to avert bruteforce attacks. In this paper, we compose a strategy on how to reverse-engineer embedded routers. Furthermore, we describe a procedure that can instantly gather a complete wireless authentication trace which enables an offline password recovery attack. Finally, we present a number of use cases where we identify extremely weak password generating algorithms in various routers which are massively deployed in The Netherlands. The algorithms are used to generate the default WPA2 password. Such a password is loaded during device initialization and hardware reset. Users that did not explicitly change their wireless password are most likely vulnerable to practical attacks which can recover their password within minutes. A stolen password allows an adversary to abuse someone else’s internet connection, for instance compromising the firewall, making a fraudulent transaction or performing other criminal activities. Together with the Dutch National Cyber Security Centre we have initiated a responsible disclosure procedure. However, since these routers are also used by many other companies in various countries, our findings seem to relate an international industry wide security issue.

Securing digital data has become tedious task as the technology is increasing. Existing encryption algorithms such as AES,DES and Blowfish ensure information security but consume lot of time as the security level increases. In this paper, Byte Rotation Encryption Algorithm (BREA) has implemented using parallel processing and multi-core utilization. BREA divides data into fixed size blocks. Each block is processed parallely using random number key. So the set of blocks are executed in parallel by utilizing all the available CPU cores. Finally, from the experimental analysis, it is observed that the proposed BREA algorithm reduces execution time when the number of cores has increased.

Hardware Trojan attack in the form of malicious modification of a design has emerged as a major security threat. Sidechannel analysis has been investigated as an alternative to conventional logic testing to detect the presence of hardware Trojans. However, these techniques suffer from decreased sensitivity toward small Trojans, especially because of the large process variations present in modern nanometer technologies. In this paper, we propose a novel noninvasive, multiple-parameter side-channel analysisbased Trojan detection approach. We use the intrinsic relationship between dynamic current and maximum operating frequency of a circuit to isolate the effect of a Trojan circuit from process noise. We propose a vector generation approach and several design/test techniques to improve the detection sensitivity. Simulation results with two large circuits, a 32-bit integer execution unit (IEU) and a 128-bit advanced encryption standard (AES) cipher, show a detection resolution of 1.12 percent amidst ±20 percent parameter variations. The approach is also validated with experimental results. Finally, the use of a combined side-channel analysis and logic testing approach is shown to provide high overall detection coverage for hardware Trojan circuits of varying types and sizes.

We present BranchScope - a new side-channel attack where the attacker infers the direction of an arbitrary conditional branch instruction in a victim program by manipulating the shared directional branch predictor. The directional component of the branch predictor stores the prediction on a given branch (taken or not-taken) and is a different component from the branch target buffer (BTB) attacked by previous work. BranchScope is the first fine-grained attack on the directional branch predictor, expanding our understanding of the side channel vulnerability of the branch prediction unit. Our attack targets complex hybrid branch predictors with unknown organization. We demonstrate how an attacker can force these predictors to switch to a simple 1-level mode to simplify the direction recovery. We carry out BranchScope on several recent Intel CPUs and also demonstrate the attack against an SGX enclave.

In recent years, the deployment of many applicationlevel countermeasures against memory errors and the increasing number of vulnerabilities discovered in the kernel has fostered a renewed interest in kernel-level exploitation. Unfortunately, no comprehensive and wellestablished mechanism exists to protect the operating system from arbitrary attacks, due to the relatively new development of the area and the challenges involved. In this paper, we propose the first design for finegrained address space randomization (ASR) inside the operating system (OS), providing an efficient and comprehensive countermeasure against classic and emerging attacks, such as return-oriented programming. To motivate our design, we investigate the differences with application-level ASR and find that some of the wellestablished assumptions in existing solutions are no longer valid inside the OS; above all, perhaps, that information leakage becomes a major concern in the new context. We show that our ASR strategy outperforms stateof-the-art solutions in terms of both performance and security without affecting the software distribution model. Finally, we present the first comprehensive live rerandomization strategy, which we found to be particularly important inside the OS. Experimental results demonstrate that our techniques yield low run-time performance overhead (less than 5% on average on both SPEC and syscall-intensive benchmarks) and limited run-time memory footprint increase (around 15% during the execution of our benchmarks). We believe our techniques can greatly enhance the level of OS security without compromising the performance and reliability of the OS.

We initiate the study of multi-user (mu) security of authenticated encryption (AE) schemes as a way to rigorously formulate, and answer, questions about the “randomized nonce” mechanism proposed for the use of the AE scheme GCM in TLS 1.3. We (1) Give definitions of mu ind (indistinguishability) and mu kr (key recovery) security for AE (2) Characterize the intent of nonce randomization as being improved mu security as a defense against mass surveillance (3) Cast the method as a (new) AE scheme RGCM (4) Analyze and compare the mu security of both GCM and RGCM in the model where the underlying block cipher is ideal, showing that the mu security of the latter is indeed superior in many practical contexts to that of the former, and (5) Propose an alternative AE scheme XGCM having the same efficiency as RGCM but better mu security and a more simple and modular design.

In this paper we introduce FELICS, a free and open-source benchmarking framework designed for fair and consistent evaluation of software implementations of lightweight cryptographic primitives for embedded devices. The framework is very flexible thanks to its modular structure, which allows for an easy integration of new metrics, target devices and evaluation scenarios. It consists of two modules that can currently asses the performance of lightweight block and stream ciphers on three widely used microcontrollers: 8-bit AVR, 16-bit MSP and 32-bit ARM. The metrics extracted are execution time, RAM consumption and binary code size. FELICS has a simple user interface and is intended to be used by cipher designers to compare new primitives with the state of the art. The extracted metrics are very detailed and assist embedded software engineers in selecting the best cipher to match the requirements of a particular application. The tool aims to increase the transparency and trust in benchmarking results of lightweight primitives and facilitates a fair comparison between different primitives using the same evaluation conditions.

A5/2 is a synchronous stream cipher that is used for protecting GSM communication. Recently, some powerful attacks [2,10] on A5/2 have been proposed. In this contribution we enhance the ciphertext-only attack [2] by Barkan, Biham, and Keller by designing special-purpose hardware for generating and solving the required systems of linear equations. For realizing the LSE solver component, we use an approach recently introduced in [5,6] describing a parallelized hardware implementation of the Gauss-Jordan algorithm. Our hardware-only attacker immediately recovers the initial secret state of A5/2 which is sufficient for decrypting all frames of a session using a few ciphertext frames without any precomputations and memory. More precisely, in contrast to [2] our hardware architecture directly attacks the GSM speech channel (TCH/FS and TCH/EFS). It requires 16 ciphertext frames and completes the attack in about 1 second. With minor changes also input from other GSM channels (e.g., SDCCH/8) can be used to mount the attack.


Question: Design, execution, and evaluation of highly optimized algorithms for AES key recovery in access-driven cache-based side-channel assaults.

This paper outlines the RC5 encryption algorithm, a swift symmetric block cipher designed for both hardware and software implementations. A distinctive feature of RC5 is its extensive reliance on data-dependent rotations, setting it apart from conventional encryption methods. With a flexible design, RC5 supports variable word sizes, a customizable number of rounds, and a secret key of adjustable length, making it highly adaptable to various security requirements. The simplicity of both the encryption and decryption processes is a notable advantage of RC5, contributing to its efficiency and ease of implementation. However, the focus on data-dependent rotations introduces a layer of complexity that enhances security but may require more sophisticated handling in certain environments. Despite this, RC5 remains a robust choice for encryption tasks where speed and adaptability are critical. Note, however, that this description of the RC5 algorithm does not directly address the AES key retrieval in access-driven cache-based side channel attacks, but it provides insight into another encryption algorithm that might be relevant in discussions about cryptographic techniques and their vulnerabilities.

We propose a new 64-bit blockcipher Piccolo supporting 80 and 128-bit keys. Adopting several novel design and implementation techniques, Piccolo achieves both high security and notably compact implementation in hardware. We show that Piccolo offers a sufficient security level against known analyses including recent related-key differential attacks and meet-in-the-middle attacks. In our smallest implementation, the hardware requirements for the 80 and the 128-bit key mode are only 683 and 758 gate equivalents, respectively. Moreover, Piccolo requires only 60 additional gate equivalents to support the decryption function due to its involution structure. Furthermore, its efficiency on the energy consumption which is evaluated by energy per bit is also remarkable. Thus, Piccolo is one of the competitive ultra-lightweight blockciphers which are suitable for extremely constrained environments such as RFID tags and sensor nodes.

In recent years, the deployment of many applicationlevel countermeasures against memory errors and the increasing number of vulnerabilities discovered in the kernel has fostered a renewed interest in kernel-level exploitation. Unfortunately, no comprehensive and wellestablished mechanism exists to protect the operating system from arbitrary attacks, due to the relatively new development of the area and the challenges involved. In this paper, we propose the first design for finegrained address space randomization (ASR) inside the operating system (OS), providing an efficient and comprehensive countermeasure against classic and emerging attacks, such as return-oriented programming. To motivate our design, we investigate the differences with application-level ASR and find that some of the wellestablished assumptions in existing solutions are no longer valid inside the OS; above all, perhaps, that information leakage becomes a major concern in the new context. We show that our ASR strategy outperforms stateof-the-art solutions in terms of both performance and security without affecting the software distribution model. Finally, we present the first comprehensive live rerandomization strategy, which we found to be particularly important inside the OS. Experimental results demonstrate that our techniques yield low run-time performance overhead (less than 5% on average on both SPEC and syscall-intensive benchmarks) and limited run-time memory footprint increase (around 15% during the execution of our benchmarks). We believe our techniques can greatly enhance the level of OS security without compromising the performance and reliability of the OS.

The cache hierarchy prevalent in todays high performance processors has to be taken into account in order to design algorithms that perform well in practice. This paper advocates the adaption of external memory algorithms to this purpose. This idea and the practical issues involved are exemplified by engineering a fast priority queue suited to external memory and cached memory that is based on <i>k</i>-way merging. It improves previous external memory algorithms by constant factors crucial for transferring it to cached memory. Running in the cache hierarchy of a workstation the algorithm is at least two times faster than an optimized implementation of binary heaps and 4-ary heaps for large inputs.

The well-known stream cipher Grain-128 is a variant version of Grain v1 with 128-bit secret key. Grain v1 is a stream cipher which has successfully been chosen as one of seven finalists by European eSTREAM project. Yet Grain-128 is vulnerable against some recently introduced attacks. A new version of Grain-128 with authentication, named Grain-128a, is proposed by Ågren, Hell, Johansson, and Meier. The designers claimed that Grain-128a is strengthened against all known attacks and observations on the original Grain-128. So far there exists no attack on Grain-128a except a differential fault attack by Banik, Maitra, and Sarkar. In this paper, we give some observations on Grain-128a, and then propose a related key chosen IV attack on Grain-128a based on these observations. Our attack can recover the 128-bit secret key of Grain-128a with a computational complexity of <formula formulatype="inline"> <tex Notation="TeX">$2^{96.322} $</tex></formula>, requiring <formula formulatype="inline"> <tex Notation="TeX">$2^{96} $</tex></formula> chosen IVs and <formula formulatype="inline"><tex Notation="TeX">$2^{103.613} $</tex> </formula> keystream bits. The success probability of our attack is 0.632. This related key attack is “minimal” in the sense that it only requires two related keys. The result shows that our attack is much better than an exhaustive key search in the related key setting.

Many kinds of memory safety vulnerabilities have been endangering software systems for decades. Amongst other approaches, fuzzing is a promising technique to unveil various software faults. Recently, feedback-guided fuzzing demonstrated its power, producing a steady stream of security-critical software bugs. Most fuzzing efforts—especially feedback fuzzing—are limited to user space components of an operating system (OS), although bugs in kernel components are more severe, because they allow an attacker to gain access to a system with full privileges. Unfortunately, kernel components are difficult to fuzz as feedback mechanisms (i.e., guided code coverage) cannot be easily applied. Additionally, non-determinism due to interrupts, kernel threads, statefulness, and similar mechanisms poses problems. Furthermore, if a process fuzzes its own kernel, a kernel crash highly impacts the performance of the fuzzer as the OS needs to reboot. In this paper, we approach the problem of coverageguided kernel fuzzing in an OS-independent and hardware-assisted way: We utilize a hypervisor and Intel’s Processor Trace (PT) technology. This allows us to remain independent of the target OS as we just require a small user space component that interacts with the targeted OS. As a result, our approach introduces almost no performance overhead, even in cases where the OS crashes, and performs up to 17,000 executions per second on an off-the-shelf laptop. We developed a framework called kernel-AFL (kAFL) to assess the security of Linux, macOS, and Windows kernel components. Among many crashes, we uncovered several flaws in the ext4 driver for Linux, the HFS and APFS file system of macOS, and the NTFS driver of Windows.

We introduce in this paper a lightweight technique for reducing work repetition caused by non–chronological backtracking commonly practiced by DPLL–based SAT solvers. The presented technique can be viewed as a partial component caching scheme. Empirical evaluation of the technique reveals significant improvements on a broad range of in-

Many digital signature schemes rely on random numbers that are unique and non-predictable per signature. Failures of random number generators may have catastrophic effects such as compromising private signature keys. In recent years, many widely-used cryptographic technologies adopted deterministic signature schemes because they are presumed to be safer to implement. In this paper, we analyze the security of deterministic ECDSA and EdDSA signature schemes and show that the elimination of random number generators in these schemes enables new kinds of fault attacks. We formalize these attacks and introduce practical attack scenarios against EdDSA using the Rowhammer fault attack. EdDSA is used in many widely used protocols such as TLS, SSH, and IPSec, and we show that these protocols are not vulnerable to our attack. We formalize the necessary requirements of protocols using these deterministic signature schemes to be vulnerable, and discuss mitigation strategies and their effect on fault attacks against deterministic signature schemes.

Sanctum offers the same promise as Intel’s Software Guard Extensions (SGX), namely strong provable isolation of software modules running concurrently and sharing resources, but protects against an important class of additional software attacks that infer private information from a program’s memory access patterns. Sanctum shuns unnecessary complexity, leading to a simpler security analysis. We follow a principled approach to eliminating entire attack surfaces through isolation, rather than plugging attack-specific privacy leaks. Most of Sanctum’s logic is implemented in trusted software, which does not perform cryptographic operations using keys, and is easier to analyze than SGX’s opaque microcode, which does. Our prototype targets a Rocket RISC-V core, an open implementation that allows any researcher to reason about its security properties. Sanctum’s extensions can be adapted to other processor cores, because we do not change any major CPU building block. Instead, we add hardware at the interfaces between generic building blocks, without impacting cycle time. Sanctum demonstrates that strong software isolation is achievable with a surprisingly small set of minimally invasive hardware changes, and a very reasonable overhead.

The shared last-level caches in CMPs play an important role in improving application performance and reducing off-chip memory bandwidth requirements. In order to use LLCs more efficiently, recent research has shown that changing the re-reference prediction on cache insertions and cache hits can significantly improve cache performance. A fundamental challenge, however, is how to best predict the re-reference pattern of an incoming cache line.
 This paper shows that cache performance can be improved by correlating the re-reference behavior of a cache line with a unique signature. We investigate the use of memory region, program counter, and instruction sequence history based signatures. We also propose a novel Signature-based Hit Predictor (SHiP) to learn the re-reference behavior of cache lines belonging to each signature. Overall, we find that SHiP offers substantial improvements over the baseline LRU replacement and state-of-the-art replacement policy proposals. On average, SHiP improves sequential and multiprogrammed application performance by roughly 10% and 12% over LRU replacement, respectively. Compared to recent replacement policy proposals such as Seg-LRU and SDBP, SHiP nearly doubles the performance gains while requiring less hardware overhead.

Aho-Corasick (AC) algorithm is a multiple patternsmatching algorithm commonly used for applications such as computer and network security, bioinformatics, image processing, among others. These applications are computationally demanding, thus optimizing performance for AC algorithm is crucial. In this paper, we present a performance optimization strategy for the AC algorithm on a Graphic Processing Unit(GPU). Our strategy efficiently utilizes the high degree of the on chip parallelism and the complicated memory hierarchy of the GPU so that the aggregate performance (or throughput) for the AC algorithm can be optimized. The strategy significantly cuts down the effective memory access latencies and efficiently utilizes the memory bandwidth. Also, it maximizes the effects of the multithreading capability of the GPU through optimal thread scheduling. Experimental results on Nvidia GeForce GTX 285 GPU show that our approach delivers up to 127 Gbps throughput performance and 222-times speedup compared with a serial version running on single core of 2.2Ghz Core2Duo Intel processor.


Question: Design, execution, and evaluation of highly effective algorithms for AES key recovery in access-driven cache-based side-channel assaults.

This paper delves into the realm of cryptographic security, specifically focusing on Differential Power Analysis (DPA) as a method to counteract access-driven cache-based side channel attacks. In such scenarios, attackers exploit the power consumption patterns of cryptographic devices to infer sensitive information, such as encryption keys. The presentation of this material is strictly for educational and illustrative purposes, with no warranties or guarantees provided by the content creators. It is emphasized that the insights shared do not necessarily reflect the official viewpoints of the contributing organization or its collaborators. Given the sensitive nature of the information, strict confidentiality measures are in place, prohibiting any unauthorized duplication, utilization, or dissemination of the material.

**Question**: A Comparative Study on the Performance of Different Ant Colony Optimization Algorithms in Solving the Traveling Salesman Problem

**Documents**: Ant Colony Optimization for the Traveling Salesman Problem
Ant Colony Optimization (ACO) is a metaheuristic inspired by the foraging behavior of ants, which has been successfully applied to solve various combinatorial optimization problems. This paper presents a comprehensive study on the performance of ACO algorithms when applied to the Traveling Salesman Problem (TSP), a well-known NP-hard problem. We compare the efficiency and effectiveness of different variants of ACO algorithms, including Ant System (AS), Max-Min Ant System (MMAS), and Rank-Based Ant System (RAS). Our experimental results show that MMAS outperforms the other two variants in terms of solution quality and computational time. Furthermore, we analyze the impact of various parameters on the performance of ACO algorithms, such as pheromone evaporation rate, ant colony size, and local search strategies. Our findings provide valuable insights into the design and application of ACO algorithms for TSP and other similar problems.

**Similar Documents**: This research investigates the application of Ant Colony Optimization (ACO) algorithms in addressing the complexities of the Traveling Salesman Problem (TSP). ACO, a computational technique inspired by the social behavior of ants, has proven to be a potent approach in tackling a wide array of combinatorial optimization challenges. This paper offers a detailed comparative analysis of ACO algorithms' performance in the context of TSP. It evaluates the performance of three distinct ACO algorithm variations: Ant System (AS), Max-Min Ant System (MMAS), and Rank-Based Ant System (RAS). Experimental outcomes highlight MMAS as the superior variant, showcasing better results in terms of solution quality and processing time. Additionally, the study delves into the influence of

Radio frequency identification (RFID) is an emerging technology which brings enormous productivity benefits in applications where objects have to be identified automatically. This paper presents issues concerning security and privacy of RFID systems which are heavily discussed in public. In contrast to the RFID community, which claims that cryptographic components are too costly for RFID tags, we describe a solution using strong symmetric authentication which is suitable for today’s requirements regarding low power consumption and low die-size. We introduce an authentication protocol which serves as a proof of concept for authenticating an RFID tag to a reader device using the Advanced Encryption Standard (AES) as cryptographic primitive. The main part of this work is a novel approach of an AES hardware implementation which encrypts a 128-bit block of data within 1000 clock cycles and has a power consumption below 9 μA on a 0.35 μm CMOS process.

This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of subpipelining can be further explored. Furthermore, composite field arithmetic is employed to reduce the area requirements, and different implementations for the inversion in subfield GF(2/sup 4/) are compared. In addition, an efficient key expansion architecture suitable for the subpipelined round units is also presented. Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV1000 e-8 bg560 device in non-feedback modes, which is faster and is 79% more efficient in terms of equivalent throughput/slice than the fastest previous FPGA implementation known to date.

In an attribute-based encryption (ABE) scheme, a ciphertext is associated with an ℓ-bit public index ind and a message m, and a secret key is associated with a Boolean predicate P. The secret key allows decrypting the ciphertext and learning m if and only if P(ind) = 1. Moreover, the scheme should be secure against collusions of users, namely, given secret keys for polynomially many predicates, an adversary learns nothing about the message if none of the secret keys can individually decrypt the ciphertext.
 We present attribute-based encryption schemes for circuits of any arbitrary polynomial size, where the public parameters and the ciphertext grow linearly with the depth of the circuit. Our construction is secure under the standard learning with errors (LWE) assumption. Previous constructions of attribute-based encryption were for Boolean formulas, captured by the complexity class NC1.
 In the course of our construction, we present a new framework for constructing ABE schemes. As a by-product of our framework, we obtain ABE schemes for polynomial-size branching programs, corresponding to the complexity class LOGSPACE, under quantitatively better assumptions.

Recent trends of hardware intellectual property (IP) piracy and reverse engineering pose major business and security concerns to an IP-based system-on-chip (SoC) design flow. In this paper, we propose a Register Transfer Level (RTL) hardware IP protection technique based on low-overhead key-based obfuscation of control and data flow. The basic idea is to transform the RTL core into control and data flow graph (CDFG) and then integrate a well-obfuscated finite state machine (FSM) of special structure, referred as “Mode-Control FSM”, into the CDFG in a manner that normal functional behavior is enabled only after application of a specific input sequence. We provide formal analysis of the effectiveness of the proposed approach and present a simple metric to quantify the level of obfuscation. We also present an integrated design flow that implements the proposed obfuscation at low computational overhead. Simulation results for two open-source IP cores show that high levels of security is achievable at nominal area and power overheads under delay constraint.

We present BranchScope - a new side-channel attack where the attacker infers the direction of an arbitrary conditional branch instruction in a victim program by manipulating the shared directional branch predictor. The directional component of the branch predictor stores the prediction on a given branch (taken or not-taken) and is a different component from the branch target buffer (BTB) attacked by previous work. BranchScope is the first fine-grained attack on the directional branch predictor, expanding our understanding of the side channel vulnerability of the branch prediction unit. Our attack targets complex hybrid branch predictors with unknown organization. We demonstrate how an attacker can force these predictors to switch to a simple 1-level mode to simplify the direction recovery. We carry out BranchScope on several recent Intel CPUs and also demonstrate the attack against an SGX enclave.

Channel State Information (CSI) has been proposed to enhance physical layer security between a transmitter and a receiver because it decorrelates over half wavelength distances in rich scattering environments. Consequently, CSI was employed to generate passwords, to authenticate the source of packets, and to inject artificial noise to thwart eavesdroppers. However, in this paper, we present CSIsnoop, and show that an attacker can infer CSI in a multi-user WLAN, even if both channel sounding sequences from the access point and CSI measurement feedback from the clients are encrypted. The insights of CSIsnoop are that the CSI of clients can be computed based on transmit beamforming weights at the access point, and that the transmit beamforming weights can be estimated from downlink multi-user transmission. We implement CSIsnoop on a software defined radio and conduct experiments in various indoor environments. Our results show that on average CSIsnoop can infer CSI of the target client with an absolute normalized correlation of over 0.99, thereby urging reconsideration of the use of CSI as a tool to enhance physical layer security in multi-user WLANs.

Unlike library code, whose instruction addresses can be randomized by address space layout randomization (ASLR), application binary code often has static instruction addresses. Attackers can exploit this limitation to craft robust shell codes for such applications, as demonstrated by a recent attack that reuses instruction gadgets from the static binary code of victim applications.
 This paper introduces binary stirring, a new technique that imbues x86 native code with the ability to self-randomize its instruction addresses each time it is launched. The input to STIR is only the application binary code without any source code, debug symbols, or relocation information. The output is a new binary whose basic block addresses are dynamically determined at load-time. Therefore, even if an attacker can find code gadgets in one instance of the binary, the instruction addresses in other instances are unpredictable. An array of binary transformation techniques enable STIR to transparently protect large, realistic applications that cannot be perfectly disassembled due to computed jumps, code-data interleaving, OS callbacks, dynamic linking and a variety of other difficult binary features. Evaluation of STIR for both Windows and Linux platforms shows that stirring introduces about 1.6% overhead on average to application runtimes.

Dynamic information flow tracking (DIFT) is an effective security countermeasure for both low-level memory corruptions and high-level semantic attacks. However, many software approaches suffer large performance degradation, and hardware approaches have high logic and storage overhead. We propose a flexible and light-weight hardware/software co-design approach to perform DIFT based on secure page allocation. Instead of associating every data with a taint tag, we aggregate data according to their taints, i.e., putting data with different attributes in separate memory pages. Our approach is a compiler-aided process with architecture support. The implementation and analysis show that the memory overhead is little, and our approach can protect critical information, including return address, indirect jump address, and system call IDs, from being overwritten by malicious users.

Hard real-time embedded systems employ high-capacity memories such as Dynamic RAMs (DRAMs) to cope with increasing data and code sizes of modern designs. However, memory controller design has so far largely focused on improving average-case performance. As a consequence, the latency of memory accesses is unpredictable, which complicates the worst-case execution time analysis necessary for hard real-time embedded systems.
 Our work introduces a novel DRAM controller design that is predictable and that significantly reduces worst-case access latencies. Instead of viewing the DRAM device as one resource that can only be shared as a whole, our approach views it as multiple resources that can be shared between one or more clients individually. We partition the physical address space following the internal structure of the DRAM device, i.e., its ranks and banks, and interleave ac- cesses to the blocks of this partition. This eliminates contention for shared resources within the device, making accesses temporally predictable and temporally isolated. This paper describes our DRAM controller design and its integration with a precision-timed (PRET) architecture called PTARM. We present analytical bounds on the latency and throughput of the proposed controller, and confirm these via simulation.

Split manufacturing can mitigate security vulnerabilities at untrusted foundries by exposing only partial designs. Even so, attackers can make educated guess according to design conventions and thereby recover entire chip designs. In this work, a routing perturbation-based defense method is proposed such that such attacks become very difficult while wirelength/timing overhead is restricted to be very small. Experimental results on benchmark circuits confirm the effectiveness of the proposed techniques. The new techniques also significantly outperform the latest previous work.


Question: Design, execution, and evaluation of highly optimized algorithms for AES key recovery in access-driven cache-based side-channel assaults.

This paper presents an innovative framework for designing, implementing, and evaluating the performance of highly efficient algorithms aimed at retrieving AES keys in access-driven cache-based side channel attacks. Unlike conventional approaches, our method focuses on optimizing the algorithms to achieve faster key retrieval while maintaining a high level of accuracy. The framework is designed to be adaptable to various cache architectures, making it versatile and widely applicable. We conduct a comprehensive analysis of the algorithm's performance under different conditions, demonstrating its robustness and efficiency. Through a series of experiments, we compare our algorithm with existing methods, highlighting significant improvements in key retrieval speed and reduced susceptibility to cache-based side channel attacks. Our findings contribute to the ongoing efforts in enhancing cryptographic security by addressing vulnerabilities in cache access patterns. The detailed analysis and results provide insights into the design of secure and efficient cryptographic systems, particularly in environments where side channel attacks are a concern.

Elliptic curve cryptography (ECC) has proven to be an effective cryptography. ECC has its own advantages such as efficient key size compared to other public key infrastructures. This paper exploits the Elliptic curve random generator defined by National Institute of Standards and Technology (NIST) to generate a sequence of arbitrary numbers based on curves. The random generation phase is based on public shared key and a changing point G, which is a generator of a curve to obtain random sequences. Then, Advanced Encryption System is applied to these sequences acquiring arbitrary keys for encrypting image. Using AES alongside well distributed randoms provides a prominent encryption technique. Our experiments show that the proposed method fulfills the basics of cryptography including simpleness and correctness. Moreover, the results of the evaluation prove the effectiveness and security of the proposed method.

This paper gives algorithms for the discrete log and the factoring problems that take random polynomial time on a quantum computer (thus giving the rst examples of quantum cryptanalysis).

Previous research on kernel monitoring and protection widely relies on higher privileged system components, such as hardware virtualization extensions, to isolate security tools from potential kernel attacks. These approaches increase both the maintenance effort and the code base size of privileged system components, which consequently increases the risk of having security vulnerabilities. SKEE, which stands for Secure Kernellevel Execution Environment, solves this fundamental problem. SKEE is a novel system that provides an isolated lightweight execution environment at the same privilege level of the kernel. SKEE is designed for commodity ARM platforms. Its main goal is to allow secure monitoring and protection of the kernel without active involvement of higher privileged software. SKEE provides a set of novel techniques to guarantee isolation. It creates a protected address space that is not accessible to the kernel, which is challenging to achieve when both the kernel and the isolated environment share the same privilege level. SKEE solves this challenge by preventing the kernel from managing its own memory translation tables. Hence, the kernel is forced to switch to SKEE to modify the system’s memory layout. In turn, SKEE verifies that the requested modification does not compromise the isolation of the protected address space. Switching from the OS kernel to SKEE exclusively passes through a well-controlled switch gate. This switch gate is carefully designed so that its execution sequence is atomic and deterministic. These properties combined guarantee that a potentially compromised kernel cannot exploit the switching sequence to compromise the isolation. If the kernel attempts to violate these properties, it will only cause the system to fail without exposing the protected address space. SKEE exclusively controls access permissions of the entire OS memory. Hence, it prevents attacks that attempt to inject unverified code into the kernel. Moreover, it can be easily extended to intercept other system events in order to support various intrusion detection and integrity verification tools. This paper presents a SKEE prototype that runs on both 32-bit ARMv7 and 64-bit ARMv8 architectures. Performance evaluation results demonstrate that SKEE is a practical solution for real world systems. 1These authors contributed equally to this work

It is desirable to store data on data storage servers such as mail servers and file servers in encrypted form to reduce security and privacy risks. But this usually implies that on e has to sacrifice functionality for security. For example, if a client wishes to retrieve only documents containing certai n words, it was not previously known how to let the data storage server perform the search and answer the query without loss of data confidentiality. In this paper, we describe our cryptographic schemes for the problem of searching on encrypted data and provide proofs of security for the resulting crypto systems. Ou r techniques have a number of crucial advantages. They are provably secure : they provideprovable secrecy for encryption, in the sense that the untrusted server cannot learn anything about the plaintext when only given the ciphertext; they providequery isolationfor searches, meaning that the untrusted server cannot learn anything more about the plaintext than the search result; they provide controlled searching, so that the untrusted server cannot search for an arbitrary word without the user’s authorization; they also supporthidden queries , so that the user may ask the untrusted server to search for a secret word without revealing the word to the server. The algorithms we present are simple, fast (for a document of length n, the encryption and search algorithms only need O(n) stream cipher and block cipher operations), and introduce almost no space and communication overhead, and hence are practical to use today. We gratefully acknowledge support for this research from se veral US government agencies. This research was suported in part by t he Defense Advanced Research Projects Agency under DARPA contract N66 01-9928913 (under supervision of the Space and Naval Warfare Syst ems Center San Diego), by the National Science foundation under grant F D99-79852, and by the United States Postal Service under grant USPS 1025 90-98-C3513. Views and conclusions contained in this document are t hose of the authors and do not necessarily represent the official opinio n or policies, either expressed or implied of the US government or any of its agencies, DARPA, NSF, USPS.

Public Key Cryptography (PKC) has been the enabling technology underlying many security services and protocols in traditional networks such as the Internet. In the context of wireless sensor networks, elliptic curve cryptography (ECC), one of the most efficient types of PKC, is being investigated to provide PKC supportin sensor network applications so that the existing PKC-based solutions can be exploited. This paper presents the design, implementation, and evaluation of TinyECC, a configurable library for ECC operations in wireless sensor networks. The primary objective of TinyECC is to provide a ready-to-use, publicly available software package for ECC-based PKC operations that can be flexibly configured and integrated into sensor network applications. TinyECC provides a number of optimization switches, which can turn specific optimizations on or off based on developers' needs. Different combinations of the optimizations have different execution time andresource consumptions, giving developers great flexibility in integrating TinyECC into sensor network applications. This paperalso reports the experimental evaluation of TinyECC on several common sensor platforms, including MICAz, Tmote Sky, and Imote2. The evaluation results show the impacts of individual optimizations on the execution time and resource consumptions, and give the most computationally efficient and the most storage efficient configuration of TinyECC.

Radio-frequency identification (RFID) technology is the enabler for applications like the future internet of things (IoT), where security plays an important role. When integrating security to RFID tags, not only the cryptographic algorithms need to be secure but also their implementation. In this work we present differential power analysis (DPA) and differential electromagnetic analysis (DEMA) attacks on a securityenabled RFID tag. The attacks are conducted on both an ASIC-chip version and on an FPGA-prototype version of the tag. The design of the ASIC version equals that of commercial RFID tags and has analog and digital part integrated on a single chip. Target of the attacks is an implementation of the Advanced Encryption Standard (AES) with 128-bit key length and DPA countermeasures. The countermeasures are shuffling of operations and insertion of dummy rounds. Our results illustrate that the effort for successfully attacking the ASIC chip in a real-world scenario is only 4.5 times higher than for the FPGA prototype in a laboratory environment. This let us come to the conclusion that the effort for attacking contactless devices like RFID tags is only slightly higher than that for contact-based devices. The results further underline that the design of countermeasures like the insertion of dummy rounds has to be done with great care, since the detection of patterns in power or electromagnetic traces can be used to significantly lower the attacking effort.

We present a simple, new paradigm for the design of collision-free hash functions. Any function emanating from this paradigm is incremental. (This means that if a message x which I have previously hashed is modi ed to x0 then rather than having to re-compute the hash of x 0 from scratch, I can quickly \update" the old hash value to the new one, in time proportional to the amount of modi cation made in x to get x.) Also any function emanating from this paradigm is parallelizable, useful for hardware implementation. We derive several speci c functions from our paradigm. All use a standard hash function, assumed ideal, and some algebraic operations. The rst function, MuHASH, uses one modular multiplication per block of the message, making it reasonably e cient, and signi cantly faster than previous incremental hash functions. Its security is proven, based on the hardness of the discrete logarithm problem. A second function, AdHASH, is even faster, using additions instead of multiplications, with security proven given either that approximation of the length of shortest lattice vectors is hard or that the weighted subset sum problem is hard. A third function, LtHASH, is a practical variant of recent lattice based functions, with security proven based, again on the hardness of shortest lattice vector approximation. Dept. of Computer Science & Engineering, University of California at San Diego, 9500 Gilman Drive, La Jolla, California 92093, USA. E-Mail: mihir@cs.ucsd.edu. URL: http://www-cse.ucsd.edu/users/mihir. Supported in part by NSF CAREER Award CCR-9624439 and a Packard Foundation Fellowship in Science and Engineering. yMIT Laboratory for Computer Science, 545 Technology Square, Cambridge, MA 02139, USA. E-Mail: miccianc@theory.lcs.mit.edu. Supported in part by DARPA contract DABT63-96-C-0018.

There have been several modes of operations available for symmetric key block ciphers, among which Galois Counter Mode (GCM) of operation is a standard. GCM mode of operation provides con dentiality with the help of symmetric key block cipher operating in counter mode. The authentication component of GCM comprises of Galois hash (GHASH) computation which is a keyed hash function. The most important component of GHASH computation is carry-less multiplication of 128bit operands which is followed by a modulo reduction. There have been a number of schemes proposed for e cient software implementation of carry-less multiplication to improve performance of GHASH by increasing the speed of multiplications. This thesis focuses on providing an e cient way of software implementation of high performance GHASH function as being proposed by Meloni et al., and also on the implementation of GHASH using a carry-less multiplication instruction provided by Intel on their Westmere architecture. The thesis work includes implementation of the high performance GHASH and its comparison to the older or standard implementation of GHASH function. It also includes comparison of the two implementations using Intel's carry-less multiplication instruction. This is the rst time that this kind of comparison is being done on software implementations of these algorithms. Our software implementations suggest that the new GHASH algorithm, which was originally proposed for the hardware implementations due to the required parallelization, can't take advantage of the Intel carry-less multiplication instruction PCLMULQDQ. On the other hand, when implementations are done without using the PCLMULQDQ instruction the new algorithm performs better, even if its inherent parallelization is not utilized. This suggest that the new algorithm will perform better on embedded systems that do not support PCLMULQDQ.

Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full speed at one time. In this regime, specialized, energy-efficient processors can increase parallelism by reducing the per-computation power requirements and allowing more computations to execute under the same power budget. To pursue this goal, this paper introduces conservation cores. Conservation cores, or c-cores, are specialized processors that focus on reducing energy and energy-delay instead of increasing performance. This focus on energy makes c-cores an excellent match for many applications that would be poor candidates for hardware acceleration (e.g., irregular integer codes). We present a toolchain for automatically synthesizing c-cores from application source code and demonstrate that they can significantly reduce energy and energy-delay for a wide range of applications. The c-cores support patching, a form of targeted reconfigurability, that allows them to adapt to new versions of the software they target. Our results show that conservation cores can reduce energy consumption by up to 16.0x for functions and by up to 2.1x for whole applications, while patching can extend the useful lifetime of individual c-cores to match that of conventional processors.

In this paper we present a fully pipelined high speed hardware architecture for Galois/Counter Mode of Operation (GCM) by analyzing the data dependencies in the GCM algorithm at the architecture level. We show that GCM encryption circuit and GCM authentication circuit have similar critical path delays resulting in an efficient pipeline structure. The proposed GCM architecture yields a throughput of 34 Gbps running at 271 MHz using a 0.18 μm CMOS standard cell library.


Question: Design of a low-power, high-speed CMOS comparator for use in A/D converter applications.

This paper presents a novel design for a high-speed, high-resolution latch comparator, specifically tailored for integration into a 12-bit, 100 MHz pipeline analog-to-digital converter (ADC). The proposed comparator is optimized for high-performance wireless local area network applications, where speed and resolution are paramount. A key feature of this comparator is its rail-to-rail input range preamplifier, which operates efficiently without the need for any external capacitance. Additionally, the output stage incorporates a unique architecture that facilitates ultra-high-speed operation while minimizing kickback noise, a critical factor in maintaining signal integrity. Simulation outcomes, achieved using 0.35 micron TSMC CMOS process technology, confirm the comparator's exceptional performance. Notably, it boasts a propagation delay of just 2.8 nanoseconds, coupled with outstanding resolution across the entire rail-to-rail input signal range. Moreover, the design exhibits remarkable power efficiency, consuming a mere 1.0 milliwatt at a 5.0-volt supply voltage. These results highlight the comparator's suitability for high-speed ADC applications in power-sensitive systems.

This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10-100× smaller than the noise generated by a static CMOS circuit. Unlike static CMOS, whose dominant dynamic power is proportional to the frequency, MCML circuits dissipate a constant power independent of clock frequency. Although these traits make MCML highly energy efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at the modest clock rate and with a low activity factor. To address this challenge, a single-core microarchitecture for MCML is explored that exploits the C-slow retiming technique, and operates at a high frequency with low complexity to save energy. This design principle contrasts with the contemporary multicore design paradigm for static CMOS that relies on a large number of gates operating in parallel at the modest speeds. The proposed architecture generates 10-40× lower power and ground noise, and operates within 13% of the performance (i.e., 1/ExecutionTime) of a conventional, eight-core static CMOS processor while exhibiting 1.6× lower energy and 9% less area. Moreover, the operation of an MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length.

This paper presents a chopper instrumentation amplifier for interfacing precision thermistor bridges. For high CMRR and DC gain, the amplifier employs a three-stage current-feedback topology with nested-Miller compensation. By chopping both the input and intermediate stages of the amplifier, a 1 mHz 1/f noise corner was achieved at an input-referred noise power spectral density (PSD) of 15 nV/¿Hz. To reduce chopper ripple, the amplifier employs a continuous-time AC-coupled ripple reduction loop. Due to its continuous-time nature, the loop causes no noise folding to DC and hence offers improved noise performance over auto-zeroed amplifiers. The loop reduces chopper ripple by more than 60 dB, to levels below the amplifier's own input-referred noise. Furthermore, a maximum input referred offset of 5 ¿ V and a CMRR greater than 120 dB were measured at a supply current of 230 ¿A at 5 V.

The “split ADC” architecture enables fully digital calibration and correction of nonlinearity errors due to capacitor mismatch in a successive approximation (SAR) ADC. The die area of a single ADC design is split into two independent halves, each converting the same input signal. Total area and power is unchanged, resulting in minimal increase in analog complexity. For each conversion, the half-sized ADCs generate two independent outputs which are digitally corrected using estimates of capacitor mismatch errors for each ADC. The ADC outputs are averaged to produce the ADC output code. The difference of the two outputs is used in a background calibration algorithm which estimates the error in the correction parameters. Any nonzero difference drives an LMS feedback loop toward zero difference which can only occur when the average error in each correction parameter is zero. A novel segmentation and shuffling scheme in the SAR capacitive DAC enables background calibration for a wide range of input signals including dc. Simulation of a 16 bit 1 Msps SAR ADC in 180 nm CMOS shows calibration convergence within 200 000 samples.

The efficient and fast control of electric power forms part of the key technologies of modern automated production. It is performed using electronic power converters. The converters transfer energy from a source to a controlled process in a quantized fashion, using semiconductor switches which are turned on and off at fast repetition rates. The algorithms which generate the switching functions – pulsewidth modulation techniques – are manifold. They range from simple averaging schemes to involved methods of real-time optimization. This paper gives an overview.

With the emergence of nanoscale material-based energy harvesters such as thermoelectric generator and microbial fuel cells, energy-harvesting-assisted self-powered electronics systems are gaining popularity. The state-of-the-art low-voltage CMOS boost converter, a critical voltage converter circuit for low power energy harvesting sources will be reviewed in this paper. Fundamentals of the boost converter circuit startup problem are discussed and recent circuit solutions to solve this problem are compared and analyzed. Necessary design considerations and trade-offs regarding circuit topology, component and CMOS process are also addressed.

In this paper a class-D audio amplifier for mobile applications is presented realized in a 0.14 μm CMOS technology tailored for mobile applications. The amplifier has a simple PDM-based digital interface for audio and control that requires only two pins and enables assembly in 9-bump WL-CSP. The complete audio path is discussed that consists of a Parser, Digital PWM controller, 1-bit DA-converters, analog feedback loop and the Class-D power stage. A reconfigurable gate driver is used that reduces quiescent current consumption and radiated emission.

The low power VLSI design has an important role in designing of many electronic systems. While designing any combinational or sequential circuits, the important parameters like power consumption, implementation area, voltage leakage and performance of the circuit are to be considered. Design of area, high speed and powerefficient data path logic systems forms the largest areas of research in VLSI system design. This paper presents a low power Carry look ahead adder design using Full swing Gate diffusion (FS-GDI) technique. The proposed CLA implementation utilizes improved full-swing GDI F1 and F2 gates, which are the counterparts of standard CMOS NAND and NOR gates. The basic Gate Diffusion Input (GDI) logic style suffers from some practical limitations like swing degradation, fabrication complexity in standard CMOS process and bulk connections. These limitations can be overcome by Full swing GDI technique. The proposed technique utilizes a single swing restoration (SR) transistor to improve the output swing of F1 and F2 GDI gates. A 16-bit CLA is designed and Simulations are performed by Mentor graphics 130nm CMOS technology ELDO simulator. Simulation results have shown a greater reduction in delay, power dissipation and area.

Positron emission tomography (PET) is a nuclear functional imaging technique that produces a three-dimensional image of functional organs in the body. PET requires high resolution, fast and low power multichannel analog to digital converter (ADC). A typical multichannel ADC for PET scanner architecture consists of several blocks. Most of the blocks can be designed by using fast, low power D flip-flops. A preset-able true single phase clocked (TSPC) D flip-flop shows numerous glitches (noise) at the output due to unnecessary toggling at the intermediate nodes. Preset-able modified TSPC (MTSPC) D flip-flop have been proposed as an alternative solution to alleviate this problem. However, the MTSPC D flip-flop requires one extra PMOS to suspend toggling of the intermediate nodes. In this work, we designed a 7-bit preset-able gray code counter by using the proposed D flip-flop. This work involves UMC 180 nm CMOS technology for preset-able 7-bit gray code counter where we achieved 1 GHz maximum operation frequency with most significant bit (MSB) delay 0.96 ns, power consumption 244.2 μW (micro watt) and power delay product (PDP) 0.23 pJ (Pico joule) from 1.8 V power supply.

In this paper a design and comparison between a fully differential RC Miller compensated CMOS op-amp and conventional op-amp is presented. High gain enables the circuit to operate efficiently in a closed loop feedback system, whereas high bandwidth makes it suitable for high speed applications. A novel RC Miller compensation technique is used to optimize the parameters of gain and bandwidth for high speed applications are illustrated in this research work. The design is also able to address any fluctuation in supply or dc input voltages and stabilizes the operation by nullifying. The design is implemented on TSMC 0.18 m CMOS process at 3.3 V as supply voltage under room temperature 27 C. The simulated result shows that a unity gain bandwidth of 136.8 MHz with a high gain of 92.27 dB is achieved for the proposed op-amp circuit. The total areas of the layouts are 0.000158 mm and 0.000532 mm for conventional and proposed respectively. Key wrods: Two-Stage Op-amp, fully differential, high gain, high bandwidth

Here, A PID controller plus a novel linear-to-nonlinear translator is proposed and applied to the boost converter to improve the operating performance of the boost converter under large transient variations in load all over the quiescent dc input voltage range. The proposed translator is inserted between the PID controller and the main power stage such that the PID controller considers the behavior of the boost converter to be quasi-linear, thereby suppressing the effect of nonlinear behavior of the boost converter on the PID controller. Besides, variations in dc gain of the control-to-output transfer function with the translator are smaller than those without the translator, thus making system control easy to attain. Also, one-comparator counter-based sampling without any A-D converter is presented herein to realize the proposed control strategy. As mentioned above, the proposed control strategy can make the boost converter stably operated under large load transient responses all over the quiescent dc input voltage range.


Question: Design of a low-power, high-speed CMOS comparator for use in A/D converter applications.

This presentation unveils an innovative technique for enhancing and automating the sizing of components in CMOS analog circuits, specifically tailored for optimizing performance measures that exhibit a unique characteristic: they can be expressed as posynomial functions of the design variables. This attribute enables circuit design challenges to be formulated as geometric programs, a particular class of convex optimization problems for which highly efficient global optimization algorithms are available. The outcome is a design synthesis method that is not only rapid but also ensures the identification of the globally optimal solution, with the final design configuration being entirely independent of the initial starting point. Furthermore, the method's high efficiency facilitates the execution of robust designs and the swift exploration of the design space. Despite the seemingly restrictive nature of geometric programs, the paper demonstrates that a broad range of circuit design issues can indeed be articulated within this framework, showcasing its versatility and practical applicability.

In the realm of low power and high speed CMOS comparator design for A/D converter applications, this novel method offers a systematic approach to optimizing circuit performance. By leveraging the posynomial representation of key performance metrics, designers can now automate the component sizing process to achieve optimal trade-offs between power consumption and speed, essential for enhancing the efficiency of A/D converters. This technique not only streamlines the design process but also ensures that the final comparator design meets stringent performance requirements while minimizing power usage, a critical consideration in modern electronic systems. The method's ability to quickly explore the design space and identify robust solutions makes it particularly suitable for the complex design challenges associated with high-performance A/D converter components.

A comprehensive study of ultra high-speed current-mode logic (CML) buffers and regenerative CML latches will be illustrated. A new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, a new 20GHz regenerative latch circuit will be introduced. Experimental results show a higher performance for the new latch architecture compared to a conventional CML latch circuit at ultra high-frequencies. It is also shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.

The design of a 12.77-MHz on-chip RC relaxation oscillator with digital compensation technique is presented. To maintain the frequency stability versus temperature and supply voltage variations, loop delay tuning by a digital feedback loop is developed in this system. In order to generate an on-chip reference for digital calibration, a replica comparator is added. The on-chip relaxation oscillator is fabricated in 0.18-μm CMOS process. The measured output frequency variation is 31 ppm/°C across -30 to 120 °C temperature range after compensation. The frequency variation over the supply voltage from 0.6 V to 1.1 V is ±0.5%/V. The measured total power consumption is 56.2 μW at 0.9-V supply voltage when the digital compensation blocks are enabled. After digital compensation, the compensation blocks can be shutdown for power saving, and the main oscillator consumes only 12.8 μW.

In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master–slave latch structures. A new simulation and optimization approach is presented, targeting both highperformance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master–slave latches and flipflops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications.

The current paper presents low-power analog integrated circuits (ICs) for wireless electrocardiogram (ECG) detection in personal health monitoring. Considering the power-efficient communication in the body sensor network (BSN), the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. The proposed system comprises the design and implementation with three subsystems, namely, (1) the ECG acquisition node, (2) the protocol for standard IEEE 802.15.4 ZigBee system, and (3) the radio frequency (RF) transmitter circuits. A preamplifier, a low-pass filter, and a successive-approximation analog-to-digital converter (SA-ADC) are integrated to detect an ECG signal. For high integration, the ZigBee protocol is adopted for wireless communication. To transmit the ECG signal through wireless communication, a quadrature voltage-controlled oscillator and a 2.4 GHz low-IF transmitter with a power amplifier and up-conversion mixer are also developed. In the receiver, a 2.4 GHz fully integrated CMOS radio-frequency front-end with a low-noise amplifier, and a quadrature mixer is proposed. The low-power wireless bio-signal acquisition SoC (WBSA-SoC) has been implemented in TSMC 0.18-μm standard CMOS process. The measurement results on the human body reveal that the ECG signals can be acquired effectively by the proposed SoC.

In this paper, a new current source gate drive circuit is proposed for high efficiency synchronous buck VRMs. The proposed circuit achieves quick turn-on and turn-off transition times to reduce switching loss and conduction loss in power MOSFETS. The driver circuit consists of two sets of four control switches and two very small inductors (typically 50 nH-300 nH each at 1 MHz). It drives both the control MOSFET and synchronous MOSFET in synchronous buck VRMs. An analysis, design procedure, optimization procedure and experimental results are presented for the proposed circuit. Experimental results demonstrate an efficiency of 86.6% at 15 A load and 81.9% at 30 A load for 12 V input and 1.3 V output at 1 MHz.

A simple technique to achieve low-voltage power-efficient class AB operational transconductance amplifiers (OTAs) is presented. It is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth product (GBW), and near-optimal current efficiency. LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. Three OTA realizations based on this technique have been fabricated in a 0.5-/spl mu/m CMOS technology. For an 80-pF load they show enhancement factors of slew rate and GBW of up to 280 and 3.6, respectively, compared to a conventional class A OTA with the same 10-/spl mu/A quiescent currents and /spl plusmn/1-V supply voltages. In addition, the overhead in terms of common-mode input range, output swing, silicon area, noise, and static power consumption, is minimal.

A digital IF to RF converter architecture with an RF VGA targeted for WCDMA transmitters is presented. The RFDAC consists of a 1.5-bits current steering DAC with an embedded semi-digital FIR filter and a mixer with an LC load. The VGA controls the output power in 10 dB steps. The prototype is fabricated in 0.18 mum CMOS technology and achieves 0 dBm output power at 2 GHz and 33 dB image rejection. The measured rms EVM and ACPR show the system fulfills the standard specifications for the WCDMA. The chip draws 123.9 mA from 1.8 V supply. The die area is 0.8 times 1.6 mm2.

A new design of the diode string with very low leakage current is proposed for use in the ESD clamp circuits across the power rails. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the leakage current of this new diode string with six stacked diodes at 5 V (3.3 V) forward bias can be reduced to only 2.1 (1.07) nA at a temperature of 125/spl deg/C in a 0.35 /spl mu/m silicide CMOS process, whereas the previous designs have a leakage current in the order of mA. The total blocking voltage of this new design with NCLSCR can be linearly adjusted by changing the number of the stacked diodes in the diode string without causing latch-up danger across the power rails. From the experimental results, the human-body-model ESD level of the ESD clamp circuit with the proposed low-leakage diode string is greater than 8 kV in a 0.35 /spl mu/m silicide CMOS process by using neither ESD implantation nor the silicide-blocking process modifications.

This paper presents a recurrent neural circuit for solving quadratic programming problems. The objective is tominimize a quadratic cost function subject to linearconstraints. The proposed circuit employs non-linearfeedback, in the form of unipolar comparators, to introducetranscendental terms in the energy function ensuring fastconvergence to the solution. The proof of validity of the energy function is also provided. The hardware complexity of the proposed circuit comparesfavorably with other proposed circuits for the same task. PSPICE simulation results arepresented for a chosen optimization problem and are foundto agree with the algebraic solution.

The demand for low voltage, low drop-out (LDO) regulators is increasing because of the growing demand for portable electronics, i.e., cellular phones, pagers, laptops, etc. LDOs are used coherently with dc-dc converters as well as standalone parts. In power supply systems, they are typically cascaded onto switching regulators to suppress noise and provide a low noise output. The need for low voltage is innate to portable low power devices and corroborated by lower breakdown voltages resulting from reductions in feature size. Low quiescent current in a battery operated system is an intrinsic performance parameter because it partially determines battery life. This paper discusses some techniques that enable the practical realizations of low quiescent current LDOs at low voltages and in existing technologies. The proposed circuit exploits the frequency response dependence on load-current to minimize quiescent current flow. Moreover, the output current capabilities of MOS power transistors are enhanced and drop-out voltages are decreased for a given device size. Other applications, like dc-dc converters, can also reap the benefits of these enhanced MOS devices. An LDO prototype incorporating the aforementioned techniques was fabricated. The circuit was operable down to input voltages of 1 V with a zero-load quiescent current flow of 23 μA. Moreover, the regulator provided 18 and 50 mA of output current at input voltages of 1 and 1.2 V respectively.


Question: Design of a low-power, high-speed CMOS comparator for use in A/D converter applications.

This paper delves into the intricacies of distortion analysis in telegraph signals, exploring an alternative approach to the traditional transient calculation method. While transient analysis has been widely applied and solved for simple terminal conditions, its extension to complex apparatus configurations presents significant challenges. The paper introduces a novel perspective, focusing on the steady-state characteristics of the telegraph system. This approach offers a distinct advantage by simplifying the calculations that would otherwise be complicated by the intricacies of terminal apparatus. Central to this method is the translation of distortion criteria from transient-based parameters to steady-state characteristics. A significant part of the paper is dedicated to outlining and exemplifying this translation process. The discussion also covers the minimum frequency range necessary for achieving a specified signaling speed, including a comparative analysis between single-sideband and double-sideband transmission techniques in the context of carrier telegraphy. Additional related topics are examined within the paper.

**Question**: An Efficient Hybrid Algorithm for the Capacitated Vehicle Routing Problem

**Documents**: An efficient hybrid algorithm for the capacitated vehicle routing problem

The capacitated vehicle routing problem (CVRP) is a well-known NP-hard problem in combinatorial optimization, with significant practical applications in logistics and transportation. This paper presents an efficient hybrid algorithm for solving the CVRP. The algorithm combines the strengths of a genetic algorithm (GA) and a local search method, specifically the 2-opt heuristic, to achieve a balance between exploration and exploitation. The GA is responsible for generating a diverse set of solutions, which are then refined by the 2-opt heuristic to improve the solution quality. The proposed hybrid approach is tested on a set of benchmark instances from the literature, and the results are compared with those obtained by other algorithms. The experimental results show that the proposed algorithm is able to find high-quality solutions in a reasonable amount of time, outperforming several state-of-the-art algorithms in terms of solution quality and computational efficiency.

**Similar Documents**: This paper introduces an innovative hybrid algorithm designed to address the capacitated vehicle routing problem (CVRP), a notorious NP-hard challenge in the field of combinatorial optimization, with profound implications in logistics and transportation sectors. The algorithm integrates the robustness of a genetic algorithm (GA) with the refinement capabilities of a local search strategy, notably the 2-opt heuristic. This combination ensures a strategic equilibrium between the exploration of solution space and the exploitation of promising solutions. The GA generates a wide array of solutions, which are subsequently enhanced by the 2-opt heuristic for improved solution quality. The effectiveness of the hybrid algorithm is

This paper presents an approach to the design of a high-precision CMOS voltage reference. The proposed circuit is designed for TSMC 0.35 m standard CMOS process. We design the ̄rstorder temperature compensation bandgap voltage reference circuit. The proposed post-simulated circuit delivers an output voltage of 0.596V and achieves the reported temperature coe±cient (TC) of 3.96 ppm/ C within the temperature range from 60 C to 130 C when the supply voltage is 1.8V. When simulated in a smaller temperature range from 40 C to 80 C, the circuit achieves the lowest reported TC of 2.09 ppm/ C. The reference current is 16.586 A. This circuit provides good performances in a wide range of temperature with very small TC.

This paper presents a 3rd order continuous-time Delta-Sigma modulator with a tri-level quantizer, which provides 3-dB reduction of quantization noise without dynamic element matching (DEM). The tri-level DAC linearity is analyzed and it shows that a highly linear tri-level DAC can be realized in fully-differential active-RC Delta-Sigma modulator. The performance of the tri-level continuous-time Delta-Sigma modulator has been verified through simulations using a standard 0.18-μm CMOS process. It achieves 81-dB SNDR at 3.2-MS/s sampling rate and consumes 1.14-μW power with ideal amplifier.

In this paper, we compare the performance of the newly introduced distributed active transformer (DAT) structure to that of conventional on-chip impedance-transformations methods. Their fundamental power-efficiency limitations in the design of high-power fully integrated amplifiers in standard silicon process technologies are analyzed. The DAT is demonstrated to be an efficient impedance-transformation and power-combining method, which combines several low-voltage push-pull amplifiers in series by magnetic coupling. To demonstrate the validity of the new concept, a 2.4-GHz 1.9-W 2-V fully integrated power-amplifier achieving a power-added efficiency of 41% with 50input and output matching has been fabricated using 0.35-μm CMOS transistors Item Type: Article Additional Information: © Copyright 2002 IEEE. Reprinted with permission. Manuscript received May 27, 2001. [Posted online: 2002-08-07] This work was supported by the Intel Corporation, the Army Research Office, the Jet Propulsion Laboratory, Infinion, and the National Science Foundation. The authors thank Conexant Systems for chip fabrication, particularly R. Magoon, F. In’tveld, J. Powell, A. Vo, and K. Moye. K. Potter, D. Ham, and H.Wu, all of the California Institute of Technology (Caltech), Pasadena, deserve special thanks for their assistance. The technical support for CAD tools from Agilent Technologies and Sonnet Software Inc., Liverpool, NY, are also appreciated. “Special Issue on Silicon-Based RF and Microwave Integrated Circuits”, IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 1, part 2 Subject

Advanced 0.16 μm BCD technology platform offering dense logic transistors (1.8 V-5 V CMOS) and high performance analog features has been developed. Thanks to dedicated field plate optimization, body and drain engineering, state of the art power devices (8 V to 42 V rated) have been obtained ensuring large Safe Operating Areas with best RONXAREA-BVDSS tradeoff.

A time-domain-control-based quasi-<inline-formula> <tex-math notation="LaTeX">$V^{2}$ </tex-math></inline-formula> buck converter with small area, fast transient response, wide load current range, and constant switching frequency is proposed in this paper. The proposed time-domain-based controller achieves compact core area and simplified constant switching frequency control by replacing the conventional voltage-domain comparator with a phase detector having an adaptive detection window. Moreover, a coupling-based inductor current emulator is also proposed to support the discontinuous conduction mode operation in the light load. The proposed buck converter is implemented using 0.35-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. The core area of the proposed buck converter is only 0.293 mm2. The measured peak efficiency in the continuous conduction mode is 92% and the end-to-end efficiency in the load current range of 25–700 mA is 73%. The undershoot/overshoot and recovery time with the up/down load current steps of 510 mA are 38/20 mV and 2.5/2.6 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>, respectively.

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low,frequency noise of the ampli$ers becomes increasingly significant. Also, the achievable aniplijier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques will be described for the compensation of the amplifier most important nonideal effects including the noise (mainly thermal and l l f noise), the input-referred dc offset voltage, as well as the finite gain resulting in a nonideal virtual ground at the input.

In this paper, modified circuit topologies of a differential voltage-controlled oscillator (VCO) and a quadrature VCO (QVCO) in a standard bulk 90-nm CMOS process are presented for low dc power and low phase-noise applications. By utilizing current-reuse and transformer-feedback techniques, the proposed VCO and QVCO can be operated at reduced dc power consumption while maintaining extraordinary circuit performance in terms of low phase-noise and low amplitude/phase errors. The VCO circuit topology is investigated to obtain the design procedure. The VCO is further applied to the QVCO design with a bottom-series coupling technique. The coupling network between two differential VCOs and device size are properly designed based on our proposed design methodology to achieve low amplitude and phase errors. Moreover, the VCO and the QVCO are fully characterized with amplitude and phase errors via a four-port vector network analyzer. With a dc power of 3 mW, the VCO exhibits a frequency tuning range from 20.3 to 21.3 GHz, a phase noise of - 116.4 dBc/Hz at 1-MHz offset, a figure-of-merit (FOM) of -198 dBc/Hz, a phase error of 3.8° , and an amplitude error of 0.9 dB. With a dc power of 6 mW, the QVCO demonstrates a phase noise of -117.4 dBc/Hz, a FOM of -195.6 dBc/Hz, a phase error of 4° , and an amplitude error of 0.6 dB. The proposed VCO and QVCO can be compared with the previously reported state-of-the-art VCOs and QVCOs in silicon-based technologies.

A fully differential Super Class AB Operational Transconductance Amplifier (OTA) is presented. To provide additional dynamic current boosting and increased gain-bandwidth product (GBW), not only adaptive biasing techniques has been applied at the differential input stage, but also Local Common Mode Feedback (LCMFB). Additionally, Quasi Floating Gate (QFG) transistors are employed, enhancing the performance of the amplifier. The OTA has been fabricated in a standard 0.5-μm CMOS process. Simulation results yield a slew rate improvement by factor 86 and a GBW enhancement by factor 16 when compared to the class A OTA while driving the same 70-pF load. Supply voltages are ±1-V and the value of the quiescent current is 10 μA. The overhead in terms of quiescent power, silicon area, and noise level is small.

Positron emission tomography (PET) is a nuclear functional imaging technique that produces a three-dimensional image of functional organs in the body. PET requires high resolution, fast and low power multichannel analog to digital converter (ADC). A typical multichannel ADC for PET scanner architecture consists of several blocks. Most of the blocks can be designed by using fast, low power D flip-flops. A preset-able true single phase clocked (TSPC) D flip-flop shows numerous glitches (noise) at the output due to unnecessary toggling at the intermediate nodes. Preset-able modified TSPC (MTSPC) D flip-flop have been proposed as an alternative solution to alleviate this problem. However, the MTSPC D flip-flop requires one extra PMOS to suspend toggling of the intermediate nodes. In this work, we designed a 7-bit preset-able gray code counter by using the proposed D flip-flop. This work involves UMC 180 nm CMOS technology for preset-able 7-bit gray code counter where we achieved 1 GHz maximum operation frequency with most significant bit (MSB) delay 0.96 ns, power consumption 244.2 μW (micro watt) and power delay product (PDP) 0.23 pJ (Pico joule) from 1.8 V power supply.

A monolithic DC-DC boost converter with current-mode hysteretic control is designed and simulated in 0.18-μm CMOS technology. The system is simple, robust, and has a fast response to external changes. It does not require an external clock, and the output is regulated by voltage feedback in addition to limiting the inductor current by sensing it. A non-overlapping clock is internally generated to drive the power switches using buffers designed to minimize power dissipation. For conversion specifications of 1.8 V to 3.3 V at 150 mA, overall efficiency of 94.5% is achieved. Line regulation is 17.5 mV/V, load regulation is 0.33% for a 100 mA current step, while the output voltage ripple is below 30 mV for nominal conditions.


Question: Design of a low-power, high-speed CMOS comparator for use in A/D converter applications.

This paper presents an innovative CMOS latched comparator design, specifically tailored for high-speed flash analog-to-digital converters (ADCs), that significantly mitigates the issue of kickback noise. Kickback noise, a critical concern in traditional comparators used in flash ADCs, can lead to input signal voltage disturbances and potential output errors. The proposed comparator design effectively addresses this problem by decoupling the analog preamplifier from the positive feedback digital dynamic latch, thereby minimizing the impact of kickback noise. Simulation outcomes, conducted using a 0.35 μm mixed-signal CMOS technology, validate the design's capability to operate at a peak clock frequency of 500 MHz with markedly reduced kickback noise levels, outperforming conventional comparator architectures in this regard.

This paper highlights the general trend towards further monolithic integration in power applications by enabling power management and interfacing solutions in advanced CMOS nodes. The need to combine high-density digital circuits, power-management circuits, and robust interfaces in a single technology platform requires the development of additional process options on top of baseline CMOS. Examples include high-voltage devices, devices to enable area-efficient ESD protection, and integrated capacitors and inductors with high quality factors. The use of bipolar devices in these technologies for protection and control purposes in power applications is also addressed.

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the timeconsuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster. & 2009 Elsevier B.V. All rights reserved.

An ultra low-power, precise voltage reference using a switched-capacitor technique in 0.35-μm CMOS is presented in this paper. The temperature dependence of the carrier mobility and channel length modulation effect can be effectively minimized by using 3.3 and 5 V N-type transistors to operate in the saturation and subthreshold regions, respectively. In place of resistors, a precise reference voltage with flexible trimming capability is achieved by using capacitors. When the supply voltage is 1 V and the temperature is 80°C, the supply current is 250 nA. The line sensitivity is 0.76%/V; the PSRR is -41 dB at 100 Hz and -17 dB at 10 MHz. Moreover, the occupied die area is 0.049 mm2.

Two novel level shifters that are suitable for block-level dynamic voltage scaling environment (namely, V/sub DD/-hopping) are proposed. In order to achieve reduction in power consumption and delay, the first proposed level shifter which is called contention mitigated level shifter (CMLS) uses a contention-reduction technique. The simulation results with 65-nm CMOS model show 24% reduction in power and 50% decrease in delay with 4% area increase compared with the conventional level shifter. The second proposed level shifter which is called bypassing enabled level shifter (BELS) implements a bypass function and it is fabricated using 0.35/spl mu/m CMOS technology. The measurement results show that the power and delay of the proposed BELS are reduced by 50% and 65%, respectively with 60% area overhead over the conventional level shifter.

We present in this paper an overview of circuit techniques dedicated to design reliable low-voltage (1-V and below) analog functions in deep submicron standard CMOS processes. The challenges of designing such low-voltage and reliable analog building blocks are addressed both at circuit and physical layout levels. State-ofthe-art circuit topologies and techniques (input level shifting, bulk and current driven, DTMOS), used to build main analog modules (operational amplifier, analog CMOS switches) are covered with the implementation of MOS capacitors.

An analysis of the impact of last stage flash in a conventional pipeline ADC is performed in this paper. The performance of a pipeline ADC can be altered significantly by calibrating the comparators in the back-end flash. Also, realizing that the input to the back-end flash (in a pipeline ADC) is not uniformly distributed, this paper proposes alternative back-end flash references to improve the overall performance of the ADC. An analysis of the performance of the pipeline with large offsets in the MDAC stages is also presented in this paper.

In this paper, the analog front end (AFE) for an inductive position sensor in an automotive electromagnetic resonance gear control applications is presented. To improve the position detection accuracy, a coil driver with an automatic two-step impedance calibration is proposed which, despite the load variation, provides the desired driving capability by controlling the main driver size. Also, a time shared analog-to-digital converter (ADC) is proposed to convert eight-phase signals while reducing the current consumption and area to 1/8 of the conventional structure. A relaxation oscillator with temperature compensation is proposed to generate a constant clock frequency in vehicle temperature conditions. This chip is fabricated using a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process and the die area is 2 mm <inline-formula> <tex-math notation="LaTeX">$\times 1.5$ </tex-math></inline-formula> mm. The power consumption of the AFE is 23.1 mW from the supply voltage of 3.3 V to drive one transmitter (Tx) coil and eight receiver (Rx) coils. The measured position detection accuracy is greater than 99.8 %. The measurement of the Tx shows a driving capability higher than 35 mA with respect to the load change.

In the design of high speed Flash ADC selection of Thermometer to Binary decoder plays an important role. This paper describes different decoder topologies suitable for Flash ADCs. Comparative analysis between them is presented in terms of hardware required, propagation delay & power consumption. Result shows that fat tree & Mux based topologies are suitable for high speed conversions, but Mux based topology is effective in terms of power consumption. Presence of bubble error reduces output correction capability. In this paper advance scheme is proposed for correction of bubble error in Mux based decoder.

A family of switched-capacitor resonant circuits using only two transistors is presented. The circuit operates under zero-current switching and, therefore, the switching loss is zero. It also offers a wide choice of voltage conversions including fractional as well as multiple and inverted voltage conversion ratios.

This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10-100× smaller than the noise generated by a static CMOS circuit. Unlike static CMOS, whose dominant dynamic power is proportional to the frequency, MCML circuits dissipate a constant power independent of clock frequency. Although these traits make MCML highly energy efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at the modest clock rate and with a low activity factor. To address this challenge, a single-core microarchitecture for MCML is explored that exploits the C-slow retiming technique, and operates at a high frequency with low complexity to save energy. This design principle contrasts with the contemporary multicore design paradigm for static CMOS that relies on a large number of gates operating in parallel at the modest speeds. The proposed architecture generates 10-40× lower power and ground noise, and operates within 13% of the performance (i.e., 1/ExecutionTime) of a conventional, eight-core static CMOS processor while exhibiting 1.6× lower energy and 9% less area. Moreover, the operation of an MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length.