Question: A self-adhesive, capacitive carbon nanotube-based electrode for recording electroencephalograph signals from hairy scalp regions.

This paper presents an innovative methodology for constructing orthonormal bases of compactly supported wavelets, capable of achieving high levels of regularity. The regularity order of these wavelets increases in direct proportion to their support width. Our approach begins with an overview of multiresolution analysis, alongside a detailed examination of various algorithms employed in vision decomposition and reconstruction techniques. The synthesis of these methodologies forms the foundation for our construction of compactly supported wavelets. This comprehensive framework not only ensures the generation of wavelets with desired regularity properties but also highlights the interplay between different algorithmic strategies in achieving such objectives. The result is a versatile and adaptable system for the creation of wavelet bases that can be tailored to meet specific regularity requirements, making it an invaluable resource in various applications requiring precise signal processing and analysis.

Giving robots the ability to classify surface textures requires appropriate sensors and algorithms. Inspired by the biology of human tactile perception, we implement a neurorobotic texture classifier with a recurrent spiking neural network, using a novel semisupervised approach for classifying dynamic stimuli. Input to the network is supplied by accelerometers mounted on a robotic arm. The sensor data are encoded by a heterogeneous population of neurons, modeled to match the spiking activity of mechanoreceptor cells. This activity is convolved by a hidden layer using bandpass filters to extract nonlinear frequency information from the spike trains. The resulting high-dimensional feature representation is then continuously classified using a neurally implemented support vector machine. We demonstrate that our system classifies 18 metal surface textures scanned in two opposite directions at a constant velocity. We also demonstrate that our approach significantly improves upon a baseline model that does not use the described feature extraction. This method can be performed in real-time using neuromorphic hardware, and can be extended to other applications that process dynamic stimuli online.

Monitoring of the physical properties of the tissues provides valuable information for the clinical diagnosis and evaluation. However, one of the challenges of an ultrasonic method for continuous monitoring of a tissue motion using a conventional clinical ultrasonic image system could be motion artifacts due to the weight and size of its handheld ultrasonic probe employed. A wearable ultrasonic sensor, made of a polyvinylidene fluoride (PVDF) polymer piezoelectric film, may be able to reduce the motion artifacts due to its lightweight and flexible properties. However, the PVDF ultrasonic sensor has a relatively weak transmitting acoustic signal strength which causes poor signal-to-noise ratio of the ultrasonic signal acquired in pulse-echo measurements, particularly for the signal reflected from deeper tissue. This paper investigated an improvement of the ultrasonic performance of the WUS using double-layer PVDF films. The sensor was constructed using two 52-μm thick PVDF films. The developed double-layer WUS showed the 1.7 times greater ultrasonic signal amplitude compared to the WUS made of a single-layer PVDF having the equivalent PVDF film thickness. Thus, the developed double-layer PVDF WUS improved the depth of the ultrasonic penetration into the tissue. The developed WUS successfully demonstrated to monitor the contractions of biceps muscles in an upper arm. In addition, a cardiac tissue motion was clearly observed in the M-mode measurement corresponding with the cardiac cycles obtained from the ECG measurement.

In this paper we present a novel type of sensing technology for hand and finger gesture recognition that utilizes light in the invisible spectrum to detect changes in position and form of body tissue like tendons and muscles. The proposed system can be easily integrated with existing wearable devices. Our approach not only enables gesture recognition but it could potentially double to perform a variety of health related monitoring tasks (e.g. heart rate, stress).

State-of-the-art carbon nanotube field-effect transistors (CNFETs) behave as Schottky-barrier-modulated transistors. It is known that vertical scaling of the gate oxide significantly improves the performance of these devices. However, decreasing the oxide thickness also results in pronounced ambipolar transistor characteristics and increased drain leakage currents. Using a novel device concept, we have fabricated high-performance enhancement-mode CNFETs exhibiting n- or p-type unipolar behavior, tunable by electrostatic and/or chemical doping, with excellent OFF-state performance and a steep subthreshold swing (S=63 mV/dec). The device design allows for aggressive oxide thickness and gate-length scaling while maintaining the desired device characteristics.

This paper proposed a multimodal fusion between brain and peripheral signals for emotion detection. The input signals were electroencephalogram, galvanic skin resistance, temperature, blood pressure and respiration, which can reflect the influence of emotion on the central nervous system and autonomic nervous system respectively. The acquisition protocol is based on a subset of pictures which correspond to three specific areas of valance-arousal emotional space (positively excited, negatively excited, and calm). The features extracted from input signals, and to improve the results, correlation dimension as a strong nonlinear feature is used for brain signals. The performance of the Quadratic Discriminant Classifier has been evaluated on different feature sets: peripheral signals, EEG's, and both. In comparison among the results of different feature sets, EEG signals seem to perform better than other physiological signals, and the results confirm the interest of using brain signals as peripherals in emotion assessment. According to the improvement in EEG results compare in each raw of the table, it seems that nonlinear features would lead to better understanding of how emotional activities work.

We have developed a multichannel electrogmyography sensor system capable of receiving and processing signals from up to 32 implanted myoelectric sensors (IMES). The appeal of implanted sensors for myoelectric control is that electromyography (EMG) signals can be measured at their source providing relatively cross-talk-free signals that can be treated as independent control sites. An external telemetry controller receives telemetry sent over a transcutaneous magnetic link by the implanted electrodes. The same link provides power and commands to the implanted electrodes. Wireless telemetry of EMG signals from sensors implanted in the residual musculature eliminates the problems associated with percutaneous wires, such as infection, breakage, and marsupialization. Each implantable sensor consists of a custom-designed application-specified integrated circuit that is packaged into a biocompatible RF BION capsule from the Alfred E. Mann Foundation. Implants are designed for permanent long-term implantation with no servicing requirements. We have a fully operational system. The system has been tested in animals. Implants have been chronically implanted in the legs of three cats and are still completely operational four months after implantation.

Recently MEMS Capacitive Pressure Sensor gains more advantage over micromachined piezoresistive pressure sensor due to high sensitivity, low power consumption, free from temperature effects, IC compatibility, etc,. The spectrum of capacitive pressure sensor application is increasing, hence it is essential to review the path of technological development and further prospective of micromachined capacitive pressure sensor. This paper focuses on the review of various types of capacitive pressure sensor principle, MEMS materials used in fabrication, procedures adopted in microfabrication for silicon and polymer material diaphragm, bonding and packaging techniques used. Selected result on capacitive sensitivity, effect of temperature on capacitive sensitivity was also presented. Finally, the development of smart sensor was discussed. MEMS Capacitive pressure sensor, Review on pressure sensor, CDPS, MEMS Fabrication, MEMS Material, pressure sensor, MEMS (Micro Electro Mechanical System)

A contact lens (CL) biosensor for in situ monitoring of tear glucose was fabricated and tested. Biocompatible 2-methacryloyloxyethyl phosphorylcholine (MPC) polymer and polydimethyl siloxane (PDMS) were employed as the biosensor material. The biosensor consists of a flexible Pt working electrode and a Ag/AgCl reference/counter electrode, which were formed by micro-electro-mechanical systems (MEMS) technique. The electrode at the sensing region was modified with glucose oxidase (GOD). The CL biosensor showed a good relationship between the output current and glucose concentration in a range of 0.03-5.0mM, with a correlation coefficient of 0.999. The calibration range covered the reported tear glucose concentrations in normal and diabetic patients. Also, the CL biosensor was applied to a rabbit for the purpose of tear glucose monitoring. The basal tear glucose was estimated to 0.11 mM. Also, the change of tear glucose induced by the change of blood sugar level was assessed by the oral glucose tolerance test. As a result, tear glucose level increased with a delay of 10 min from blood sugar level. The result showed that the CL biosensor is expected to provide further detailed information about the relationship between dynamics of blood glucose and tear glucose.

Herein, the fabrication of all-organic conductive wires is demonstrated by utilizing patterning techniques such as inkjet printing and sponge stencil to apply poly(3,4-ethylenedioxythiophene) polystyrenesulfonate (PEDOT:PSS) onto nonwoven polyethylene terephthalate (PET) fabric. The coating of the conducting polymer is only present on the surface of the substrate (penetration depth ∼ 200 μm) to retain the functionality and wearability of the textile. The wires fabricated by different patterning techniques provide a wide range of resistance, i.e., tens of kΩ/□ to less than 2 Ω/□ that allows the resistance to be tailored to a specific application. The sheet resistance is measured to be as low as 1.6 Ω/□, and the breakdown current is as high as 0.37 A for a 1 mm wide line. The specific breakdown current exceeds the previously reported values of macroscopic carbon nanotube based materials. Simple circuits composed of the printed wires are demonstrated, and resistance of the circuit from the measurement agrees with the calculated value based on Kirchhoff's rules. Additionally, the printed PEDOT:PSS wires show less than 6.2% change in sheet resistance after three washing and drying cycles using detergent.

A liquid leakage sensor on adhesive tape with alarming function has been developed. The film sensor tape consists of three layers: a base film layer, a substrate film layer, and a protective film layer. Three conductive lines and one resistive line are printed on the substrate film layer with a nano-sized silver conductive ink by the electronic gravure printing method. The location of liquid leakage has been found to be monitored accurately by applying the pulse voltage to the conductive and resistance lines in a periodic polarity switching mode. The leakage tests for various electrolyte liquids have been performed and the accuracy of leakage error position has been achieved to be about 0.25% on 200 meter long tape length.


Question: A self-adhesive, capacitive carbon nanotube electrode for recording electroencephalograph signals from hairy scalp regions.

This paper details an exploratory investigation into recognizing emotional states from speech to enhance multimedia content. With the growing prevalence of computer-generated characters like avatars and virtual chatbots, the ability to convey emotion through these digital personas becomes increasingly significant. The research employs a dataset of 721 short speech clips, manually collected from films and television scripts, which encapsulate four distinct emotional states: anger, happiness, sadness, and a neutral, emotionless condition. A novel perspective on emotion evaluation in speech is introduced, acknowledging the complexity of emotions and their often-blended nature in human speech. Despite the difficulty in precisely categorizing speech into singular emotional categories, the majority of emotional states can be effectively described as a blend of multiple emotions. Drawing on this insight, support vector machines (SVMs) are trained to discern utterances within the four defined categories. This method enables the development of an agent capable of not only recognizing but also expressing a nuanced range of emotions, significantly enriching the interaction and content of multimedia experiences.

Electronic Textiles (e-textiles) are fabrics that feature electronics and interconnections woven into them, presenting physical flexibility and typical size that cannot be achieved with other existing electronic manufacturing techniques. Components and interconnections are intrinsic to the fabric and thus are less visible and not susceptible of becoming tangled or snagged by surrounding objects. E-textiles can also more easily adapt to fast changes in the computational and sensing requirements of any specific application, this one representing a useful feature for power management and context awareness. The vision behind wearable computing foresees future electronic systems to be an integral part of our everyday outfits. Such electronic devices have to meet special requirements concerning wearability. Wearable systems will be characterized by their ability to automatically recognize the activity and the behavioral status of their own user as well as of the situation around her/him, and to use this information to adjust the systems' configuration and functionality. This review focuses on recent advances in the field of Smart Textiles and pays particular attention to the materials and their manufacturing process. Each technique shows advantages and disadvantages and our aim is to highlight a possible trade-off between flexibility, ergonomics, low power consumption, integration and eventually autonomy.

The current paper presents low-power analog integrated circuits (ICs) for wireless electrocardiogram (ECG) detection in personal health monitoring. Considering the power-efficient communication in the body sensor network (BSN), the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. The proposed system comprises the design and implementation with three subsystems, namely, (1) the ECG acquisition node, (2) the protocol for standard IEEE 802.15.4 ZigBee system, and (3) the radio frequency (RF) transmitter circuits. A preamplifier, a low-pass filter, and a successive-approximation analog-to-digital converter (SA-ADC) are integrated to detect an ECG signal. For high integration, the ZigBee protocol is adopted for wireless communication. To transmit the ECG signal through wireless communication, a quadrature voltage-controlled oscillator and a 2.4 GHz low-IF transmitter with a power amplifier and up-conversion mixer are also developed. In the receiver, a 2.4 GHz fully integrated CMOS radio-frequency front-end with a low-noise amplifier, and a quadrature mixer is proposed. The low-power wireless bio-signal acquisition SoC (WBSA-SoC) has been implemented in TSMC 0.18-μm standard CMOS process. The measurement results on the human body reveal that the ECG signals can be acquired effectively by the proposed SoC.

A novel integrated power unit realizes both energy harvesting and energy storage by a textile triboelectric nanogenerator (TENG)-cloth and a flexible lithium-ion battery (LIB) belt, respectively. The mechanical energy of daily human motion is converted into electricity by the TENG-cloth, sustaining the energy of the LIB belt to power wearable smart electronics.

This brief presents a design strategy for a neural recording amplifier array with ultralow-power low-noise operation that is suitable for large-scale integration. The topology combines a highly efficient but supply-sensitive single-ended first stage with a shared reference channel and a differential second stage to effect feedforward supply noise cancellation, combining the low power of single-ended amplifiers with improved supply rejection. For a two-channel amplifier, the measurements show a midband gain of 58.7 dB and a passband from 490 mHz to 10.5 kHz. The amplifier consumes 2.85 μA per channel from a 1-V supply and exhibits an input-referred noise of 3.04 μVrms from 0.1 Hz to 100 kHz, corresponding to a noise efficiency factor of 1.93. The power supply rejection ratio is better than 50 dB in the passband. The amplifier is fabricated in a 90-nm CMOS process and occupies 0.137 mm2 of chip area.

Current touch input technologies are best suited for small and flat applications, such as smartphones, tablets and kiosks. In general, they are too expensive to scale to large surfaces, such as walls and furniture, and cannot provide input on objects having irregular and complex geometries, such as tools and toys. We introduce Electrick, a low-cost and versatile sensing technique that enables touch input on a wide variety of objects and surfaces, whether small or large, flat or irregular. This is achieved by using electric field tomography in concert with an electrically conductive material, which can be easily and cheaply added to objects and surfaces. We show that our technique is compatible with commonplace manufacturing methods, such as spray/brush coating, vacuum forming, and casting/molding enabling a wide range of possible uses and outputs. Our technique can also bring touch interactivity to rapidly fabricated objects, including those that are laser cut or 3D printed. Through a series of studies and illustrative example uses, we show that Electrick can enable new interactive opportunities on a diverse set of objects and surfaces that were previously static.

OBJECTIVE
Brain-computer interfaces (BCI) enable direct communication with a computer, using neural activity as the control signal. This neural signal is generally chosen from a variety of well-studied electroencephalogram (EEG) signals. For a given BCI paradigm, feature extractors and classifiers are tailored to the distinct characteristics of its expected EEG control signal, limiting its application to that specific signal. Convolutional neural networks (CNNs), which have been used in computer vision and speech recognition to perform automatic feature extraction and classification, have successfully been applied to EEG-based BCIs; however, they have mainly been applied to single BCI paradigms and thus it remains unclear how these architectures generalize to other paradigms. Here, we ask if we can design a single CNN architecture to accurately classify EEG signals from different BCI paradigms, while simultaneously being as compact as possible.

APPROACH
In this work we introduce EEGNet, a compact convolutional neural network for EEG-based BCIs. We introduce the use of depthwise and separable convolutions to construct an EEG-specific model which encapsulates well-known EEG feature extraction concepts for BCI. We compare EEGNet, both for within-subject and cross-subject classification, to current state-of-the-art approaches across four BCI paradigms: P300 visual-evoked potentials, error-related negativity responses (ERN), movement-related cortical potentials (MRCP), and sensory motor rhythms (SMR).

MAIN RESULTS
We show that EEGNet generalizes across paradigms better than, and achieves comparably high performance to, the reference algorithms when only limited training data is available across all tested paradigms. In addition, we demonstrate three different approaches to visualize the contents of a trained EEGNet model to enable interpretation of the learned features.

SIGNIFICANCE
Our results suggest that EEGNet is robust enough to learn a wide variety of interpretable features over a range of BCI tasks. Our models can be found at: https://github.com/vlawhern/arl-eegmodels.

Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene.

Electrodermal activity (EDA) is now the preferred term for changes in electrical conductance of the skin, including phasic changes that have been referred to as galvanic skin responses (GSR), that result from sympathetic neuronal activity. EDA is a sensitive psychophysiological index of changes in autonomic sympathetic arousal that are integrated with emotional and cognitive states. Until recently there was little direct knowledge of brain mechanisms governing generation and control of EDA in humans. However, studies of patients with discrete brain lesions and, more recently, functional imaging techniques have clarified the contribution of brain regions implicated in emotion, attention, and cognition to peripheral EDA responses. Moreover, such studies enable an understanding of mechanisms by which states of bodily arousal, indexed by EDA, influence cognition and bias motivational behavior.

The next generation of implantable high-power neuroprosthetic devices such as visual prostheses and brain computer interfaces are going to be powered by transcutaneous inductive power links formed between a pair of printed spiral coils (PSC) that are batch-fabricated using micromachining technology. Optimizing the power efficiency of the wireless link is imperative to minimize the size of the external energy source, heating dissipation in the tissue, and interference with other devices. Previous design methodologies for coils made of 1-D filaments are not comprehensive and accurate enough to consider all geometrical aspects of PSCs with planar 3-D conductors as well as design constraints imposed by implantable device application and fabrication technology. We have outlined the theoretical foundation of optimal power transmission efficiency in an inductive link, and combined it with semi-empirical models to predict parasitic components in PSCs. We have used this foundation to devise an iterative PSC design methodology that starts with a set of realistic design constraints and ends with the optimal PSC pair geometries. We have executed this procedure on two design examples at 1 and 5 MHz achieving power transmission efficiencies of 41.2% and 85.8%, respectively, at 10-mm spacing. All results are verified with simulations using a commercial field solver (HFSS) as well as measurements using PSCs fabricated on printed circuit boards.

Brain Computer Interface (BCI) has been recently increased in research. Functional Near Infrared Spectroscope (fNIRs) is one the latest technologies which utilize light in the near-infrared range to determine brain activities. Because near infrared technology allows design of safe, portable, wearable, non-invasive and wireless qualities monitoring systems, fNIRs monitoring of brain hemodynamics can be value in helping to understand brain tasks. In this paper, we present results of fNIRs signal analysis indicating that there exist distinct patterns of hemodynamic responses which recognize brain tasks toward developing a BCI. We applied two different mathematics tools separately, Wavelets analysis for preprocessing as signal filters and feature extractions and Neural networks for cognition brain tasks as a classification module. We also discuss and compare with other methods while our proposals perform better with an average accuracy of 99.9% for classification. Keywords—functional near infrared spectroscope (fNIRs), braincomputer interface (BCI), wavelets, neural networks, brain activity, neuroimaging.


Question: Area, power, and latency factors to consider for STT-MRAM as a replacement for main memory.

This paper investigates the potential of using Spin-Transfer Torque Random Access Memory (STT-RAM) as a viable alternative to Dynamic Random Access Memory (DRAM) in main memory systems. The primary objective is to achieve performance parity with DRAM while significantly reducing power consumption. To this end, we conduct a comprehensive analysis of STT-RAM's performance and energy efficiency, pinpointing key optimization strategies that can enhance its characteristics. Notably, we demonstrate that techniques such as partial write and row buffer write bypass can markedly improve STT-RAM's main memory performance and energy efficiency. Our experimental findings reveal that, with optimization, a STT-RAM main memory of equal capacity can match the performance of DRAM main memory, all while achieving an average 60% decrease in main memory energy consumption. This makes STT-RAM a compelling choice for energy-efficient main memory applications.

Power consumption is forecast by the International Technology Roadmap of Semiconductors (ITRS) to pose long-term technical challenges for the semiconductor industry. The purpose of this paper is threefold: (1) to provide an overview of strategies for powering MEMS via non-regenerative and regenerative power supplies; (2) to review the fundamentals of piezoelectric energy harvesting, along with recent advancements, and (3) to discuss future trends and applications for piezoelectric energy harvesting technology. The paper concludes with a discussion of research needs that are critical for the enhancement of piezoelectric energy harvesting devices. (Some figures in this article are in colour only in the electronic version)

In a memristor crossbar array, a memristor is positioned on each row-column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this work, we study the sneak path problem in crossbars arrays, in which current can sneak through other cells, resulting in reading a wrong state of the memristor. Our main contributions are a new characterization of arrays free of sneak paths, and efficient methods to read the array cells while avoiding sneak paths. To each read method we match a constraint on the array content that guarantees sneak-path free readout, and calculate the resulting capacity.

The random telegraph noise (RTN) related read instability in resistive random access memory (RRAM) is evaluated by employing the RTN peak-to-peak (P-p) amplitude as a figure of merit (FoM). Variation of the FoM value over multiple set/reset cycles is found to follow the log-normal distribution. P-p decreases with the reduction of the read current, which allows scaling of the RRAM operating current. The RTN effect is attributed to the mechanism of activation/deactivation of the electron traps in (in HRS) or near (in LRS) the filament that affects the current through the RRAM device.

Errors in dynamic random access memory (DRAM) are a common form of hardware failure in modern compute clusters. Failures are costly both in terms of hardware replacement costs and service disruption. While a large body of work exists on DRAM in laboratory conditions, little has been reported on real DRAM failures in large production clusters. In this paper, we analyze measurements of memory errors in a large fleet of commodity servers over a period of 2.5 years. The collected data covers multiple vendors, DRAM capacities and technologies, and comprises many millions of DIMM days.
 The goal of this paper is to answer questions such as the following: How common are memory errors in practice? What are their statistical properties? How are they affected by external factors, such as temperature and utilization, and by chip-specific factors, such as chip density, memory technology and DIMM age?
 We find that DRAM error behavior in the field differs in many key aspects from commonly held assumptions. For example, we observe DRAM error rates that are orders of magnitude higher than previously reported, with 25,000 to 70,000 errors per billion device hours per Mbit and more than 8% of DIMMs affected by errors per year. We provide strong evidence that memory errors are dominated by hard errors, rather than soft errors, which previous work suspects to be the dominant error mode. We find that temperature, known to strongly impact DIMM error rates in lab conditions, has a surprisingly small effect on error behavior in the field, when taking all other factors into account. Finally, unlike commonly feared, we don't observe any indication that newer generations of DIMMs have worse error behavior.

Physically Unclonable Functions (PUFs) are commonly used in cryptography to identify devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have numerous advantages over PUF designs that exploit alternative substrates: DRAM is a major component of many modern systems, and a DRAM-based PUF can generate many unique identiers. However, none of the prior DRAM PUF proposals provide implementations suitable for runtime-accessible PUF evaluation on commodity DRAM devices. Prior DRAM PUFs exhibit unacceptably high latencies, especially at low temperatures (e.g., >125.8s on average for a 64KiB memory segment below 55C), and they cause high system interference by keeping part of DRAM unavailable during PUF evaluation. In this paper, we introduce the DRAM latency PUF, a new class of fast, reliable DRAM PUFs. The key idea is to reduce DRAM read access latency below the reliable datasheet specications using software-only system calls. Doing so results in error patterns that reect the compound eects of manufacturing variations in various DRAM structures (e.g., capacitors, wires, sense ampli- ers). Based on a rigorous experimental characterization of 223 modern LPDDR4 DRAM chips, we demonstrate that these error patterns 1) satisfy runtime-accessible PUF requirements, and 2) are quickly generated (i.e., at 88.2ms) irrespective of operating temperature using a real system with no additional hardware modications. We show that, for a constant DRAM capacity overhead of 64KiB, our implementation of the DRAM latency PUF enables an average (minimum, maximum) PUF evaluation time speedup of 152x (109x, 181x) at 70C and 1426x (868x, 1783x) at 55C when compared to a DRAM retention PUF and achieves greater speedups at even lower temperatures.

FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive current. We investigate in this paper gate sizing of finFET devices, and we provide a comparison with 32nm bulk CMOS. Wider finFET devices are built utilizing multiple parallel fins between the source and drain. Independent gating of the finFET's double gates allows significant reduction in leakage current. We perform temperature-aware circuit optimization by modeling delay using temperature-dependent parameters, and by imposing constraints that limit the maximum allowable number of parallel fins. We show that finFET circuits are superior in performance and produce less static power when compared to 32nm circuits.

This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10-100× smaller than the noise generated by a static CMOS circuit. Unlike static CMOS, whose dominant dynamic power is proportional to the frequency, MCML circuits dissipate a constant power independent of clock frequency. Although these traits make MCML highly energy efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at the modest clock rate and with a low activity factor. To address this challenge, a single-core microarchitecture for MCML is explored that exploits the C-slow retiming technique, and operates at a high frequency with low complexity to save energy. This design principle contrasts with the contemporary multicore design paradigm for static CMOS that relies on a large number of gates operating in parallel at the modest speeds. The proposed architecture generates 10-40× lower power and ground noise, and operates within 13% of the performance (i.e., 1/ExecutionTime) of a conventional, eight-core static CMOS processor while exhibiting 1.6× lower energy and 9% less area. Moreover, the operation of an MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length.

The device layout structure has proven to have profound effects to its electrical characteristics for advanced technology nodes, which, if not taken into account during the design cycle, will have devastating impact to the circuit functionality. A new design methodology is presented in this paper, which can help circuit designers identify early in the design stage the performance implication due to shift of critical device instance parameters from its layout.

While hybrid capacitive-resistive D/A Converter (DAC) has been known for many years, its potential for energy-efficient operation is sometimes overlooked. This paper investigates the utilization of hybrid DACs in successive-approximation register A/D converters. To improve energy efficiency of SAR ADCs, a new hybrid DAC is introduced. In an exemplar 10-bit 100-MS/s ADC, simulation results show that the energy efficiency and chip area (of passive devices) can be improved by more than an order of magnitude.

In this brief, we propose a novel level shifter circuit that is capable of converting subthreshold to above-threshold signal levels. In contrast to other existing implementations, it does not require a static current flow and can therefore offer considerable static power savings. The circuit has been optimized and simulated in a 90-nm process technology. It operates correctly across process corners for supply voltages from 100 mV to 1 V on the low-voltage side. At the target design voltage of 200 mV, the level shifter has a propagation delay of 18.4 ns and a static power dissipation of 6.6 nW. For a 1-MHz input signal, the total energy per transition is 93.9 fJ. Simulation results are compared to an existing subthreshold to above-threshold level shifter implementation from the paper of Chen et al.


Question: Area, power, and latency aspects of employing STT-MRAM as a replacement for primary memory.

This paper presents an in-depth exploration of phase change memory (PCM) as a viable substitute for dynamic random-access memory (DRAM) in addressing the challenges posed by memory scaling. As traditional memory technologies like DRAM face limitations due to unreliability in charge storage and sensing at smaller scales, PCM emerges as a promising alternative, relying on current and thermal mechanisms that scale more effectively. To harness PCM's potential as a DRAM replacement, architectural modifications must be considered to tackle its inherent drawbacks, including longer access latencies, high write energy consumption, and limited endurance.
We introduce architectural enhancements for PCM, developed with a thorough understanding of its technological parameters, that aim to mitigate these limitations and enhance its competitiveness with DRAM. Without such enhancements, a basic PCM system operates at 1.6 times the latency and consumes 2.2 times the energy compared to a DRAM system. However, by implementing buffer reorganizations and optimizing row design—employing narrower rows to lower write energy and multiple rows to enhance locality and write coalescing—the latency and energy gap is narrowed to 1.2 times and equalized, respectively. Additionally, partial writes are utilized to improve memory endurance, extending the lifetime to 5.6 years. It is further anticipated that advancements in process scaling will contribute to reducing PCM's energy costs and enhancing its endurance, making it a more compelling option for main memory systems.

Energy-proportional designs would enable large energy savings in servers, potentially doubling their efficiency in real-life use. Achieving energy proportionality will require significant improvements in the energy usage profile of every system component, particularly the memory and disk subsystems.

Our analysis shows that many "big-memory" server workloads, such as databases, in-memory caches, and graph analytics, pay a high cost for page-based virtual memory. They consume as much as 10% of execution cycles on TLB misses, even using large pages. On the other hand, we find that these workloads use read-write permission on most pages, are provisioned not to swap, and rarely benefit from the full flexibility of page-based virtual memory.
 To remove the TLB miss overhead for big-memory workloads, we propose mapping part of a process's linear virtual address space with a direct segment, while page mapping the rest of the virtual address space. Direct segments use minimal hardware---base, limit and offset registers per core---to map contiguous virtual memory regions directly to contiguous physical memory. They eliminate the possibility of TLB misses for key data structures such as database buffer pools and in-memory key-value stores. Memory mapped by a direct segment may be converted back to paging when needed.
 We prototype direct-segment software support for x86-64 in Linux and emulate direct-segment hardware. For our workloads, direct segments eliminate almost all TLB misses and reduce the execution time wasted on TLB misses to less than 0.5%.

In recent years, deep neural networks (DNN) have demonstrated significant business impact in large scale analysis and classification tasks such as speech recognition, visual object detection, pattern extraction, etc. Training of large DNNs, however, is universally considered as time consuming and computationally intensive task that demands datacenter-scale computational resources recruited for many days. Here we propose a concept of resistive processing unit (RPU) devices that can potentially accelerate DNN training by orders of magnitude while using much less power. The proposed RPU device can store and update the weight values locally thus minimizing data movement during training and allowing to fully exploit the locality and the parallelism of the training algorithm. We evaluate the effect of various RPU device features/non-idealities and system parameters on performance in order to derive the device and system level specifications for implementation of an accelerator chip for DNN training in a realistic CMOS-compatible technology. For large DNNs with about 1 billion weights this massively parallel RPU architecture can achieve acceleration factors of 30, 000 × compared to state-of-the-art microprocessors while providing power efficiency of 84, 000 GigaOps∕s∕W. Problems that currently require days of training on a datacenter-size cluster with thousands of machines can be addressed within hours on a single RPU accelerator. A system consisting of a cluster of RPU accelerators will be able to tackle Big Data problems with trillions of parameters that is impossible to address today like, for example, natural speech recognition and translation between all world languages, real-time analytics on large streams of business and scientific data, integration, and analysis of multimodal sensory data flows from a massive number of IoT (Internet of Things) sensors.

A novel sensing current protection enhanced (SCPE) technique and high-voltage (HV) generating systems are adopted to greatly enhance the advantages of the twin-bit cell. The SCPE technique provides the tradeoff of sensing margin loss between “1” and “0” bits sensing case to realize fast read access. The read speed is improved by 7.7%. HV generating systems with parallel-series-transform and capacitance-shared techniques are proposed to satisfy the complicated requirements of output capability and current drivability with lower area penalty. The HV periphery area decreases by 71%. A 1.5-V 280-KBytes embedded NOR flash memory IP has been fabricated in HHGrace (Shanghai Huahong Grace Semiconductor Manufacturing Corporation) 90-nm 4 poly 4 metal CMOS process. The complicated operation voltages and access time of 23.5 ns have been achieved at 1.5 V. The die size of the proposed IP is 0.437 mm<inline-formula> <tex-math notation="LaTeX">$^{2}$ </tex-math></inline-formula> and the area size of charge pump has been reduced to 0.006 mm<inline-formula> <tex-math notation="LaTeX">$^{2}$ </tex-math></inline-formula> on average.

以容忍。还有一点让人印象深刻: 对于不同的程序,这些提升和能 耗降低并不需要使用不同的加速 器实现方式——它们通过相同的 近似加速器得到,那些加速器可 用于所有程序中所有类型的可近 似代码区。 除了文中描述的之外,通过让 近似计算引擎在明显低得多的电压 下运行,还能节约更多的能源。业 界增长的真正引擎——登纳德缩放 (Dennard scaling)——允许晶体 管减少尺寸,同时消耗更少的能源, 得到更高的性能。但是登纳德缩放 正趋近极限。设备的尺寸已经缩减 到了原子级别。而且,在不牺牲设 备可靠性的情况下,无法继续显著 降低电压。新技术会带来不错的能 耗性能,但由于需要利用冗余来补 偿它们的不可靠性,这一优势被抵 消了。因此,对于传统的交易系统 而言,未来的技术不大可能大幅提 升其能耗性能。然而,对于那些生 成近似结果的系统(比如作者描述 的系统),需要的冗余可能有所不 同且要简单得多。对于这些系统类 型,低电压运行是可行的。 未 来, 当 我 们 使 用 缩 小 的 CMOS 和后硅技术,利用海量计算 处理世上产生的海量数据时,近似 计算似乎是我们最有可能取得成功 的希望。下面的文章就是为实现此 目标所需开展的工作的一个很好的 例子。

Backup and recovery is an important feature of database systems since it protects data against unexpected hardware and software failures. Database systems can provide data safety and reliability by creating a backup and restoring the backup from a failure. Database administrators can use backup/recovery tools that are provided with database systems or backup/recovery methods with operating systems. However, the existing tools perform time-consuming jobs and the existing methods may negatively affect run-time performance during normal operation even though high-performance SSDs are used. In this paper, we present an SSD-assisted backup/recovery scheme for database systems. In our scheme, we extend the out-of-place update characteristics of flash-based SSDs for backup/recovery operations. To this end, we exploit the resources (e.g., flash translation layer and DRAM cache with supercapacitors) inside SSDs, and we call our SSD with new backup/recovery features BR-SSD. We design and implement the backup/recovery functionality in the Samsung enterprise-class SSD (i.e., SM843Tn) for more realistic systems. Furthermore, we conduct a case study of BR-SSDs in replicated database systems and modify MySQL with replication to integrate BR-SSDs. The experimental result demonstrates that our scheme provides fast recovery while it does not negatively affect the run-time performance during normal operation.

We present a new advanced 0.18um BCD(Bipolar-CMOS-DMOS) technology with the key features being a 40V HV-MOS and an SSTC(Sidewall Selective Transistor Cell) type EEPROM as well as complimentary available analog devices such as a high gain BJT, 4fF/um2 MIM capacitor, and 10k Ω/sq. poly resistor. To reduce device area and enhance latch up immunity, a 15um depth deep trench isolation process has been developed, which will help to significantly reduce the chip size.

Memory-augmented recurrent neural networks (M-RNNs) have demonstrated empirically that they are very attractive for many applications, but a good theoretical understanding of their behaviors is unclear yet. In this paper, three analytical indicators named duration, addressability, and capacity of general forms of the additional memory in M-RNNs are formalized. The analysis results of the interactions among these indicators reveal that it is hard for an M-RNN to simultaneously provide good performance on more than two out of three of indicators. Meanwhile, the duration, addressability, and capacity are applied to analyze and compare two M-RNNs: long short term memory and neural turing machine for different cases. The comparison results show that none of the models has better performance on one indicator than the other model all the time. Moreover, it is found that separating memory system into sub-memories can bring the increasing duration and addressability and the decreasing capacity for the whole memory system.

A comprehensive analysis of write operations (SET and RESET) in a resistance-change memory (resistive random access memory) crossbar array is carried out. Three types of resistive switching memory cells-nonlinear, rectifying-SET, and rectifying-RESET-are compared with each other in terms of voltage delivery, current delivery, and power consumption. Two different write schemes, V/2 and V/3, were considered, and the V/2 write scheme is preferred due to much lower power consumption. A simple numerical method was developed that simulates entire current flows and node voltages within a crossbar array and provides a quantitative tool for the accurate analysis of crossbar arrays and guidelines for developing reliable write operation.

In a memristor crossbar array, a memristor is positioned on each row-column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this work, we study the sneak path problem in crossbars arrays, in which current can sneak through other cells, resulting in reading a wrong state of the memristor. Our main contributions are a new characterization of arrays free of sneak paths, and efficient methods to read the array cells while avoiding sneak paths. To each read method we match a constraint on the array content that guarantees sneak-path free readout, and calculate the resulting capacity.


Question: Area, power, and latency aspects of utilizing STT-MRAM as a replacement for primary memory.

This paper introduces a groundbreaking nonvolatile memory technology, coined as Spin-RAM, which employs spin torque transfer magnetization switching (STS) as its operational mechanism. Spin-RAM is a departure from traditional MRAM (Magnetoresistive Random Access Memory), as it achieves programming through the interaction of a current-induced spin momentum torque with the magnetic moment in magnetic tunnel junctions (MTJs), eliminating the need for an external magnetic field. This innovative programming method was made possible by the unique design of our MTJ, featuring an oval shape measuring 100x150 nm. The memory cell architecture is based on a single transistor and a single MTJ (1T1MTJ) configuration. The 4kbit prototype of Spin-RAM was developed using a 4-level metal, 0.18 μm CMOS process. Our findings showcase exceptional performance, including a write speed of 2 ns and a write current as low as 200 μA. These attributes affirm Spin-RAM's potential as a high-speed, low-power, and highly scalable solution for next-generation universal memory applications, making it a compelling alternative to traditional main memory technologies.

The high-speed interface of DQ pins in DDR3 DRAM requires special ESD considerations. During ESD characterization testing, high voltages from the power rail could pass through the pre-driver PMOSFET to damage the pull-down NMOSFET gate oxide. Special circuit design of the pre-driver circuit is required to eliminate this ESD failure mechanism.

With the increasing clock rate and transistor count of today’s microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and power-delivery issues are becoming especially critical for high-performance computing systems. In this work, we investigate dynamic thermal management as a technique to control CPUpower dissipation. With the increasing usage of clock gating techniques, the average power dissipation typically seen by common applications is becoming much less than the chip’s rated maximum power dissipation. However; system designers still must design thermal heat sinks to withstand the worst-case scenario. We define and investigate the major components of any dynamic thermal management scheme. Specijcally we explore the tradeoffs between several mechanisms for responding to periods of thermal trauma and we consider the effects of hardware and sofnyare implementations. With appropriate dynamic thermal management, the CPU can be designed for a much lower maximum power rating, with minimal performance impact for typical applications.

This paper presents a recursive digital low-dropout (RLDO) regulator that improves response time, quiescent power, and load regulation dynamic range over prior digital LDO designs by 1–2 orders of magnitude. The proposed RLDO enables a practical digital replacement to analog LDOs by using an SAR-like binary search algorithm in a coarse loop and a sub-LSB pulse width modulation duty control scheme in a fine loop. A proportional-derivative compensation scheme is employed to ensure stable operation independent of load current, the size of the output decoupling capacitor, and clock frequency. Implemented in 0.0023 mm2 in 65 nm CMOS, the 7-bit RLDO achieves, at a 0.5-V input, a response time of 15.1 ns with a figure of merit of 199.4 ps, along with stable operation across a 20 000 $\times $  dynamic load range.

Hard real-time embedded systems employ high-capacity memories such as Dynamic RAMs (DRAMs) to cope with increasing data and code sizes of modern designs. However, memory controller design has so far largely focused on improving average-case performance. As a consequence, the latency of memory accesses is unpredictable, which complicates the worst-case execution time analysis necessary for hard real-time embedded systems.
 Our work introduces a novel DRAM controller design that is predictable and that significantly reduces worst-case access latencies. Instead of viewing the DRAM device as one resource that can only be shared as a whole, our approach views it as multiple resources that can be shared between one or more clients individually. We partition the physical address space following the internal structure of the DRAM device, i.e., its ranks and banks, and interleave ac- cesses to the blocks of this partition. This eliminates contention for shared resources within the device, making accesses temporally predictable and temporally isolated. This paper describes our DRAM controller design and its integration with a precision-timed (PRET) architecture called PTARM. We present analytical bounds on the latency and throughput of the proposed controller, and confirm these via simulation.

Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. vi

An ultra-thin phase-change bridge (PCB) memory cell, implemented with doped GeSb, is shown with < 100muA RESET current. The device concept provides for simplified scaling to small cross-sectional area (60nm2) through ultra-thin (3nm) films; the doped GeSb phase-change material offers the potential for both fast crystallization and good data retention

In a memristor crossbar array, a memristor is positioned on each row-column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this work, we study the sneak path problem in crossbars arrays, in which current can sneak through other cells, resulting in reading a wrong state of the memristor. Our main contributions are a new characterization of arrays free of sneak paths, and efficient methods to read the array cells while avoiding sneak paths. To each read method we match a constraint on the array content that guarantees sneak-path free readout, and calculate the resulting capacity.

Emerging 3D stacked memory systems provide significantly more bandwidth than current DDR modules. However, general purpose processors do not take full advantage of these resources offered by the memory modules. Taking advantage of the increased bandwidth requires the use of specialized processing units. In this paper, we evaluate the benefits of placing hardware accelerators at the bottom layer of a 3D stacked memory system compared to accelerators that are placed external to the memory stack. Our evaluation of the design using cycle-accurate simulation and RTL synthesis shows that, for important data intensive kernels, near-memory accelerators inside a single 3D memory package provide 3x-13x speedup over a Quad-core Xeon processor. Most of the benefits are from the application of accelerators, as the near-memory configurations provide marginal benefits compared to the same number of accelerators placed on a die external to the memory package. This comparable performance for external accelerators is due to the high bandwidth afforded by the high-speed off-chip links. On the other hand, near-memory accelerators consume 7%-39% less energy than the external accelerators.

Energy-proportional designs would enable large energy savings in servers, potentially doubling their efficiency in real-life use. Achieving energy proportionality will require significant improvements in the energy usage profile of every system component, particularly the memory and disk subsystems.

A power-on-reset (POR) circuit is extremely important in digital and mixed-signal ICs. It is used to initialize critical nodes of digital circuitry inside the chip during power-on. A novel POR circuit having zero quiescent current and an adjustable delay is proposed and demonstrated. The circuit has been designed in 0.5μm CMOS process to work for a supply voltage ranging from 1.8V to 5.5V. The circuit generates a POR signal after a predetermined delay, after the supply voltage crosses a predefined threshold voltage. This delay can be increased or decreased via programmable fuses. The POR threshold does not depend upon the supply ramp rate. The Brown-Out (BO) voltage for the proposed circuit matches the minimum supply voltage required by the digital circuitry inside the IC. The circuit consumes zero steady state current, making it ideal for low power applications.


Question: Considering area, power, and latency factors, evaluating STT-MRAM as a replacement for main memory.

This paper introduces an innovative ultra-thin phase-change bridge (PCB) memory cell utilizing doped GeSb, demonstrating operation with a remarkably low RESET current of less than 100 microamperes. The design philosophy behind this device enables straightforward scaling to significantly reduced cross-sectional dimensions, as small as 60 square nanometers, achieved through the use of ultra-thin films measuring just 3 nanometers in thickness. The choice of doped GeSb as the phase-change material holds promise for two critical aspects: rapid crystallization speeds and superior data retention capabilities. These features make the ultra-thin PCB memory cell a compelling candidate for advanced memory applications requiring both efficiency and reliability.

Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search primitives on network processors and even custom application-specific integrated circuits (ASICs), achieving tight bounds on worst case performance with standard memories often requires a very careful analysis of all possible access patterns. An alternative, and often times more simple solution, is possible if a ternary CAM (TCAM) is used to perform a fully parallel search across the entire data set. Unfortunately, this parallelism means that large portions of the chip are switching during each cycle, causing large amounts of power to be consumed. While researchers at all levels of design (from algorithms to circuits) have begun to explore new ways of managing the power consumption, quantifying design alternatives is difficult due to a lack of available models. In this paper, we examine the structure of a modern TCAM and present a simple, yet accurate, power and delay model. We present techniques to estimate the dynamic power consumption and leakage power of a TCAM structure and validate the model using a combination of industrial TCAM datasheets and prior published works. Such a model is a critical first step in bridging the intellectual divide between circuit-level and algorithm-level optimizations. To demonstrate the utility of our model, we present an extensive analysis of the model by varying various architectural parameters and describe how our model can be easily extended to handle several circuit optimizations in the TCAM structure. In addition, we present a comparative study of SRAM and TCAM energy consumption to directly quantify the many design options which will be very useful for network designers to explore various power management schemes.

The emergence of IoT (Internet of Things) has brought various studies on low-power techniques back to embedded systems. In general, minimizing power consumed by program executions is the main consideration of system design. While running programs, executing data-dependent program code results in a large number of memory accesses which consume huge amount of power. Further, most embedded systems consist of multiple types of memory devices, i.e., heterogeneous memory system, to benefit the different characteristics of memory devices. In this paper, we conduct a research on low-power techniques to reduce the power consumption of heterogeneous memory to achieve ultra-low-power in the system level. This study proposes a segment-aware energy-efficient management to improve the power efficiency considering the characteristics and structures of the memory devices. In the proposed approach, the technique migrates program code from allocated memory device to another if the consumed power is considered to be less. We also analyze and evaluate the comprehensive effects on energy efficiency by applying the technique as well. Compared to the unmodified program code, our model reduces power consumption up to 12.98% by migrating functions.

Energy-proportional designs would enable large energy savings in servers, potentially doubling their efficiency in real-life use. Achieving energy proportionality will require significant improvements in the energy usage profile of every system component, particularly the memory and disk subsystems.

Cobalt as a material promises to change the conductor landscape in many areas, particularly logic contact and interconnect. In this paper, we focus on Cobalt as the conductor for logic interconnect — a potential Cu replacement. We demonstrate Co fill capability down to 10nm CD, and show that Co-Cu resistivity cross-over will occur below 14nm CD. Single damascene Co-ULK structures are used to establish an optimized metallization stack with robust CMP performance that has electromigration and TDDB reliability better than copper interconnect.

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

In this article, a methodology to extract Flash EEPROM memory contents is presented. Samples are first backside prepared to expose the tunnel oxide of floating gate transistors. Then, a Scanning Electron Microscope (SEM) in the so called Passive Voltage Contrast (PVC) mode allows distinguishing ‘0’ and ‘1’ bit values stored in individual memory cell. Using SEM operator-free acquisition and standard image processing technique we demonstrate the possible automating of such technique over a full memory. The presented fast, efficient and low cost technique is successfully implemented on 0.35μm technology node microcontrollers and on a 0.21μm smart card type integrated circuit. The technique is at least two orders of magnitude faster than state-of-the-art Scanning Probe Microscopy (SPM) methods. Without adequate protection an adversary could obtain the full memory array content within minutes. The technique is a first step for reverse engineering secure embedded systems.

Long DRAM latency is a critical performance bottleneck in current systems. DRAM access latency is defined by three fundamental operations that take place within the DRAM cell array: (i) activation of a memory row, which opens the row to perform accesses; (ii) precharge, which prepares the cell array for the next memory access; and (iii) restoration of the row, which restores the values of cells in the row that were destroyed due to activation. There is significant latency variation for each of these operations across the cells of a single DRAM chip due to irregularity in the manufacturing process. As a result, some cells are inherently faster to access, while others are inherently slower. Unfortunately, existing systems do not exploit this variation.
 The goal of this work is to (i) experimentally characterize and understand the latency variation across cells within a DRAM chip for these three fundamental DRAM operations, and (ii) develop new mechanisms that exploit our understanding of the latency variation to reliably improve performance. To this end, we comprehensively characterize 240 DRAM chips from three major vendors, and make several new observations about latency variation within DRAM. We find that (i) there is large latency variation across the cells for each of the three operations; (ii) variation characteristics exhibit significant spatial locality: slower cells are clustered in certain regions of a DRAM chip; and (iii) the three fundamental operations exhibit different reliability characteristics when the latency of each operation is reduced.
 Based on our observations, we propose Flexible-LatencY DRAM (FLY-DRAM), a mechanism that exploits latency variation across DRAM cells within a DRAM chip to improve system performance. The key idea of FLY-DRAM is to exploit the spatial locality of slower cells within DRAM, and access the faster DRAM regions with reduced latencies for the fundamental operations. Our evaluations show that FLY-DRAM improves the performance of a wide range of applications by 13.3%, 17.6%, and 19.5%, on average, for each of the three different vendors' real DRAM chips, in a simulated 8-core system. We conclude that the experimental characterization and analysis of latency variation within modern DRAM, provided by this work, can lead to new techniques that improve DRAM and system performance.

This paper describes digital circuit architectures for automatic speech recognition (ASR) and voice activity detection (VAD) with improved accuracy, programmability, and scalability. Our ASR architecture is designed to minimize off-chip memory bandwidth, which is the main driver of system power consumption. A SIMD processor with 32 parallel execution units efficiently evaluates feed-forward deep neural networks (NNs) for ASR, limiting memory usage with a sparse quantized weight matrix format. We argue that VADs should prioritize accuracy over area and power, and introduce a VAD circuit that uses an NN to classify modulation frequency features with 22.3-<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power consumption. The 65-nm test chip is shown to perform a variety of ASR tasks in real time, with vocabularies ranging from 11 words to 145 000 words and full-chip power consumption ranging from 172 <inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> to 7.78 mW.

Defining a processor micro-architecture for a targeted productspace involves multi-dimensional optimization across performance, power and reliability axes. A key decision in sucha definition process is the circuit-and technology-driven parameterof the nominal (voltage, frequency) operating point. This is a challenging task, since optimizing individually orpair-wise amongst these metrics usually results in a designthat falls short of the specification in at least one of the threedimensions. Aided by academic research, industry has nowadopted early-stage definition methodologies that considerboth energy-and performance-related metrics. Reliabilityrelatedenhancements, on the other hand, tend to get factoredin via a separate thread of activity. This task is typically pursuedwithout thorough pre-silicon quantifications of the energyor even the performance cost. In the late-CMOS designera, reliability needs to move from a post-silicon afterthoughtor validation-only effort to a pre-silicon definitionprocess. In this paper, we present BRAVO, a methodologyfor such reliability-aware design space exploration. BRAVOis supported by a multi-core simulation framework that integratesperformance, power and reliability modeling capability. Errors induced by both soft and hard fault incidence arecaptured within the reliability models. We introduce the notionof the Balanced Reliability Metric (BRM), that we useto evaluate overall reliability of the processor across soft andhard error incidences. We demonstrate up to 79% improvementin reliability in terms of this metric, for only a 6% dropin overall energy efficiency over design points that maximizeenergy efficiency. We also demonstrate several real-life usecaseapplications of BRAVO in an industrial setting.

In this paper, we characterize a state-of-the-art 3D floating gate NAND flash memory through comprehensive experiments on an FPGA platform. Then, we present distinct observations on performance and reliability, such as operation latencies and various error patterns. We believe that through our work, novel 3D NAND flash-oriented designs can be developed to achieve better performance and reliability.


Question: Area, power, and latency factors in evaluating STT-MRAM as a replacement for main memory.

This paper explores the potential of phase-change random access memory (PCRAM) as a scalable technology for future storage-class memory, focusing on its ability to scale down in size to accommodate the shrinking dimensions of memory cells in upcoming technology nodes. Central to the success of PCRAM is its capacity to address critical challenges such as materials properties, power consumption during programming and read operations, thermal cross-talk between cells, and failure mechanisms. The authors delve into experimental findings that shed light on the scaling properties of phase-change materials, including the study of phase transitions in nanoparticles and ultrathin films, which are directly influenced by particle size and film thickness. These material investigations have led to the development of prototype PCRAM devices with remarkably small phase-change material cross-sections, as diminutive as 3 nm x 20 nm. The device measurements confirm the impressive scaling potential of this technology, aligning with predictions from comprehensive device simulations. Additionally, the paper touches upon the complexities of device integration and cell design, manufacturability, and reliability, highlighting the comprehensive approach to ensuring PCRAM's viability as a scalable memory solution.

This paper introduces an efficient technique called “stack processing” that can be used in the cost-performance evaluation of a large class of storage hierarchies. The technique depends on a classification of page replacement algorithms as “stack algorithms” for which various properties are derived. These properties may be of use in the general areas of program modeling and system analysis, as well as in the evaluation of storage hierarchies. For a better understanding of storage hierarchies, we briefly review some basic concepts of their design.

In recent years, deep neural networks (DNN) have demonstrated significant business impact in large scale analysis and classification tasks such as speech recognition, visual object detection, pattern extraction, etc. Training of large DNNs, however, is universally considered as time consuming and computationally intensive task that demands datacenter-scale computational resources recruited for many days. Here we propose a concept of resistive processing unit (RPU) devices that can potentially accelerate DNN training by orders of magnitude while using much less power. The proposed RPU device can store and update the weight values locally thus minimizing data movement during training and allowing to fully exploit the locality and the parallelism of the training algorithm. We evaluate the effect of various RPU device features/non-idealities and system parameters on performance in order to derive the device and system level specifications for implementation of an accelerator chip for DNN training in a realistic CMOS-compatible technology. For large DNNs with about 1 billion weights this massively parallel RPU architecture can achieve acceleration factors of 30, 000 × compared to state-of-the-art microprocessors while providing power efficiency of 84, 000 GigaOps∕s∕W. Problems that currently require days of training on a datacenter-size cluster with thousands of machines can be addressed within hours on a single RPU accelerator. A system consisting of a cluster of RPU accelerators will be able to tackle Big Data problems with trillions of parameters that is impossible to address today like, for example, natural speech recognition and translation between all world languages, real-time analytics on large streams of business and scientific data, integration, and analysis of multimodal sensory data flows from a massive number of IoT (Internet of Things) sensors.

In order to meet the stringent requirements of low latency as well as high throughput, web service providers with large data centers have been replacing magnetic disk drives with flash memory solid-state drives (SSDs). They commonly use relational and NoSQL database engines to manage OLTP workloads in the warehouse-scale computing environments. These modern database engines rely heavily on redundant writes and frequent cache flushes to guarantee the atomicity and durability of transactional updates. This has become a serious bottleneck of performance in both relational and NoSQL database engines. This paper presents a new SSD prototype called DuraSSD equipped with tantalum capacitors. The tantalum capacitors make the device cache inside DuraSSD durable, and additional firmware features of DuraSSD take advantage of the durable cache to support the atomicity and durability of page writes. It is the first time that a flash memory SSD with durable cache has been used to achieve an order of magnitude improvement in transaction throughput without compromising the atomicity and durability. Considering that the simple capacitors increase the total cost of an SSD no more than one percent, DuraSSD clearly provides a cost-effective means for transactional support. DuraSSD is also expected to alleviate the problem of high tail latency by minimizing write stalls.

Device reliability and manufacturability have emerged as dominant concerns in end-of-road CMOS devices. An increasing number of hardware failures are attributed to manufacturability or reliability problems. Maintaining an acceptable manufacturing yield for chips containing tens of billions of transistors with wide variations in device parameters has been identified as a great challenge. Additionally, today’s nanometer scale devices suffer from accelerated aging effects because of the extreme operating temperature and electric fields they are subjected to. Unless addressed in design, aging-related defects can significantly reduce the lifetime of a product. In this article, we investigate a micro-architectural scheme for improving yield and reliability of homogeneous chip multiprocessors (CMPs). The proposed solution involves a hardware framework that enables us to utilize the redundancies inherent in a multicore system to keep the system operational in the face of partial failures. A micro-architectural modification allows a faulty core in a CMP to use another core’s resources to service any instruction that the former cannot execute correctly by itself. This service improves yield and reliability but may cause loss of performance. The target platform for quantitative evaluation of performance under degradation is a dual-core and a quad-core chip multiprocessor with one or more cores sustaining partial failure. Simulation studies indicate that when a large, high-latency, and sparingly used unit such as a floating-point unit fails in a core, correct execution may be sustained through outsourcing with at most a 16% impact on performance for a floating-point intensive application. For applications with moderate floating-point load, the degradation is insignificant. The performance impact may be mitigated even further by judicious selection of the cores to commandeer depending on the current load on each of the candidate cores. The area overhead is also negligible due to resource reuse.

Variation of DRAM retention time and reliability problem induced by thermal stress was investigated. Most of the DRAM cells revealed 2-state retention time with thermal stress. The effects of hydrogen annealing condition and fluorine implantation on the variation of retention time and reliability are discussed.

This paper presents two adder compressors architectures addressing high-speed and low power. Adder compressors are used to implement arithmetic circuits such as multipliers and digital signal processing units like the Fast Fourier Transform (FTT). To address the objective of high-speed and low power, it is well known that optimization efforts should be applied in all abstraction levels. In this paper are combined optimizations at logic, electrical and physical level. At the logic level, the circuit is optimized by using multiplexers instead of XOR gates to reduce delay, power and area. At the electrical level, this work presents an architecture that generate the XOR and XNOR signals simultaneously, this reduce internal glitches hence dynamic power as well. And finally at the physical level, and automatic layout generation tool (ASTRAN) is used to make the adder compressors layouts. This tool has proved to reduce power consumption and delay due to the smaller input capacitances of the complex gates generated compared to manual-designed layouts.

The memory performances of the HfOX based bipolar resistive memory, including switching speed and memory reliability, are greatly improved in this work. Record high switching speed down to 300 ps is achieved. The cycling test shed a clear light on the wearing behavior of resistance states, and the correlation between over-RESET phenomenon and the worn low resistance state in the devices is discussed. The modified bottom electrode is proposed for the memory device to maintain the memory window and to endure resistive switching up to 1010 cycles.

Instruction memoization is a promising technique to reduce the power consumption and increase the performance of future low-end/mobile multimedia systems. Power and performance efficiency can be improved by reusing instances of an already executed operation. Unfortunately, this technique may not always be worth the effort due to the power consumption and area impact of the tables required to leverage an adequate level of reuse. In this paper, we introduce and evaluate a novel way of understanding multimedia floating-point operations based on the fuzzy computation paradigm: performance and power consumption can be improved at the cost of small precision losses in computation. By exploiting this implicit characteristic of multimedia applications, we propose a new technique called tolerant memoization. This technique expands the capabilities of classic memoization by associating entries with similar inputs to the same output. We evaluate this new technique by measuring the effect of tolerant memoization for floating-point operations in a low-power multimedia processor and discuss the trade-offs between performance and quality of the media outputs. We report energy improvements of 12 percent for a set of key multimedia applications with small LUT of 6 Kbytes, compared to 3 percent obtained using previously proposed techniques.

A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35nm while not scaling the gate oxide as a means to improve performance and reduce power. Increased NMOS and PMOS drive currents are achieved by enhanced channel strain and junction engineering. 193nm lithography along with APSM mask technology is used on critical layers to provide aggressive design rules and a 6-T SRAM cell size of 0.57/spl mu/m/sup 2/. Process yield, performance and reliability are demonstrated on a 70 Mbit SRAM test vehicle with >0.5 billion transistors.

Poly fuses are used as the base element for one time programmable cells in a standard CMOS process. Using a defined programming current, the resistance of the poly fuse increases irreversibly over several orders of magnitude. The goal of this study is to show that a poly fuse has a sufficient life time stability to be used as a storage element even in high reliability circuits. This paper shows the drift of the resistance of a poly fuse over the whole range of programming currents for a standard polycide 0.35 /spl mu/m CMOS process. The poly fuse for the selected process is build using two different layers, which gives a special performance in terms of programming current.


Question: An overview of the applications of augmented reality in various fields.

Progress and Innovations in Augmented Reality

Augmented Reality (AR), a field that has been evolving for over a decade, has witnessed significant advancements in recent years. Initially, a comprehensive survey was published in 1997 [3], based on a 1995 SIGGRAPH course lecture, which laid the groundwork for the field, outlined various challenges, and summarized the progress made up to that point. Subsequently, the field has experienced rapid expansion. In the late 1990s, specialized conferences emerged, such as the International Workshop and Symposium on Augmented Reality [29], the International Symposium on Mixed Reality [30], and the Designing Augmented Reality Environments workshop. Notably, well-funded interdisciplinary research groups were established, focusing on AR, including Japan's Mixed Reality Systems Laboratory [50] and Germany's Project ARVIKA [61]. An open-source software toolkit, the ARToolkit, was developed to facilitate the swift creation of AR applications [2]. Given the plethora of recent innovations, an updated review is essential to inform and inspire ongoing research in this dynamic domain.

We present a real-time stereoscopic video-see-through augmented reality (AR) system applied to the medical procedure known as ultrasound-guided needle biopsy of the breast. The AR system was used by a physician during procedures on breast models and during non-invasive examinations of human subjects. The system merges rendered live ultrasound data and geometric elements with stereo images of the patient acquired through head-mounted video cameras and presents these merged images to the physician in a head-mounted display. The physician sees a volume visualization of the ultrasound data directly under the ultrasound probe, properly registered within the patient and with the biopsy needle. Using this system, a physician successfully guided a needle into an artificial tumor within a training phantom of a human breast. We discuss the construction of the AR system and the issues and decisions which led to the system architecture and the design of the video see-through head-mounted display. We designed methods to properly resolve occlusion of the real and synthetic image elements. We developed techniques for realtime volume visualization of timeand position-varying ultrasound data. We devised a hybrid tracking system which achieves improved registration of synthetic and real imagery and we improved on previous techniques for calibration of a magnetic tracker. CR

This paper aims to present a review of recent as well as classic image registration methods. Image registration is the process of overlaying images (two or more) of the same scene taken at different times, from different viewpoints, and/or by different sensors. The registration geometrically align two images (the reference and sensed images). The reviewed approaches are classified according to their nature (areabased and feature-based) and according to four basic steps of image registration procedure: feature detection, feature matching, mapping function design, and image transformation and resampling. Main contributions, advantages, and drawbacks of the methods are mentioned in the paper. Problematic issues of image registration and outlook for the future research are discussed too. The major goal of the paper is to provide a comprehensive reference source for the researchers involved in image registration, regardless of particular application areas. q 2003 Elsevier B.V. All rights reserved.

Rehabilitation for stroke afflicted patients, through exercises tailored for individual needs, aims at relearning basic motor skills, especially in the extremities. Rehabilitation through Augmented Reality (AR) based games engage and motivate patients to perform exercises which, otherwise, maybe boring and monotonic. Also, mirror therapy allows users to observe one's own movements in the game providing them with good visual feedback. This paper presents an augmented reality based system for rehabilitation by playing four interactive, cognitive and fun Exergames (exercise and gaming).
 The system uses low-cost RGB-D cameras such as Microsoft Kinect V2 to capture and generate 3D model of the person by extracting him/her from the entire captured data and immersing it in different interactive virtual environments. Animation based limb movement enhancement along with cognitive aspects incorporated in the game can help in positive reinforcement, progressive challenges and motion improvement. Recording module of the toolkit allows future reference and facilitates feedback from the physician. 10 able-bodied users, 2 psychological experts and 2 Physical Medicine and Rehabilitation physicians evaluated the user experience and usability aspects of the exergames. Results obtained shows the games to be fun and realistic, and at the same time engaging and motivating for performing exercises.

The increasingly widespread use of simulations in education underlines the fact that these teaching tools compared to other methods or media allow students to approach and experience new topics in a more realistic way. This realism enhances their learning and understanding of complex subjects. So far it has been difficult to interactively simulate three-dimensional dynamic learning content. In this field, the continuing development of Virtual Reality (VR) offers new opportunities for educators to convey a wide variety of subjects. It is the aim of this paper to characterize the nature of Virtual Reality as an educational setting for simulations, and to show that Studierstube, our multi-user collaborative Virtual Environment, comprises the necessary features for applying VR-techniques to educational purposes. We further discuss the general applicability of VR to various fields of education and demonstrate its specific application as a tool for teaching elementary three-dimensional geometry.

The Walking-In-Place interaction technique was introduced to navigate infinitely in 3D virtual worlds by walking in place in the real world. The technique has been initially developed for users standing in immersive setups and was built upon sophisticated visual displays and tracking equipments.
 In this paper, we propose to revisit the whole pipeline of the Walking-In-Place technique to match a larger set of configurations and apply it notably to the context of desktop Virtual Reality. With our novel "Shake-Your-Head" technique, the user is left with the possibility to sit down, and to use small screens and standard input devices such as a basic webcam for tracking. The locomotion simulation can compute various motions such as turning, jumping and crawling, using as sole input the head movements of the user. We also introduce the use of additional visual feedback based on camera motions to enhance the walking sensations.
 An experiment was conducted to compare our technique with classical input devices used for navigating in desktop VR. Interestingly, the results showed that our technique could even allow faster navigations when sitting, after a short learning. Our technique was also perceived as more fun and increasing presence, and was generally more appreciated for VR navigation.

Mobile C-arm is an essential tool in everyday trauma and orthopedics surgery. Minimally invasive solutions, based on X-ray imaging and coregistered external navigation created a lot of interest within the surgical community and started to replace the traditional open surgery for many procedures. These solutions usually increase the accuracy and reduce the trauma. In general, they introduce new hardware into the OR and add the line of sight constraints imposed by optical tracking systems. They thus impose radical changes to the surgical setup and overall procedure. We augment a commonly used mobile C-arm with a standard video camera and a double mirror system allowing real-time fusion of optical and X-ray images. The video camera is mounted such that its optical center virtually coincides with the C-arm's X-ray source. After a one-time calibration routine, the acquired X-ray and optical images are coregistered. This paper describes the design of such a system, quantifies its technical accuracy, and provides a qualitative proof of its efficiency through cadaver studies conducted by trauma surgeons. In particular, it studies the relevance of this system for surgical navigation within pedicle screw placement, vertebroplasty, and intramedullary nail locking procedures. The image overlay provides an intuitive interface for surgical guidance with an accuracy of <;1 mm, ideally with the use of only one single X-ray image. The new system is smoothly integrated into the clinical application with no additional hardware especially for down-the-beam instrument guidance based on the anteroposterior oblique view, where the instrument axis is aligned with the X-ray source. Throughout all experiments, the camera augmented mobile C-arm system proved to be an intuitive and robust guidance solution for selected clinical routines.

We describe a novel system for rapid prototyping of laserbased optical and holographic layouts. Users of this optical prototyping tool – called the Illuminating Light system – move physical representations of various optical elements about a workspace, while the system tracks these components and projects back onto the workspace surface the simulated propagation of laser light through the evolving layout. This application is built atop the Luminous Room infrastructure, an aggregate of interlinked, computer-controlled projector-camera units called I/O Bulbs. Philosophically, the work embodies the emerging ideas of the Luminous Room and builds on the notions of ‘graspable media’. We briefly introduce the I/O Bulb and Luminous Room concepts and discuss their current implementations. After an overview of the optical domain that the Illuminating Light system is designed to address, we present the overall system design and implementation, including that of an intermediary toolkit called voodoo which provides a general facility for object identification and tracking.

Augmented Reality (AR) based navigation has emerged as an impressive, yet seamless way of guiding users in unknown environments. Its quality of experience depends on many factors, including the accuracy of camera pose estimation, response delay, and energy consumption. In this paper, we present SeeNav - a seamless and energy-efficient AR navigation system for indoor environments. SeeNav combines image-based localization and inertial tracking to provide an accurate and robust camera pose estimation. As vision processing is much more compute intensive than the processing of inertial sensor data, SeeNav offloads the former one from resource-constrained mobile devices to a cloud to improve tracking performance and reduce power consumption. More than that, SeeNav implements a context-aware task scheduling algorithm that further minimizes energy consumption while maintaining the accuracy of camera pose estimation. Our experimental results, including a user study, show that SeeNav provides seamless navigation experience and reduces the overall energy consumption by 21.56% with context-aware task scheduling.

This paper explores a user interface technique which augments an immersive head tracked display with a hand-held miniature copy of the virtual environment. We call this interface technique the Worlds in Miniature (WIM) metaphor. In addition to the first-person perspective offered by a virtual reality system, a World in Miniature offers a second dynamic viewport onto the virtual environment. Objects may be directly manipulated either through the immersive viewport or through the three-dimensional viewport offered by the WIM. In addition to describing object manipulation, this paper explores ways in which Worlds in Miniature can act as a single unifying metaphor for such application independent interaction techniques as object selection, navigation, path planning, and visualization. The WIM metaphor offers multiple points of view and multiple scales at which the user can operate, without requiring explicit modes or commands. Informal user observation indicates that users adapt to the Worlds in Miniature metaphor quickly and that physical props are helpful in manipulating the WIM and other objects in the environment.

Scene text extraction is recent research area in the field of Computer Vision. Text component in an image is of particular interest, as it is easy to understand by both humans as well as machines and can be used in variety of applications like content-based image retrieval, aids for visually impaired people, translator for tourists. Although there exists a lot of research activities in this field, it is still remained as a challenging problem, mainly due to two issues: different variety of text patterns like fonts, colors, sizes, orientations; and presence of background outliers similar to text characters, such as windows, bricks. In this paper, an android application named as TravelMate is developed, which is a user-friendly application to assist the tourist navigation, while they are roaming in foreign countries. Proposed application is able to extract text from an image, which is captured by an android mobile camera. Extraction is performed using stroke width transform (SWT) approach and connected component analysis. Extracted texts are recognized using Google's open source optical character recognition (OCR) engine ‘Tesseract’ and translated to a target language using Google's translation. The entire result is displayed back onto the screen of the mobile Phone.