Question: Utilizing multiplicative recurrent neural networks for modeling compositionality.

The Role of Dynamics in Modeling Time with Recurrent Neural Networks

In the intricate landscape of human behavior, time plays a pivotal role. Consequently, the challenge of effectively representing time within connectionist models assumes significant importance. A viable strategy, initially proposed by Jordan (1986), advocates for an implicit representation of time, focusing on its impact on processing rather than an explicit spatial representation. This approach involves the strategic use of recurrent connections to bestow networks with a form of dynamic memory, where patterns from hidden units are recurrently fed back to themselves. The resulting internal representations emerge as a synthesis of task requirements in the context of preceding internal states. A series of simulations, ranging from straightforward tasks like a temporal variant of the XOR problem to more complex endeavors such as uncovering syntactic and semantic features for words, are presented. These networks exhibit the capability to learn nuanced internal representations that seamlessly blend task-specific demands with memory requirements. In this paradigm, the concept of memory becomes inextricably intertwined with the processing of tasks. The representations developed by these networks are rich and structured, enabling them to be highly context-sensitive while also facilitating generalizations across various item classes. These findings offer a promising avenue for modeling lexical categories and distinguishing between types and tokens within a dynamic framework.

In this paper, we propose a bi-attention, a multi-layer attention and an attention mechanism and convolution neural network based text representation and classification model (ACNN). The bi-attention have two attention mechanism to learn two context vectors, forward RNN with attention to learn forward context vector c⃗ $\overrightarrow {\mathbf {c}}$ and backward RNN with attention to learn backward context vector c⃖ $\overleftarrow {\mathbf {c}}$, and then concatenation c⃗ $\overrightarrow {\mathbf {c}}$ and c⃖ $\overleftarrow {\mathbf {c}}$ to get context vector c. The multi-layer attention is the stack of the bi-attention. In the ACNN, the context vector c is obtained by the bi-attention, then the convolution operation is performed on the context vector c, and the max-pooling operation is used to reduce the dimension. After max-pooling operation the text is converted to low-dimensional sentence vector m. Finally, the Softmax classifier be used for text classification. We test our model on 8 benchmarks text classification datasets, and our model achieved a better or the same performance compare with the state-of-the-art methods.

We introduce an encoder-decoder recurrent neural network model called Recurrent Neural Aligner (RNA) that can be used for sequence to sequence mapping tasks. Like connectionist temporal classification (CTC) models, RNA defines a probability distribution over target label sequences including blank labels corresponding to each time step in input. The probability of a label sequence is calculated by marginalizing over all possible blank label positions. Unlike CTC, RNA does not make a conditional independence assumption for label predictions; it uses the predicted label at time t−1 as an additional input to the recurrent model when predicting the label at time t. We apply this model to end-to-end speech recognition. RNA is capable of streaming recognition since the decoder does not employ attention mechanism. The model is trained on transcribed acoustic data to predict graphemes and no external language and pronunciation models are used for decoding. We employ an approximate dynamic programming method to optimize negative log likelihood, and a sampling-based sequence discriminative training technique to fine-tune the model to minimize expected word error rate. We show that the model achieves competitive accuracy without using an external language model nor doing beam search decoding.

Neural machine translation (NMT) models typically operate with a fixed vocabulary, but translation is an open-vocabulary problem. Previous work addresses the translation of out-of-vocabulary words by backing off to a dictionary. In this paper, we introduce a simpler and more effective approach, making the NMT model capable of open-vocabulary translation by encoding rare and unknown words as sequences of subword units. This is based on the intuition that various word classes are translatable via smaller units than words, for instance names (via character copying or transliteration), compounds (via compositional translation), and cognates and loanwords (via phonological and morphological transformations). We discuss the suitability of different word segmentation techniques, including simple character ngram models and a segmentation based on the byte pair encoding compression algorithm, and empirically show that subword models improve over a back-off dictionary baseline for the WMT 15 translation tasks English→German and English→Russian by up to 1.1 and 1.3 BLEU, respectively.

In this paper we present a cross-lingual extension of a neural tensor network model for knowledge base completion. We exploit multilingual synsets from BabelNet to translate English triples to other languages and then augment the reference knowledge base with cross-lingual triples. We project monolingual embeddings of different languages to a shared multilingual space and use them for network initialization (i.e., as initial concept embeddings). We then train the network with triples from the cross-lingually augmented knowledge base. Results on WordNet link prediction show that leveraging cross-lingual information yields significant gains over exploiting only monolingual triples.

Transfer and multi-task learning have traditionally focused on either a single source-target pair or very few, similar tasks. Ideally, the linguistic levels of morphology, syntax and semantics would benefit each other by being trained in a single model. We introduce a joint many-task model together with a strategy for successively growing its depth to solve increasingly complex tasks. Higher layers include shortcut connections to lower-level task predictions to reflect linguistic hierarchies. We use a simple regularization term to allow for optimizing all model weights to improve one task’s loss without exhibiting catastrophic interference of the other tasks. Our single end-to-end model obtains state-of-the-art or competitive results on five different tasks from tagging, parsing, relatedness, and entailment tasks.

As the amount of unstructured text data that humanity produces overall and on the Internet grows, so does the need to intelligently to process it and extract different types of knowledge from it. Convolutional neural networks (CNNs) and recurrent neural networks (RNNs) have been applied to natural language processing systems with comparative, remarkable results. The CNN is a noble approach to extract higher level features that are invariant to local translation. However, it requires stacking multiple convolutional layers in order to capture long-term dependencies, due to the locality of the convolutional and pooling layers. In this paper, we describe a joint CNN and RNN framework to overcome this problem. Briefly, we use an unsupervised neural language model to train initial word embeddings that are further tuned by our deep learning network, then, the pre-trained parameters of the network are used to initialize the model. At a final stage, the proposed framework combines former information with a set of feature maps learned by a convolutional layer with long-term dependencies learned via long-short-term memory. Empirically, we show that our approach, with slight hyperparameter tuning and static vectors, achieves outstanding results on multiple sentiment analysis benchmarks. Our approach outperforms several existing approaches in term of accuracy; our results are also competitive with the state-of-the-art results on the Stanford Large Movie Review data set with 93.3% accuracy, and the Stanford Sentiment Treebank data set with 48.8% fine-grained and 89.2% binary accuracy, respectively. Our approach has a significant role in reducing the number of parameters and constructing the convolutional layer followed by the recurrent layer as a substitute for the pooling layer. Our results show that we were able to reduce the loss of detailed, local information and capture long-term dependencies with an efficient framework that has fewer parameters and a high level of performance.

We present a new stochastic learning machine for speech separation based on the variational recurrent neural network (VRNN). This VRNN is constructed from the perspectives of generative stochastic network and variational auto-encoder. The idea is to faithfully characterize the randomness of hidden state of a recurrent neural network through variational learning. The neural parameters under this latent variable model are estimated by maximizing the variational lower bound of log marginal likelihood. An inference network driven by the variational distribution is trained from a set of mixed signals and the associated source targets. A novel supervised VRNN is developed for speech separation. The proposed VRNN provides a stochastic point of view which accommodates the uncertainty in hidden states and facilitates the analysis of model construction. The masking function is further employed in network outputs for speech separation. The benefit of using VRNN is demonstrated by the experiments on monaural speech separation.

Traditional convolutional neural network (CNN) based query classification uses linear feature mapping in its convolution operation. The recurrent neural network (RNN), differs from a CNN in representing word sequence with their ordering information kept explicitly. We propose using a deep long-short-term-memory (DLSTM) based feature mapping to learn feature representation for CNN. The DLSTM, which is a stack of LSTM units, has different order of feature representations at different depth of LSTM unit. The bottom LSTM unit equipped with input and output gates, extracts the first order feature representation from current word. To extract higher order nonlinear feature representation, the LSTM unit at higher position gets input from two parts. First part is the lower LSTM unit’s memory cell from previous word. Second part is the lower LSTM unit’s hidden output from current word. In this way, the DLSTM captures the nonlinear nonconsecutive interaction within n-grams. Using an architecture that combines a stack of the DLSTM layers with a tradition CNN layer, we have observed new state-of-the-art query classification accuracy on benchmark data sets for query classification.

Memory-augmented recurrent neural networks (M-RNNs) have demonstrated empirically that they are very attractive for many applications, but a good theoretical understanding of their behaviors is unclear yet. In this paper, three analytical indicators named duration, addressability, and capacity of general forms of the additional memory in M-RNNs are formalized. The analysis results of the interactions among these indicators reveal that it is hard for an M-RNN to simultaneously provide good performance on more than two out of three of indicators. Meanwhile, the duration, addressability, and capacity are applied to analyze and compare two M-RNNs: long short term memory and neural turing machine for different cases. The comparison results show that none of the models has better performance on one indicator than the other model all the time. Moreover, it is found that separating memory system into sub-memories can bring the increasing duration and addressability and the decreasing capacity for the whole memory system.

Previous work combines word-level and character-level representations using concatenation or scalar weighting, which is suboptimal for high-level tasks like reading comprehension. We present a fine-grained gating mechanism to dynamically combine word-level and character-level representations based on properties of the words. We also extend the idea of fine-grained gating to modeling the interaction between questions and paragraphs for reading comprehension. Experiments show that our approach can improve the performance on reading comprehension tasks, achieving new state-of-the-art results on the Children’s Book Test and Who Did What datasets. To demonstrate the generality of our gating mechanism, we also show improved results on a social media tag prediction task.1


Question: Design of a power-optimized voltage level shifter for high-speed dual supply systems.

This article introduces a novel, energy-efficient voltage level shifter design that efficiently transforms very low input voltages into higher voltage levels. To minimize static power consumption, the proposed architecture employs a current generator that activates solely during transitional periods when the input signal's logic level does not align with the output's logic level. Additionally, the pull-up device's strength is reduced when the pull-down device is actively pulling down the output node, ensuring the circuit remains operational even when the input voltage is below the threshold voltage of a MOSFET. The theoretical analysis of the proposed design's operation is also provided. Post-layout simulation results, obtained using a 0.18-μm CMOS technology, demonstrate that at an input low supply voltage of 0.4 V and a high supply voltage of 1.8 V, the level shifter achieves a propagation delay of 30 ns, a static power dissipation of 130 pW, and an energy consumption of 327 fJ per transition for a 1-MHz input signal.

The focus here is on the development of a power-optimized voltage level shifter that can effectively convert input voltages from subthreshold to above-threshold levels. The design minimizes static power dissipation by employing a current generator that only operates during transitions when the input and output logic levels are mismatched. Furthermore, the pull-up device's strength is adjusted to reduce power consumption when the pull-down device is active, allowing the circuit to function even with input voltages lower than the threshold voltage of a MOSFET. Detailed analytical investigation of the design's operation is also presented. Simulation results from a 0.18-μm CMOS technology show that the level shifter, operating at an input low supply voltage of 0.4 V and a high supply voltage of 1.8 V, has a propagation delay of 30 ns, a static power dissipation of 130 pW, and consumes 327 fJ of energy per transition with a 1-MHz input signal.

In this paper, an ultra wideband analog voltage-mode buffer is presented which can drive a load impedance of 50 Ω. The presented feedback-based buffer uses a compound amplifier which is a parallel combination of a high-DC gain operational amplifier and a operation transconductance amplifier to achieve a high unity gain bandwidth. A proof-of-concept prototype is designed and fabricated in a 0.13 μm CMOS process. The simulation and measurement results of the proposed buffer are in good agreement. The prototype buffer circuit consumes 7.34 mW from a 1.3-V supply, while buffering a 2 GHz sinusoidal input signal with a 0.4 V peak-to-peak (Vpp) amplitude and driving an AC-coupled 50-Ω load.

This paper presents a novel dynamic latched comparator that demonstrates lower offset voltage and higher load drivability than the conventional dynamic latched comparators. With two additional inverters inserted between the input- and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage is improved. The complementary version of the regenerative latch stage, which provides larger output drive current than the conventional one at a limited area, is implemented. The proposed circuit is designed using 90nm CMOS technology and 1V power supply voltage, and it demonstrates up to 19% less offset voltage and 62% less sensitivity of the delay to the input voltage difference (17ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption.

A high-speed differential clocked comparator circuit is presented. The comparator consists of a preamplifier and a latch stage followed by a dynamic latch that operates as an output sampler. The output sampler circuit consists of a full transmission gate (TG) and two inverters. The use of this sampling stage results in a reduction in the power consumption of this high-speed comparator. Simulations show that charge injection of the TG adds constructively to the sampled signal value, therefore amplifying the sampled signal with a modest gain of 1.15. Combined with the high gain of the inverters, the sampled signals are amplified toward the rail voltages. This comparator is designed and fabricated in a 0.35 /spl mu/m standard digital CMOS technology. Measurement results show a sampling frequency of 1 GHz with 16 mV resolution for a 1 V input signal range and 2 mW power consumption from a 3.3 V supply. The architecture can be scaled down to smaller feature sizes and lower supply voltages.

This paper describes a transmitter driver based on a CMOS inverter with a resistive feedback. By employing the proposed driver topology, the pre-driver can be greatly simplified, resulting in a remarkable reduction of the overall driver power consumption. It also offers another advantage that the implementation of equalization is straightforward, compared with a conventional voltage-mode driver. Furthermore, the output impedance remains relatively constant while the data is being transmitted, resulting in good signal integrity. For evaluation of the driver performance, a fully functional 20 Gb/s transmitter is implemented, including a PRBS generator, a serializer, and a half-rate clock generator. In order to enhance the overall speed of the digital circuits for 20 Gb/s data transmission, the resistive feedback is applied to the time-critical inverters, which enables shorter rise/fall times. The prototype chip is fabricated in a 65 nm CMOS technology. The implemented driver circuit operates up to the data rate of 20 Gb/s, exhibiting an energy efficiency of 0.4 pJ/b for the output swing of 250 mVpp,diff.

This paper presents a dc–dc boost converter topology for low input and high output voltage applications, such as photovoltaic systems, fuel cell systems, high-intensity discharge lamp, and electric vehicles. The suggested configuration consists of a three-winding coupled-inductor, a single switch and two hybrid voltage multiplier cells. Furthermore, two independent hybrid voltage multiplier cells are in parallel when the single switch S is turned on, and they are in series when the switch S is turned off. So, the advantages of the proposed converter structure are summarized as follows: 1) A coupled inductor with three windings is introduced in the presented converter structure. The two secondary windings of the coupled inductor are, respectively, used to form a hybrid multiplier cell on the one hand, on the other hand, it increases the control freedom of the voltage gain, enhances the utility rate of magnetic core and power density, and reduces the stress of power components to provide a stable constant dc output voltage. 2) The two hybrid multiplier cells can absorb synchronously the energy of stray inductance, which not only reduces the current stress of corresponding diodes, but also greatly alleviates the spike voltage of the main switch, which improves the efficiency. 3) The two hybrid multiplier cells are connected in series to supply power energy for the load, so the voltage gain is extended greatly due to this particular structure. Thus, low-voltage low-conduction-loss devices can be selected and the reverse-recovery currents within the diodes are inhibited. The operating principles and the steady state analyses of the proposed converter are discussed in detail. Finally, a test prototype has been implemented in the laboratory, and the simulated and experimental results show satisfactory agreement with the theoretical analysis.

The asymmetrical half-bridge (AHB) flyback converter is an attractive topology for operation at higher switching frequencies because it can operate with zero-voltage switching of the primary-side switches and zero-current switching of the secondary-side rectifier. In this paper, a detailed analysis and design procedure of the AHB flyback converter for the universal-line-voltage-range applications is presented. The performance of the AHB flyback converter is evaluated by loss analysis based on the simulation waveforms obtained in Simplis and experimentally verified on a laboratory prototype of a 65-W (19.5-V, 3.33-A) universal-line-voltage-range adapter.

A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than two V/sub GS/ drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The op amp is characterized by low static power consumption and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5-/spl mu/m CMOS technology verify the scheme operating with /spl plusmn/0.9-V supplies and close to rail-to-rail input and output swing.

A feed-forward noise cancellation (FFNC) technique to improve the power supply noise rejection (PSR) of a low dropout regulator (LDO) is presented. The proposed FFNC operates in conjunction with a conventional LDO and extends the noise rejection bandwidth by nearly an order of magnitude. Fabricated in 0.18µm CMOS, at 10mA load current, the prototype achieves a PSR of −50dB and −25dB at 1MHz and 10MHz supply noise frequencies, respectively. Compared to a conventional LDO, this represents an improvement of at least 30dB at 1MHz and 15dB at 10MHz. The prototype uses only 20pF load capacitance and occupies an active area of 0.04mm2.

An SPDT switch consisting of both nMOS and pMOS transistors is presented. Compared with conventional SPDT switches using only nMOS transistors under the same bias condition, the proposed switch exhibits better power-handling capability (PHC). The mechanism for the PHC improvement is explained. A prototype is implemented using a 0.18-um CMOS process. Measurement results show that, at 2.4 GHz, the insertion loss is 0.62 dB when the nMOS transistors are on and 0.91 dB when the pMOS transistors are on. For both modes, the measured return loss and isolation are better than 10 dB and 19 dB, respectively, up to 6 GHz. Under 1.8-V operation, the switch is able to handle a 26.1-dBm input power when the nMOS transistors are on and a 24.0-dBm input power when the pMOS transistors are on.

Toshiba's 5th generation BiCD/CD-0.13 is a new process platform for analog power applications based on 0.13µm CMOS technology. The process platform has six varieties of rated voltage, 5V, 6V, 18V, 25V, 40V, and 60V. 5 to 18V CD-0.13 process use P-type silicon substrate. 25 to 60V BiCD-0.13 process use N-Epi wafer with N+/P+ buried layer on P type silicon substrate. Each LDMOS recode ultra-low on-resistance compared with that of previous papers, and we will realize the highest performance analog power IC's using this technology.


Question: A voltage level shifter design optimized for power consumption in high-speed dual supply applications.

This paper presents a novel level converter (LC) designed for efficient voltage shifting between sub-threshold and conventional high voltage logic levels, specifically optimized for low-energy consumption and enhanced robustness. The LC employs a pair of PMOS diodes to ensure reliable operation with sub-threshold logic inputs, making it particularly suitable for power-conscious systems. A key feature of this design is its ability to adapt its switching delay to the input logic voltage, further optimizing power usage. The proposed LC's simplified circuit structure contributes to a lower energy footprint compared to existing sub-threshold LCs. Through simulation, the enhanced performance and reduced energy consumption of the LC are clearly demonstrated. To validate the design, a test chip was manufactured using a 0.18 µm CMOS process. Experimental results confirm the LC's functionality, with successful operation at an input voltage as low as 127 mV and an output voltage of 1.8V, underscoring its robustness and efficiency.

A new ESD protection design method is introduced that optimizes the CDM circuit response of an RC-triggered rail clamp network for I/O protection. The design is verified by VF-TLP and CDM test data of I/O test rings with two different output driver options.

This paper presents a reconfigurable, low offset, low noise and high speed dynamic clocked-comparator for medium to high resolution Analog to Digital Converters (ADCs). The proposed comparator reduces the input referred noise by half and shows a better output driving capability when compared with the previous work. The offset, noise and power consumption can be controlled by a clock delay which allows simple reconfiguration. Moreover, the proposed offset calibration technique improves the offset voltage from 11.6mV to 533μV at 1 sigma. A prototype of the comparator is implemented in 90nm 1P8M CMOS with experimental results showing 320μV input referred noise at 1.5GHz with 1.2V supply.

Embedded systems are usually energy constrained. Moreover, in these systems, increased productivity and reduced time to market are essential for product success. To design complex embedded systems while reducing the development time and cost, there is a great tendency to use commercial off-the-shelf (“COTS”) devices. At system level, dynamic voltage and frequency scaling (DVFS) is one of the most effective techniques for energy reduction. Nonetheless, many widely used COTS processors either do not have DVFS or apply DVFS only to processor cores. In this paper, an easy-to-implement COTS-based evaluation platform for low-energy embedded systems is presented. To achieve energy saving, DVFS is provided for the whole microcontroller (including core, phase-locked loop, memory, and I/O). In addition, facilities are provided for experimenting with fault-tolerance techniques. The platform is equipped with energy measurement and debugging equipment. Physical experiments show that applying DVFS on the whole microcontroller provides up to 47% and 12% energy saving compared with the sole use of dynamic power management and applying DVFS only on the core, respectively. Although the platform is designed for ARM-based embedded systems, our approach is general and can be applied to other types of systems.

This paper presents analysis and modeling for a bidirectional push-pull dc-dc converter. In particular, attention is paid to leakage current reduction with PWM plus phase-shift control. The leakage current in different operating modes has been compared to identify the efficient modes for various operation conditions. The state space averaging method is adopted to derive the small signal and large signal models of the most efficient mode. A 30~70V/300V prototype was built. Both simulation results and experimental results prove the validity of the model.

AbstructMultilevel voltage source converters are emerging as a new breed of power converter options for high-power applications. The multilevel voltage source converters typically synthesize the staircase voltage wave from several levels of dc capacitor voltages. One of the major limitations of the multilevel converters is the voltage unbalance between different levels. The techniques to balance the voltage between different levels normally involve voltage clamping or capacitor charge control. There are several ways of implementing voltage balance in multilevel converters. Without considering the traditional magnetic coupled converters, this paper presents three recently developed multilevel voltage source converters: 1) diode-clamp, 2) flyingcapacitors, and 3) cascaded-inverters with separate dc sources. The operating principle, features, constraints, and potential applications of these converters will be discussed.

CMOS transmit-receive (T/R) switches have been integrated in a 0.18-/spl mu/m standard CMOS technology for wireless applications at 2.4 and 5.2 GHz. This switch design achieves low loss and high linearity by increasing the substrate impedance of a MOSFET at the frequency of operation using a properly tuned LC tank. The switch design is asymmetric to accommodate the different linearity and isolation requirements in the transmit and receive modes. In the transmit mode, the switch exhibits 1.5-dB insertion loss, 28-dBm power, 1-dB compression point (P/sub 1dB/), and 30-dB isolation, at 2.4 and 5.2 GHz. In the receive mode, the switch achieves 1.6-dB insertion loss, 11.5-dBm P/sub 1dB/, and 15-dB isolation, at 2.4 and 5.2 GHz. The linearity obtained in the transmit mode is the highest reported to date in a standard CMOS process. The switch passes the 4-kV Human Body Model electrostatic discharge test. These results show that the switch design is suitable for narrow-band applications requiring a moderate-high transmitter power level (<1 W).

This paper presents BCD process integrating 7V to 70V power devices on 0.13um CMOS platform for various power management applications. BJT, Zener diode and Schottky diode are available and non-volatile memory is embedded as well. LDMOS shows best-in-class specific Ron (RSP) vs. BVDSS characteristics (i.e., 70V NMOS has RSP of 69mΩ-mm2 with BVDSS of 89V). Modular process scheme is used for flexibility to various requirements of applications.

In Miller and current buffer compensation techniques, the compensation capacitor often loads the output node. If a voltage buffer is used in feedback, the compensation capacitor obviates the loading on the output node. In this paper, we introduce an implementation of a voltage buffer compensation using a Flipped Voltage Follower (FVF) for stabilizing a two-stage CMOS op-amp. The op-amps are implemented in a 180-nm CMOS process with a power supply of 1.8V while operating with a quiescent current of 110μA. Results indicate that the proposed voltage buffer compensation using FVF improves the Unity Gain Frequency from 5.5MHz to 12.2MHz compared to Miller compensation. Also, the proposed technique enhances the transient response while lowering the compensation capacitance by 47% and 17.7% compared to Miller and common-drain compensation topologies. Utilization of FVF or its variants as a voltage buffer in a feedback compensation network has wide potential applications in the analog design space.

Power Dissipation of Digital circuits can be reduced by 15% 25% by using appropriate logic restructuring and also it can be reduced by 40% 60% by lowering switching activity. Here, Gate Diffusion Input Technique which is based on a Shannon expansion is analyzed for minimizing the power consumption and delay of static digital circuits. This technique as compare to other currently used logic design style, allows less power consumption and reduced propagation delay for low-power design of combinatorial digital circuits with minimum number of transistors. In this paper, basic building blocks of digital system and few combinational circuits are analyzed using GDI and other CMOS techniques. All circuits are designed at 180nm technology in CADENCE and simulate using VIRTUOSO SPECTRE simulator at 100 MHz frequency. Comparative analysis has been done among GDI and other parallel design styles for designing ripple adder, CLA adder and bit magnitude comparator. Simulation result shows GDI technique saves 53. 3%, 55. 6% and 75. 6% power in ripple adder, CLA adder and bit magnitude comparator respectively as compare to CMOS. Also delay is reduced with 25. 2%, 3. 4% and 6. 9% as compare to CMOS. Analysis conclude that GDI is revolutionary high speed and low power consumption technique.

A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications.


Question: A voltage level shifter design optimized for power in high-speed dual supply systems.

This paper presents an innovative design methodology for a 180-mV subthreshold Fast Fourier Transform (FFT) processor, tailored for power optimization in emerging embedded systems such as wireless sensor networks. In these applications, the primary objective is to minimize energy consumption rather than maximizing processor speed. Building upon the minimum energy analysis framework proposed by Chandrakasan et al., the optimal operating parameters for clock frequencies, supply voltage, and threshold voltage are determined. The analysis reveals that the lowest energy consumption is often achieved in the subthreshold region, where supply voltages are below the device thresholds. To capitalize on this insight, novel subthreshold logic and memory design techniques are developed and implemented in a high-performance FFT processor. The processor features an energy-efficient architecture that supports variable FFT lengths (ranging from 128 to 1024 points) and variable bit-precision (8-bit and 16-bit), enabling exploration of the estimated minimum energy point. The design is realized using a standard 0.18-μm CMOS logic process and demonstrates operation at an ultra-low voltage of 180 mV. At the minimum energy point, achieved at a 350-mV supply voltage, the 16-bit 1024-point FFT processor consumes a mere 155 nJ per FFT operation, operating at a clock frequency of 10 kHz. This showcases the processor's remarkable energy efficiency, making it highly suitable for power-constrained embedded applications.

We present a fully differential two-stage Miller op-amp operating from a 0.5 V power supply. The input signal is applied to the bulk nodes of the input devices. A prototype was designed in a standard 0.18 /spl mu/m CMOS process using standard 0.5 V V/sub T/ devices. It has a measured 52 dB DC gain, a 2.5 MHz gain-bandwidth and consumes 110 /spl mu/W.

With fast power semiconductor devices based on GaN and SiC becoming more common, there is a need for improved driving circuits. Transformers with smaller inter-winding capacitance in the isolated gate drive power supply helps in reducing the conducted EMI emission from the power converter to auxiliary sources. This paper presents a transformer with a small volume, a low power loss and a small inter-capacitance in a gate drive power supply to fast switching devices, such as GaN HEMT and SiC MOSFET. The transformer core is embedded into PCB to increase the integration density. Two different transformer designs, the coplanar-winding PCB embedded transformer and the toroidal PCB embedded transformer, are presented and compared. The former has a 0.8 pF inter-capacitance and the latter has 85% efficiency with 73 W/in3 power density. Both designs are dedicated to a 2 W gate drive power supply for wide-band-gap device, which can operate at 200 °C ambient temperature.

This paper proposes a novel soft-switching interleaved boost converter composed of two shunted elementary boost conversion units and an auxiliary inductor. This converter is able to turn on both the active power switches at zero voltage to reduce their switching losses and evidently raise the conversion efficiency. Since the two parallel-operated elementary boost units are identical, operation analysis and design for the converter module becomes quite simple. A laboratory test circuit is built, and the circuit operation shows satisfactory agreement with the theoretical analysis. The experimental results show that this converter module performs very well with the output efficiency as high as 95%.

High voltage gain dc-dc converters are required in many industrial applications such as photovoltaic and fuel cell energy systems, high-intensity discharge lamp (HID), dc back-up energy systems, and electric vehicles. This paper presents a novel input-parallel output-series boost converter with dual coupled inductors and a voltage multiplier module. On the one hand, the primary windings of two coupled inductors are connected in parallel to share the input current and reduce the current ripple at the input. On the other hand, the proposed converter inherits the merits of interleaved series-connected output capacitors for high voltage gain, low output voltage ripple, and low switch voltage stress. Moreover, the secondary sides of two coupled inductors are connected in series to a regenerative capacitor by a diode for extending the voltage gain and balancing the primary-parallel currents. In addition, the active switches are turned on at zero current and the reverse recovery problem of diodes is alleviated by reasonable leakage inductances of the coupled inductors. Besides, the energy of leakage inductances can be recycled. A prototype circuit rated 500-W output power is implemented in the laboratory, and the experimental results shows satisfactory agreement with the theoretical analysis.

In the transportation field, the empty weight of the vehicle has to be as light as possible in order to have the highest energetic efficiency. For onboard storage electrical systems, DC/DC converters are usually used to control the power flows in the vehicle. This paper focuses on two different DC/DC converter applications: high current/low voltage on the one hand and low current/high voltage on the other hand. For all power mobile applications, a standard dc/dc converter is not realizable due to mass and volume constraints. As the inductor is usually the biggest and heaviest component in the system, it is important to develop a new structure allowing the reduction of its size and weight. The chosen technology is based on interleaved channels operating in discontinuous mode, also using reverse conduction of power MOSFET transistors. For both of the cases described above, a prototype has been built composed of 8 and 4 channels respectively. The first converter is used for power assistance (250 A/18 V) using the MOS reverse conduction property. In this particular case, efficiency is up to 96.3 %. The second is developed for a mobile solar application (3.8 A/270 V). Efficiencies are up to 98.4 %

An SPDT switch consisting of both nMOS and pMOS transistors is presented. Compared with conventional SPDT switches using only nMOS transistors under the same bias condition, the proposed switch exhibits better power-handling capability (PHC). The mechanism for the PHC improvement is explained. A prototype is implemented using a 0.18-um CMOS process. Measurement results show that, at 2.4 GHz, the insertion loss is 0.62 dB when the nMOS transistors are on and 0.91 dB when the pMOS transistors are on. For both modes, the measured return loss and isolation are better than 10 dB and 19 dB, respectively, up to 6 GHz. Under 1.8-V operation, the switch is able to handle a 26.1-dBm input power when the nMOS transistors are on and a 24.0-dBm input power when the pMOS transistors are on.

This paper presents a variable threshold voltage CMOS comparator for flash analog to digital converter. The proposed comparator has single-ended type of architecture. The comparator is designed and analyzed by Cadence Virtuoso Analog Design Environment using UMC 180nm technology. The proposed comparator consumes peak power of 34. 97 ?W from 1. 8 V power supply. It achieves the power delay product (PDP) of 8 fJ and propagation delay of 230 ps. The designed comparator eliminates the requirement of resistive ladder network for reference voltage generation. This makes it highly suitable in the design of flash analog to digital converter.

AbstructMultilevel voltage source converters are emerging as a new breed of power converter options for high-power applications. The multilevel voltage source converters typically synthesize the staircase voltage wave from several levels of dc capacitor voltages. One of the major limitations of the multilevel converters is the voltage unbalance between different levels. The techniques to balance the voltage between different levels normally involve voltage clamping or capacitor charge control. There are several ways of implementing voltage balance in multilevel converters. Without considering the traditional magnetic coupled converters, this paper presents three recently developed multilevel voltage source converters: 1) diode-clamp, 2) flyingcapacitors, and 3) cascaded-inverters with separate dc sources. The operating principle, features, constraints, and potential applications of these converters will be discussed.

In this paper, a fully integrated low voltage charge pump for thermoelectric energy harvesters is presented. The proposed dual-mode architecture achieves both the low startup voltage in a startup mode and high conversion efficiency in a normal operation mode without off-chip inductors and capacitors. In the measurement, the proposed circuit successfully converts 120-mV input to 770-mV output with 38.8% conversion efficiency.

In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master–slave latch structures. A new simulation and optimization approach is presented, targeting both highperformance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master–slave latches and flipflops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications.


Question: A voltage level shifter design optimized for power consumption in high-speed dual supply applications.

This article presents an innovative level shifter circuit designed to efficiently convert signals from subthreshold to above-threshold levels. Unlike conventional designs, this circuit does not necessitate a continuous static current, leading to substantial reductions in static power consumption. Optimized and simulated using a 90-nm process technology, the circuit ensures reliable operation across various process conditions for supply voltages ranging from 100 mV to 1 V on the low-voltage side. Specifically, at a design voltage of 200 mV, the level shifter exhibits a propagation delay of 18.4 ns and a static power dissipation of 6.6 nW. When tested with a 1-MHz input signal, the total energy consumption per transition is measured at 93.9 fJ. These findings are juxtaposed with those from a previously published subthreshold to above-threshold level shifter by Chen and colleagues, highlighting the improved performance and efficiency of the proposed circuit.

**Question**: Evaluating the Role of Renewable Energy in Enhancing Grid Stability

**Documents**: An Assessment of Renewable Energy's Impact on Grid Reliability and Stability
This study investigates the influence of renewable energy integration on the reliability and stability of the power grid. With the increasing penetration of renewable energy sources (RES), such as wind and solar power, concerns have been raised regarding the potential impacts on grid stability. This paper analyzes these concerns by examining the variability and intermittency of RES and their effects on grid operations. The study employs a comprehensive modeling approach to simulate grid behavior under various RES penetration scenarios. Results indicate that while high levels of RES can indeed pose challenges to grid stability, these can be effectively managed through the implementation of advanced control strategies and energy storage systems. The findings highlight the need for a coordinated effort between grid operators, policy makers, and technology developers to ensure the seamless integration of renewable energy while maintaining grid reliability.

**Similar Documents**: This research explores the effects of renewable energy sources (RES) on the stability and reliability of the power grid. As the adoption of RES, particularly wind and solar power, grows, there is a heightened interest in understanding how these energy forms affect grid stability. This paper delves into the issue by scrutinizing the variability and intermittent nature of RES and their implications for grid management. Utilizing a detailed modeling technique, the study simulates grid performance under diverse RES integration scenarios. The analysis reveals that although significant RES penetration can introduce complexities to grid stability, these challenges can be mitigated through the strategic deployment of advanced control mechanisms

This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10-100× smaller than the noise generated by a static CMOS circuit. Unlike static CMOS, whose dominant dynamic power is proportional to the frequency, MCML circuits dissipate a constant power independent of clock frequency. Although these traits make MCML highly energy efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at the modest clock rate and with a low activity factor. To address this challenge, a single-core microarchitecture for MCML is explored that exploits the C-slow retiming technique, and operates at a high frequency with low complexity to save energy. This design principle contrasts with the contemporary multicore design paradigm for static CMOS that relies on a large number of gates operating in parallel at the modest speeds. The proposed architecture generates 10-40× lower power and ground noise, and operates within 13% of the performance (i.e., 1/ExecutionTime) of a conventional, eight-core static CMOS processor while exhibiting 1.6× lower energy and 9% less area. Moreover, the operation of an MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length.

This paper proposes a novel soft-switching interleaved boost converter composed of two shunted elementary boost conversion units and an auxiliary inductor. This converter is able to turn on both the active power switches at zero voltage to reduce their switching losses and evidently raise the conversion efficiency. Since the two parallel-operated elementary boost units are identical, operation analysis and design for the converter module becomes quite simple. A laboratory test circuit is built, and the circuit operation shows satisfactory agreement with the theoretical analysis. The experimental results show that this converter module performs very well with the output efficiency as high as 95%.

The main aim of this paper is to improve the performance of high current dual active bridge converters when operated over a wide voltage range. A typical application is for fuel cell vehicles where a bi-directional interface between a 12V battery and a high voltage DC bus is required. The battery side voltage ranges from 11V to 16V while the fuel cell is operated between 220V and 447V and the required power is typically 1kW. Careful analysis shows that the high currents on the battery side cause significant design issues in order to obtain a high efficiency. The standard phase shift modulation method can result in high conduction and switching losses. This paper proposes a combined triangular and trapezoidal modulation method to reduce losses over the wide operating range. Approximately, a 2% improvement in efficiency can be expected. An experimental system is used to verify the improved performance of the dual active bridge using the proposed advanced modulation method.

Input-series and output-parallel (ISOP) converters are suitable for the high input voltage and low output voltage conversion applications. An ISOP current mode AC/AC converter with high frequency link is proposed. The control strategy and operation principle of the ISOP AC/AC converter are investigated. The control strategy ensures the proper sharing of the input voltage and the proper sharing of the output current among the ISOP AC/AC converter. By simulation, the correctness of the operation principle and the control strategy of the ISOP AC/AC converter are proved.

This paper presents an NMOS pseudo-digital low-dropout (PD-LDO) regulator that supports low-voltage operation by eliminating the amplifier of an analog LDO. The proposed pseudo-digital control loop consists of a latched comparator, a 2X charge pump and a RC network. It detects the output voltage and provides a continuous gate control signal for the power transistor by charging and discharging the RC network. Fast transient response is achieved due to the source follower structure of the power NMOS, with a small output capacitor and small occupied chip area and without consuming large quiescent current. The proof-of-concept design of the proposed PD-LDO is implemented in a 0.18-J.1m CMOS process. The minimum supply voltage is 0.7 V, with a dropout voltage of 100 mV and a maximum load current of 100 mA. Using only 20 pF of on-chip output capacitor and 10 MHz comparator clock frequency, the undershoot is 106 mV with 90 mA load current step and 150 ns edge time. The quiescent current is only 6.3 μA and the active chip area is 0.08 mm2.

Embedded NAND-type read-only-memory (NAND-ROM) provides large-capacity, high-reliability, on-chip non-volatile storage. However, NAND-ROM suffers from code-dependent read noises and cannot survive at low supply voltages (VDDs). These code-dependent read noises are primarily due to the charge-sharing effect, bitline leakage current, and crosstalk between bitlines, which become worse at lower VDD. This study proposes a dynamic split source-line (DSSL) scheme for NAND-ROM. The proposed scheme overcomes code-dependent read noises while improving the read access time and suppressing the active-mode gate leakage current, with only a 1% area penalty in the cell array. Experiments on a fabricated 256 Kb macro using a 90 nm industrial logic process demonstrate that the proposed DSSL scheme achieves 100% code-pattern coverage under a small sensing margin. Additionally, the DSSL NAND-ROM works with a wide range of supply voltages (1-0.31 V) with a 38%, 45.8%, and 37% improvement in speed, power, and standby current, respectively, at VDD = 1 V.

A novel on-chip impedance matching and powercombining method, the distributed active transformer is presented. It combines several low-voltage push–pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50match. It also uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any offchip component, such as tuned bonding wires or external inductors. Furthermore, it desensitizes the operation of the amplifier to the inductance of bonding wires making the design more reproducible. To demonstrate the feasibility of this concept, a 2.4-GHz 2-W 2-V truly fully integrated power amplifier with 50input and output matching has been fabricated using 0.35m CMOS transistors. It achieves a power added efficiency (PAE) of 41% at this power level. It can also produce 450 mW using a 1-V supply. Harmonic suppression is 64 dBc or better. This new topology makes possible a truly fully integrated watt-level gigahertz range low-voltage CMOS power amplifier for the first time.

Embedded systems are usually energy constrained. Moreover, in these systems, increased productivity and reduced time to market are essential for product success. To design complex embedded systems while reducing the development time and cost, there is a great tendency to use commercial off-the-shelf (“COTS”) devices. At system level, dynamic voltage and frequency scaling (DVFS) is one of the most effective techniques for energy reduction. Nonetheless, many widely used COTS processors either do not have DVFS or apply DVFS only to processor cores. In this paper, an easy-to-implement COTS-based evaluation platform for low-energy embedded systems is presented. To achieve energy saving, DVFS is provided for the whole microcontroller (including core, phase-locked loop, memory, and I/O). In addition, facilities are provided for experimenting with fault-tolerance techniques. The platform is equipped with energy measurement and debugging equipment. Physical experiments show that applying DVFS on the whole microcontroller provides up to 47% and 12% energy saving compared with the sole use of dynamic power management and applying DVFS only on the core, respectively. Although the platform is designed for ARM-based embedded systems, our approach is general and can be applied to other types of systems.

This brief evaluates the effect of conducted electromagnetic interference (EMI) that is injected in the power supply of a classic Kuijk bandgap reference voltage circuit. Two modified Kuijk bandgap topologies with high immunity to EMI are introduced and compared to the original structure. Measurements of a test IC confirm the theoretical analyses.

A simple technique to achieve low-voltage power-efficient class AB operational transconductance amplifiers (OTAs) is presented. It is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth product (GBW), and near-optimal current efficiency. LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. Three OTA realizations based on this technique have been fabricated in a 0.5-/spl mu/m CMOS technology. For an 80-pF load they show enhancement factors of slew rate and GBW of up to 280 and 3.6, respectively, compared to a conventional class A OTA with the same 10-/spl mu/A quiescent currents and /spl plusmn/1-V supply voltages. In addition, the overhead in terms of common-mode input range, output swing, silicon area, noise, and static power consumption, is minimal.


Question: Design of a power-optimized voltage level shifter for high-speed dual-supply applications.

This paper presents a novel design strategy for a level shifter capable of operating efficiently across a wide voltage range, from subthreshold to above threshold levels. The proposed design is optimized for power consumption, making it particularly suitable for high-speed dual supply applications where power efficiency is critical. Unlike conventional level shifters that often struggle with power dissipation and speed trade-offs, especially when transitioning between different voltage domains, the new design offers a more streamlined solution. It achieves this by incorporating advanced circuit techniques that minimize power loss during voltage level shifting, ensuring that the device can maintain high-speed performance while operating on dual supply voltages. The design is thoroughly evaluated through simulation, demonstrating its ability to effectively manage power consumption without compromising on speed, even under varying supply conditions. This makes it an ideal choice for integrated circuits that require robust and efficient voltage level shifting in high-speed, dual supply environments.

**Question**: A Comparative Study on Different Approaches for Text Summarization

**Documents**: Text Summarization Techniques: A Review

**Similar Documents**: This comprehensive review explores the various techniques and methodologies employed in the field of text summarization. It provides an in-depth analysis of different approaches, ranging from traditional statistical methods to more recent deep learning models, highlighting their strengths and weaknesses. The review covers extractive summarization, which involves selecting key sentences from the original text to form a summary, as well as abstractive summarization, which generates new sentences that convey the essence of the text. It also discusses the role of machine learning and natural language processing in enhancing the quality and coherence of text summaries. The paper offers insights into the latest research trends and challenges in text summarization, making it a valuable resource for researchers and practitioners looking to understand and develop effective summarization techniques.

**Question**: An Investigation into the Impact of Social Media on Mental Health

**Documents**: The Effects of Social Media on Mental Health: A Literature Review

**Similar Documents**: This literature review delves into the complex relationship between social media usage and mental health outcomes. It synthesizes findings from numerous studies to provide a comprehensive understanding of how social media platforms can influence mental well-being. The review examines both positive and negative effects, including the potential for social media to foster connections and support networks, as well as its association with increased feelings of anxiety, depression, and loneliness. It also discusses the role of individual differences, such as age, gender, and personality traits, in moderating these effects. The review concludes by identifying gaps in current research and suggesting areas for future investigation, particularly in understanding the

A 12-bit SAR ADC architecture with dual reference shifting and interpolation technique has been proposed and implemented with 8-way time interleaving in 65nm CMOS. The proposed technique converts 4 bits per SAR conversion cycle with reduced overhead, which is a key to achieve both high speed and resolution while maintaining low power consumption. The measured peak SNDR is 72dB and remains above 65.3dB at 1-GHz input frequency at sample rate of 1.6 GS/s. It achieves a record power efficiency of 17.8fJ/conv-step among the recently published high-speed/resolution ADCs.

An analytical investigation of a dual-mode ring oscillator is presented. The ring oscillator is designed using a CMOS 0.18-μm technology with differential eight-stage delay cells employing auxiliary input devices. With a proper startup control, the oscillator operates in two different modes covering two different frequency bands. A nonlinear model, along with the linearization method, is used to obtain the transient and steady-state behaviors of the dual-mode ring oscillator. The analytical derivations are verified through HSPICE simulation. The oscillator operates at the frequency bands from 2-5 GHz and from 0.1-2 GHz, respectively.

This paper proposes a new soft-switched continuous-conduction-mode (CCM) boost converter suitable for high-power applications such as power factor correction, hybrid electric vehicles, and fuel cell power conversion systems. The proposed converter achieves zero-voltage-switched (ZVS) turn-on of active switches in CCM and zero-current-switched turn-off of diodes leading to negligible reverse-recovery loss. The components' voltage ratings and energy volumes of passive components of the proposed converter are greatly reduced compared to the conventional zero-voltage-transition converter. Voltage conversion ratio is almost doubled compared to the conventional boost converter. Extension of the proposed concept to realize multiphase dc-dc converters is discussed. Experimental results from a 1.5-kW prototype are provided to validate the proposed concept.

In this paper, an area-efficient cross-coupled charge pump for standalone chip using on-chip solar cell is proposed. The proposed cross-coupled charge pump outputs higher voltage than conventional cross-coupled charge pump on the same area by adding capacitors to drive MOS transistors. The proposed circuit is fabricated in 0.18um standard CMOS process, and outputs 80mV higher than the conventional circuit with 500mV input and 100kHz clock frequency.

A fully integrated step-down switched-capacitor dc–dc converter ring with 123 phases has been designed that could achieve fast dynamic voltage scaling for the microprocessor of wearable devices. The symmetrical multiphase converter ring surrounds its load in the square and supplies power to the on-chip power grid that is easily accessible at any point of the chip edges. The frequency of the <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula>-controlled oscillator is adjusted through its supply voltage <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula>, which allows the unity-gain frequency to be designed higher than the switching frequency. The converter ring has been fabricated in a low-leakage 65-nm CMOS process. This converter achieves a response time of 3 ns, a reference tracking speed of 2.5 V/<inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>, and a minimum output ripple of 2.2 mV. The peak efficiency is 80% at the power density of 66.6 mW/mm2, and the maximum power density is 180 mW/mm2.

This paper analyzes the signaling and digital power overhead of pre-emphasis voltage-mode transmitters. Utilizing a shunt branch in parallel with the differential channel to implement pre-emphasis is shown to have the best overall energy-efficiency. Leveraging this technique, an efficient pre-emphasis voltage mode transmitter architecture with output amplitude control, pre-emphasis coefficient control, and online impedance calibration is proposed and demonstrated. A 65 nm LP CMOS implementation of this architecture dissipates ~ 10 mW from a 1.2 V supply when transmitting 10 Gb/s 200 mV differential amplitude data with 2-tap pre-emphasis, achieving 1 pJ/bit energy efficiency.

In this paper, we propose an output driver which has constant slew rate over PVT variation. To make output driver's slew rate to be constant, rising and failing time of pre-driving node of output driver is kept constant by predriver, which has constant pull-up and pull-down path resistance. To make output voltage swing level to be constant, another replica bias circuit was used with CMOS push-pull output driver. HSPICE simulations show that the slew rate is 3.21 V/nS on fast condition and 3.12V/nS on slow condition with 1.4K pre-driver's path resistance. This circuit was implemented with 0.18 /spl mu/m CMOS process.

This paper presents a reconfigurable, low offset, low noise and high speed dynamic clocked-comparator for medium to high resolution Analog to Digital Converters (ADCs). The proposed comparator reduces the input referred noise by half and shows a better output driving capability when compared with the previous work. The offset, noise and power consumption can be controlled by a clock delay which allows simple reconfiguration. Moreover, the proposed offset calibration technique improves the offset voltage from 11.6mV to 533μV at 1 sigma. A prototype of the comparator is implemented in 90nm 1P8M CMOS with experimental results showing 320μV input referred noise at 1.5GHz with 1.2V supply.

This paper presents a new fully differential operational transconductance amplifier (OTA) for low-voltage and fast-settling switched-capacitor circuits in digital CMOS technology. The proposed two-stage OTA is a hybrid class A/AB that combines a folded cascode as the first stage with active current mirrors as the second stage. It employs a hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling.

In this paper, an input-series two-transistor forward converter is proposed and investigated, which is aimed at high-input voltage multiple-output applications. In this converter, all of the switches are operating synchronously, and the input voltage sharing (IVS) of each series-module is achieved automatically by the coupling of primary windings of the common forward integrated transformer. The active IVS processes are analyzed based on the model of the forward integrated transformer. Through the influence analysis when the mismatches in various series-modules are considered, design principles of the key parameters in each series-module are discussed to suppress the input voltage difference. Finally, a 96-W laboratory-made prototype composed of two forward series-modules is built, and the feasibility of the proposed method and the theoretical analysis are verified by the experimental results.


Question: Verifiable data possession at untrusted storage locations

This paper introduces the concept of aggregate and verifiably encrypted signatures derived from bilinear maps, offering a novel approach to digital signature aggregation and encryption verification. An aggregate signature scheme enables the merging of multiple signatures into a single, concise signature, significantly reducing the storage and transmission requirements for verifying a set of signatures. Given n signatures on n distinct messages from n distinct users, the scheme allows for the consolidation of these signatures into one compact signature, ensuring that the verifier can confirm each user's signature on their respective message (i.e., user i signed message Mi for i = 1, ..., n). The paper presents security models for such signatures and discusses their applications, including the reduction of certificate chain sizes by aggregating all signatures in the chain and decreasing message size in secure routing protocols like SBGP.

The aggregate signature scheme is constructed using a recent short signature scheme based on bilinear maps, originally proposed by Boneh, Lynn, and Shacham. This method not only offers efficient aggregation but also leads to the development of verifiably encrypted signatures. These signatures enable the verifier to check if a given ciphertext C is the encryption of a signature on a given message M, which is particularly useful in contract-signing protocols. Additionally, the paper demonstrates how similar ideas can be applied to extend the short signature scheme to provide simple ring signatures, enhancing the versatility of the aggregate and verifiably encrypted signature framework.

This paper presents efficient off-line anonymous e-cash schemes where a user can withdraw a wallet containing 2 coins each of which she can spend unlinkably. Our first result is a scheme, secure under the strong RSA and the y-DDHI assumptions, where the complexity of the withdrawal and spend operations is O( + k) and the user’s wallet can be stored using O( +k) bits, where k is a security parameter. The best previously known schemes require at least one of these complexities to be O(2 · k). In fact, compared to previous e-cash schemes, our whole wallet of 2 coins has about the same size as one coin in these schemes. Our scheme also offers exculpability of users, that is, the bank can prove to third parties that a user has double-spent. We then extend our scheme to our second result, the first e-cash scheme that provides traceable coins without a trusted third party. That is, once a user has double spent one of the 2 coins in her wallet, all her spendings of these coins can be traced. However, the price for this is that the complexity of the spending and of the withdrawal protocols becomes O( · k) and O( · k + k) bits, respectively, and wallets take O( · k) bits of storage. All our schemes are secure in the random oracle model.

Bitcoin and Ethereum are novel mechanisms for decentralizing the concept of money and computation. Extending decentralization to the human identity concept, we can think of using blockchain for creating a list of verified human identities with a one-person-one-ID property. UniqueID is a Decentralized Autonomous Organization(DAO) for maintaining human identities such that every physical human entity can have no more that one account. One part of this identity is simply the user’s claim on one of his unique, permanent, and measurable characteristics -biometrics. Blockchain has proved its integrity as a platform for storing and performing computations on such claims. The biggest challenge here is to ensure that the user has submitted his own valid biometric data. Human verifiers can check if there is any inconsistency in other users’ data, by peer-to-peer checks. For preventing bad behavior and centralization in the verification process, UniqueID benefits from novel governance mechanisms to choose verifiers and punish unjust ones. Also, there are incentives for honest verifiers and users by newly generated tokens. We show how the users’ privacy can be preserved by using stateof-the-art cryptographic techniques, and so they can use their identity without any concerns for votings, financial and banking purposes, social media accounts, reputation systems etc.

Securely maintaining log records over extended periods of time is very important to the proper functioning of any organization. Integrity of the log files and that of the logging process need to be ensured at all times. In addition, as log files often contain sensitive information, confidentiality and privacy of log records are equally important. However, deploying a secure logging infrastructure involves substantial capital expenses that many organizations may find overwhelming. Delegating log management to the cloud appears to be a viable cost saving measure. In this paper, we identify the challenges for a secure cloud-based log management service and propose a framework for doing the same.

Zero-knowledge proofs of knowledge and fully-homomorphic encryption are two areas that have seen considerable advances in recent years, and these two techniques are used in conjunction in the context of verifiable decryption. Existing solutions for verifiable decryption are aimed at the batch setting, however there are many applications in which there will only be one ciphertext that requires a proof of decryption. The purpose of this paper is to provide a zero-knowledge proof of correct decryption on an FHE ciphertext, which for instance could hold the result of a cryptographic election. We give two main contributions. Firstly, we present a bootstrapping-like protocol to switch from one FHE scheme to another. The first scheme has efficient homomorphic capabilities; the second admits a simple zero-knowledge protocol. To illustrate this, we use the Brakerski et al. (ITCS, 2012) scheme for the former, and Gentry’s original scheme (STOC, 2009) for the latter. Secondly, we present a simple one-shot zero-knowledge protocol for verifiable decryption using Gentry’s original FHE scheme.

We propose a mediated certificateless encryption scheme without pairing operations for securely sharing sensitive information in public clouds. Mediated certificateless public key encryption (mCL-PKE) solves the key escrow problem in identity based encryption and certificate revocation problem in public key cryptography. However, existing mCL-PKE schemes are either inefficient because of the use of expensive pairing operations or vulnerable against partial decryption attacks. In order to address the performance and security issues, in this paper, we first propose a mCL-PKE scheme without using pairing operations. We apply our mCL-PKE scheme to construct a practical solution to the problem of sharing sensitive information in public clouds. The cloud is employed as a secure storage as well as a key generation center. In our system, the data owner encrypts the sensitive data using the cloud generated users' public keys based on its access control policies and uploads the encrypted data to the cloud. Upon successful authorization, the cloud partially decrypts the encrypted data for the users. The users subsequently fully decrypt the partially decrypted data using their private keys. The confidentiality of the content and the keys is preserved with respect to the cloud, because the cloud cannot fully decrypt the information. We also propose an extension to the above approach to improve the efficiency of encryption at the data owner. We implement our mCL-PKE scheme and the overall cloud based system, and evaluate its security and performance. Our results show that our schemes are efficient and practical.

Multicast stream authentication and signing is an important and challenging problem. Applications include the continuous authentication of radio and TV Internet broadcasts, and authenticated data distribution by satellite. The main challenges are fourfold. First, authenticity must be guaranteed even when only the sender of the data is trusted. Second, the scheme needs to scale to potentially millions of receivers. Third, streamed media distribution can have high packet loss. Finally, the system needs to be efficient to support fast packet rates. We propose two efficient schemes, TESLA and EMSS, for secure lossy multicast streams. TESLA, short for Timed Efficient Stream Loss-tolerant Authentication, offers sender authentication, strong loss robustness, high scalability, and minimal overhead, at the cost of loose initial time synchronization and slightly delayed authentication. EMSS, short for Efficient Multi-chained Stream Signature, provides nonrepudiation of origin, high loss resistance, and low overhead, at the cost of slightly delayed verification. This work began in Summer 1999 when Adrian Perrig and Dawn Song were visiting the IBM T. J. Watson research lab. Initial research on stream authentication was done during Summer 1999 by Ran Canetti, Adrian Perrig, and Dawn Song at IBM. Additional improvements were suggested by J. D. Tygar in Fall 1999 at UC Berkeley. Implementation was done in Fall 1999 by Adrian Perrig at UC Berkeley. The work on stream signatures was done by J. D. Tygar, Adrian Perrig, and Dawn Song at UC Berkeley. Additional work was performed by Ran Canetti in Spring 2000. Ran Canetti is at IBM T. J. Watson Research Center, and Adrian Perrig, Dawn Song, and J. D. Tygar are at the Computer Science Division, UC Berkeley. This research was suported in part by the Defense Advanced Research Projects Agency under DARPA contract N6601-99-28913 (under supervision of the Space and Naval Warfare Systems Center San Diego), by the National Science foundation under grant FD99-79852, and by the United States Postal Service under grant USPS 1025 90-98-C-3513. Views and conclusions contained in this document are those of the authors and do not necessarily represent the official opinion or policies, either expressed or implied of the US government or any of its agencies, DARPA, NSF, USPS, or IBM.

This paper reviews some of the difficulties that arise in the verification of kernelized secure systems and suggests new techniques for their resolution.
 It is proposed that secure systems should be conceived as distributed systems in which security is achieved partly through the physical separation of its individual components and partly through the mediation of trusted functions performed within some of those components. The purpose of a security kernel is simply to allow such a 'distributed' system to actually run within a single processor; policy enforcement is not the concern of a security kernel.
 This approach decouples verification of components which perform trusted functions from verification of the security kernel. This latter task may be accomplished by a new verification technique called 'proof of separability' which explicitly addresses the security relevant aspects of interrupt handling and other issues ignored by present methods.

Goal: Highly available data storage in large-scale distributed systems in which * Hosts are transiently inaccessible * Individual host failures are common Current peer-to-peer systems are prime examples * Highly dynamic, challenging environment * hosts join and leave frequently in short-term * Hosts leave permanently over long-term * Workload varies in terms of popularity, access patterns, file size These systems require automated availability management.

Sergei Arnautov, Bohdan Trach, Franz Gregor, Thomas Knauth, Andre Martin, Christian Priebe, Joshua Lind, Divya Muthukumaran, Dan O’Keeffe, Mark L Stillwell, David Goltzsche, David Eyers, Rüdiger Kapitza, Peter Pietzuch, and Christof Fetzer Fakultät Informatik, TU Dresden, christof.fetzer@tu-dresden.de Dept. of Computing, Imperial College London, prp@imperial.ac.uk Informatik, TU Braunschweig, rrkapitz@ibr.cs.tu-bs.de Dept. of Computer Science, University of Otago, dme@cs.otago.ac.nz

Trust is a critical factor in cloud computing; in present practice it depends largely on perception of reputation, and self assessment by providers of cloud services. We begin this paper with a survey of existing mechanisms for establishing trust, and comment on their limitations. We then address those limitations by proposing more rigorous mechanisms based on evidence, attribute certification, and validation, and conclude by suggesting a framework for integrating various trust mechanisms together to reveal chains of trust in the cloud.


Question: Verifiable data possession at untrusted storage sites.

This paper introduces and investigates proofs of retrievability (PORs), a novel concept designed for large files or bitstrings. A POR scheme empowers an archive or backup service (the prover) to furnish a succinct proof to a user (the verifier) that the target file F can be retrieved. This assurance indicates that the archive maintains and can transmit sufficient file data for the user to reconstruct F in its entirety. Conceptually, a POR can be likened to a cryptographic proof of knowledge (POK), albeit one specifically tailored for handling large files.

We delve into POR protocols where the communication costs, the number of memory accesses for the prover, and the storage requirements of the user are all small, effectively independent of the length of F. Our work not only proposes new, practical POR constructions but also examines implementation nuances and optimizations relevant to previously explored, related schemes.

A significant distinction between a POR and a POK lies in the fact that neither the prover nor the verifier necessarily possess knowledge of F. The formulation of a new and unique security definition for PORs is yet another contribution of our research.

PORs are envisioned as a critical tool for semi-trusted online archives. While existing cryptographic methods assist users in ensuring the privacy and integrity of retrieved files, users also have a natural desire to confirm that archives neither alter nor delete files before retrieval. The objective of a POR is to facilitate these verifications without requiring users to download the files. Furthermore, a POR can offer quality-of-service guarantees, demonstrating that a file can be retrieved within a specific time frame.

Bit coin is the first digital currency to see widespread adoption. While payments are conducted between pseudonyms, Bit coin cannot offer strong privacy guarantees: payment transactions are recorded in a public decentralized ledger, from which much information can be deduced. Zero coin (Miers et al., IEEE S&P 2013) tackles some of these privacy issues by unlinking transactions from the payment's origin. Yet, it still reveals payments' destinations and amounts, and is limited in functionality. In this paper, we construct a full-fledged ledger-based digital currency with strong privacy guarantees. Our results leverage recent advances in zero-knowledge Succinct Non-interactive Arguments of Knowledge (zk-SNARKs). First, we formulate and construct decentralized anonymous payment schemes (DAP schemes). A DAP scheme enables users to directly pay each other privately: the corresponding transaction hides the payment's origin, destination, and transferred amount. We provide formal definitions and proofs of the construction's security. Second, we build Zero cash, a practical instantiation of our DAP scheme construction. In Zero cash, transactions are less than 1 kB and take under 6 ms to verify - orders of magnitude more efficient than the less-anonymous Zero coin and competitive with plain Bit coin.

A (t; k; n; S) ramp scheme is a protocol to distribute a secret s chosen inS among a setP of n participants in such a way that: 1) sets of participants of cardinality greater than or equal to k can reconstruct the secrets; 2) sets of participants of cardinality less than or equal tot have no information on s, whereas 3) sets of participants of cardinality greater than t and less thank might have “some” information on s. In this correspondence we analyze multiple ramp schemes, which are protocols to share many secrets among a set P of participants, using different ramp schemes. In particular, we prove a tight lower bound on the size of the shares held by each participant and on the dealer’s randomness in multiple ramp schemes.

This paper studies two design tasks faced by a geo-distributed cloud data market: which data to purchase data purchasing and where to place/replicate the data for delivery data placement. We show that the joint problem of data purchasing and data placement within a cloud data market can be viewed as a facility location problem and is thus NP-hard. However, we give a provably optimal algorithm for the case of a data market made up of a single data center and then generalize the structure from the single data center setting in order to develop a near-optimal, polynomial-time algorithm for a geo-distributed data market. The resulting design, $\mathsf {Datum}$ , decomposes the joint purchasing and placement problem into two subproblems, one for data purchasing and one for data placement, using a transformation of the underlying bandwidth costs. We show, via a case study, that $\mathsf {Datum}$ is near optimal within 1.6% in practical settings.

The need for anonymity preservation within the justice domain requires the introduction of a trusted third party as an intermediary, while integrating individual databases within its boundaries. After the trusted third party encrypts records, it is no longer possible to perform checks on the data quality and correct data anomalies. Therefore, this research examines the concepts of data quality, data integration, record linkage and trusted third party and, then, combines these with four expert interviews in order to identify ways to assess and improve data quality while linking privacy-sensitive data. Next, the trusted data linkage framework (TDLF) is presented to aid data quality management while combining citizens’ privacy-sensitive data from different organisations. Finally, we evaluate the framework in a case study to demonstrate how the quality of structured judicial data can be managed prior to its encryption, while using multiple databases as sources of data and a different final recipient.

Remote attestation is the activity of making a claim about properties of a target by supplying evidence to an appraiser over a network. We identify five central principles to guide development of attestation systems. We argue that (i) attestation must be able to deliver temporally fresh evidence; (ii) comprehensive information about the target should be accessible; (iii) the target, or its owner, should be able to constrain disclosure of information about the target; (iv) attestation claims should have explicit semantics to allow decisions to be derived from several claims; and (v) the underlying attestation mechanism must be trustworthy. We illustrate how to acquire evidence from a running system, and how to transport it via protocols to remote appraisers. We propose an architecture for attestation guided by these principles. Virtualized platforms, which are increasingly well supported on stock hardware, provide a natural basis for our attestation architecture.

Now a day's cloud computing is used in many areas like industry, military colleges etc to storing huge amount of data. We can retrieve data from cloud on request of user. To store data on cloud we have to face many issues. To provide the solution to these issues there are n number of ways. Cryptography and steganography techniques are more popular now a day's for data security. Use of a single algorithm is not effective for high level security to data in cloud computing. In this paper we have introduced new security mechanism using symmetric key cryptography algorithm and steganography. In this proposed system AES, blowfish, RC6 and BRA algorithms are used to provide block wise security to data. All algorithm key size is 128 bit. LSB steganography technique is introduced for key information security. Key information contains which part of file is encrypted using by which algorithm and key. File is splited into eight parts. Each and every part of file is encrypted using different algorithm. All parts of file are encrypted simultaneously with the help of multithreading technique. Data encryption Keys are inserted into cover image using LSB technique. Stego image is send to valid receiver using email. For file decryption purpose reverse process of encryption is applied.

Search over encrypted data is a critically important enabling technique in cloud computing, where encryption-before-outsourcing is a fundamental solution to protecting user data privacy in the untrusted cloud server environment. Many secure search schemes have been focusing on the single-contributor scenario, where the outsourced dataset or the secure searchable index of the dataset are encrypted and managed by a single owner, typically based on symmetric cryptography. In this paper, we focus on a different yet more challenging scenario where the outsourced dataset can be contributed from multiple owners and are searchable by multiple users, i.e., multi-user multi-contributor case. Inspired by attribute-based encryption (ABE), we present the first attribute-based keyword search scheme with efficient user revocation (ABKS-UR) that enables scalable fine-grained (i.e., file-level) search authorization. Our scheme allows multiple owners to encrypt and outsource their data to the cloud server independently. Users can generate their own search capabilities without relying on an always online trusted authority. Fine-grained search authorization is also implemented by the owner-enforced access policy on the index of each file. Further, by incorporating proxy re-encryption and lazy re-encryption techniques, we are able to delegate heavy system update workload during user revocation to the resourceful semi-trusted cloud server. We formalize the security definition and prove the proposed ABKS-UR scheme selectively secure against chosen-keyword attack. To build confidence of data user in the proposed secure search system, we also design a search result verification scheme. Finally, performance evaluation shows the efficiency of our scheme.

Sego is a hypervisor-based system that gives strong privacy and integrity guarantees to trusted applications, even when the guest operating system is compromised or hostile. Sego verifies operating system services, like the file system, instead of replacing them. By associating trusted metadata with user data across all system devices, Sego verifies system services more efficiently than previous systems, especially services that depend on data contents. We extensively evaluate Sego's performance on real workloads and implement a kernel fault injector to validate Sego's file system-agnostic crash consistency and recovery protocol.

Keeping communication private has become increasingly important in an era of mass surveillance and statesponsored attacks. While hiding the contents of a conversation has well-known solutions, hiding the associated metadata (participants, duration, etc.) remains a challenge, especially if one cannot trust ISPs or proxy servers. This paper describes a communication system called Pung that provably hides all content and metadata while withstanding global adversaries. Pung is a key-value store where clients deposit and retrieve messages without anyone— including Pung’s servers—learning of the existence of a conversation. Pung is based on private information retrieval, which we make more practical for our setting with new techniques. These include a private multi-retrieval scheme, an application of the power of two choices, and batch codes. These extensions allow Pung to handle 103× more users than prior systems with a similar threat model.

We propose the first differentially private aggregation algorithm for distributed time-series data that offers good practical utility without any trusted server. This addresses two important challenges in participatory data-mining applications where (i) individual users collect temporally correlated time-series data (such as location traces, web history, personal health data), and (ii) an untrusted third-party aggregator wishes to run aggregate queries on the data.
 To ensure differential privacy for time-series data despite the presence of temporal correlation, we propose the Fourier Perturbation Algorithm (FPAk). Standard differential privacy techniques perform poorly for time-series data. To answer n queries, such techniques can result in a noise of Θ(n) to each query answer, making the answers practically useless if n is large. Our FPAk algorithm perturbs the Discrete Fourier Transform of the query answers. For answering n queries, FPAk improves the expected error from Θ(n) to roughly Θ(k) where k is the number of Fourier coefficients that can (approximately) reconstruct all the n query answers. Our experiments show that k << n for many real-life data-sets resulting in a huge error-improvement for FPAk.
 To deal with the absence of a trusted central server, we propose the Distributed Laplace Perturbation Algorithm (DLPA) to add noise in a distributed way in order to guarantee differential privacy. To the best of our knowledge, DLPA is the first distributed differentially private algorithm that can scale with a large number of users: DLPA outperforms the only other distributed solution for differential privacy proposed so far, by reducing the computational load per user from O(U) to O(1) where U is the number of users.