Question: Building and optimal search in interpolated motion graphs.

This paper explores the integration of Laban Movement Analysis (LMA) principles, particularly Effort and Shape, into the procedural generation of human-like movements for computer animation. While much research has focused on limb gestures and postural attitudes, the naturalness of these movements remains a challenge. We propose that the psychological concept of gesture alone is insufficient for capturing the nuanced qualities necessary for animated characters. Drawing from LMA, we highlight the significance of Effort and Shape parameters in describing the qualitative aspects of movements. Moreover, we emphasize the importance of considering the holistic engagement of the body and the consistent phrasing of Effort and Shape across movements for achieving naturalness in procedurally generated gestures. To this end, we introduce EMOTE (Expressive MOTion Engine), a 3D character animation system that applies Effort and Shape qualities to pre-defined movements, resulting in more lifelike and expressive synthetic gestures. This approach not only enhances the realism of animated characters but also offers a framework for the construction and optimization of interpolated motion graphs, aligning with the core inquiry of this discussion.

Data association is the backbone to many multiple object tracking (MOT) methods. In this paper we formulate data association as a Generalized Maximum Multi Clique problem (GMMCP). We show that this is the ideal case of modeling tracking in real world scenario where all the pairwise relationships between targets in a batch of frames are taken into account. Previous works assume simplified version of our tracker either in problem formulation or problem optimization. However, we propose a solution using GMMCP where no simplification is assumed in either steps. We show that the NP hard problem of GMMCP can be formulated through Binary-Integer Program where for small and medium size MOT problems the solution can be found efficiently. We further propose a speed-up method, employing Aggregated Dummy Nodes for modeling occlusion and miss-detection, which reduces the size of the input graph without using any heuristics. We show that, using the speedup method, our tracker lends itself to real-time implementation which is plausible in many applications. We evaluated our tracker on six challenging sequences of Town Center, TUD-Crossing, TUD-Stadtmitte, Parking-lot 1, Parking-lot 2 and Parking-lot pizza and show favorable improvement against state of art.

The Iterative Closest Point (ICP) algorithm is widely used to register two roughly aligned surfaces. Its most expensive step is the search for the closest point. Many efficient variants have been proposed to speed up this step, however they do not guarantee that the closest point on a triangulated surface is found. Instead they might result in an approximation of the closest point. In this paper we present a method for the closest point search that is fast and exact. The method was implemented and used to evaluate the accuracy of head motion estimation using dense 3D data obtained from a stereo camera system. The results show that the accuracy of the estimated head motion is better than 1 mm for translational movements and better than 1 degree for rotations. Key-Words: Iterative Closest Point, 3D Registration, Stereo, Head Motion Estimation

Stroke correspondence construction is a precondition for vectorized 2D animation inbetweening and remains a challenging problem. This paper introduces the FTP-SC, a fuzzy topology preserving stroke correspondence technique, which is accurate and provides the user more effective control on the correspondence result than previous matching approaches. The method employs a two-stage scheme to progressively establish the stroke correspondence construction between the keyframes. In the first stage, the stroke correspondences with high confidence are constructed by enforcing the preservation of the so-called “fuzzy topology” which encodes intrinsic connectivity among the neighboring strokes. Starting with the high-confidence correspondences, the second stage performs a greedy matching algorithm to generate a full correspondence between the strokes. Experimental results show that the FTP-SC outperforms the existing approaches and can establish the stroke correspondence with a reasonable amount of user interaction even for keyframes with large geometric and spatial variations between strokes. CCS Concepts •Computing methodologies → Animation; Parametric curve and surface models;

Recent scientific and technological advances have witnessed an abundance of structural patterns modeled as graphs. As a result, it is of special interest to process graph containment queries effectively on large graph databases. Given a graph database G, and a query graph q, the graph containment query is to retrieve all graphs in G which contain q as subgraph(s). Due to the vast number of graphs in G and the nature of complexity for subgraph isomorphism testing, it is desirable to make use of high-quality graph indexing mechanisms to reduce the overall query processing cost. In this paper, we propose a new cost-effective graph indexing method based on frequent tree-features of the graph database. We analyze the effectiveness and efficiency of tree as indexing feature from three critical aspects: feature size, feature selection cost, and pruning power. In order to achieve better pruning ability than existing graph-based indexing methods, we select, in addition to frequent tree-features (Tree), a small number of discriminative graphs (∆) on demand, without a costly graph mining process beforehand. Our study verifies that (Tree+∆) is a better choice than graph for indexing purpose, denoted (Tree+∆ ≥Graph), to address the graph containment query problem. It has two implications: (1) the index construction by (Tree+∆) is efficient, and (2) the graph containment query processing by (Tree+∆) is efficient. Our experimental studies demonstrate that (Tree+∆) has a compact index structure, achieves an order of magnitude better performance in index construction, and most importantly, outperforms up-to-date graphbased indexing methods: gIndex and C-Tree, in graph containment query processing.

This paper presents a new algorithm for mobile robot localization, called Monte Carlo Localization (MCL). MCL is a version of Markov localization, a family of probabilistic approaches that have recently been applied with great practical success. However, previous approaches were either computationally cumbersome (such as grid-based approaches that represent the state space by high-resolution 3D grids), or had to resort to extremely coarse-grained resolutions. Our approach is computationally efficient while retaining the ability to represent (almost) arbitrary distributions. MCL applies sampling-based methods for approximating probability distributions, in a way that places computation “where needed.” The number of samples is adapted on-line, thereby invoking large sample sets only when necessary. Empirical results illustrate that MCL yields improved accuracy while requiring an order of magnitude less computation when compared to previous approaches. It is also much easier to implement.

Optical flow cannot be computed locally, since only one independent measurement is available from the image sequence at a point, while the flow velocity has two components. A second constraint is needed. A method for finding the optical flow pattern is presented which assumes that the apparent velocity of the brightness pattern varies smoothly almost everywhere in the image. An iterative implementation is shown which successfully computes the optical flow for a number of synthetic image sequences. The algorithm is robust in that it can handle image sequences that are quantized rather coarsely in space and time. It is also insensitive to quantization of brightness levels and additive noise. Examples are included where the assumption of smoothness is violated at singular points or along lines in the image.

We introduce a dynamic technique for fast route planning in large road networks. For the first time, it is possible to handle the practically relevant scenarios that arise in present-day navigation systems: When an edge weight changes (e.g., due to a traffic jam), we can update the preprocessed information in 2–40 ms allowing subsequent fast queries in about one millisecond on average. When we want to perform only a single query, we can skip the comparatively expensive update step and directly perform a prudent query that automatically takes the changed situation into account. If the overall cost function changes (e.g., due to a different vehicle type), recomputing the preprocessed information takes typically less than two minutes. The foundation of our dynamic method is a new static approach that generalises and combines several previous speedup techniques. It has outstandingly low memory requirements of only a few bytes per node.

ÐA new view-based approach to the representation and recognition of human movement is presented. The basis of the representation is a temporal templateÐa static vector-image where the vector value at each point is a function of the motion properties at the corresponding spatial location in an image sequence. Using aerobics exercises as a test domain, we explore the representational power of a simple, two component version of the templates: The first value is a binary value indicating the presence of motion and the second value is a function of the recency of motion in a sequence. We then develop a recognition method matching temporal templates against stored instances of views of known actions. The method automatically performs temporal segmentation, is invariant to linear changes in speed, and runs in real-time on standard platforms. Index TermsÐMotion recognition, computer vision.

Human analysis in images and video is a hard problem due to the large variation in human pose, clothing, camera view-points, lighting and other factors. While the explicit modeling of this variability is difficult, the huge amount of available person images motivates for the implicit, data-driven approach to human analysis. In this work we aim to explore this approach using the large amount of images spanning a subspace of human appearance. We model this subspace by connecting images into a graph and propagating information through such a graph using a discriminatively-trained graphical model. We particularly address the problems of human pose estimation and action recognition and demonstrate how image graphs help solving these problems jointly. We report results on still images with human actions from the KTH dataset.

We present a concept and formalism, the string graph, which represents all that is inferable about a DNA sequence from a collection of shotgun sequencing reads collected from it. We give time and space efficient algorithms for constructing a string graph given the collection of overlaps between the reads and, in particular, present a novel linear expected time algorithm for transitive reduction in this context. The result demonstrates that the decomposition of reads into kmers employed in the de Bruijn graph approach described earlier is not essential, and exposes its close connection to the unitig approach we developed at Celera. This paper is a preliminary piece giving the basic algorithm and results that demonstrate the efficiency and scalability of the method. These ideas are being used to build a next-generation whole genome assembler called BOA (Berkeley Open Assembler) that will easily scale to mammalian genomes.


Question: A parasitic inductance and capacitance-supported active gate driving method to reduce switching loss in SiC MOSFETs.

This document introduces an innovative active gate driver (AGD) for IGBT modules designed to enhance their operational efficiency under both standard and fault conditions. The proposed AGD incorporates a di/dt feedback-controlled current source and sink, alongside a push-pull buffer, to dynamically control the gate current during switching transients. This strategy significantly reduces switching loss, delay times, and the duration of the Miller plateau during turn-on and turn-off phases, without compromising the stress levels of current and voltage. In the event of an overcurrent condition, the AGD offers a rapid protection mechanism for IGBT modules, assessing the fault current magnitude through the di/dt feedback signal. Notably, the AGD supports adaptable protection modes, preventing unnecessary interruptions to converter operations during transient short circuits. To evaluate the effectiveness of the proposed AGD under diverse conditions, including variations in gate resistance during turn-on/off, current levels, and types of short-circuit faults, a step-down converter was constructed. Comprehensive experimental results and detailed analyses are provided to substantiate the viability and superiority of the proposed AGD methodology.

We propose a novel nLDMOS structure and a design concept in BCD technology with the best-in-class performance. The drift profile is optimized and the multi-oxide in the drift region is adopted to approach the RESURF limit of on-resistance vs. BVdss characteristic (i.e., 36V DMOS has a Ron_sp of 20mohm-mm2 with a BVdss of 50V; 45V DMOS has a Ron_sp of 28mohm-mm2 with a BVdss of 65V). Moreover, this modification requires merely three extra masks in the Non-Epitaxy LV process to achieve this improvement. Therefore it is not only a high performance but also a low cost solution.

This paper presents a new topology of higher order power filter for grid-tied voltage-source inverters, named the LLCL filter, which inserts a small inductor in the branch loop of the capacitor in the traditional LCL filter to compose a series resonant circuit at the switching frequency. Particularly, it can attenuate the switching-frequency current ripple components much better than an LCL filter, leading to a decrease in the total inductance and volume. Furthermore, by decreasing the inductance of a grid-side inductor, it raises the characteristic resonance frequency, which is beneficial to the inverter system control. The parameter design criteria of the proposed LLCL filter is also introduced. The comparative analysis and discussions regarding the traditional LCL filter and the proposed LLCL filter have been presented and evaluated through experiment on a 1.8-kW-single-phase grid-tied inverter prototype.

Switched-capacitor DC-DC converters are useful alternatives to inductor-based converters in many lowpower and medium-power applications. This work develops a straightforward analysis method to determine a switched-capacitor converter’s output impedance (a measure of performance and power loss). This resistive impedance is a function of frequency and has two asymptotic limits, one corresponding to very high switching frequency where resistive paths dominate the impedance, and one corresponding to very low switching frequency where charge transfers among idealized capacitors dominate the impedance. An optimization method is developed to improve the performance of these converters through component sizing based on practical constraints. Several switched-capacitor converter topologies are compared in the two asymptotic limits. Switched-capacitor converter performance (based on conduction loss) is compared with that of two magnetics-based DC-DC converters. At moderate to high conversion ratios, the switchedcapacitor converter has significantly less conduction loss than an inductor-based buck converter. Some aspects of converter implementation are discussed, including the power loss due to device parasitics and methods for transistor control. Implementation using both integrated and discrete devices is discussed. With the correct analysis methods, switched-capacitor DC-DC converters can provide an attractive alternative to conventional power converters.

This paper introduces a large air-gap capacitive wireless power transfer (WPT) system for electric vehicle charging that achieves a power transfer density exceeding the state-of-the-art by more than a factor of four. This high power transfer density is achieved by operating at a high switching frequency (6.78 MHz), combined with an innovative approach to designing matching networks that enable effective power transfer at this high frequency. In this approach, the matching networks are designed such that the parasitic capacitances present in a vehicle charging environment are absorbed and utilized as part of the wireless power transfer mechanism. A new modeling approach is developed to simplify the complex network of parasitic capacitances into equivalent capacitances that are directly utilized as the matching network capacitors. A systematic procedure to accurately measure these equivalent capacitances is also presented. A prototype capacitive WPT system with 150 cm2 coupling plates, operating at 6.78 MHz and incorporating matching networks designed using the proposed approach, is built and tested. The prototype system transfers 589 W of power across a 12-cm air gap, achieving a power transfer density of 19.6 kW/m2.

This paper highlights the general trend towards further monolithic integration in power applications by enabling power management and interfacing solutions in advanced CMOS nodes. The need to combine high-density digital circuits, power-management circuits, and robust interfaces in a single technology platform requires the development of additional process options on top of baseline CMOS. Examples include high-voltage devices, devices to enable area-efficient ESD protection, and integrated capacitors and inductors with high quality factors. The use of bipolar devices in these technologies for protection and control purposes in power applications is also addressed.

A new isolated current-fed pulsewidth modulation dc-dc converter-current-fed dual-bridge dc-dc converter-with small inductance and no deadtime operation is presented and analyzed. The new topology has more than 3times smaller inductance than that of current-fed full-bridge converter, thus having faster transient response speed. Other characteristics include simple self-driven synchronous rectification, simple housekeeping power supply, and smaller output filter capacitance. Detailed analysis shows the proposed converter can have either lower voltage stress on all primary side power switches or soft switching properties when different driving schemes are applied. A 48-V/125-W prototype dc-dc converter with dual output has been tested for the verification of the principles. Both simulations and experiments verify the feasibility and advantages of the new topology

The profile of shallow trench isolation (STI) is designed to improve LDMOS specific on-resistance (Rsp), BVDSS, safe operating area (SOA), and hot carrier lifetimes (HCL) in an integrated BiCMOS power technology. Silicon etch, liner oxidation and CMP processes are tuned to improve the tradeoffs in a power technology showing significant improvement to both p-channel and n-channel Rsp compared to devices fabricated with the STI profile inherited from the original submicron CMOS platform. Extensive TCAD and experiments were carried out to gain insight into the physical mechanisms and further improve device performance after STI process optimization. The final process and device structures yield SOAs that are limited only by thermal constraints up to rated voltages

This paper aims to design a PID compensator for the control of Synchronous Rectifier (SR) Buck Converter to improve its conversion efficiency under different load conditions. Since the diode rectifier is replaced by a high frequency MOSFET switch, the SR control method itself will be sufficient under heavy load condition, to attain better normal mode performance. However, this technique does not hold well in light load condition, due to increased switching losses. A new control technique accompanied with PID compensator is introduced in the paper will enable synchronous buck converter to realize ZVS, while feeding light loads. This is also least cost and highly efficient easy technique without use of extra auxiliary switches and RLC components. This control technique also proved to be efficient under input voltage variations. Simulation is done in MATLAB Simulink for proving stabilization provided by the PID compensator for synchronous rectifier (SR) buck converter. Keywords—Synchronous Rectifier (SR), Continuous Condu-ction Mode (CCM), Discontinuous Conduction Mode (DCM), Zero Voltage Switching (ZVS), Proportional-IntegralDerivative (PID).

Process-induced mechanical stress is used to enhance carrier transport and achieve higher drive currents in current CMOS technologies. In this paper, we study how stress-induced performance enhancements are affected by layout properties and suggest guidelines for improving layouts so that performance gains are maximized. All MOS devices in this work include STI and nitride stress liners as sources of stress. Additionally, the PMOS devices incorporate the stress effects caused by the embedded SiGe S/D layer common in today's processes. First, we study how stress and drive current depend on layout parameters such as active area length and contact placement. We develop an intuition for the drive current dependency on these parameters and propose simple guidelines to improve a layout while considering mechanical stress effects. We then use these guidelines to improve the standard cell layouts in a 65nm industrial library. Experimental results show that we can enhance NMOS and PMOS drive currents by ~5% and ~12%, respectively, while only increasing NMOS leakage current by 1.48X and PMOS leakage current by 3.78X. By applying our guidelines to a 3-input NOR gate and a 3-input NAND gate, we are able to achieve a ~13.5% PMOS drive current improvement in the NOR gate and a ~7% NMOS drive current improvement in the NAND gate, without increasing cell area in either case

Synchronous rectification offers an effective solution to improve efficiency of low-output-voltage flyback converters. Conventional synchronous flyback topologies using discrete synchronous rectifier face challenges in precise timing control on the secondary side. In this paper, MHz-frequency operation of a flyback DC-DC converter using a new monolithic self-synchronized rectifier (SSR) is investigated and demonstrated. The SSR IC, acting solely on its own drain-source voltage instead of external control signals, considerably simplifies converter design, improves system efficiency, and enables MHz operating frequency. Analysis, modeling, and experimental results are presented.


Question: A parasitic inductance and capacitance-supported active gate driving method for reducing switching loss in SiC MOSFETs.

This article investigates the high switching performance of a 1700-V, 50-A Silicon Carbide (SiC) Power MOSFET compared to Silicon (Si) IGBT/BiMOSFET for advanced power conversion applications. Given the wider band gap of SiC over Si, SiC MOSFETs exhibit significantly lower drift region resistance, a key resistive element in high-voltage power devices. The reduced on-state resistance and inherent low switching loss of SiC MOSFETs enable enhanced efficiency and reduced size in converters compared to Si-based devices. We present the switching performance of a novel 1700-V, 50-A SiC MOSFET developed by Cree, Inc. The hard-switching losses of these SiC MOSFETs are evaluated under various circuit parameters and operating conditions and contrasted with those of 1700-V Si BiMOSFETs and 1700-V Si IGBTs using a consistent test setup. Based on conduction and switching losses, the operating limits of output power and switching frequency for these devices are determined in a dc-dc boost converter and compared. The dv/dt and di/dt characteristics of the SiC MOSFET are recorded and discussed in the context of converter design. To ensure continuous operation, three dc-dc boost converters using these devices are designed and tested at 10 kW power with 1 kV output voltage and 10 kHz switching frequency. A 1700-V SiC Schottky diode is employed as the blocking diode in each case. The converter efficiencies are calculated, and the junction temperature of each device is estimated. To showcase high-frequency switching, the SiC MOSFET is operated up to 150 kHz within the allowable junction temperature range. The zero-voltage switching turn-ON behavior of a switch combination consisting of the 1700-V SiC MOSFET and 1700-V SiC Schottky diode connected in series is also evaluated and compared with that of bipolar Si devices. The findings highlight significant power loss reduction when utilizing SiC MOSFETs.

In the conventional full-bridge LLC converter, the duty cycle is kept as 0.5 and the phase-shift angle of the half-bridge modules is 0° to be a symmetrical operation, which makes the resonant tank operating frequency only equal to the switching frequency of the power devices. By regulating the duty cycles of the upper and lower switches in each half-bridge module to be 0.75 and 0.25 and the phase-shift angle of the half-bridge modules to be 180°, the asymmetrical duty cycle controlled full-bridge LLC resonant converter is derived. The proposed asymmetrical duty cycle controlled scheme halves the switching frequency of the primary switches. As a result, the driving losses are effectively reduced. Compared with the conventional full-bridge LLC converter, the soft-switching condition of the derived asymmetrical controlled LLC converter becomes easier to reduce the resonant current. Consequently, the conduction losses are decreased and the conversion efficiency is improved. The asymmetrical control scheme can be also extended to the stacked structure for high input voltage applications. Finally, two LLC converter prototypes both with 200-kHz resonant frequency for asymmetrical and symmetrical control schemes are built and compared to validate the effectiveness of the proposed control strategy.

Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator(PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.

In the present, a power decoupling method without additional component is proposed for a dc to single-phase ac converter, which consists of a flying capacitor dc/dc converter (FCC) and the voltage source inverter (VSI). In particular, a small flying capacitor in the FCC is used for both a boost operation and a double-line-frequency power ripple reduction. Thus, the dc-link capacitor value can be minimized in order to avoid the use of a large electrolytic capacitor. In addition, component design, of, e.g., the boost inductor and the flying capacitor, is clarified when the proposed control is applied. Experiments were carried out using a 1.5-kW prototype in order to verify the validity of the proposed control. The experimental results revealed that the use of the proposed control reduced the dc-link voltage ripple by 74.5%, and the total harmonic distortion (THD) of the inverter output current was less than 5%. Moreover, a maximum system efficiency of 95.4% was achieved at a load of 1.1 kW. Finally, the high power density design is evaluated by the Pareto front optimization. The power densities of three power decoupling topologies, such as a boost topology, a buck topology, and the proposed topology are compared. As a result, the proposed topology achieves the highest power density (5.3 kW/dm3) among the topologies considered herein.

In this paper, a novel design technique of common-gate inductive feedback is presented for millimeter-wave low-noise amplifiers (LNAs). For this technique, by adopting a gate inductor at the common-gate transistor of the cascode stage, the gain of the LNA can be enhanced even under a wideband operation. Using a 65nm CMOS process, transmission-line-based and spiral-inductor-based LNAs are fabricated for demonstration. With a dc power consumption of 33.6 mW from a 1.2-V supply voltage, the transmission-line-based LNA exhibits a gain of 20.6 dB and a noise figure of 5.4 dB at 60 GHz while the 3dB bandwidth is 14.1 GHz. As for the spiral-inductor-based LNA, consuming a dc power of 28.8 mW from a 1.2-V supply voltage, the circuit shows a gain of 18.0 dB and a noise figure of 4.5 dB at 60 GHz while the 3dB bandwidth is 12.2 GHz.

Induction heating is a well-known technique to produce very high temperature for applications. A large number of topologies have been developed in this area such as voltage and current source inverter. Recent developments in switching schemes and control methods have made the voltage-source resonant inverters widely used in several applications that require output power control. The series-resonant inverter needs an output transformer for matching the output power to the load but it carry high current as a result additional real power loss is occur and overall efficiency also is reduced. This project proposes a high efficiency LLC resonant inverter for induction heating applications by using asymmetrical voltage cancellation control .The proposed control method is implemented in a full-bridge topology for induction heating application. The output power is controlled using the asymmetrical voltage cancellation technique. The LLC resonant tank is designed without the use of output transformer. This results in an increase of the net efficiency of the induction heating system. The circuit is simulated using MATLAB .The circuit is implemented using PIC controller. Both simulation and hardware results are compared.

In this paper, a new filling process using an anisotropic epitaxial growth was proposed as the fabrication method of a super junction (SJ) MOSFET. The anisotropic growth controlled with silicon (Si) and chlorine (Cl) source gases was applied to filling of the high-aspect-ratio trenches without voids. Using the process we succeeded in filling trenches with aspect ratio of 18, which is the highest aspect ratio works previously reported, and we fabricated a 200V SJ-MOSFET with a 2.7mum pitch trench gate structure. Consequently, the MOSFET showed electrical characteristics of the lowest on-resistance of 1.5 m-ohm-cm 2 and a breakdown voltage of 225V

This paper highlights the general trend towards further monolithic integration in power applications by enabling power management and interfacing solutions in advanced CMOS nodes. The need to combine high-density digital circuits, power-management circuits, and robust interfaces in a single technology platform requires the development of additional process options on top of baseline CMOS. Examples include high-voltage devices, devices to enable area-efficient ESD protection, and integrated capacitors and inductors with high quality factors. The use of bipolar devices in these technologies for protection and control purposes in power applications is also addressed.

High operating frequency and integration technique are two main approaches to achieve high power density for the switching mode power supply. The emerging gallium nitride (GaN)-based power device enables a multimegahertz high-efficiency point-of-load (POL) converter with high current capability. The low-temperature cofire ceramic (LTCC)-based integration technique successfully extends the three-dimensional (3-D) integrated POL module from the low current level to the high current level (>10 A). This paper presents the low-profile LTCC inductor substrate design and evaluation for a multimegahertz 3-D integrated POL converter with large output current. The detailed study about the impact of frequency on the LTCC inductor shows that the high frequency not only shrinks the volume of the inductor, but also simplifies the inductor structure. The comparison between the LTCC inductor and the discrete inductor demonstrates that the LTCC inductor dramatically boosts the converter light-load efficiency due to its nonlinear inductance. Because of the low-profile design, the power density of the single-phase POL module with LTCC inductor achieves 1.1 kW/in3 at 5 MHz. The performance of the LTCC inductor can be further improved by the inverse coupling, which results in more than 40% core thickness and core loss reduction. Therefore, the power density of a two-phase integrated POL module is pushed to 1.5 kW/in3, which is around ten times of the power density of state-of-the-art industry products with the same current level.

FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive current. We investigate in this paper gate sizing of finFET devices, and we provide a comparison with 32nm bulk CMOS. Wider finFET devices are built utilizing multiple parallel fins between the source and drain. Independent gating of the finFET's double gates allows significant reduction in leakage current. We perform temperature-aware circuit optimization by modeling delay using temperature-dependent parameters, and by imposing constraints that limit the maximum allowable number of parallel fins. We show that finFET circuits are superior in performance and produce less static power when compared to 32nm circuits.

This paper presents a new topology of higher order power filter for grid-tied voltage-source inverters, named the LLCL filter, which inserts a small inductor in the branch loop of the capacitor in the traditional LCL filter to compose a series resonant circuit at the switching frequency. Particularly, it can attenuate the switching-frequency current ripple components much better than an LCL filter, leading to a decrease in the total inductance and volume. Furthermore, by decreasing the inductance of a grid-side inductor, it raises the characteristic resonance frequency, which is beneficial to the inverter system control. The parameter design criteria of the proposed LLCL filter is also introduced. The comparative analysis and discussions regarding the traditional LCL filter and the proposed LLCL filter have been presented and evaluated through experiment on a 1.8-kW-single-phase grid-tied inverter prototype.


Question: A parasitic inductance and capacitance-supported active gate driving method for reducing switching loss in SiC MOSFETs.

This paper delves into the turn-on performance of a reverse blocking insulated gate bipolar transistor (RB IGBT), a specialized IGBT designed to withstand blocking voltages of both polarities. Despite its superior conduction properties, the RB IGBT exhibits subpar switching (turn-on) performance compared to a standard IGBT and blocking diode combination, hindering its widespread adoption in practical applications. Here, we analyze the turn-on losses and reverse recovery current of the RB IGBT under various gate driver techniques and propose an innovative gate driver for optimization. Conventional gate drivers lack the capability to fine-tune switching dynamics, whereas the proposed driver offers a straightforward and effective method to control and minimize reverse recovery current and turn-on losses. By employing feedforward control of the gate-emitter voltage, the driver regulates the collector current slope and reverse recovery current. Additionally, during the voltage falling phase, the inherent increase in gate current allows for the control of the collector-emitter voltage slope, resulting in reduced voltage tail and total turn-on losses, irrespective of the reverse recovery current. The efficacy of the proposed gate driver is substantiated through experimental validation, with the outcomes presented and discussed in detail.

This paper is mainly concerned with a high frequency soft-switching PWM inverter suitable for consumer induction heating system. Proposed system is composed of soft switching chopper based voltage boost PFC input stage and phase shifted PWM controlled full bridge ZCZVS high frequency inverter stage. Its fundamentals of operating performances are illustrated and evaluated on the experimental results. Its effectiveness is substantially proved on the basis of the experimental results from a practical point of view.

This paper studies the electrostatic discharge (ESD)-protected RF low-noise amplifiers (LNAs) in 65-nm CMOS technology. Three different ESD designs, including double-diode, modified silicon-controlled rectifier (SCR), and modified-SCR with double-diode configurations, are employed to realize ESD-protected LNAs at 5.8 GHz. By using the modified-SCR in conjunction with double-diode, a 5.8-GHz LNA with multiple ESD current paths demonstrates a 4.3-A transmission line pulse (TLP) failure level, corresponding to a ~ 6.5-kV Human-Body-Mode (HBM) ESD protection level. Under a supply voltage of 1.2 V and a drain current of 6.5 mA, the proposed ESD-protected LNA demonstrates a noise figure of 2.57 dB with an associated power gain of 16.7 dB. The input third-order intercept point (IIP3) is - 11 dBm, the input and output return losses are greater than 15.9 and 20 dB, respectively.

In this paper, grid-connected interleaved voltage source inverters for PMSG wind power generation system with coupled inductors is introduced. In parallel operation, the undesirable circulating current flows between inverters. There are some differences in circulating currents according to source configuration. It is mathematically analyzed and simulated for the verification of analysis. In case of interleaved inverters, the uncontrollable circulating current in switching frequency level flows between inverter modules regardless of source configuration such as common or separated if filter inductance which is placed between inverters is significantly low. In order to suppress high frequency circulating current, the coupled inductors are employed in each phase. A case of 1.5MVA grid-connected interleaved inverters using coupled inductors prototype for the PMSG wind power generation Back To Back converters in parallel are introduced and experimentally verified the proposed topology.

Turn-on performance of a reverse blocking insulated gate bipolar transistor (RB IGBT) is discussed in this paper. The RB IGBT is a specially designed IGBT having ability to sustain blocking voltage of both the polarities. Such a switch shows superior conduction but much worst switching (turn- on) performances compared to a combination of an ordinary IGBT and blocking diode. Because of that, optimization of the switching performance is a key issue that makes the RB IGB not well accepted in the real applications. In this paper, the RB IGBT turn-on losses and reverse recovery current are analyzed for different gate driver techniques, and a new gate driver is proposed. Commonly used conventional gate drivers do not have capability for the switching dynamics optimization. In contrast to this, the new proposed gate driver provides robust and simple way to control and optimize the reverse recovery current and turn-on losses. The collector current slope and reverse recovery current are controlled by the means of the gate emitter voltage control in feedforward manner. In addition, the collector emitter voltage slope is controlled during the voltage falling phase by the means of inherent increase of the gate current. Therefore, the collector emitter voltage tail and the total turn- on losses are reduced, independently on the reverse recovery current. The proposed gate driver was experimentally verified and the results presented and discussed.

A power electronic inverter is developed for a high frequency induction heating application. This equipment is available for the implementation of ZVS LCL resonance method was used. Using IGBT 20MVA, 100kHz LCL resonant induction heating equipment during the development process, 100kHz IGBT module development process and understanding gained from the design of LCL resonant Zero Crossing through the PLL control over operation of the IGBT Soft Switching, and focused on minimizing losses. In addition, through the actual design and implementation of devices using the area to test drive the development of large inverter technology based on the test

The unipolar sinusoidal pulse width modulation full-bridge transformerless photovoltaic (PV) inverter can achieve high efficiency by using latest superjunction metal-oxide-semiconductor field-effect transistor (MOSFET) together with silicon carbide (SiC) diodes. However, the MOSFETs aSiCre limited to use in transformerless PV inverter due to the low reverse-recovery characteristics of the body diode. In this paper, a family of new transformerless PV inverter topology for a single-phase grid-tied operation is proposed using superjunction MOSFETs and SiC diodes as no reverse-recovery issues are required for the main power switches for unity power operation. The added clamping branch clamps the freewheeling voltage at the half of dc input voltage during the freewheeling period. As a result, the common-mode voltage kept constant during the whole grid period that reduces the leakage current significantly. In addition, dead time is not necessary for main power switches at both the high-frequency commutation and the grid zero crossing instant, results low-current distortion at output. Finally, a 1-kW prototype is built and tested to verify the theoretical analysis. The experimental results show 98.5% maximum efficiency and 98.32% European efficiency. Furthermore, to show the effectiveness, the proposed topology is compared with the other transformerless topologies.

This paper presents the design and implementation of a 100 kW three-level T-type (3L-T2), single-phase power electronics building block (PEBB). The PEBB features switching power devices with associated gate drivers, DC-link capacitors and interconnection busbar. A hybrid switch (HyS), which includes a Si IGBT and a SiC MOSFET in parallel, forms the switching power device in the PEBB. An low-inductive multi-layer laminated busbar was designed to have symmetrical current commutation loops. A major contribution is that this is achieved while no three-level T-type power module was used. A loop inductance of 29 nH was achieved which is lower than the existing state-of-the-art three-level designs in literature. The fabricated prototype PEBB achieves a specific power density of 27.7 kW/kg and a volumetric power density of 308.61 W/in3. Single-phase operation of the PEBB has been demonstrated at the switching frequency of 28 kHz.

A 2:1 351 V hard-switched boost converter was constructed using high-voltage GaN high-electron-mobility transistors grown on Si substrates and GaN Schottky diodes grown on Sapphire substrates. The high speed and low on-resistance of the GaN devices enables extremely fast switching times and low losses, resulting in a high conversion efficiency of 95% with 425-W output power at 1 MHz. The boost converter has a power density of 175 W/in3. To our knowledge, these results are the best reported on GaN devices, and the highest for 1MHz switching.

Data centers are increasing in number and size at astounding rates, while operational cost, thermal management, size, and performance continue to be the driving metrics for the power subsystems in the associated computing equipment. This paper presents a SiC-based phase-shifted full bridge (PSFB) converter designed for 10kW output power and targeted at data center applications. The design approach focused on tuning of the converter efficiency and minimizing the thermal management system, resulting in a high-density converter. A unique thermal management system has also been employed, resulting in both increased power density and better thermal management. In this paper, the implementation of this converter is described in detail, along with empirical results, both electrical and thermal.

In this paper, a novel design technique of common-gate inductive feedback is presented for millimeter-wave low-noise amplifiers (LNAs). For this technique, by adopting a gate inductor at the common-gate transistor of the cascode stage, the gain of the LNA can be enhanced even under a wideband operation. Using a 65nm CMOS process, transmission-line-based and spiral-inductor-based LNAs are fabricated for demonstration. With a dc power consumption of 33.6 mW from a 1.2-V supply voltage, the transmission-line-based LNA exhibits a gain of 20.6 dB and a noise figure of 5.4 dB at 60 GHz while the 3dB bandwidth is 14.1 GHz. As for the spiral-inductor-based LNA, consuming a dc power of 28.8 mW from a 1.2-V supply voltage, the circuit shows a gain of 18.0 dB and a noise figure of 4.5 dB at 60 GHz while the 3dB bandwidth is 12.2 GHz.


Question: A parasitic inductance and capacitance-supported active gate driving method for reducing switching loss in SiC MOSFETs.

This paper presents an innovative active gate drive (AGD) technique designed for enhancing the performance of high-power IGBTs. The approach integrates a series of critical requirements to ensure optimal switching behavior under demanding hard switching scenarios. It achieves a balance between the need for a slower drive to minimize noise and switching stress, and the demand for a faster drive to enable high-speed switching and reduce switching energy loss. Additionally, the gate drive mechanism effectively suppresses oscillations during low-current turn-on transients in the IGBT. The paper critically evaluates the traditional gate drive circuit design, highlighting its inherent contradictions, and substantiates through experimental evidence that the proposed three-phase active gate drive method serves as a viable and efficient solution to these challenges.

Silicon offers a new set of possibilities and challenges for RF, microwave, and millimeter-wave applications. While the high cutoff frequencies of the SiGe heterojunction bipolar transistors and the ever-shrinking feature sizes of MOSFETs hold a lot of promise, new design techniques need to be devised to deal with the realities of these technologies, such as low breakdown voltages, lossy substrates, low-Q passives, long interconnect parasitics, and high-frequency coupling issues. As an example of complete system integration in silicon, this paper presents the first fully integrated 24-GHz eight-element phased array receiver in 0.18-/spl mu/m silicon-germanium and the first fully integrated 24-GHz four-element phased array transmitter with integrated power amplifiers in 0.18-/spl mu/m CMOS. The transmitter and receiver are capable of beam forming and can be used for communication, ranging, positioning, and sensing applications.

We propose a novel nLDMOS structure and a design concept in BCD technology with the best-in-class performance. The drift profile is optimized and the multi-oxide in the drift region is adopted to approach the RESURF limit of on-resistance vs. BVdss characteristic (i.e., 36V DMOS has a Ron_sp of 20mohm-mm2 with a BVdss of 50V; 45V DMOS has a Ron_sp of 28mohm-mm2 with a BVdss of 65V). Moreover, this modification requires merely three extra masks in the Non-Epitaxy LV process to achieve this improvement. Therefore it is not only a high performance but also a low cost solution.

Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator(PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.

A novel multi-stack CMOS device structure is proposed, the operation of the structure is fully analyzed for high power CMOS switch design. The structure is also implemented in a standard 0.18-um triple-well CMOS process, and its performance is fully characterized. The proposed switch device incorporates multi-stack NMOS switches, one of which has a switch at the bulk and the others of which have a connection between the bulk and the source in order to provide high power handling capability to the transmit switch side. In order to demonstrate the improvement of power handling capability, performance of the conventional structure and the proposed structure are fully analyzed, compared from various simulation results, and verified with measurement results in detail. Experimental data show that the isolation of the proposed test structure is 25 dB higher at 30 dBm input power level than that of conventional structures, which was caused by the significant reduction of leakage current of the switch device in OFF state. In addition, insertion loss of the Rx switch can be maintained as 1.5 dB by applying body switching technique in 900 MHz.

This paper discusses application of direct charge measurement (DCM) on characterizing on-chip interconnect capacitance. Measurement equipment and techniques are leveraged from Flat Panel Display testing. On-chip active device is not an essential necessity for DCM test structure and it is easy to implement parallel measurements. Femto-Farad measurement sensitivity is achieved without having on-chip active device. Measurement results of silicon and glass substrates, including parallel measurements, are presented.

This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.

In this paper, a novel design technique of common-gate inductive feedback is presented for millimeter-wave low-noise amplifiers (LNAs). For this technique, by adopting a gate inductor at the common-gate transistor of the cascode stage, the gain of the LNA can be enhanced even under a wideband operation. Using a 65nm CMOS process, transmission-line-based and spiral-inductor-based LNAs are fabricated for demonstration. With a dc power consumption of 33.6 mW from a 1.2-V supply voltage, the transmission-line-based LNA exhibits a gain of 20.6 dB and a noise figure of 5.4 dB at 60 GHz while the 3dB bandwidth is 14.1 GHz. As for the spiral-inductor-based LNA, consuming a dc power of 28.8 mW from a 1.2-V supply voltage, the circuit shows a gain of 18.0 dB and a noise figure of 4.5 dB at 60 GHz while the 3dB bandwidth is 12.2 GHz.

In this paper, the design of a class E2 resonant DC/DC converter, operating at UHF band, is proposed. Combining the use of GaN HEMT devices, both for the inverter and the synchronous rectifier, with high Q lumped-element multi-harmonic matching networks, a peak efficiency value of 72% has been obtained at 780 MHz with a 10.3 W output power. By means of a Pulse Width Modulation (PWM) over the gate driving envelope, the output voltage may be controlled while keeping low switching losses, with an estimated small-signal bandwidth (BW) and a slew rate of 11 MHz and 630 V/µSeg, respectively.

In the present, a power decoupling method without additional component is proposed for a dc to single-phase ac converter, which consists of a flying capacitor dc/dc converter (FCC) and the voltage source inverter (VSI). In particular, a small flying capacitor in the FCC is used for both a boost operation and a double-line-frequency power ripple reduction. Thus, the dc-link capacitor value can be minimized in order to avoid the use of a large electrolytic capacitor. In addition, component design, of, e.g., the boost inductor and the flying capacitor, is clarified when the proposed control is applied. Experiments were carried out using a 1.5-kW prototype in order to verify the validity of the proposed control. The experimental results revealed that the use of the proposed control reduced the dc-link voltage ripple by 74.5%, and the total harmonic distortion (THD) of the inverter output current was less than 5%. Moreover, a maximum system efficiency of 95.4% was achieved at a load of 1.1 kW. Finally, the high power density design is evaluated by the Pareto front optimization. The power densities of three power decoupling topologies, such as a boost topology, a buck topology, and the proposed topology are compared. As a result, the proposed topology achieves the highest power density (5.3 kW/dm3) among the topologies considered herein.

This paper presents an approach to optimal dimensioning of active cell balancing architectures, which are of increasing relevance in Electrical Energy Storages (EESs) for Electric Vehicles (EVs) or stationary applications such as smart grids. Active cell balancing equalizes the state of charge of cells within a battery pack via charge transfers, increasing the effective capacity and lifetime. While optimization approaches have been introduced into the design process of several aspects of EESs, active cell balancing architectures have, until now, not been systematically optimized in terms of their components. Therefore, this paper analyzes existing architectures to develop design metrics for energy dissipation, installation volume, and balancing current. Based on these design metrics, a methodology to efficiently obtain Pareto-optimal configurations for a wide range of inductors and transistors at different balancing currents is developed. Our methodology is then applied to a case study, optimizing two state-of-the-art architectures using realistic balancing algorithms. The results give evidence of the applicability of systematic optimization in the domain of cell balancing, leading to higher energy efficiencies with minimized installation space.


Question: A parasitic inductance and capacitance-supported active gate driving method for reducing switching loss in SiC MOSFETs.

This paper presents an innovative drive and protection circuit tailored for reverse-blocking insulated gate bipolar transistors (RB-IGBTs), particularly relevant for their application in matrix converters. The drive circuit is designed to mitigate the turn-on and turn-off transients, ensuring controlled transitions by incorporating a dynamic current source. This approach effectively limits the rate of change of collector current (di/dt) and the rate of change of collector-emitter voltage (dv/dt), thereby reducing stress on the device during switching events. The circuit architecture combines a standard push-pull driver with two controllable current sources: a current generator and a current sink. These sources are activated during switching transitions, enhancing the circuit's performance and reliability. As for protection, the paper introduces a sophisticated collector current detection circuit specifically designed for RB-IGBTs. This circuit monitors the collector current by sensing the collector-emitter voltage of the device, providing a robust method for detecting current signatures during commutation transitions in matrix converters. The effectiveness of the proposed drive and protection circuit is validated through a series of experiments, with detailed results and analyses presented to demonstrate its practical benefits.

The double-layer capacitor (DLC) for power applications is a new device. A simple resistive capacitive equivalent circuit is insufficient to characterize its terminal behaviour. Based on physical reasoning, an equivalent circuit is proposed to provide the power electronics engineer with a model for the terminal behaviour of the DLC. The equivalent model consists of three Re branches, one of them with a voltage dependent capacitor. A method to identify the circuit parameters is presented. Measurements of carbon-based DLCs for power applications are presented, analysed, and the equivalent circuit response is compared with experimental results.

An enhanced charge pump for the antenna switch controller using the silicon-on-insulator (SOI) CMOS technology is presented in this brief. The pseudo cross-coupled technique is proposed to reduce parasitic capacitances at charging/discharging nodes through charge transferring paths, which improves the current drive capability and provides better accuracy of the output voltage. Furthermore, the codesign between the gate control voltages of power MOS transistors and the clock drive signals of pumping capacitors has been investigated to eliminate the reversion loss and reduce the ripple voltage. The pseudo cross-coupled charge pump has been fabricated in the 0.18-  $\mu\text{m}$ SOI CMOS technology with an area of 0.065 mm2. According to the comparison results of the conventional and enhanced charge pumps, the start-up time and the recovery time are typically shortened by 71.4% and 21.7%, owing to the improvement of the current drive capability, and the ripple voltage at no-load condition is greatly reduced by 46.1%.

This paper presents a new topology of higher order power filter for grid-tied voltage-source inverters, named the LLCL filter, which inserts a small inductor in the branch loop of the capacitor in the traditional LCL filter to compose a series resonant circuit at the switching frequency. Particularly, it can attenuate the switching-frequency current ripple components much better than an LCL filter, leading to a decrease in the total inductance and volume. Furthermore, by decreasing the inductance of a grid-side inductor, it raises the characteristic resonance frequency, which is beneficial to the inverter system control. The parameter design criteria of the proposed LLCL filter is also introduced. The comparative analysis and discussions regarding the traditional LCL filter and the proposed LLCL filter have been presented and evaluated through experiment on a 1.8-kW-single-phase grid-tied inverter prototype.

Bidirectional bridgeless PFC is an advantageous topology for high power application among many bridgeless PFCs due to small EMI filter size and no reverse recovery problem. However due to the large junction capacitance of secondary leg's diodes, the dead angle is shown in the zero-crossing area. Thus, the input current distortion is intensified, and the unnecessary switching loss decreases the efficiency. In this paper, a simple gate skipping technique is implemented to the zero-crossing area of the bidirectional bridgeless PFC. As a result, the unnecessary switching loss of boost switches and the input current distortion are reduced. The improvement of the proposed method is verified by experimental results with the high line input and 800W(400V/2A) output prototype.

This paper describes the design and the experimental investigation of a gate drive unit with closed-loop control of the collector current slope diC/dt for multichip insulated-gate bipolar transistors (IGBTs). Compared to a pure resistive gate drive, the proposed diC/dt control offers the ability to adjust the collector current slope freely which helps to find an optimized relation between switching losses and secure operation of the freewheeling diode for every type of IGBT. Based on the description of IGBT's switching behavior, the design and the realization of the gate drive are presented. The test setup and the comparison of switching tests with and without the proposed diC/dt control are discussed.

Multi-threshold CMOS (MTCMOS) power gating is a design technique in which a power gating transistor is connected between the logic transistors and either power or ground, thus creating a virtual supply rail or virtual ground rail, respectively. Power gating transistor sizing, transition (sleep mode to active mode) current, short circuit current and transition time are design issues for power gating design. The use of power gating design results in the delay overhead in the active mode. If both nMOS and pMOS sleep transistor are used in power gating, delay overhead will increase. This paper proposes the design methodology for reducing the delay of the logic circuits during active mode. This methodology limits the maximum value of transition current to a specified value and eliminates short circuit current. Experiment results show 16.83% reduction in the delay.

The properties of a single-phase quasi Z-source inverter (qZSI) and a single-phase quasi-switched boost inverter (qSBI), both of which are single-stage buck-boost inverters, are investigated and compared. For the same operating conditions, qSBI has the following advantages over qZSI: 1) Three capacitors are saved; 2) the current rating on both of its switches and diodes is lower; 3) its boost factor is higher with an equivalent parasitic effect; and 4) its efficiency is higher. However, qSBI has one more active switch and one more diode than Z-source/ qZSIs. In addition, the capacitor voltage stress of qSBI is higher than that of qZSI. The dc and ac component circuit analysis, impedance design with low-frequency and high-frequency ripples, component stresses, and power loss calculation are presented. A prototype based on a TMS320F28335 DSP is built in order to compare the operating principle of qSBI and qZSI.

The test and the characterization of medium or high-power electronic converters, under nominal operating conditions, are made difficult by the requirement of high-power electrical source and load. In addition, the energy lost during the test may be very significant. The opposition method, which consists of an association of two identical converters supplied by the same source, one operating as a generator, the other as a receptor, can be a better way to do these test. Another advantage is the possibility to realize accurate measurements of the different losses in the converters under test. In the first part of this paper, the characteristics of the method concerning loss measurements are compared to those of the electrical or calorimetric methods, then it is shown how it can be applied to different types of power electronic converters, choppers, switched mode power supplies, and pulsewidth modulation inverters. In the second part, different examples of studies conducted by the authors, and using this method, are presented. They have varying goals, from the test of soft-switching inverters to the characterization of integrated gate-commutated thyristor (IGCT) devices mounted into 2-MW choppers.

A 1.5 A normally-off GaN transistor for power applications in p-type GaN gate technology with a modified epitaxial concept is presented. A higher threshold voltage is achieved while keeping the on-state resistance low by using an Al-GaN buffer instead of a GaN buffer. Additionally, the AlGaN buffer acts as a back-barrier and suppresses source-drain punch-through currents in the off-state. P-GaN gate GaN transistors with AlGaN buffer will therefore yield higher breakdown voltages as compared to standard GaN buffer versions which results in an excellent VBr-to-RON ratio. The proposed normally-off technology shows save operation under elevated ambient temperature up to 200 °C without thermal runaway. In contrast to standard normally-on AlGaN/GaN HEMTs, a reverse diode operation is possible for offstate conditions which may enable improved inverter circuits.

This paper proposes and analyzes a new power electronics circuit topology for wireless inductive power transfer application using current-fed half-bridge converter with CCL-LC resonant network. The major focus is analysis and implementation of a new current-fed resonant topology with current-sharing and voltage doubling features. Generally, inductive power transfer circuits with current fed converter use parallel CL resonant tank to transfer power effectively through air gap. However, in medium power application, this topology suffers from a major limitation of high voltage stress across the inverter semiconductor devices owing to high reactive power consumed by loosely coupled coil. In proposed topology, this is mitigated by adding a capacitor in series with the coil developing series-parallel CCL tank. The power flow is controlled through variable frequency modulation. Soft-switching of the devices is obtained irrespective of the load current. For grid-to-vehicle or solar-to-vehicle, the converter is analyzed and detailed design procedure is illustrated. Experimental results are presented to verify the analysis and demonstrate the performance.


Question: Anno: A visual utility for transcribing and annotating handwritten documents in real-time.

This paper introduces the ASK Corpus, a specialized language learner corpus focused on Norwegian as a second language. The corpus is meticulously designed to include essays sourced from language proficiency tests conducted at two distinct levels, alongside demographic details of the test participants. To ensure comprehensive analysis, the corpus also incorporates texts and corresponding personal information from native Norwegian speakers serving as a control group. All textual and demographic data are meticulously annotated in XML, adhering to the TEI Guidelines, a standard for encoding texts in digital form.

A novel feature of the ASK Corpus is the introduction of enhanced attributes to the TEI corr and sic tags, specifically designed to facilitate the identification and classification of "errors" within the texts. For each error identified, a corrected form is also annotated, enriching the data for detailed analysis. To further enhance the corpus's utility, an automated tagging system, the "Oslo-Bergen Tagger," originally developed for standard Norwegian, is employed. This system is complemented by a manual correction facility, ensuring high-quality tagging and annotation.

The ASK Corpus is equipped with a sophisticated query system, the Corpus Workbench, developed by the University of Stuttgart, coupled with a user-friendly web search interface developed at Aksis, University of Bergen. This system enables researchers to conduct complex searches, combining words, error types, grammatical annotations, and personal data, facilitating in-depth analysis of language learning patterns and proficiency levels among second language learners of Norwegian.

Due to the complex structure and handwritten deformation, the offline handwritten Chinese characters recognition has been one of the most challenging problems. In this paper, an offline handwritten Chinese character recognition tool has been developed based on the Tesseract open source OCR engine. The tool mainly contributes on the following two points: First, a handwritten Chinese character features library is generated, which is independent of a specific user's writing style, Second, by preprocessing the input image and adjusting the Tesseract engine, multiple candidate recognition results are output based on weight ranking. The recognition accuracy rate of this tool is above 88% for both known user test set and unknown user test set. It has shown that the Tesseract engine is feasible for offline handwritten Chinese character recognition to a certain degree.

In a multi-lingual multi-script country like India, a single text line of a document page may contain words of two or more scripts. For the Optical Character Recognition of such a document page it is necessary to identify different scripts from the document. In this paper, an automatic technique for word -wise identification of English, Devnagari and Urdu scripts from a single document is proposed. Here, at first, the document is segmented into lines and then the lines are segmented into possible words. Using characteristics of different scripts, the identification scheme is developed.

Document image processing has become an increasingly important technology in the automation of office documentation tasks. Automatic document scanners such as text readers and OCR (Optical Character Recognition) systems are an essential component of systems capable of those tasks. One of the problems in this field is that the document to be read is not always placed correctly on a flatbed scanner. This means that the document may be skewed on the scanner bed, resulting in a skewed image. This skew has a detrimental effect on document on document analysis, document understanding, and character segmentation and recognition. Consequently, detecting the skew of a document image and correcting it are important issues in realising a practical document reader. In this paper we describe a new algorithm for skew detection. We then compare the performance and results of this skew detection algorithm to other publidhed methods form O'Gorman, Hinds, Le, Baird, Posel and Akuyama. Finally, we discuss the theory of skew detection and the different apporaches taken to solve the problem of skew in documents. The skew correction algorithm we propose has been shown to be extremenly fast, with run times averaging under 0.25 CPU seconds to calculate the angle on the DEC 5000/20 workstation.

Recent technological advances in connected-speech recognition and position sensing in space have encouraged the notion that voice and gesture inputs at the graphics interface can converge to provide a concerted, natural user modality.
 The work described herein involves the user commanding simple shapes about a large-screen graphics display surface. Because voice can be augmented with simultaneous pointing, the free usage of pronouns becomes possible, with a corresponding gain in naturalness and economy of expression. Conversely, gesture aided by voice gains precision in its power to reference.

There are immense efforts to design a complete OCR for most of the world’s leading languages, however, multilingual documents either of handwritten or of printed form. As a united attempt, Unicode based OCRs were studied mostly with some positive outcomes, despite the fact that a large character set slows down the recognition significantly. In this paper, we come out with a method to classify words to a language as the word segmentation is complete. For the purpose, we identified the characteristics of writings of several languages and utilized projecting method combined with some other feature extraction methods. In addition, this paper intends a modified statistical approach to correct the skewness before processing a segmented document. The proposed procedure, evaluated for a collection of both handwritten and printed documents, came with excellent outcomes in assigning words to languages. General Terms Pattern Recognition, Document Processing, Optical Character Recognition.

A model based approach for rectifying the camera image of the bound document has been developed, i.e., the surface of the document is represented by a general cylindrical surface. The principle of using the model to unwrap the image is discussed. Practically, the skeleton of each horizontal text line is extracted to help estimate the parameter of the model, and rectify the images. To use the model, only a few priori is required, and no more auxiliary device is necessary. Experiment results are given to demonstrate the feasibility and the stability of the method.

We present QuickCut, an interactive video editing tool designed to help authors efficiently edit narrated video. QuickCut takes an audio recording of the narration voiceover and a collection of raw video footage as input. Users then review the raw footage and provide spoken annotations describing the relevant actions and objects in the scene. QuickCut time-aligns a transcript of the annotations with the raw footage and a transcript of the narration to the voiceover. These aligned transcripts enable authors to quickly match story events in the narration with semantically relevant video segments and form alignment constraints between them. Given a set of such constraints, QuickCut applies dynamic programming optimization to choose frame-level cut points between the video segments while maintaining alignments with the narration and adhering to low-level film editing guidelines. We demonstrate QuickCut's effectiveness by using it to generate a variety of short (less than 2 minutes) narrated videos. Each result required between 14 and 52 minutes of user time to edit (i.e. between 8 and 31 minutes for each minute of output video), which is far less than typical authoring times with existing video editing workflows.

Annotated data is prerequisite for many NLP applications. Acquiring large-scale annotated corpora is a major bottleneck, requiring significant time and resources. Recent work has proposed turning annotation into a game to increase its appeal and lower its cost; however, current games are largely text-based and closely resemble traditional annotation tasks. We propose a new linguistic annotation paradigm that produces annotations from playing graphical video games. The effectiveness of this design is demonstrated using two video games: one to create a mapping from WordNet senses to images, and a second game that performs Word Sense Disambiguation. Both games produce accurate results. The first game yields annotation quality equal to that of experts and a cost reduction of 73% over equivalent crowdsourcing; the second game provides a 16.3% improvement in accuracy over current state-of-the-art sense disambiguation games with WordNet.

Examining large-scale, long-term application use is critical to understanding how an application meets the needs of its user community. However, there have been few published analyses of long-term use of desktop applications, and none that have examined applications that support creating and modifying content using direct manipulation. In this paper, we present an analysis of 2 years of usage data from an instrumented version of the GNU Image Manipulation Program, including data from over 200 users. In the course of our analysis, we show that previous findings concerning the sparseness of command use and idiosyncrasy of users’ command vocabularies extend to a new domain and interaction style. These findings motivate continued research in adaptive and mixed-initiative interfaces. We also describe the novel application of a clustering technique to characterize a user community’s higher-level tasks from low-level logging data.

This paper presents a model to convert natural Bengali language to text. The proposed model requires the usage of the open sourced framework Sphinx 4 which is written in Java and provides the required procedural coding tools to develop an acoustic model for a custom language like Bengali. Our main objective was to ensure that the system was adequately trained on a word by word basis from various speakers so that it could recognize new speakers fluently. We used a free digital audio workstation (DAW) called Audacity to manipulate the collected recording data via continuous frequency profiling techniques to reduce the Signal-to-Noise-Ratio (SNR), vocal leveling, normalization and syllable splitting as well as merging which ensure an error free 1:1-word mapping of each utterance with its mirror transcription file text. To evaluate the performance of proposed model, we utilize an audio dataset of recorded speech data from 10 individual speakers consisting of both males and females using custom transcript files that we wrote. Experimental results demonstrate that the proposed model exhibits average 71.7% accuracy for our tested dataset.


Question: Anno: A visual utility for the transcription and real-time annotation of handwritten documents.

Introducing ScribFreak: An Adaptive Tool for Linguistic Annotation of Handwritten Documents
ScribFreak is a specialized annotation tool designed to facilitate the transcription and on-the-fly annotation of handwritten documents. It features a modular architecture that enables seamless adaptation to various domains and annotation tasks. This is achieved through a flexible plug-in system, which allows users to incorporate custom visualization components, annotation specifications, and automated annotation capabilities, all without the need for re-compilation. ScribFreak's APIs are designed to support active learning by enabling automatic annotators or taggers to guide future annotation efforts. Currently, ScribFreak supports a range of annotation types for English, Chinese, and Arabic, including constituent parse structures, dependent annotations, and ACE named-entity and coreference annotations. The Java source code for ScribFreak is freely available under the Mozilla Public License 1.1, accessible at: http://scribfreak.sourceforge.net. This website also offers detailed screenshots and a web-deployable version of the tool for immediate use.

Handwriting Analysis or Graphology is a scientific method of identifying, evaluating and understanding personality through the strokes and patterns revealed by handwriting. Handwriting reveals the true personality including emotional outlay, fears, honesty, defenses and many others. Professional handwriting examiners called graphologist often identify the writer with a piece of handwriting. Accuracy of handwriting analysis depends on how skilled the analyst is. Although human intervention in handwriting analysis has been effective, it is costly and prone to fatigue. Hence the proposed methodology focuses on developing a tool for behavioral analysis which can predict the personality traits automatically with the aid of a computer without the human intervention. In this paper a method has been proposed to predict the personality of a person from the baseline, the pen pressure, the letter‘t’, the lower loop of letter ‘y’ and the slant of the writing as found in an individual’s handwriting. These parameters are the inputs to a Rule-Base which outputs the personality trait of the writer.

The increasingly large number of available writings describing technical and scientific progress, calls for advanced analytic tools for their efficient analysis. This is true for many application scenarios in science and industry and for different types of writings, comprising patents and scientific articles. Despite important differences between patents and scientific articles, both have a variety of common characteristics that lead to similar search and analysis tasks. However, the analysis and visualization of these documents is not a trivial task due to the complexity of the documents as well as the large number of possible relations between their multivariate attributes. In this survey, we review interactive analysis and visualization approaches of patents and scientific articles, ranging from exploration tools to sophisticated mining methods. In a bottom-up approach, we categorize them according to two aspects: (a) data type (text, citations, authors, metadata, and combinations thereof), and (b) task (finding and comparing single entities, seeking elementary relations, finding complex patterns, and in particular temporal patterns, and investigating connections between multiple behaviours). Finally, we identify challenges and research directions in this area that ask for future investigations.

We seek to improve the xperience of using pen computing devices by augmenting them with haptic, tactile feedback displays. We present the design of the haptic display for pen computers, and explore interaction techniques that allow users to feel GUI elements, textures, photographs and other interface elements with a pen. We discuss research directions in haptic displays for pen devices and report results of an early experimental study that evaluated the benefits of tactile feedback in pen computing.

Information graphics, or infographics, are visual representations of information, data or knowledge. Understanding of infographics in documents is a relatively new research problem, which becomes more challenging when infographics appear as raster images. This paper describes technical details and practical applications of the system we built for recognizing and understanding imaged infographics located in document pages. To recognize infographics in raster form, both graphical symbol extraction and text recognition need to be performed. The two kinds of information are then auto-associated to capture and store the semantic information carried by the infographics. Two practical applications of the system are introduced in this paper, including supplement to traditional optical character recognition (OCR) system and providing enriched information for question answering (QA). To test the performance of our system, we conducted experiments using a collection of downloaded and scanned infographic images. Another set of scanned document pages from the University of Washington document image database were used to demonstrate how the system output can be used by other applications. The results obtained confirm the practical value of the system.

Most scientific documents on the web are unstructured or semi-structured, and the automatic document metadata extraction process becomes an important task. This paper describes a framework for automatic metadata extraction from scientific papers. Based on a spatial and visual knowledge principle, our system can extract title, authors and abstract from scientific papers. We utilize format information such as font size and position to guide the metadata extraction process. The experiment results show that our system achieves a high accuracy in header metadata extraction which can effectively assist the automatic index creation for digital libraries.

Current dialogue systems generally operate in a pipelined, modular fashion on one complete utterance at a time. Evidence from human language understanding shows that human understanding operates incrementally and makes use of multiple sources of information during the parsing process, including traditionally “later” components such as pragmatics. In this paper we describe a spoken dialogue system that understands language incrementally, provides visual feedback on possible referents during the course of the user’s utterance, and allows for overlapping speech and actions. We further present findings from an empirical study showing that the resulting dialogue system is faster overall than its nonincremental counterpart. Furthermore, the incremental system is preferred to its nonincremental counterpart – beyond what is accounted for by factors such as speed and accuracy. These results indicate that successful incremental understanding systems will improve both performance and usability.

Hand-drawn animation is a major art form and communication medium, but can be challenging to produce. We present a system to help people create frame-by-frame animations through manual sketches. We design our interface to be minimalistic: it contains only a canvas and a few controls. When users draw on the canvas, our system silently analyzes all past sketches and predicts what might be drawn in the future across spatial locations and temporal frames. The interface also offers suggestions to beautify existing drawings. Our system can reduce manual workload and improve output quality without compromising natural drawing flow and control: users can accept, ignore, or modify such predictions visualized on the canvas by simple gestures. Our key idea is to extend the local similarity method in [Xing et al. 2014], which handles only low-level spatial repetitions such as hatches within a single frame, to a global similarity that can capture high-level structures across multiple frames such as dynamic objects. We evaluate our system through a preliminary user study and confirm that it can enhance both users' objective performance and subjective satisfaction.

Several ontologies have been created in the last years for the semantic annotation of scholarly publications and scientific documents. This rich variety of ontologies makes it difficult for those willing to annotate their documents to know which ones they should select for such activity. This paper presents a classification and description of these state-of-the-art ontologies, together with the rationale behind the different approaches. Finally, we provide an example of how some of these ontologies can be used for the annotation of a scientific document.

This paper provides a thorough evaluation of a set of six important Arabic OCR systems available in the market; namely: Abbyy FineReader, Leadtools, Readiris, Sakhr, Tesseract and NovoVerus. We test the OCR systems using a randomly selected images from the well known Arabic Printed Text Image database (250 images from the APTI database) and using a set of 8 images from an Arabic book. The APTI database contains 45.313.600 of both decomposable and non-decomposable word images. In the evaluation, we conduct two tests. The first test is based on usual metrics used in the literature. In the second test, we provide a novel measure for Arabic language, which can be used for other non-Latin languages.

We present a data-processing pipeline based on sparse feature learning and describe its applications to music annotation and retrieval. Content-based music annotation and retrieval systems process audio starting with features. While commonly used features, such as MFCC, are handcrafted to extract characteristics of the audio in a succinct way, there is increasing interest in learning features automatically from data using unsupervised algorithms. We describe a systemic approach applying feature-learning algorithms to music data, in particular, focusing on a highdimensional sparse-feature representation. Our experiments show that, using only a linear classifier, the newly learned features produce results on the CAL500 dataset comparable to state-of-the-art music annotation and retrieval systems.


Question: Anno: A visual utility for the transcription and real-time annotation of handwritten documents.

This paper explores the differences between JSON (JavaScript Object Notation) and XML (eXtensible Markup Language) in the context of AJAX (Asynchronous JavaScript and XML) applications, which are fundamental to the Web 2.0 landscape. Historically, XML has been the go-to format for data loading, requiring resolution through DOM (Document Object Model) on both client-side and server-side. However, this process can lead to significant resource consumption and diminish user experience. JSON, as a lightweight alternative, offers enhanced flexibility and efficiency. Through empirical analysis, we compare JSON and XML, ultimately employing JSON as the data-transfer format in a real-world project. Our findings confirm that JSON serves as a more effective data-loading mechanism for AJAX applications, optimizing performance and user-friendliness.

In this paper, we review our experience with constructing one such large annotated corpus--the Penn Treebank, a corpus consisting of over 4.5 million words of American English. During the first three-year phase of the Penn Treebank Project (1989-1992), this corpus has been annotated for part-of-speech (POS) information. In addition, over half of it has been annotated for skeletal syntactic structure. Comments University of Pennsylvania Department of Computer and Information Science Technical Report No. MSCIS-93-87. This technical report is available at ScholarlyCommons: http://repository.upenn.edu/cis_reports/237 Building A Large Annotated Corpus of English: The Penn Treebank MS-CIS-93-87 LINC LAB 260 Mitchell P. Marcus Beatrice Santorini Mary Ann Marcinkiewicz University of Pennsylvania School of Engineering and Applied Science Computer and Information Science Department Philadelphia, PA 19104-6389

This paper presents a model to convert natural Bengali language to text. The proposed model requires the usage of the open sourced framework Sphinx 4 which is written in Java and provides the required procedural coding tools to develop an acoustic model for a custom language like Bengali. Our main objective was to ensure that the system was adequately trained on a word by word basis from various speakers so that it could recognize new speakers fluently. We used a free digital audio workstation (DAW) called Audacity to manipulate the collected recording data via continuous frequency profiling techniques to reduce the Signal-to-Noise-Ratio (SNR), vocal leveling, normalization and syllable splitting as well as merging which ensure an error free 1:1-word mapping of each utterance with its mirror transcription file text. To evaluate the performance of proposed model, we utilize an audio dataset of recorded speech data from 10 individual speakers consisting of both males and females using custom transcript files that we wrote. Experimental results demonstrate that the proposed model exhibits average 71.7% accuracy for our tested dataset.

This paper presents an objective comparative evaluation of layout analysis methods for scanned historical documents. It describes the competition (modus operandi, dataset and evaluation methodology) held in the context of ICDAR2011 and the International Workshop on Historical Document Imaging and Processing (HIP2011), presenting the results of the evaluation of four submitted methods. A commercial state-of-the-art system is also evaluated for comparison. Two scenarios are reported in this paper, one evaluating the ability of methods to accurately segment regions and the other evaluating the whole pipeline of segmentation and region classification (with a text extraction goal). The results indicate that there is a convergence to a certain methodology with some variations in the approach. However, there is still a considerable need to develop robust methods that deal with the idiosyncrasies of historical documents.

This paper presents an approach to proceed with semantic annotation in historical documents from the 19th century that discuss the constitution of the mother language, the Portuguese Language in Brazil. The objective is to generate a group of semantically annotated documents in agreement with a domain ontology. To provide this domain ontology, the Linguistic Instrument Ontology was employed, and it supported the process of automatic semantic annotation. The results obtained with the annotation were analyzed in comparison with the Gold Standard and they presented an elevated level of coincidence, between 0.86 and 1.00 for the F1-score measure. Besides that, it was possible to locate new documents about the discussed domain in a sample of the Revistas Brazileiras. These results prove the efficacy of the approach of automatic semantic annotation.

Populating large-scale structured databases from unstructured sources is a critical and challenging task in data analytics. As automated feature engineering methods grow increasingly prevalent, constructing sufficiently large labeled training sets has become the primary hurdle in building machine learning information extraction systems. In light of this, we have taken a new approach called data programming [7]. Rather than hand-labeling data, in the data programming paradigm, users generate large amounts of noisy training labels by programmatically encoding domain heuristics as simple rules. Using this approach over more traditional distant supervision methods and fully supervised approaches using labeled data, we have been able to construct knowledge base systems more rapidly and with higher quality. Since the ability to quickly prototype, evaluate, and debug these rules is a key component of this paradigm, we introduce DDLite, an interactive development framework for data programming. This paper reports feedback collected from DDLite users across a diverse set of entity extraction tasks. We share observations from several DDLite hackathons in which 10 biomedical researchers prototyped information extraction pipelines for chemicals, diseases, and anatomical named entities. Initial results were promising, with the disease tagging team obtaining an F1 score within 10 points of the state-of-the-art in only a single day-long hackathon's work. Our key insights concern the challenges of writing diverse rule sets for generating labels, and exploring training data. These findings motivate several areas of active data programming research.

Most scientific documents on the web are unstructured or semi-structured, and the automatic document metadata extraction process becomes an important task. This paper describes a framework for automatic metadata extraction from scientific papers. Based on a spatial and visual knowledge principle, our system can extract title, authors and abstract from scientific papers. We utilize format information such as font size and position to guide the metadata extraction process. The experiment results show that our system achieves a high accuracy in header metadata extraction which can effectively assist the automatic index creation for digital libraries.

Stylometry today uses either stand-alone dedicated programs, custom-made by stylometrists, or applies existing software, often one for each stage of the analysis. Stylometry with R can be placed somewhere in-between, as the powerful open-source statistical programming environment provides, on the one hand, the opportunity of building statistical applications from scratch, and, on the other, allows less advanced researchers to use ready-made scripts and libraries. In our own stylometric adventure with R, one of the aims was to build a tool (or a set of tools) that would combine sophisticated state-of-the-art algorithms of classification and/or clustering with a user-friendly interface. In particular, we wanted to implement a number of multidimensional methods that could be used by scholars without programming skills. And more: it soon became evident that once our R scripts are made, provided with a graphic user interface and more or less documented, they are highly usable in class; experience shows that this is an excellent way to work around R’s normally steep learning curve without losing anything of the environment’s considerable computing power and speed.

A handwritten digit recognition system was used in a demonstration project to visualize artificial neural networks, in particular Kohonen’s self-organizing feature map. The purpose of this project was to introduce neural networks through a relatively easy-to-understand application to the general public. This paper describes several techniques used for preprocessing the handwritten digits, as well as a number of ways in which neural networks were used for the recognition task. Whereas the main goal was a purely educational one, a moderate recognition rate of 98% was reached on a test set.

We propose a methodology for a novel type of discourse annotation whose model is tuned to the analysis of a text as narrative. This is intended to be the basis of a “story bank” resource that would facilitate the automatic analysis of narrative structure and content. The methodology calls for annotators to construct propositions that approximate a reference text, by selecting predicates and arguments from among controlled vocabularies drawn from resources such as WordNet and VerbNet. Annotators then integrate the propositions into a conceptual graph that maps out the entire discourse; the edges represent temporal, causal and other relationships at the level of story content. Because annotators must identify the recurring objects and themes that appear in the text, they also perform coreference resolution and word sense disambiguation as they encode propositions. We describe a collection experiment and a method for determining inter-annotator agreement when multiple annotators encode the same short story. Finally, we describe ongoing work toward extending the method to integrate the annotator’s interpretations of character agency (the goals, plans and beliefs that are relevant, yet not explictly stated in the text).

This paper presents a cross platform multilingual multimedia Indian Sign Language (ISL) dictionary building tool. ISL is a linguistically under-investigated language with no source of well documented electronic data. Research on ISL linguistics also gets hindered due to a lack of ISL knowledge and the unavailability of any educational tools. Our system can be used to associate signs corresponding to a given text. The current system also facilitates the phonological annotation of Indian signs in the form of HamNoSys structure. The generated HamNoSys string can be given as input to an avatar module to produce an animated sign representation.