Question: Precision and detail of Kinect depth information for indoor mapping purposes.

This paper presents a comprehensive calibration methodology for Time-of-Flight (ToF) sensors, aiming to enhance the precision of range sensing in various applications. ToF sensors have emerged as a viable alternative to traditional distance measurement techniques, such as laser scanning and stereo-vision based on images, due to their capability to offer full-range distance data at high speeds. These sensors are pivotal in cutting-edge research domains, including real-time object identification, collision avoidance, and scene reconstruction. However, ToF sensors, particularly the Photonic Mixer Device (PMD), are not without limitations; they are subject to several error sources that can compromise the accuracy of the distance measurements. In light of this, the paper delves into the primary error factors affecting ToF cameras and introduces a novel calibration strategy that integrates intrinsic, distance-dependent, and reflectivity-related error calibrations into a unified, user-friendly system. A significant aspect of this approach is the introduction of an intensity-based calibration model, which demands less input data than existing models, thereby substantially decreasing the volume of calibration data required. This advancement represents a crucial contribution to the field, optimizing the calibration process and improving the overall performance of ToF sensors in indoor mapping and other applications. 2010 Elsevier Inc. All rights reserved.

This paper proposes an indoor positioning system (IPS) based on WLAN using a single fifth-generation (5G) Wi-Fi access point. The proposed method uses fingerprint and classification models based on KNN (K-nearest neighbor) and Bayes rule. The fingerprint is formed by beam RSS (Received Signal Strength) samples, collected in some 2D locations of the indoor environment. Numerical simulations shown that using the best beam samples, it is possible to locate the stationary user's mobile device with average error less than 2.5 m.

Calibration of the LiDAR sensor with RGB camera finds its usage in many application fields from enhancing image classification to the environment perception and mapping. This paper presents a pipeline for mutual pose and orientation estimation of the mentioned sensors using a coarse to fine approach. Previously published methods use multiple views of a known chessboard marker for computing the calibration parameters, or they are limited to the calibration of the sensors with a small mutual displacement only. Our approach presents a novel 3D marker for coarse calibration which can be robustly detected in both the camera image and the LiDAR scan. It also requires only a single pair of camera-LiDAR frames for estimating large sensors displacement. Consequent refinement step searches for more accurate calibration in small subspace of calibration parameters. The paper also presents a novel way for evaluation of the calibration precision using projection error.

One major goal of vision is to infer physical models of objects, surfaces, and their layout from sensors. In this paper, we aim to interpret indoor scenes from one RGBD image. Our representation encodes the layout of orthogonal walls and the extent of objects, modeled with CAD-like 3D shapes. We parse both the visible and occluded portions of the scene and all observable objects, producing a complete 3D parse. Such a scene interpretation is useful for robotics and visual reasoning, but difficult to produce due to the well-known challenge of segmentation, the high degree of occlusion, and the diversity of objects in indoor scenes. We take a data-driven approach, generating sets of potential object regions, matching to regions in training images, and transferring and aligning associated 3D models while encouraging fit to observations and spatial consistency. We use support inference to aid interpretation and propose a retrieval scheme that uses convolutional neural networks to classify regions and retrieve objects with similar shapes. We demonstrate the performance of our method on our newly annotated NYUd v2 dataset (Silberman et al., in: Computer vision-ECCV, 2012, pp 746–760, 2012) with detailed 3D shapes.

We present an interactive material acquisition system for average users to capture the spatially-varying appearance of daily objects. While an object is being scanned, our system computes its appearance on-the-fly and provides quick visual feedback. We build the system entirely on low-end, off-the-shelf components: a Kinect, a mirror ball and printed markers. We exploit the Kinect infra-red emitter/receiver, originally designed for depth computation, as an active hand-held reflectometer, to segment the object into clusters of similar specular materials and estimate the roughness parameters of BRDFs simultaneously. Next, the diffuse albedo and specular intensity of the spatially-varying materials are rapidly computed in an inverse rendering framework, using data from the Kinect RGB camera. We demonstrate captured results of a range of materials, and physically validate our system. CR Categories: I.3.7 [Computer Graphics]: Three-Dimensional Graphics and Realism—Color, shading, shadowing, and texture

In this paper, we present RKD-SLAM, a robust keyframe-based dense SLAM approach for an RGB-D camera that can robustly handle fast motion and dense loop closure, and run without time limitation in a moderate size scene. It not only can be used to scan high-quality 3D models, but also can satisfy the demand of VR and AR applications. First, we combine color and depth information to construct a very fast keyframe-based tracking method on a CPU, which can work robustly in challenging cases (e.g. fast camera motion and complex loops). For reducing accumulation error, we also introduce a very efficient incremental bundle adjustment (BA) algorithm, which can greatly save unnecessary computation and perform local and global BA in a unified optimization framework. An efficient keyframe-based depth representation and fusion method is proposed to generate and timely update the dense 3D surface with online correction according to the refined camera poses of keyframes through BA. The experimental results and comparisons on a variety of challenging datasets and TUM RGB-D benchmark demonstrate the effectiveness of the proposed system.

Online 3D reconstruction of real-world scenes has been attracting increasing interests from both the academia and industry, especially with the consumer-level depth cameras becoming widely available. Recent most online reconstruction systems take live depth data from a moving Kinect camera and incrementally fuse them to a single high-quality 3D model in real time. Although most real-world scenes have static environment, the daily objects in a scene often move dynamically, which are non-trivial to reconstruct especially when the camera is also not still. To solve this problem, we propose a single depth camera-based real-time approach for simultaneous reconstruction of dynamic object and static environment, and provide solutions for its key issues. In particular, we first introduce a robust optimization scheme which takes advantage of raycasted maps to segment moving object and background from the live depth map. The corresponding depth data are then fused to the volumes, respectively. These volumes are raycasted to extract views of the implicit surface which can be used as a consistent reference frame for the next iteration of segmentation and tracking. Particularly, in order to handle fast motion of dynamic object and handheld camera in the fusion stage, we propose a sequential 6D pose prediction method which largely increases the registration robustness and avoids registration failures occurred in conventional methods. Experimental results show that our approach can reconstruct moving object as well as static environment with rich details, and outperform conventional methods in multiple aspects.

The recent introduction of depth cameras like Leap Motion Controller allows researchers to exploit the depth information to recognize hand gesture more robustly. This paper proposes a novel hand gesture recognition system with Leap Motion Controller. A series of features are extracted from Leap Motion tracking data, we feed these features along with HOG feature extracted from sensor images into a multiclass SVM classifier to recognize performed gesture, dimension reduction and feature weighted fusion are also discussed. Our results show that our model is much more accurate than previous work.

We propose a general framework for aligning continuous (oblique) video onto 3D sensor data. We align a point cloud computed from the video onto the point cloud directly obtained from a 3D sensor. This is in contrast to existing techniques where the 2D images are aligned to a 3D model derived from the 3D sensor data. Using point clouds enables the alignment for scenes full of objects that are difficult to model; for example, trees. To compute 3D point clouds from video, motion stereo is used along with a state-of-the-art algorithm for camera pose estimation. Our experiments with real data demonstrate the advantages of the proposed registration algorithm for texturing models in large-scale semi-urban environments. The capability to align video before a 3D model is built from the 3D sensor data offers new practical opportunities for 3D modeling. We introduce a novel modeling-through-registration approach that fuses 3D information from both the 3D sensor and the video. Initial experiments with real data illustrate the potential of the proposed approach.

Accurate and high-quality depth maps are required in lots of 3D applications, such as multi-view rendering, 3D reconstruction and 3DTV. However, the resolution of captured depth image is much lower than that of its corresponding color image, which affects its application performance. In this paper, we propose a novel depth map super-resolution (SR) method by taking view synthesis quality into account. The proposed approach mainly includes two technical contributions. First, since the captured low-resolution (LR) depth map may be corrupted by noise and occlusion, we propose a credibility based multi-view depth maps fusion strategy, which considers the view synthesis quality and interview correlation, to refine the LR depth map. Second, we propose a view synthesis quality based trilateral depth-map up-sampling method, which considers depth smoothness, texture similarity and view synthesis quality in the up-sampling filter. Experimental results demonstrate that the proposed method outperforms state-of-the-art depth SR methods for both super-resolved depth maps and synthesized views. Furthermore, the proposed method is robust to noise and achieves promising results under noise-corruption conditions.

We present the first dense SLAM system capable of reconstructing non-rigidly deforming scenes in real-time, by fusing together RGBD scans captured from commodity sensors. Our DynamicFusion approach reconstructs scene geometry whilst simultaneously estimating a dense volumetric 6D motion field that warps the estimated geometry into a live frame. Like KinectFusion, our system produces increasingly denoised, detailed, and complete reconstructions as more measurements are fused, and displays the updated model in real time. Because we do not require a template or other prior scene model, the approach is applicable to a wide range of moving objects and scenes.


Question: Precision and detail of Kinect depth information for indoor mapping use cases.

This paper introduces a novel approach for estimating camera pose within an unfamiliar environment, specifically tailored for augmented reality (AR) applications in confined spaces. Contrary to previous attempts which have often involved adapting simultaneous localization and mapping (SLAM) algorithms designed for robotic navigation, we present a system that is finely tuned for the unique challenges of tracking handheld cameras in small AR workspaces. Our methodology involves a dual-process strategy, executed in parallel on a dual-core processor, dividing the process into two distinct tasks: one thread focuses on the reliable tracking of unpredictable handheld motion, while the other concurrently generates a three-dimensional map of feature points from previously captured video frames. This innovative separation enables the utilization of resource-intensive batch optimization methods, typically incompatible with real-time operations. Consequently, our system is capable of creating highly detailed maps, encompassing thousands of landmarks, which can be tracked at the video frame rate. The system's accuracy and robustness are on par with those of advanced model-based systems, showcasing its potential for enhancing the precision and reliability of AR experiences in indoor settings.

In this paper we have proposed and designed FindingHuMo (Finding Human Motion), a real-time user tracking system for Smart Environments. FindingHuMo can perform device-free tracking of multiple (unknown and variable number of) users in the Hallway Environments, just from non-invasive and anonymous (not user specific) binary motion sensor data stream. The significance of our designed system are as follows: (a) fast tracking of individual targets from binary motion data stream from a static wireless sensor network in the infrastructure. This needs to resolve unreliable node sequences, system noise and path ambiguity, (b) Scaling for multi-user tracking where user motion trajectories may crossover with each other in all possible ways. This needs to resolve path ambiguity to isolate overlapping trajectories, FindingHumo applies the following techniques on the collected motion data stream: (i) a proposed motion data driven adaptive order Hidden Markov Model with Viterbi decoding (called Adaptive-HMM), and then (ii) an innovative path disambiguation algorithm (called CPDA). Using this methodology the system accurately detects and isolates motion trajectories of individual users. The system performance is illustrated with results from real-time system deployment experience in a Smart Environment.

Indoor localization and tracking of persons and assets with centimeter-level accuracy for inventory, security, medical monitoring, and training, as well as gesture interfaces for domotics, is highly desirable in the framework of the emerging IoT paradigm. Low cost, tiny, battery, or batteryless operated position sensors are required. 3-D localization can be computed by combining three or more distance measurements between sensor and reference points. Our aim is to give the capability of measuring the distance from a reference point to radio frequency identification (RFID) tags. The main challenge is in the estimation of the distances with millimeter accuracy in presence of both size and power supply strict constraints, and thus with very limited computational power. An accurate ranging technique using cross-correlation and small RFID-based sensors is proposed. Its originality resides in moving the main computational efforts from the sensor to an external processing unit with sufficient computational and supply power, thus overcoming the sensor limits. The system is composed of a beacon that emits ultrasound chirps and RF sync signals, a RFID-based distance sensor, a commercial RFID reader, and a processing unit. Main advantages are the high miniaturization and low power consumption of the remote sensor, and its compatibility with existing RFID standards.

In this paper a novel evaluation framework for measuring the performance of real-time action recognition methods is presented. The evaluation framework will extend the time-based event detection metric to model multiple distinct action classes. The proposed metric provides more accurate indications of the performance of action recognition algorithms for games and other similar applications since it takes into consideration restrictions related to time and consecutive repetitions. Furthermore, a new dataset, G3D for real-time action recognition in gaming containing synchronised video, depth and skeleton data is provided. Our results indicate the need of an advanced metric especially designed for games and other similar real-time applications.

Our model achieves the state-of-the-art performance on SUNRGBD, NYUdepth v2. It can be leveraged to improve the groundtruth annotations of newly captured 3943 RGB-D images in the SUNRGBD dataset. 2.2% improvement over previous state-of-the-art average accuracy and best on 15 categories Photometric data is vital for scene labeling while depth is an auxiliary information source. LSMT-CF model is important for fusing context features from different sources.

This paper describes the implementation of a LCD stripe projection system, based on a new processing scheme called line shift processing. One advantage of the method is, that the projection device can, but is not required to be stable over time nor does it have to be calibrated. The new method therefore allows us to use an off-the-shelf multimedia projector to acquire dense 3-D data (several 100K Triangles) of large objects in a matter of seconds. Since we are able to control our source of illumination, we can also acquire registered color information using standard monochrome cameras. Besides the description of the system some practical examples are given. The calibration of the system is also addressed.

In many applications, maintaining a consistent dense map of the environment is key to enabling robotic platforms to perform higher level decision making. Several works have addressed the challenge of creating precise dense 3D maps. However, during operation over longer missions, reconstructions can easily become inconsistent due to accumulated camera tracking error and delayed loop closure. Without explicitly addressing the problem of map consistency, recovery from such distortions tends to be difficult. We present a novel system for dense 3D mapping which addresses the challenge of building consistent maps while dealing with scalability. Central to our approach is the representation of the environment as a manifold map, comprised of overlapping Truncated Signed Distance Field (TSDF) volumes. These volumes are localized through featurebased bundle adjustment. Our main contribution is to use a probabilistic measure to identify stable regions in the map, and fuse the contributing subvolumes. This approach allows us to reduce map growth while still maintaining consistency. We demonstrate the proposed system on publicly available datasets, as well as on a number of our own datasets, and demonstrate the efficacy of the proposed approach for building consistent and scalable maps.

We introduce a new dataset, Human3.6M, of 3.6 Million accurate 3D Human poses, acquired by recording the performance of 5 female and 6 male subjects, under 4 different viewpoints, for training realistic human sensing systems and for evaluating the next generation of human pose estimation models and algorithms. Besides increasing the size of the datasets in the current state-of-the-art by several orders of magnitude, we also aim to complement such datasets with a diverse set of motions and poses encountered as part of typical human activities (taking photos, talking on the phone, posing, greeting, eating, etc.), with additional synchronized image, human motion capture, and time of flight (depth) data, and with accurate 3D body scans of all the subject actors involved. We also provide controlled mixed reality evaluation scenarios where 3D human models are animated using motion capture and inserted using correct 3D geometry, in complex real environments, viewed with moving cameras, and under occlusion. Finally, we provide a set of large-scale statistical models and detailed evaluation baselines for the dataset illustrating its diversity and the scope for improvement by future work in the research community. Our experiments show that our best large-scale model can leverage our full training set to obtain a 20% improvement in performance compared to a training set of the scale of the largest existing public dataset for this problem. Yet the potential for improvement by leveraging higher capacity, more complex models with our large dataset, is substantially vaster and should stimulate future research. The dataset together with code for the associated large-scale learning models, features, visualization tools, as well as the evaluation server, is available online at http://vision.imar.ro/human3.6m.

We present a method for discovering object models from 3D meshes of indoor environments. Our algorithm first decomposes the scene into a set of candidate mesh segments and then ranks each segment according to its “objectness” - a quality that distinguishes objects from clutter. To do so, we propose five intrinsic shape measures: compactness, symmetry, smoothness, and local and global convexity. We additionally propose a recurrence measure, codifying the intuition that frequently occurring geometries are more likely to correspond to complete objects. We evaluate our method in both supervised and unsupervised regimes on a dataset of 58 indoor scenes collected using an Open Source implementation of Kinect Fusion [1]. We show that our approach can reliably and efficiently distinguish objects from clutter, with Average Precision score of .92. We make our dataset available to the public.

A new generation of active 3D range sensors, such as time-of-flight cameras, enables recording of full-frame depth maps at video frame rate. Unfortunately, the captured data are typically starkly contaminated by noise and the sensors feature only a rather limited image resolution. We therefore present a pipeline to enhance the quality and increase the spatial resolution of range data in real-time by upsampling the range information with the data from a high resolution video camera. Our algorithm is an adaptive multi-lateral upsampling filter that takes into account the inherent noisy nature of real-time depth data. Thus, we can greatly improve reconstruction quality, boost the resolution of the data to that of the video sensor, and prevent unwanted artifacts like texture copy into geometry. Our technique has been crafted to achieve improvement in depth map quality while maintaining high computational efficiency for a real-time application. By implementing our approach on the GPU, the creation of a real-time 3D camera with video camera resolution is feasible.

[3] Sharp, T., Keskin, C., Robertson, D., Taylor, J., Shotton, J., Leichter, D.K.C.R.I., Wei, A.V.Y., Krupka, D.F.P.K.E., Fitzgibbon, A., Izadi, S.: Accurate, robust, and flexible real-time hand tracking. In: CHI (2015) [4] Oberweger, M., Wohlhart, P., Lepetit, V.: Training a feedback loop for hand pose estimation. In: ICCV (2015) [18] Oberweger, M., Wohlhart, P., Lepetit, V.: Hands deep in deep learning for hand pose estimation. arXiv preprint arXiv:1502.06807 (2015) [19] Tang, D., Taylor, J., Kohli, P., Keskin, C., Kim, T.K., Shotton, J.: Opening the black box: Hierarchical sampling optimization for estimating human hand pose. In: ICCV (2015) * Indicates equal contribution. Results T θ


Question: The precision and detail of Kinect depth information for use in indoor mapping scenarios.

This document explores the calibration of 3D range cameras, specifically those based on the time-of-flight principle using Photonic Mixing Devices (PMD), in conjunction with standard 2D CCD cameras. Given the PMD-cameras' narrow field-of-view (fov) and low-resolution pixel counts, traditional calibration techniques are insufficient. Moreover, these 3D range data sets are marred by systematic errors that require correction. A novel calibration methodology is thus devised to accurately determine the full intrinsic calibration of the PMD-camera, encompassing optical lens distortions and systematic range errors, while simultaneously calibrating the external orientation in tandem with multiple 2D cameras rigidly attached to the PMD-camera. This approach relies on a planar checkerboard pattern as the calibration reference, observed from various angles and distances. By integrating the PMD-camera with standard CCD cameras, the internal camera parameters can be estimated with greater precision, thereby circumventing the constraints imposed by the PMD's limited fov. Furthermore, the additional cameras facilitate the calibration of the PMD-camera's systematic depth measurement errors. The document highlights the significant reduction in correlation between rotation and translation estimation achieved through this method.

We present a method for discovering object models from 3D meshes of indoor environments. Our algorithm first decomposes the scene into a set of candidate mesh segments and then ranks each segment according to its “objectness” - a quality that distinguishes objects from clutter. To do so, we propose five intrinsic shape measures: compactness, symmetry, smoothness, and local and global convexity. We additionally propose a recurrence measure, codifying the intuition that frequently occurring geometries are more likely to correspond to complete objects. We evaluate our method in both supervised and unsupervised regimes on a dataset of 58 indoor scenes collected using an Open Source implementation of Kinect Fusion [1]. We show that our approach can reliably and efficiently distinguish objects from clutter, with Average Precision score of .92. We make our dataset available to the public.

We describe a technique that automatically generates plausible depth maps from videos using non-parametric depth sampling. We demonstrate our technique in cases where past methods fail (non-translating cameras and dynamic scenes). Our technique is applicable to single images as well as videos. For videos, we use local motion cues to improve the inferred depth maps, while optical flow is used to ensure temporal depth consistency. For training and evaluation, we use a Kinect-based system to collect a large data set containing stereoscopic videos with known depths. We show that our depth estimation technique outperforms the state-of-the-art on benchmark databases. Our technique can be used to automatically convert a monoscopic video into stereo for 3D visualization, and we demonstrate this through a variety of visually pleasing results for indoor and outdoor scenes, including results from the feature film Charade.

Automatic recognition of human actions from video has been studied for many years. Although still very difficult in uncontrolled scenarios, it has been successful in more restricted settings (e.g., fixed viewpoint, no occlusions) with recognition rates approaching 100%. However, the best-performing methods are complex and computationally-demanding and thus not well-suited for real-time deployments. This paper proposes to leverage the Kinect camera for close-range gesture recognition using two methods. Both methods use feature vectors that are derived from the skeleton model provided by the Kinect SDK in real-time. Although both methods perform nearest-neighbor classification, one method does this in the space of features using the Euclidean distance metric, while the other method does this in the space of feature covariances using a log-Euclidean metric. Both methods recognize 8 hand gestures in real time achieving correct-classification rates of over 99% on a dataset of 20 subjects but the method based on Euclidean distance requires feature-vector collections to be of the same size, is sensitive to temporal misalignment, and has higher computation and storage requirements.

We present Travi-Navi - a vision-guided navigation system that enables a self-motivated user to easily bootstrap and deploy indoor navigation services, without comprehensive indoor localization systems or even the availability of floor maps. Travi-Navi records high quality images during the course of a guider's walk on the navigation paths, collects a rich set of sensor readings, and packs them into a navigation trace. The followers track the navigation trace, get prompt visual instructions and image tips, and receive alerts when they deviate from the correct paths. Travi-Navi also finds the most efficient shortcuts whenever possible. We encounter and solve several challenges, including robust tracking, shortcut identification, and high quality image capture while walking. We implement Travi-Navi and conduct extensive experiments. The evaluation results show that Travi-Navi can track and navigate users with timely instructions, typically within a 4-step offset, and detect deviation events within 9 steps.

Depth maps captured by range scanning devices or by using optical cameras often suffer from missing regions due to occlusions, reflectivity, limited scanning area, sensor imperfections, etc. In this paper, we propose a fast and reliable algorithm for depth map inpainting using the tensor voting (TV) framework. For less complex missing regions, local edge and depth information is utilized for synthesizing missing values. The depth variations are modeled by local planes using 3D TV, and missing values are estimated using plane equations. For large and complex missing regions, we collect and evaluate depth estimates from self-similar (training) datasets. We align the depth maps of the training set with the target (defective) depth map and evaluate the goodness of depth estimates among candidate values using 3D TV. We demonstrate the effectiveness of the proposed approaches on real as well as synthetic data.

We present a novel method for accurate and efficient upsampling of sparse depth data, guided by high-resolution imagery. Our approach goes beyond the use of intensity cues only and additionally exploits object boundary cues through structured edge detection and semantic scene labeling for guidance. Both cues are combined within a geodesic distance measure that allows for boundary-preserving depth interpolation while utilizing local context. We model the observed scene structure by locally planar elements and formulate the upsampling task as a global energy minimization problem. Our method determines globally consistent solutions and preserves fine details and sharp depth boundaries. In our experiments on several public datasets at different levels of application, we demonstrate superior performance of our approach over the state-of-the-art, even for very sparse measurements.

In this paper, we developed an image-based indoor localization system using omnidirectional panoramic images to which location information is added. By the combination of the robust image matching by PCA-SIFT and fast nearest neighbor search algorithm based on Locality Sensitive Hashing (LSH), our system can estimate users' positions with high accuracy and in a short time. To improve the precision, we introduced the "confidence" of the image matching results. We conducted experiments at the Railway Museum and we obtained 426 omnidirectional panoramic reference images and 1067 supplemental images for image matching. Experimental results using 126 test images demonstrated that the location detection accuracy is above 90% with about 2.2s of processing time.

In last decade lot of efforts had been made by research community to create sign language recognition system which provide a medium of communication for differently-abled people and their machine translations help others having trouble in understanding such sign languages. Computer vision and machine learning can be collectively applied to create such systems. In this paper, we present a sign language recognition system which makes use of depth images that were captured using a Microsoft Kinect® camera. Using computer vision algorithms, we develop a characteristic depth and motion profile for each sign language gesture. The feature matrix thus generated was trained using a multi-class SVM classifier and the final results were compared with existing techniques. The dataset used is of sign language gestures for the digits 0-9.

Autonomous parking in an indoor parking lot without human intervention is one of the most demanded and challenging tasks of autonomous driving systems. The key to this task is precise real-time indoor localization. However, state-of-the-art low-level visual feature-based simultaneous localization and mapping systems (VSLAM) suffer in monotonous or texture-less scenes and under poor illumination or dynamic conditions. Additionally, low-level feature-based mapping results are hard for human beings to use directly. In this paper, we propose a semantic landmark-based robust VSLAM for real-time localization of autonomous vehicles in indoor parking lots. The parking slots are extracted as meaningful landmarks and enriched with confidence levels. We then propose a robust optimization framework to solve the aliasing problem of semantic landmarks by dynamically eliminating suboptimal constraints in the pose graph and correcting erroneous parking slots associations. As a result, a semantic map of the parking lot, which can be used by both autonomous driving systems and human beings, is established automatically and robustly. We evaluated the real-time localization performance using multiple autonomous vehicles, and an repeatability of 0.3 m track tracing was achieved at a 10 kph of autonomous driving.

We propose UnLoc, an unsupervised indoor localization scheme that bypasses the need for war-driving. Our key observation is that certain locations in an indoor environment present identifiable signatures on one or more sensing dimensions. An elevator, for instance, imposes a distinct pattern on a smartphone's accelerometer; a corridor-corner may overhear a unique set of WiFi access points; a specific spot may experience an unusual magnetic fluctuation. We hypothesize that these kind of signatures naturally exist in the environment, and can be envisioned as internal landmarks of a building. Mobile devices that "sense" these landmarks can recalibrate their locations, while dead-reckoning schemes can track them between landmarks. Results from 3 different indoor settings, including a shopping mall, demonstrate median location errors of 1:69m. War-driving is not necessary, neither are floorplans the system simultaneously computes the locations of users and landmarks, in a manner that they converge reasonably quickly. We believe this is an unconventional approach to indoor localization, holding promise for real-world deployment.


Question: A fully integrated 5-GHz full PMOS low-phase-noise LC voltage-controlled oscillator.

This paper explores the 1/f noise characteristics of NMOS and PMOS transistors and their implications for the design of voltage-controlled oscillators (VCOs) in a 0.25 /spl mu/m CMOS process featuring a pure SiO/sub 2/ gate oxide layer. Remarkably, the findings reveal that surface channel PMOS transistors exhibit approximately ten times lower 1/f noise than their NMOS counterparts, particularly when V/sub GS/-V/sub TH/ is less than around 0.4 V. Leveraging this data, the study demonstrates that a VCO constructed entirely from surface channel PMOS transistors can achieve a close-in phase noise reduction of approximately 14 dB compared to a VCO utilizing all surface channel NMOS transistors. This highlights the potential of PMOS transistors for enhancing the performance of VCOs in terms of phase noise, especially at close-in frequencies.

CMOS transmit-receive (T/R) switches have been integrated in a 0.18-/spl mu/m standard CMOS technology for wireless applications at 2.4 and 5.2 GHz. This switch design achieves low loss and high linearity by increasing the substrate impedance of a MOSFET at the frequency of operation using a properly tuned LC tank. The switch design is asymmetric to accommodate the different linearity and isolation requirements in the transmit and receive modes. In the transmit mode, the switch exhibits 1.5-dB insertion loss, 28-dBm power, 1-dB compression point (P/sub 1dB/), and 30-dB isolation, at 2.4 and 5.2 GHz. In the receive mode, the switch achieves 1.6-dB insertion loss, 11.5-dBm P/sub 1dB/, and 15-dB isolation, at 2.4 and 5.2 GHz. The linearity obtained in the transmit mode is the highest reported to date in a standard CMOS process. The switch passes the 4-kV Human Body Model electrostatic discharge test. These results show that the switch design is suitable for narrow-band applications requiring a moderate-high transmitter power level (<1 W).

In this work, the analysis of the flipped voltage follower (FVF) based single-transistor-control (STC) LDO is given. Two evolved versions of FVF, cascaded FVF (CAFVF) and level shifted FVF (LSFVF), are studied. Then, a buffered FVF (BFVF) for LDO application is proposed, combining the virtues of both CAFVF and LSFVF structures. It alleviates the minimum loading requirement of FVF and the simulation result shows that it has faster transient response and better load regulation.

A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined phase-interpolator and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation. This technique can be used for designing a fractional-N PLL with low in-band phase noise and low spurious tones with low power consumption. The short-current-free pipelined phase-interpolator used in this work is capable of achieving high-linearity with low-power while minimizing the intrinsic jitter. A number of other circuit techniques and layout techniques are also employed in this design for ensuring high-performance operation with minimal chip area and power consumption. The proposed fractional-N PLL is implemented in standard 65 nm CMOS technology. The PLL has an operating range of 600 MHz from 4.34 GHz to 4.94 GHz. In fractional-N mode, the proposed PLL achieves -249.5 dB FoM and less than -59 dBc fractional spurs.

In this paper a charge pump circuit is presented: it is based on PMOS pass transistors with dynamic control of the gate and body voltages. By controlling the gate and the bulk of each PMOS pass transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the other with negligible voltage drop. Furthermore, the overdrive voltage of the pass transistors grows progressively from the first to the last stage. Hence, a larger output voltage can be achieved compared to conventional charge pumps, still retaining a simple two-phase clocking scheme, along with the Dickson basic architecture. The prototype was fabricated using the STMicroelectronics T10 90nm CMOS process. Measurements results are also presented confirming the validity of the design

This paper presents a direct-conversion receiver for FCC-compliant ultra-wideband (UWB) Gaussian-shaped pulses that are transmitted in one of fourteen 500-MHz-wide channels within the 3.1-10.6-GHz band. The receiver is fabricated in 0.18-mum SiGe BiCMOS. The packaged chip consists of an unmatched wideband low-noise amplifier (LNA), filter, phase-splitter, 5-GHz ISM band switchable notch filter, 3.1-10.6-GHz local oscillator (LO) amplifiers, mixers, and baseband channel-select filters/buffers. The required quadrature single-ended LO signals are generated externally. The average conversion gain and input P1dB are 32 dB and -41 dBm, respectively. The unmatched LNA provides a system noise figure of 3.3 to 5 dB over the entire band. The chip draws 30 mA from 1.8 V. To verify the unmatched LNA's performance in a complete system, wireless testing of the front-end embedded in a full receiver at 100 Mbps reveals a 10-3 bit-error rate (BER) at -80 dBm sensitivity. The notch filter suppresses out-of-band interferers and reduces the effects of intermodulation products that appear in the baseband. BER improvements of an order of magnitude and greater are demonstrated with the filter

A current mode control integrated circuit with accuracy current sensing circuit ( CSC ) for buck converter is presented in this the proposed accurate integrated current sensed inductor with the internal ramp be used for DC-DC converter feedback proposed CSC doesn't need an op amp to implement, and has been fabricated with a standard 0.35 mum CMOS process. Simulation result show that the switching converter can be operated up to 1 MHZ. The supply is suitable for signal cell lithium-ion battery supply power efficiency is over 85% for supply voltage from 2.5 V to 5 V and output current is 200 mA. The performance of the proposed circuit is the good compared to the other circuits.

This paper focuses on the analysis and the design methodology of the step-impedance phase-inverter rat-race coupler on a silicon-based process. The issues of impedance limitation and bandwidth are discussed in detail. Our proposed concept utilizes a high silicon dielectric constant, phase-inverter structure, step-impedance technique, and Chebyshev response to make the rat-race coupler more compact (~ 64% reduction) and highly balanced over a wide operating bandwidth. Moreover, the inter-digital coplanar stripline used in the step-impedance section effectively reduces the characteristic impedance of the transmission line for large size shrinkage and insertion-loss reduction. The demonstrated step-impedance rat-race coupler directly on silicon substrate has 6- ~ 7-dB insertion loss from 5 to 15 GHz and small variations in amplitude/phase balance. Compared with our previous work, the proposed rat-race coupler achieves a 3-dB improvement in the insertion loss. Thus, a 0.13-μm CMOS Gilbert down-converter with a miniature phase-inverter rat-race coupler at the RF path for wideband single-to-differential signal conversion achieves a noise figure of 16 dB.

Continuous conduction mode (CCM) boost converter is difficult to compensate due to the right half plane (RHP) zero. This paper presents a quasi fixed frequency constant on time (COT) controlled boost converter, it has no loop compensation requirement. With the proposed COT control, pulse frequency modulation (PFM) comes free at light load, which improves the light load efficiency compared with traditional PWM control. A compact on-time generator that controls the operation frequency is proposed. And a current sink based feedback circuit is used to improve the quality of feedback signal.The COT controller is designed with 1.5 mum BCD process. Simulation results demonstrate that the COT boost converter has fast load transient response and quasi fixed frequency operation.

An auto-zero and chopper operational amplifier with a 4.5-60 V supply voltage range is realized, using a 0.18 μm CMOS process augmented by 5 V CMOS and 60 V DMOS transistors. It achieves a maximum offset voltage drift of 0.02 μV/°C, a minimum CMRR of 145 dB, a noise PSD of 6.8 nV/√Hz, and a 3.1 MHz unity gain bandwidth, while dissipating 840 μA of current. Up-modulated chopper ripple is suppressed by auto- zeroing. Furthermore, glitches from the charge injection of the input switches are mitigated by employing six parallel input stages with 800 kHz interleaved clocks. This moves the majority of the glitch energy up to 4.8 MHz, while leaving little energy at 800 kHz. As a result, the requirements on an external low-pass glitch filter is relaxed, and a wider usable signal bandwidth can be obtained. Maximum input bias current due to charge injection mismatch is reduced from 1.5 nA to 150 pA by post production trimming with an on-chip charge mismatch compensation circuit.

A reference-less highly digital half-rate clock and data recovery (CDR) circuit with improved tolerance to input duty cycle error is presented. Using a chain of frequency dividers, the pro posed frequency detector produces a known sub-harmonic tone from the incoming random data. A digital frequency-locked loop uses the extracted tone, and drives the oscillator to any sub-rate of the input data frequency. The early/late outputs of a conventional half-rate bang-bang phase detector are used to determine the duty-cycle error in the incoming random data and adjust the oscillator clock phases to maximize receiver timing margins. Fabricated in 0.13 μm CMOS technology, the prototype digital CDR op erates without any errors from 0.5 Gb/s to 2.5 Gb/s. At 2 Gb/s, the prototype consumes 6.1 mW power from a 1.2 V supply. The pro posed clock-phase calibration is capable of correcting upto ±20% of input data duty-cycle error.


Question: A fully integrated full PMOS low-phase-noise LC VCO operating at 5 GHz.

This paper delves into the design considerations for complementary metal-oxide-semiconductor (CMOS) differential LC oscillators, specifically focusing on phase noise analysis. It elucidates the impact of tail current and power dissipation within the tank circuit on voltage amplitude. The paper identifies and evaluates various noise sources in the complementary cross-coupled pair, providing insights into their contribution to phase noise. Experimental results validate the theoretical predictions across a wide range of tail currents and supply voltages. As a practical demonstration, a 1.8-GHz LC oscillator is showcased, achieving a phase noise of 121 dBc/Hz at 600 kHz, while consuming 6 mW of power. This performance is attained using on-chip spiral inductors, highlighting the oscillator's efficiency and suitability for integrated circuit applications.

This paper presents a new configuration for a linear operational transconductance amplifier (OTA) using a signal attenuation technique. The OTA is designed to operate with a ±0.8V supply voltage and consumes 0.45mW power. All simulations are performed by ELDO model BSIM3v3 technology CMOS TSMC 0.18μm. The simulation results of this circuit showed a high DC gain of 73.6dB with a unity frequency of 50.19MHz and a total harmonic distortion of -60.81dB at 100 kHz for an input voltage of 1Vpp. Based on this circuit, a voltage mode universal filter has been implemented. The simulation results are in a good agreement with the theoretical calculations.

A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of 43 dB for 900 mVpp at 30 MHz. The OTA, fabricated in 0.5m CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filter’s group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of 46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a 1.65-V power supply.

It is traditionally challenging to implement higher-order PWM closed-loop Class-D audio amplifiers using analog intensive techniques in deep-submicron, low voltage process technologies. This is primarily attributed to reduced power supply, degraded analog transistor characteristics, including short-channel effects, increased flicker noise, random telegraph noise, transistor reliability concerns and passive component performance. In this paper, we introduce a global closed-loop mixed-signal architecture incorporating digital control and integrate a fourth-order amplifier prototype in 55 nm CMOS. A systematic approach to analyze, design and compensate the feedback loop in the digital domain is also presented. The versatility of implementing the loop gain poles and zeros digitally attains high gain throughout the audio band and attenuates residual high frequency ripples around the loop, simultaneously accomplishing improvements in THD+N and PSRR. The overall architecture is inherently amenable to implementation in deep-submicron and is therefore compatible with scaled CMOS. The measured prototype achieves a high 105 dBA SNR, 0.0031% THD+N, 92 dB PSRR and 85% efficiency when supplying 1 W into emulated 8 Ω speaker load. This performance is competitive with conventional designs using large feature size precision CMOS or specialized BCD technologies and reports the highest output power (1.5 W) for deep-submicron designs.

A low-power ground-referenced audio decoder with PSRR-enhanced class-AB headphone amplifiers presents <;0.0016% THD in the whole audio band against the supply ripple by a negative charge-pump. Realized in the 40nm CMOS, the fully-integrated stereo decoder achieves 91dB SNDR and 100dB dynamic range while driving a 16Ω headphone load and consumes 5.2mW from a 1.8V power supply. The core area is 0.093mm2/channel only.

This paper presents the first simultaneous 8-transmit and 8-receive paths 75-85 GHz phased array RFIC for FMCW automotive radars. The receive path has two separate I/Q mixers each connected to 4-element phased arrays for RF and digital beamforming. The chip also contains a build-in-self-test system (BIST) for the transmit and receive paths. Measurements on a flip-chip prototype show a gain >24 dB at 77 GHz, -25 dB coupling between adjacent channels in the transmit and receive paths (<;-45 dB between non-adjacent channels), and <;-50 dB coupling between the transmit and receive portions of the chip.

This paper discusses the design of a self-biased folded cascode operational amplifier at an ultra low power supply voltage. The proposed design is first of its kind at 0.5 V where self-biasing techniques are used to reduce power and area overheads. The self-biasing scheme in this design is developed by using a current mirror for low voltage operation. This design is implemented in a 90 nm CMOS technology using Cadence General Purpose Design Kit (GPDK).

In this paper, a novel design technique of common-gate inductive feedback is presented for millimeter-wave low-noise amplifiers (LNAs). For this technique, by adopting a gate inductor at the common-gate transistor of the cascode stage, the gain of the LNA can be enhanced even under a wideband operation. Using a 65nm CMOS process, transmission-line-based and spiral-inductor-based LNAs are fabricated for demonstration. With a dc power consumption of 33.6 mW from a 1.2-V supply voltage, the transmission-line-based LNA exhibits a gain of 20.6 dB and a noise figure of 5.4 dB at 60 GHz while the 3dB bandwidth is 14.1 GHz. As for the spiral-inductor-based LNA, consuming a dc power of 28.8 mW from a 1.2-V supply voltage, the circuit shows a gain of 18.0 dB and a noise figure of 4.5 dB at 60 GHz while the 3dB bandwidth is 12.2 GHz.

This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10-100× smaller than the noise generated by a static CMOS circuit. Unlike static CMOS, whose dominant dynamic power is proportional to the frequency, MCML circuits dissipate a constant power independent of clock frequency. Although these traits make MCML highly energy efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at the modest clock rate and with a low activity factor. To address this challenge, a single-core microarchitecture for MCML is explored that exploits the C-slow retiming technique, and operates at a high frequency with low complexity to save energy. This design principle contrasts with the contemporary multicore design paradigm for static CMOS that relies on a large number of gates operating in parallel at the modest speeds. The proposed architecture generates 10-40× lower power and ground noise, and operates within 13% of the performance (i.e., 1/ExecutionTime) of a conventional, eight-core static CMOS processor while exhibiting 1.6× lower energy and 9% less area. Moreover, the operation of an MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length.

This paper describes a bioamplifier that employs a voltage-controlled-pseudo-resistor to achieve tunable bandwidth and wide operating voltage range for biomedical applications. The versatile pseudo-resistor employed provides ultra-high resistance for ac coupling to cancel the dc offset from electrode–tissue interface. The voltage-controlled-pseudo-resistor consists of serial-connected PMOS transistors working at the subthreshold region and an auto-tuning circuit that makes sure the constant (time-invariant) control-voltage of the pseudo-resistor. This bandwidth-tunable bioamplifier is designed in a 0.18-μm standard CMOS process, achieving a gain of 40.2 dB with 10.35-μW power consumption. The designed chip was also used to develop the proof-of-concept prototype. An operation bandwidth of 9.5 kHz, inputreferred noise of 5.2 μVrms from 6.3 Hz to 9.5 kHz and 5.54 μVrms from 250 Hz to 9.5 kHz, and a tunable cutoff-frequency from 6.3–600 Hz were demonstrated to prove our design. & 2015 Elsevier Ltd. All rights reserved.

This paper introduces a new low voltage sub-nanosecond monolithic pulsed current driver for light detection and ranging (LIDAR) applications. Unique architecture based on a controlled current source and Vernier activation sequence, combined with a monolithic implementation that allows operation with low input voltage levels, high-resolution pulse width and sub-nanosecond rise and fall times. An on-chip low voltage pulsed driver sub-nanosecond prototype has been implemented in a TS 0.18-μm 5V-gated power management process. It incorporates an integrated wide range sesnseFET based current sensor and a rail-to-rail comparator for current regulation. To characterize the avalanche capabilities of the integrated lateral MOSFET power devices required for the driver IC, a separate line of investigation has been carried out. Several lateral diffused MOS (LDMOS) power devices have been custom designed and experimentally evaluated for a life-cycle performance characterization. Post-layout analysis of the power driver IC is in a good agreement with the theoretical predictions. For a 5V input voltage, rise and fall times of the laser pulse light output are on the order of hundreds of picoseconds, with currents up to 5A. To validate the concept of high-resolution pulse width generation and short fall time, a discrete prototype has been constructed and experimentally tested.


Question: A fully integrated 5-GHz full PMOS low-phase-noise LC voltage-controlled oscillator.

This tutorial delves into the complexities of oscillator phase noise, offering a comprehensive analysis that bridges the gap between theoretical predictions and practical measurements. Traditional linear time-invariant (LTI) theories provide foundational insights into phase noise design but fall short in accurately forecasting phase noise levels. This discrepancy arises due to the multiple frequency transformations that device noise undergoes, a process that cannot be fully captured by theories assuming time invariance. Despite the nonlinearity required for amplitude stabilization, oscillators' noise-to-phase transfer function remains linear. The time-varying phase noise model discussed herein not only reconciles theoretical predictions with empirical data but also highlights the significance of symmetry in mitigating the upconversion of 1/f noise into close-in phase noise. Moreover, it elucidates the cyclostationary effects and the mechanism of AM-PM conversion, providing a fresh perspective on the superior performance of Colpitts oscillators. The tutorial proposes innovative oscillator topologies and includes case studies on tuned LC and ring oscillators to illustrate the practical implications of the theoretical framework. Appendices address simulation challenges and the integration of amplitude noise considerations, offering a holistic view of oscillator phase noise analysis.

In this paper, a noncontact proximity vital sign sensor, using a phase locked loop (PLL) incorporated with voltage controlled oscillator (VCO) built-in planar type circular resonator, is proposed to enhance sensitivity in severe environments. The planar type circular resonator acts as a series feedback element of the VCO as well as a near-field receiving antenna. The frequency deviation of the VCO related to the body proximity effect ranges from 0.07 MHz/mm to 1.8 MHz/mm (6.8 mV/mm to 205 mV/mm in sensitivity) up to a distance of 50 mm, while the amount of VCO drift is about 21 MHz in the condition of 60 °C temperature range and discrete component tolerance of ±5%. Total frequency variation occurs in the capture range of the PLL which is 60 MHz. Thus, its loop control voltage converts the amount of frequency deviation into a difference of direct current (DC) voltage, which is utilized to extract vital signs regardless of the ambient temperature. The experimental results reveal that the proposed sensor placed 50 mm away from a subject can reliably detect respiration and heartbeat signals without the ambiguity of harmonic signals caused by respiration signal at an operating frequency of 2.4 GHz.

A low-cost phased-array antenna at 10 GHz is presented for a scan angle of ±50°. The array employs continuously tunable phase shifters based on a screen printed barium-strontium-titanate thick-film ceramic. Due to the use of artificial transmission line topology, the proposed phase-shifter design has a very compact size (3 mm × 2.8 mm) for 342° total phase shift. In the frequency range from 8 to 10 GHz, it exhibits a figure of merit >;52°/dB, which is among the best of phase shifters based on ferroelectric thick films. In a prototyped phased array, the RF circuit consists of a feeding network, phase shifters, and antenna elements, which are integrated into one planar metallization layer. Furthermore, a simple way for routing bias lines for phase shifters is demonstrated using high resistive electrodes. Using screen printed thick films and applying a simplified fabrication process for the RF and bias circuitry can reduce the total expense of phased arrays considerably.

The use of integrated circuit techniques in position sensing applications can offer significant advantages over discrete component solutions, such as miniaturization, reduced cost, increased reliability and enhanced sensitivity. We realized a signal conditioner that includes an application specific integrated circuit (ASIC) and an external microcontroller for readout and control of non-contact high-frequency inductive position sensors. Both the system architecture and details on the key blocks are described. The ASIC was designed in a 0.6-¿m CMOS process technology and preliminary measured results are presented. The signal conditioner architecture is universal and can be used for other sensor types such as LVDTs.

We examine the current development of highly integrated 60-GHz radios with an interest in antenna-circuit interfaces. We design and analyze grid array antennas with special attention to the differential feeding and the patterned ground plane. More importantly, we integrate two grid array antennas in a package; propose the way of assembling it to the system printed circuit board; and demonstrate a total solution of low cost and thin profile to highly integrated 60-GHz radios. We show that the package in low temperature cofired ceramic (LTCC) technology measures only 13×13×0.575 mm3 ; can carry a 60-GHz radio die of current and future sizes with flip-chip bonding; and achieves good antenna performance in the 60-GHz band with maximum gain of 13.5 and 14.5 dBi for the single-ended and differential antennas, respectively.

CMOS implementations for RF applications often employ technology modifications to reduce the silicon substrate loss at high frequencies. The most common techniques include the use of a high-resistivity substrate (/spl rho/>10 /spl Omega/-cm) or silicon-on-insulator (SOI) substrate and precise bondwire inductors. However, these techniques are incompatible with low-cost CMOS manufacture. This design demonstrates use of CMOS with a conventional low-resistivity epi-substrate and on-chip inductors for applications above 10 GHz.

The architecture, design, and implementation of two clock-free analog class D audio power amplifiers using 0.5 ¿m CMOS standard technology are introduced. The amplifiers are designed to consume significantly less power than former implementations. Both designs operate with a 2.7 V single voltage supply and deliver a maximum output power of 250 mW into an 8 ¿ speaker. The two class-D amplifiers are based on a hysteretic sliding mode controller, which avoids the complex task of generating the highly linear triangle carrier signal used in conventional architectures. The first design generates a two-level modulated signal, known as binary modulated amplifier (BMA); the second topology implements a three-level modulated signal, also called ternary modulated amplifier (TMA). The architectures and implementations are simple and compact, providing very low quiescent power consumption. Experimental results of the BMA/TMA yield an efficiency of 89/90% and a total harmonic distortion plus noise (THD+N) of 0.02/0.03%, respectively. The efficiency and linearity is comparable to state-of-the-art amplifiers but the static power consumption is less than one tenth of previous proposed architectures. Both class D amplifiers achieve a power supply rejection ratio greater than 75 dB at 217 Hz, and a signal-to-noise ratio (SNR) higher than 90 dB within the whole audio band. Each amplifier occupies less than 1.5 mm2.

In this paper, a new current source gate drive circuit is proposed for high efficiency synchronous buck VRMs. The proposed circuit achieves quick turn-on and turn-off transition times to reduce switching loss and conduction loss in power MOSFETS. The driver circuit consists of two sets of four control switches and two very small inductors (typically 50 nH-300 nH each at 1 MHz). It drives both the control MOSFET and synchronous MOSFET in synchronous buck VRMs. An analysis, design procedure, optimization procedure and experimental results are presented for the proposed circuit. Experimental results demonstrate an efficiency of 86.6% at 15 A load and 81.9% at 30 A load for 12 V input and 1.3 V output at 1 MHz.

A 60 GHz wide locking range Miller divider is presented in this letter. To enhance the locking range of divider and save power consumption, we proposed a Miller divider based on weak inversion mixer. The proposed Miller divider is implemented in 65 nm CMOS and exhibits 57% locking range from 35.7 to 64.2 GHz at an input power of 0 dBm while consuming 1.6-mW dc power at 0.4 V supply. Compared to the previously reported CMOS millimeter wave frequency dividers, the proposed divider achieves the widest fractional bandwidth without any frequency tuning mechanism.

A single-chip 65GHz Doppler radar transceiver with on-chip patch antenna is reported. Implemented in a production 0.18mum SiGe BiCMOS process, it features a differential output transmit power of 4.3dBm, 16.5dB single-ended down-conversion gain and a double-sideband noise figure of 12.8dB. The radar includes a 65GHz 2-stage cascode LNA with S 11<-15dB at 50-94GHz and 14dB gain at 65GHz, a double-balanced down-convert mixer, a SiGe HBT IF amplifier with low 1/f noise, a VCO and a 65GHz output buffer. The LO is provided by an integrated varactor-tuned 61-67GHz VCO optimized for low phase noise. The patch antenna is designed to be impedance-matched for dual-band operation at 62.8 and 64.6GHz. The use of lumped inductors in all blocks and a vertically-stacked transformer for single-ended to differential conversion in the receive path help reduce the transceiver area to 1mm times 1mm

Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator(PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.


Question: A fully integrated, full PMOS, low-phase-noise LC VCO operating at 5 GHz.

This paper offers a comprehensive examination of clock jitter and phase noise in both single-ended and differential ring oscillators, providing a unified perspective. Utilizing impulse sensitivity functions, the authors derive analytical expressions to elucidate the jitter and phase noise characteristics of these oscillators. The study delves into the impact of various factors on jitter and phase noise, including the number of stages, power consumption, oscillation frequency, and short-channel effects. Additionally, the paper discusses jitter and phase noise caused by substrate and supply noise, highlighting the significance of symmetry in mitigating the upconversion of 1/f noise. The research offers valuable design insights for achieving low jitter and phase noise, supported by a strong correlation between theoretical predictions and experimental measurements.

**Question**: A Comparative Study of Metaheuristic Algorithms for Solving the Traveling Salesman Problem

**Documents**: A Comparative Study of Ant Colony Optimization and Genetic Algorithms for the Traveling Salesman Problem
In this paper, a comparative study between Ant Colony Optimization (ACO) and Genetic Algorithms (GA) is conducted for solving the Traveling Salesman Problem (TSP). The performance of these algorithms is evaluated based on the quality of the solution and the computational time required. The study involves different instances of TSP with varying sizes to assess the scalability of these algorithms. The results show that both ACO and GA can effectively solve TSP instances, but their performance varies depending on the problem size. ACO demonstrates better performance for smaller TSP instances, while GA is more effective for larger instances. The study also identifies the optimal parameter settings for each algorithm to achieve the best performance.

**Similar Documents**: This paper presents a detailed comparison between Ant Colony Optimization (ACO) and Genetic Algorithms (GA) in addressing the Traveling Salesman Problem (TSP). The evaluation focuses on solution quality and computational time, employing a range of TSP instances with different sizes to test the algorithms' robustness and adaptability. The findings reveal that both ACO and GA are capable of solving TSP effectively, albeit with distinct performance profiles. Specifically, ACO excels in handling smaller TSP instances, whereas GA outperforms in larger instances. Moreover, the study uncovers the ideal parameter configurations for each algorithm to optimize their performance, providing valuable insights for practitioners and researchers in the field of metaheuristic optimization.

The architecture, design, and implementation of two clock-free analog class D audio power amplifiers using 0.5 ¿m CMOS standard technology are introduced. The amplifiers are designed to consume significantly less power than former implementations. Both designs operate with a 2.7 V single voltage supply and deliver a maximum output power of 250 mW into an 8 ¿ speaker. The two class-D amplifiers are based on a hysteretic sliding mode controller, which avoids the complex task of generating the highly linear triangle carrier signal used in conventional architectures. The first design generates a two-level modulated signal, known as binary modulated amplifier (BMA); the second topology implements a three-level modulated signal, also called ternary modulated amplifier (TMA). The architectures and implementations are simple and compact, providing very low quiescent power consumption. Experimental results of the BMA/TMA yield an efficiency of 89/90% and a total harmonic distortion plus noise (THD+N) of 0.02/0.03%, respectively. The efficiency and linearity is comparable to state-of-the-art amplifiers but the static power consumption is less than one tenth of previous proposed architectures. Both class D amplifiers achieve a power supply rejection ratio greater than 75 dB at 217 Hz, and a signal-to-noise ratio (SNR) higher than 90 dB within the whole audio band. Each amplifier occupies less than 1.5 mm2.

A novel transformer feedback featuring wideband input matching and noise cancellation is proposed and demonstrated in a wideband differential LNA for software-defined-radio (SDR) applications. Implemented in 0.13μm CMOS with an area of 0.32mm2, the LNA prototype measures a wideband input matching S11 of less than -10dB from 1.2GHz to 6.6GHz and minimum NF of 1.8dB while consuming 11mA at 1.2V supply.

CMOS implementations for RF applications often employ technology modifications to reduce the silicon substrate loss at high frequencies. The most common techniques include the use of a high-resistivity substrate (/spl rho/>10 /spl Omega/-cm) or silicon-on-insulator (SOI) substrate and precise bondwire inductors. However, these techniques are incompatible with low-cost CMOS manufacture. This design demonstrates use of CMOS with a conventional low-resistivity epi-substrate and on-chip inductors for applications above 10 GHz.

An ultra-low power wake-up receiver for body channel communication (BCC) is implemented in 130 nm CMOS process. The proposed wake-up receiver uses the injection-locking ring oscillator (ILRO) to replace the RF amplifier with low power consumption. Through the ILRO, the frequency modulated input signal is amplified to the full swing rectangular signal directly demodulated by the following low power PLL-based FSK demodulator. In addition, the energy-efficient BCC link mitigates the sensitivity and selectivity requirements for the receiver, which significantly reduces the power consumption. Furthermore, the auto frequency calibrator (AFC) is adopted to compensate the free running frequency of the ring oscillator which is caused by temperature variation and leakage current. The AFC reuses the PLL-based demodulator to periodically set the free running frequency to the desired frequency without any area overhead. As a result, the proposed wake-up receiver achieves a sensitivity of -62.7 dBm at a data rate of 200 kbps while consuming only 37.5 μW from the 0.7 V supply.

Design for Reliability of Low-voltage, Switched-capacitor Circuits by Andrew Masami Abo Doctor of Philosophy in Engineering University of California, Berkeley Professor Paul R. Gray, Chair Analog, switched-capacitor circuits play a critical role in mixed-signal, analogto-digital interfaces. They implement a large class of functions, such as sampling, filtering, and digitization. Furthermore, their implementation makes them suitable for integration with complex, digital-signal-processing blocks in a compatible, low-cost technology–particularly CMOS. Even as an increasingly larger amount of signal processing is done in the digital domain, this critical, analogto-digital interface is fundamentally necessary. Examples of some integrated applications include camcorders, wireless LAN transceivers, digital set-top boxes, and others. Advances in CMOS technology, however, are driving the operating voltage of integrated circuits increasingly lower. As device dimensions shrink, the applied voltages will need to be proportionately scaled in order to guarantee long-term reliability and manage power density. The reliability constraints of the technology dictate that the analog circuitry operate at the same low voltage as the digital circuitry. Furthermore, in achieving low-voltage operation, the reliability constraints of the technology must not be violated. This work examines the voltage limitations of CMOS technology and how analog circuits can maximize the utility of MOS devices without degrading relia-

Developing next-generation cellular technology (5G) in the mm-wave bands will require low-cost phased-array transceivers [1]. Even with the benefit of beamforming, due to space constraints in the mobile form-factor, increasing TX output power while maintaining acceptable PA PAE, LNA NF, and overall transceiver power consumption is important to maximizing link budget allowable path loss and minimizing handset case temperature. Further, the phased-array transceiver will need to be able to support dual-polarization communication. An IF interface to the analog baseband is desired for low power consumption in the handset or user equipment (UE) active antenna and to enable use of arrays of transceivers for customer premises equipment (CPE) or basestation (BS) antenna arrays with a low-loss IF power-combining/splitting network implemented on an antenna backplane carrying multiple tiled antenna modules.

In this letter, a slotline to substrate integrated waveguide transition is proposed for the development of substrate integrated circuits. The insertion loss of the back-to-back transition is less than 1 dB from 8.7 to 9.0 GHz. With this transition, a planar magic-T is studied and designed. Measured results indicate a very good performance of the fabricated magic-T is observed within the experimental frequency range of 8.4-9.4 GHz. The amplitude and phase imbalances are less than 0.2 dB and 1.5deg, respectively.

In this paper a design and comparison between a fully differential RC Miller compensated CMOS op-amp and conventional op-amp is presented. High gain enables the circuit to operate efficiently in a closed loop feedback system, whereas high bandwidth makes it suitable for high speed applications. A novel RC Miller compensation technique is used to optimize the parameters of gain and bandwidth for high speed applications are illustrated in this research work. The design is also able to address any fluctuation in supply or dc input voltages and stabilizes the operation by nullifying. The design is implemented on TSMC 0.18 m CMOS process at 3.3 V as supply voltage under room temperature 27 C. The simulated result shows that a unity gain bandwidth of 136.8 MHz with a high gain of 92.27 dB is achieved for the proposed op-amp circuit. The total areas of the layouts are 0.000158 mm and 0.000532 mm for conventional and proposed respectively. Key wrods: Two-Stage Op-amp, fully differential, high gain, high bandwidth

Recent advances in MEMS-based oscillators have resulted in their proliferation in timing applications that were once exclusive to quartz-based devices [1]. For applications requiring low phase noise - e.g., cellular, GPS and high-speed serial links - one possible approach is to bias the MEMS resonator at a higher DC voltage to reduce its motional impedance and increase signal energy [2]. Realizing high-voltage charge pumps in bulk CMOS technology is limited by the breakdown voltage of the well/substrate diodes shown in Fig. 23.8.1(a) and Fig. 23.8.1(b). This breakdown limit is even lower with technology scaling and is <;10V in a 22nm CMOS node. Systems with high-voltage requirements often resort to older, high-voltage-tolerant nodes or exotic technologies that limit MEMS integration into SoCs. This work demonstrates a charge pump design in 65nm technology with a three-fold increase in the output voltage range. Highvoltage tolerance is enabled by the proposed well-biasing arrangement and oxide isolation. The pump achieves 34V output by using three different charge pump cells that tradeoff achievable voltage range and power efficiency to achieve a peak efficiency of 38%. Additionally, finger capacitors are optimized to ensure reliability while maintaining efficiency.

A 1 V low voltage delta-sigma fractional-N frequency divider for multi-band (780/868/915 MHz and 2.4 GHz) WSN frequency synthesizers is presented. The frequency divider consists of a dual-modulus prescaler, a pulse-swallow counter and a delta-sigma modulator. The high-speed and low-voltage phase-switching dualmodulus prescaler is used in the frequency divider. Low threshold voltage transistors are applied to overcome low voltage supply and forward phase-switching technique is adopted to prevent glitches. The modified deltasigma modulator with long output sequence length and less spurs is adopted to minimize the fractional spurs. The frequency divider is designed in 0.18 μm TSMC RF CMOS technology under 1 V supply instead of the standard 1.8 V supply. The total chip area is 1190 μm × 485 μm including I/O pads. The post simulation results show the frequency divider operates normally over a wide range of 1.3-5.0 GHz and the core circuit (without test buffers) consumes 2.3 mW. Copyright © 2013 IFSA.


Question: A fully integrated 5-GHz full PMOS low-phase-noise LC voltage-controlled oscillator.

This paper offers an in-depth examination of phase noise characteristics in two types of inductorless CMOS oscillators. Through a primary analysis of a linear oscillatory system, a novel noise shaping function is derived, alongside a fresh interpretation of the quality factor, Q. A linear model is applied to CMOS ring oscillators to estimate their phase noise, revealing three distinct phase noise phenomena: additive noise, high-frequency multiplicative noise, and low-frequency multiplicative noise. These phenomena are systematically analyzed and mathematically described. Using the same principles, a CMOS relaxation oscillator is similarly scrutinized. The paper also delves into the methodologies and challenges associated with time-domain noise simulation. To validate the theoretical predictions, two experimental oscillators were fabricated using a 0.5m CMOS technology. The theoretical phase noise values for a 2-GHz ring oscillator and a 900-MHz relaxation oscillator, measured at a 5 MHz offset, are found to align with empirical results within an error margin of approximately 4 dB. This study underscores the intricate relationship between design parameters and phase noise in CMOS oscillators, offering valuable insights for the development of high-performance oscillators.

Multi-phase converters have become a topic of great interest due to the high output power capacity and output ripple cancellation effect. They are even more beneficial to nowadays high-frequency fully integrated converters with output capacitor integrated on-chip. As one of the dominant chip area consumers, reducing the size of the on-chip decoupling capacitors directly leads to cost down. It is reported that a 5× capacitor area reduction can be achieved with a four-phase converter compared to a single-phase one [1]. However, the penalty is obvious. Every extra phase comes with an inductor, which is also counted as cost and becomes more dominant with increase in the number of phases.

A low-distortion third-order class-D amplifier that is fully integrated into a 0.18-μ m CMOS process was designed for direct battery hookup in a mobile application. A class-D amplifier for direct battery hookup must have a sufficiently high power supply rejection ratio (PSRR) in preparation for noise, such as when a global system for mobile communications (GSM) bursts ripples through the system power line. This amplifier has a high PSRR of 88 dB for 217-Hz power supply ripples, using a third-order loop filter. System performance and stability are improved by applying the design technique of input-feedforward delta-sigma (ΔΣ) modulators to the pulse-width modulation (PWM) class-D amplifier. A filterless method that can remove the external LC filter is employed, which offers great advantages in terms of PCB space and system cost. This amplifier achieves a power efficiency of 85.5% while delivering an output power of 750 mW into an 8-Ω load from a 3.7-V supply voltage. Maximum achieved output power at 1% total harmonic distortion plus noise (THD+N) from a 4.9-V supply voltage into an 8-Ω load is 1.15 W. This class-D amplifier is designed to have a broad operational range of 2.7-4.9 V for the direct use of mobile phone battery power. It has a total area of 1.01 mm2 and achieves a THD+N of 0.018%.

CMOS transmit-receive (T/R) switches have been integrated in a 0.18-/spl mu/m standard CMOS technology for wireless applications at 2.4 and 5.2 GHz. This switch design achieves low loss and high linearity by increasing the substrate impedance of a MOSFET at the frequency of operation using a properly tuned LC tank. The switch design is asymmetric to accommodate the different linearity and isolation requirements in the transmit and receive modes. In the transmit mode, the switch exhibits 1.5-dB insertion loss, 28-dBm power, 1-dB compression point (P/sub 1dB/), and 30-dB isolation, at 2.4 and 5.2 GHz. In the receive mode, the switch achieves 1.6-dB insertion loss, 11.5-dBm P/sub 1dB/, and 15-dB isolation, at 2.4 and 5.2 GHz. The linearity obtained in the transmit mode is the highest reported to date in a standard CMOS process. The switch passes the 4-kV Human Body Model electrostatic discharge test. These results show that the switch design is suitable for narrow-band applications requiring a moderate-high transmitter power level (<1 W).

This paper reports the design and analysis of 21-29-GHz CMOS low-noise amplifier (LNA), balun and mixer in a standard 0.18-μm CMOS process for ultra-wideband automotive radar systems. To verify the proposed LNA, balun, and mixer architectures, a simplified receiver front-end comprising an LNA, a double-balanced Gilbert-cell-based mixer, and two Marchand baluns was implemented. The wideband Marchand baluns can convert the single RF and local oscillator (LO) signals to nearly perfect differential signals over the 21-29-GHz band. The performance of the mixer is improved with the current-bleeding technique and a parallel resonant inductor at the differential outputs of the RF transconductance stage. Over the 21-29-GHz band, the receiver front-end exhibits excellent noise figure of 4.6±0.5 dB, conversion gain of 23.7±1.4 dB, RF port reflection coefficient lower than -8.8 dB, LO-IF isolation lower than -47 dB, LO-RF isolation lower than -55 dB, and RF-IF isolation lower than -35.5 dB. The circuit occupies a chip area of 1.25×1.06 mm2, including the test pads. The dc power dissipation is only 39.2 mW.

The digital low dropout regulator (D-LDO) has drawn significant attention recently for its low-voltage operation and process scalability. However, the tradeoff between current efficiency and transient response speed has limited its applications. In this brief, a coarse-fine-tuning technique with burst-mode operation is proposed to the D-LDO. Once the voltage undershoot/ overshoot is detected, the coarse tuning quickly finds out the coarse control word in which the load current should be located, with large power MOS strength and high sampling frequency for a fixed time. Then, the fine-tuning, with reduced power MOS strength and sampling frequency, regulates the D-LDO to the desired output voltage and takes over the steady-state operation for high accuracy and current efficiency. The proposed D-LDO is verified in a 65-nm CMOS process with a 0.01-mm2 active area. The measured voltage undershoot and overshoot are 55 and 47 mV, respectively, with load steps of 2 to 100 mA with a 20-ns edge time. The quiescent current is 82 μA, with a 0.43-ps figure of merit achieved. Moreover, the reference tracking speed is 1.5 V/μs.

In this letter, a broadband linear and efficient power amplifier for base-stations in long-term evolution (LTE) applications is designed, fabricated, and experimentally verified, employing Cree's CGH40010F GaN HEMT. A novel method of baseband, fundamental and harmonic impedances control is used to provide high linearity and efficiency across a broad bandwidth. When producing a two-tone carrier-to-intermodulation ratio (C/I) of 30 dBc, the circuit has demonstrated a two-tone power added efficiency (PAE) between 45%-60% across the frequency range from 1.6 to 2.6 GHz while delivering 36.0-38.5 dBm average output power. For a single-carrier 20 MHz LTE signal with a peak-to-average ratio (PAR) of 6.5 dB, a measured high PAE of 40%-55% can be achieved at an average output power of 35.3-37.5 dBm with an adjacent channel leakage ratio (ACLR) of about -30 dBc from 1.6 to 2.6 GHz.

In this paper, an ultra-wideband (UWB) common gate low-noise amplifier (LNA) with gm-boosted and noise-cancelling techniques is presented In this scheme we utilize gm-boosted stage for cancelling the noise of matching device. The bandwidth extension and flat gain are achieved by using of series and shunt peaking techniques. Simulated in .13 um Cmos technology, the proposed LNA achieved 2.38-3.4dB NF and S11 less than -11dB in the 3.1-10.6 GHz band Maximum power gain(S21) is 11dB and -3dB bandwidth is 1.25-11.33 GHz. The power consumption of LNA is 5.8mW.

When low ripple is required from a switched mode dc-dc converter, dissipative active filters offer an alternative to passive LC and coupled inductor filters. Analytical and experimental results are presented for a simple active ripple filter. The filter employs a pair of current transformers as sensors for feedforward and feedback control and two metal-oxide-semiconductor field-effect transistors (MOSFETs) as cancellation current drivers. Measurements demonstrate good ripple attenuation up to 5 MHz, more than 70 dB being obtained at 100 kHz, the switching frequency of a test converter. The overall efficiency was measured as 95%, with room for further improvement. The filter is suitable for input and output smoothing in dc-dc converters for aerospace and other critical applications.

A 45GHz Doherty power amplifier is implemented in 45nm SOI CMOS. Two-stack FET amplifiers are used as main and auxiliary amplifiers, allowing a supply voltage of 2.5V and high output power. The use of slow-wave coplanar waveguides (CPW) improves the PAE and gain by approximately 3% and 1dB, and reduces the die area by 20%. This amplifier exhibits more than 18dBm saturated output power, with peak power gain of 7dB. It occupies 0.64mm2 while achieving a peak PAE of 23%; at 6dB back-off the PAE is 17%.

This paper describes the first 32 kHz low-power MEMS-based oscillator in production. The primary goal is to provide a small form-factor oscillator (1.5 × 0.8 mm 2 ) for use as a crystal replacement in space-constrained mobile devices. The oscillator generates an output frequency of 32.768 kHz and its binary divisors down to 1 Hz. The frequency stability over the industrial temperature range (-40 °C to 85 °C) is ±100 ppm as an oscillator (XO) or ±3 ppm with optional calibration as a temperature compensated oscillator (TCXO). Supply currents are 0.9 μA for the XO and 1.0 μA for the TCXO at supply voltages from 1.4 V to 4.5 V. The MEMS resonator is a capacitively-transduced tuning fork at 524 kHz. The circuitry is fabricated in 180 nm CMOS and includes low power sustaining circuit, fractional-N PLL, temperature sensor, digital control, and low swing driver.