Question: A streamlined design methodology for Dadda multipliers utilizing compression techniques.

The Imminent Challenge to Moore's Law: Thermal Noise and the Future of Micro and Nano Electronics

The remarkable advancements in computing technology, characterized by the exponential increase in memory capacity and clock speeds, have profoundly influenced modern life. This rapid progress is often attributed to Moore's law, a principle that predicts the doubling of transistors on a microchip every two years, leading to a significant decrease in cost and increase in performance. However, the physical constraints imposed by thermodynamics are threatening to disrupt this trajectory in the near future, potentially leading to the end of Moore's law within the next 6 to 8 years, or even sooner.

A key factor contributing to this potential disruption is the escalating thermal noise voltage, also known as Johnson-Nyquist noise, which becomes more pronounced as the characteristic capacitances decrease with miniaturization. This phenomenon poses a significant challenge, especially when coupled with the necessity to lower supply voltages in order to manage power dissipation amidst increasing clock frequencies. The interplay between these factors has the potential to abruptly halt the exponential growth predicted by Moore's law, marking a critical turning point in the development of micro and nano electronics.

This looming crisis necessitates a reevaluation of current design strategies and the exploration of alternative approaches to overcome the limitations imposed by thermal noise. Innovations in chip design, material science, and cooling technologies will be crucial in sustaining the progress in computing technology and preventing the premature demise of Moore's law. The scientific community must address this impending challenge to ensure the continued advancement of micro and nano electronics, safeguarding the future of technology and its impact on the economy.

The implications of this impending limitation are far-reaching, affecting not only the technology sector but also the broader economy that has become increasingly dependent on the exponential growth of computing power. It is imperative that solutions are sought to mitigate the effects of thermal noise and to continue the march of progress in micro and nano electronics, preserving the benefits that Moore's law has bestowed upon society.

We show in this paper that multi-layer dependability is an indispensable way to cope with the increasing amount of technology-induced dependability problems that threaten to proceed further scaling. We introduce the definition of multi-layer dependability and present our design flow within this paradigm that seamlessly integrates techniques starting at circuit layer all the way up to application layer and thereby accounting for ASIC-based architectures as well as for reconfigurable-based architectures. At the end, we give evidence that the paradigm of multi-layer dependability bears a large potential for significantly increasing dependability at reasonable effort.

The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instruction-level parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the most important market for high-performance servers, the above trends emphasize the need to consider alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors targeted at commercial servers.
 This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multi-processing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.

This paper presents a hardware design of context-based adaptive binary arithmetic coding (CABAC) for the emerging High efficiency video coding (HEVC) standard. While aiming at higher compression efficiency, the CABAC in HEVC also invests a lot of effort in the pursuit of parallelism and reducing hardware cost. Simulation results show that our design processes 1.18 bins per cycle on average. It can work at 357 MHz with 48.940K gates targeting 0.13 μm CMOS process. This processing rate can support real-time encoding for all sequences under common test conditions of HEVC standard conforming to the main profile level 6.1 of main tier or main profile level 5.1 of high tier.

This thesis is dedicated to symmetric cryptographic algorithms. The major focus of the work is on block ciphers themselves as well as on hash functions and message authentication codes based on block ciphers. Three main approaches to the cryptanalysis of symmetric cryptographic algorithms are pursued. First, several block cipher constructions are analyzed mathematically using statistical cryptanalysis. Second, practical attacks on real-world symmetric cryptosystems are considered. Finally, novel cryptanalytic techniques using side-channel leakage are studied with applications to block ciphers and message authentication codes. Differential and linear cryptanalyses are well-known statistical attacks on block ciphers. This thesis studies the security of unbalanced Feistel networks with contracting MDS diffusion with respect to differential and linear cryptanalysis. Upper bounds on the differential trail probabilities and linear probabilities of linear trails in such constructions are proven. It is shown that such unbalanced Feistel networks can be highly efficient and are comparable to many known balanced Feistel network constructions with respect to differential and linear cryptanalysis. Ultra-lightweight substitution-permutation networks with diffusion layers based on the co-design of S-boxes and bit permutations are proposed. This results in lightweight block ciphers and block cipher based compression functions for hash functions designed and analyzed. These constructions have very small footprint and can be efficiently implemented on the majority of RFID tags This work also studies practical attacks on real-world symmetric cryptographic systems. Attacks are proposed on the KeeLoq block cipher and authentication systems widely used for automotive access control and component identification. Cryptanalysis of the A5/2 stream cipher used for protecting GSM connections worldwide is performed. Linear slide attacks on KeeLoq are proposed resulting in the fastest known attack on the KeeLoq block cipher working for all keys. Severe weaknesses of the KeeLoq key management are identified. The KeeLoq real-world authentication protocols for access control and component identification are also analyzed. A special-purpose hardware architecture for attacking A5/2 is developed that allows for real-time key recovery within one second for different GSM channels. This engine is based on an optimized hardware algorithm for fast Gaussian elimination over binary finite fields.

This paper presents a recursive digital low-dropout (RLDO) regulator that improves response time, quiescent power, and load regulation dynamic range over prior digital LDO designs by 1–2 orders of magnitude. The proposed RLDO enables a practical digital replacement to analog LDOs by using an SAR-like binary search algorithm in a coarse loop and a sub-LSB pulse width modulation duty control scheme in a fine loop. A proportional-derivative compensation scheme is employed to ensure stable operation independent of load current, the size of the output decoupling capacitor, and clock frequency. Implemented in 0.0023 mm2 in 65 nm CMOS, the 7-bit RLDO achieves, at a 0.5-V input, a response time of 15.1 ns with a figure of merit of 199.4 ps, along with stable operation across a 20 000 $\times $  dynamic load range.

This paper presents a recurrent neural circuit for solving quadratic programming problems. The objective is tominimize a quadratic cost function subject to linearconstraints. The proposed circuit employs non-linearfeedback, in the form of unipolar comparators, to introducetranscendental terms in the energy function ensuring fastconvergence to the solution. The proof of validity of the energy function is also provided. The hardware complexity of the proposed circuit comparesfavorably with other proposed circuits for the same task. PSPICE simulation results arepresented for a chosen optimization problem and are foundto agree with the algebraic solution.

The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 μm2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.

Approximate computing has been recognized as an effective low power technique for applications with intrinsic error tolerance, such as image processing and machine learning. Existing efforts on this front are mostly focused on approximate circuit design, approximate logic synthesis or processor architecture approximation techniques. This work aims at how to make good use of approximate circuits at system and block level. In particular, approximation aware scheduling, functional unit allocation and binding algorithms are developed for data intensive applications. Simple yet credible error models, which are essential for precision control in the optimizations, are investigated. The algorithms are further extended to include bitwidth optimization in fixed point computations. Experimental results, including those from Verilog simulations, indicate that the proposed techniques facilitate desired energy savings under latency and accuracy constraints.

Scan compression is widely used in high-volume testing of complex integrated circuits. With an increase in design complexity, the increased density of unknown (X) values from output responses reduces compression efficiency. In order to effectively block X values and maximize the effectiveness of test compression, a scan-compression architecture has recently been proposed, in which deterministic test patterns can be loaded into selected scan cells by controlling the initial state of the pseudo-random pattern generator (PRPG). A careful selection of the PRPG length is however essential to reduce test cost. We propose an optimization method based on support-vector regression to determine the PRPG length for test-cost reduction in a given scan-compression architecture. A correlation-based feature selection methodology is also proposed to reduce the amount of data needed for the accurate selection of the PRPG length. Experimental results on industrial designs highlight the effectiveness of the proposed method.

The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realization of fast and secure implementations of cryptographic algorithms. Under this work, such an implementation has been done for Advanced Encryption Standard (AES) on fast, efficient and low power Field Programmable Gate Arrays (FPGAs) whereby computational intensive cryptographic processes are offloaded from the main processor thus results in achieving highspeed secure wireless connectivity. The dedicated resources of Spartan-3 FPGAs have been effectively utilized to develop wider logic function which minimizes the critical paths by confining logic to single Configurable Logic Block (CLB), thus improving the performance, density and power consumption of the design. The resultant design consumes only 4 Block RAMs and 487 Slices to fit both AES cores and its key scheduling.


Question: An effective design strategy for Dadda multipliers utilizing compression techniques.

This document investigates the design and performance of low-power, higher-order compressors, specifically focusing on 4-2 and 5-2 compressor units, which serve as fundamental components in binary multiplier circuits. An in-depth comparison of multiple circuit architectures for 4-2 compressors is conducted, evaluating their respective delay and power consumption characteristics. Simulation results obtained using HSPICE software are utilized to assess these designs. Building upon this analysis, the paper introduces a novel 5-2 compressor circuit, which boasts a 12% reduction in delay and a 37% decrease in power consumption, representing significant advancements in efficiency for binary multiplier design.

**Question**: A Comparative Study of Evolutionary Algorithms for the Vehicle Routing Problem

**Documents**: A new ant colony optimization algorithm for the vehicle routing problem
A new ant colony optimization (ACO) algorithm is proposed for the vehicle routing problem (VRP) with time windows. In this algorithm, the ants construct their solutions by using a combination of pheromone information and heuristic information. The pheromone update rule is based on the best solution found so far. The algorithm is tested on a set of benchmark instances from the literature and compared with other well-known ACO algorithms. The computational results show that the proposed algorithm is able to find good solutions for the VRP with time windows.

**Similar Documents**: This paper presents an innovative ant colony optimization (ACO) algorithm tailored to address the vehicle routing problem (VRP) with time windows. The proposed algorithm utilizes a dual approach, integrating pheromone information with heuristic data to guide the ants in constructing their solutions. A distinctive feature of this algorithm is its pheromone update mechanism, which is contingent upon the best solution identified during the optimization process. To validate its efficacy, the algorithm is subjected to a series of benchmark instances, drawn from established literature, and its performance is benchmarked against other prominent ACO algorithms. The empirical findings highlight the algorithm's capability to efficiently generate high-quality solutions for VRPs with time window constraints.

Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates have appeared in the literature recently. These designs relied on the intuition and cleverness of the designers, without involving formal design procedures. Hence, a formal design procedure for realising a minimal transistor CMOS pass network XOR-XNOR cell, that is fully compensated for threshold voltage drop in MOS transistors, is presented. This new cell can reliably operate within certain bounds when the power supply voltage is scaled down, as long as due consideration is given to the sizing of the MOS transistors during the initial design step. A low transistor count full adder cell using the new XOR-XNOR cell is also presented.

As the precision of the capacitance ratios among binary-weighted capacitors is the key to accuracy/performance of charge-scaling digital-to-analog converters, it is very important to generate a highly matched common-centroid layout with minimum routing-induced parasitics. However, most of the previous works only focused on common-centroid placement optimization with the consideration of random and systematic mismatch. This paper introduces a novel common-centroid capacitor layout generation approach to minimize the parasitic impact on circuit accuracy/performance. Experimental results show that, compared with the manual layout, the layout generated by the presented approach can achieve even smaller layout area and better circuit accuracy/performance within much shorter time.

A comprehensive analysis of a multistage Doherty amplifier, which can be used to achieve higher efficiency at a lower output power level compared to the classical Doherty amplifier, is presented. Generalized design equations that explain the operation of a three-stage Doherty amplifier, which can be easily extended to an N-stage Doherty amplifier, are derived. In addition, the optimum device periphery, which minimizes AM-AM distortion for perfect Doherty amplifier operation, is analyzed. For the first time, a multistage Doherty power amplifier that meets wide-band code-division multiple-access (WCDMA) requirements is demonstrated. The designed power amplifier exhibits a power-added efficiency (PAE) of 42% at 6-dB output power backoff and 27% at 12-dB output power backoff. These PAEs are more than 2/spl times/ and 7/spl times/ better, respectively, than that of a single-stage linear power amplifier at the same output power backoff levels. The power amplifier is capable of delivering up to 33 dBm of output power, and has a maximum adjacent channel power leakage ratio of -35 and -47 dBc at 5- and 10-MHz offset, respectively. To the best of the authors' knowledge, these represent the best reported results of a Doherty amplifier for WCDMA application in the 1.95-GHz band to date.

The “split ADC” architecture enables fully digital calibration and correction of nonlinearity errors due to capacitor mismatch in a successive approximation (SAR) ADC. The die area of a single ADC design is split into two independent halves, each converting the same input signal. Total area and power is unchanged, resulting in minimal increase in analog complexity. For each conversion, the half-sized ADCs generate two independent outputs which are digitally corrected using estimates of capacitor mismatch errors for each ADC. The ADC outputs are averaged to produce the ADC output code. The difference of the two outputs is used in a background calibration algorithm which estimates the error in the correction parameters. Any nonzero difference drives an LMS feedback loop toward zero difference which can only occur when the average error in each correction parameter is zero. A novel segmentation and shuffling scheme in the SAR capacitive DAC enables background calibration for a wide range of input signals including dc. Simulation of a 16 bit 1 Msps SAR ADC in 180 nm CMOS shows calibration convergence within 200 000 samples.

To save resources for Internet of Things (IoT) devices, a proposed approach segments operands and corresponding basic arithmetic operations that can be carried out by approximate function units for almost all applications. The approach also increases the security of IoT devices by hiding information for IP watermarking, digital fingerprinting, and lightweight encryption.

This work reports on the design and test of a CMOS-based Switched Capacitor (SC) DC-DC conversion integrated circuit (IC) for the point-of-load (POL) application conventionally addressed with the buck converter. A 12V-to-1.5V converter is fabricated in a 0.18µm technology, with an active die area of 3mm2. There is a significant reduction in printed circuit board (PCB) footprint, passive component height and cost when compared to surveyed buck converters. The converter achieves 93% peak efficiency and an efficiency of 80% over an output current range of 7mA to 1A. This work demonstrates the vast potential of SC converters for wide-range voltage conversion in deep-submicron CMOS technologies, when cost and efficiency are of critical importance.

A highly digital two-stage fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loop (PLL) architecture utilizing a first-order 1-bit <inline-formula> <tex-math notation="LaTeX">$ \Delta \!\Sigma $ </tex-math></inline-formula> frequency-to-digital converter (FDC) is proposed and implemented in a 65nm CMOS process. Performance of the first-order 1-bit <inline-formula> <tex-math notation="LaTeX">$ \Delta \!\Sigma $ </tex-math></inline-formula> FDC is improved by using a phase interpolator-based fractional divider that reduces phase quantizer input span and by using a multiplying delay-locked loop that increases its oversampling ratio. We also describe an analogy between a time-to-digital converter (TDC) and a <inline-formula> <tex-math notation="LaTeX">$ \Delta \!\Sigma $ </tex-math></inline-formula> FDC followed by an accumulator that allows us to leverage the TDC-based PLL analysis techniques to study the impact of <inline-formula> <tex-math notation="LaTeX">$ \Delta \!\Sigma $ </tex-math></inline-formula> FDC characteristics on <inline-formula> <tex-math notation="LaTeX">$ \Delta \!\Sigma $ </tex-math></inline-formula> FDC-based fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> PLL (FDCPLL) performance. Utilizing proposed techniques, a prototype PLL achieves 1 MHz bandwidth, −101.6 dBc/Hz in-band phase noise, and <inline-formula> <tex-math notation="LaTeX">$ {\textrm {1.22 ps}_{\textrm {rms}}}$ </tex-math></inline-formula> (1 kHz–40 MHz) jitter while generating 5.031GHz output from 31.25MHz reference clock input. For the same output frequency, the stand-alone second-stage fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> FDCPLL achieves 1MHz bandwidth, −106.1dBc/Hz in-band phase noise, and <inline-formula> <tex-math notation="LaTeX">$ {\textrm {403 fs}_{\textrm {rms}}}$ </tex-math></inline-formula> jitter with a 500MHz reference clock input. The two-stage PLL consumes 10.1mW power from a 1V supply, out of which 7.1 mW is consumed by the second-stage FDCPLL.

An improved oped for generating +40 voltage multiplier technique has been develV internally in p-channel MNOS integrated circuits to enrtble them to be operated from standard +5and : 12-V supply rails. With this technique, the multiplication efficiency and current driving capabtilty are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 ~m X 240 pm. It is operated with a clock frequency of 1 MHz and can supManuscript received December 9, 1975; revised February 18, 1976. This paper is based on part of a presentation entitled “A non-volatile MNOS quad-latch,” which was presented at the First European SolidState Circuits Conference, Canterbury, England, September 2-5, 1975. The author is with the Allen Clark Research Centre, The Plessey Company Ltd., CasweJl, Towcester, Northants., England. MNOS Voltage ply a maximum load current of about 10 NA. The output impedance is 3.2 Mfl. INTRODUCTION ALTHOUGH MNOS technology is now well established for fabricating nonvolatile memory circuits, the relatively high potentials necessary to write or erase information, typically 30-40 V, are an obvious disadvantage. In many applications, the need to generate these voltages has prevented the use of MNOS devices being economically viable, especially when only a few bits of nonvolatile data are required. To overcome this problem, a method of on-chip high-voltage generation using a new voltage multiplier technique has been developed, enabling MNOS circuits to be operated with standard DICKSON: ON-CHIP HIGH-VOLTAGEGENERATION 375

This paper presents a 3rd-order continuous time delta-sigma modulator for a worldwide digital TV-receiver whose SNDR is 69.8 dB. An ultimate low power tuning system using RC-relaxation oscillator is developed in order to achieve high yield against PVT variations. A 3rd-order modulator with modified single opamp resonator contributes to cost reduction by realizing very compact circuit. The mechanism to occur 2nd-order harmonic distortion at current feedback DAC was analyzed and a reduction scheme of the distortion enabled the modulator to achieved FOM of 0.18 pJ/conv-step.

Deep neural networks (DNNs) continue to make significant advances, solving tasks from image classification to translation or reinforcement learning. One aspect of the field receiving considerable attention is efficiently executing deep models in resource-constrained environments, such as mobile or embedded devices. This paper focuses on this problem, and proposes two new compression methods, which jointly leverage weight quantization and distillation of larger networks, called “teachers,” into compressed “student” networks. The first method we propose is called quantized distillation and leverages distillation during the training process, by incorporating distillation loss, expressed with respect to the teacher network, into the training of a smaller student network whose weights are quantized to a limited set of levels. The second method, differentiable quantization, optimizes the location of quantization points through stochastic gradient descent, to better fit the behavior of the teacher model. We validate both methods through experiments on convolutional and recurrent architectures. We show that quantized shallow students can reach similar accuracy levels to state-of-the-art full-precision teacher models, while providing up to order of magnitude compression, and inference speedup that is almost linear in the depth reduction. In sum, our results enable DNNs for resource-constrained environments to leverage architecture and accuracy advances developed on more powerful devices.


Question: An effective design strategy for Dadda multipliers utilizing compression techniques.

This paper delves into the impact of power-supply noise on phase-locked loops (PLL) within radio frequency (RF) and mixed signal very large scale integration (VLSI) circuits, leading to timing jitter. An in-depth analysis of the timing jitter induced by power supply rail noise is provided. The study starts by introducing stochastic models for power supply noise in VLSI circuits, considering various levels of on-chip decoupling capacitance. Subsequently, the phase noise of the voltage-controlled oscillator (VCO) is calculated, relating it to the statistical characteristics of the supply noise. Ultimately, the PLL's timing jitter is forecasted as a reaction to the VCO's phase noise. To validate the theoretical framework, a PLL circuit was crafted using a 0.35μ CMOS process, and the mathematical model was applied to gauge the timing jitter. Experimental outcomes corroborate the precision of the proposed model, highlighting its relevance in understanding and mitigating jitter in PLL circuits.

The paper describes switched-capacitor dc-dc converters (charge pumps) suitable for on-chip, low-power applications. The proposed configurations are based on connecting two identical but opposite-phase SC converters in parallel, thus eliminating the need for separate bootstrap gate drivers. We focus on emerging very low-power VLSI applications such as batterypowered or self-powered signal processors where high power conversion efficiency is important and where power levels are in the milliwatt range. Conduction and switching losses are considered to allow design optimization in terms of switching frequency and component sizes. Open-loop and closed-loop operation of an experimental, fully integrated, 10MHz voltage doubler is described. The doubler has 2V or 3V input and generates 3.3V or 5V output at up to 5mW load. The converter circuit fabricated in a standard 1.2μ CMOS technology takes 0.7mm of the chip area.

This paper describes an integrated frequency multiplier, implemented as a Gilbert cell based frequency doubler in a 130 nm SiGe BiCMOS technology. The circuit demonstrates a 3 dB bandwidth of 97–134GHz with peak output power of 1 dBm for 1 dBm input power. The fundamental suppression, measured at the single-ended output, is better than 21 dBc while the frequency doubler consumes 69mW from a 3.3V supply. The doubler is preceded by a differential amplifier functioning as an active balun to generate a differential signal for the Gilbert cell.

This paper presents a new design of three-valued logic gates on the basis of carbon nanotube transistors. Next, the proposed circuit is compared with the existing models of circuits. The simulation results, using HSPICE indicate that the proposed model outperform the existing models in terms of power and delay. Moreover, using load-transistor results in 48.23% reductions in terms of power-delay-product (PDP) compared with the best model ever observed. Furthermore, the implementation of ternary arithmetic circuits such as half adder and multiplier using load-transistor has been investigated. An added common term between Sum and Carry output in half-adder (HA) and Carry and Product output in lower multiplier (MUL) has been used in arithmetic circuits. Considering the fact that a better proposal with higher performance has been utilized for the implementation of three-valued gates, our model results in the reduction of 9.95% and 23.87% PDP in HA and MUL respectively compared with the best models observed.

An improved oped for generating +40 voltage multiplier technique has been develV internally in p-channel MNOS integrated circuits to enrtble them to be operated from standard +5and : 12-V supply rails. With this technique, the multiplication efficiency and current driving capabtilty are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 ~m X 240 pm. It is operated with a clock frequency of 1 MHz and can supManuscript received December 9, 1975; revised February 18, 1976. This paper is based on part of a presentation entitled “A non-volatile MNOS quad-latch,” which was presented at the First European SolidState Circuits Conference, Canterbury, England, September 2-5, 1975. The author is with the Allen Clark Research Centre, The Plessey Company Ltd., CasweJl, Towcester, Northants., England. MNOS Voltage ply a maximum load current of about 10 NA. The output impedance is 3.2 Mfl. INTRODUCTION ALTHOUGH MNOS technology is now well established for fabricating nonvolatile memory circuits, the relatively high potentials necessary to write or erase information, typically 30-40 V, are an obvious disadvantage. In many applications, the need to generate these voltages has prevented the use of MNOS devices being economically viable, especially when only a few bits of nonvolatile data are required. To overcome this problem, a method of on-chip high-voltage generation using a new voltage multiplier technique has been developed, enabling MNOS circuits to be operated with standard DICKSON: ON-CHIP HIGH-VOLTAGEGENERATION 375

A high-speed and high-resolution comparator intended to be implemented in a 12 bit 100 MHz pipeline analog-to-digital converter (ADC) for frequency wireless local area network application is proposed. The designed comparator presents a rail-to-rail input range preamplifier without any capacitance required. This comparator with a novel architecture of output stage achieves very high speed at a low kickback noise. The simulation results using a 0.35 mum TSMC CMOS process technology show that this comparator exhibits a propagation delay of 2.8 ns and has a very high resolution for a rail-to-rail input signal range, while consumes only 1.0 mW of power with 5.0 V voltage supply.

We show in this paper that multi-layer dependability is an indispensable way to cope with the increasing amount of technology-induced dependability problems that threaten to proceed further scaling. We introduce the definition of multi-layer dependability and present our design flow within this paradigm that seamlessly integrates techniques starting at circuit layer all the way up to application layer and thereby accounting for ASIC-based architectures as well as for reconfigurable-based architectures. At the end, we give evidence that the paradigm of multi-layer dependability bears a large potential for significantly increasing dependability at reasonable effort.

We provide a tutorial on arithmetic coding, showing how it provides nearly optimal data compression and how it can be matched with almost any probabilistic model. We indicate the main disadvantage of arithmetic coding, its slowness, and give the basis of a fast, space-e cient, approximate arithmetic coder with only minimal loss of compression e ciency. Our coder is based on the replacement of arithmetic by table lookups coupled with a new deterministic probability estimation scheme. Index terms : Data compression, arithmetic coding, adaptive modeling, analysis of algorithms, data structures, low precision arithmetic. A similar version of this paper appears in Image and Text Compression, James A. Storer, ed., Kluwer Academic Publishers, Norwell, MA, 1992, 85{112. A shortened version of this paper appears in the proceedings of the International Conference on Advances in Communication and Control (COMCON 3), Victoria, British Columbia, Canada, October 16{18, 1991. Support was provided in part by NASA Graduate Student Researchers Program grant NGT{ 50420 and by a National Science Foundation Presidential Young Investigators Award grant with matching funds from IBM. Additional support was provided by a Universities Space Research Association/CESDIS associate membership. Support was provided in part by National Science Foundation Presidential Young Investigator Award CCR{9047466 with matching funds from IBM, by NSF research grant CCR{9007851, by Army Research O ce grant DAAL03{91{G{0035, and by the O ce of Naval Research and the Defense Advanced Research Projects Agency under contract N00014{91{J{4052ARPA Order No. 8225. Additional support was provided by a Universities Space Research Association/CESDIS associate membership.

To save resources for Internet of Things (IoT) devices, a proposed approach segments operands and corresponding basic arithmetic operations that can be carried out by approximate function units for almost all applications. The approach also increases the security of IoT devices by hiding information for IP watermarking, digital fingerprinting, and lightweight encryption.

We present an analog subsampling PLL based on a digital-to-time converter (DTC), which operates with almost no performance gap (176/198 fs RMS jitter) between the integer and the worst case fractional operation, achieving -246.6 dB FOM in the worst case fractional mode. The PLL is capable of two-point, 10 Mbit/s GMSK modulation with -40.5 dB EVM around a 10.24 GHz fractional carrier. The analog nonidealities-DTC gain, DTC nonlinearity, modulating VCO bank gain, and nonlinearity-are calibrated in the background while the system operates normally. This results in ~15 dB fractional spur improvement (from -41 dBc to -56.5 dBc) during synthesis and ~15 dB EVM improvement (from -25 dB to -40.5 dB) during modulation. The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them. We demonstrate state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.

This paper presents a reconfigurable, low offset, low noise and high speed dynamic clocked-comparator for medium to high resolution Analog to Digital Converters (ADCs). The proposed comparator reduces the input referred noise by half and shows a better output driving capability when compared with the previous work. The offset, noise and power consumption can be controlled by a clock delay which allows simple reconfiguration. Moreover, the proposed offset calibration technique improves the offset voltage from 11.6mV to 533μV at 1 sigma. A prototype of the comparator is implemented in 90nm 1P8M CMOS with experimental results showing 320μV input referred noise at 1.5GHz with 1.2V supply.


Question: An effective design strategy for Dadda multipliers utilizing compression techniques.

This paper conducts an in-depth performance analysis of 1-bit CMOS full adder cells, focusing on their efficiency in terms of power consumption. The adder cell is meticulously dissected into smaller components for detailed study and evaluation. Various designs for each component are devised, prototyped, and thoroughly simulated to understand their performance. The research culminates in the creation of twenty distinct 1-bit full adder cells, many of which are innovative circuit designs. These cells exhibit a range of characteristics including power consumption, speed, area usage, and driving capability. To validate the practical implications of these designs, they are integrated into two real-world circuit structures for simulation. The outcome of this study is a comprehensive library of full adder cells, providing circuit designers with a selection of options tailored to the specific requirements of their applications.

**Question**: An Efficient Design of Dadda Multiplier Using Compression Techniques

**Documents**: Design and Analysis of a Low Power Dadda Multiplier Using Hybrid Full Adder
A Dadda multiplier is designed and analyzed for low power applications using a hybrid full adder (HFA) in 0.18 μm CMOS technology. The hybrid full adder is designed by combining the features of carry select adder (CSA) and carry look ahead adder (CLA) for reducing the delay and power consumption. The proposed Dadda multiplier uses a new hybrid full adder which is designed by combining the features of carry select adder and carry look ahead adder. The proposed Dadda multiplier is designed using the standard cell library of 0.18 μm CMOS technology. The design is simulated using Hspice and the results are compared with the conventional Dadda multiplier. The proposed Dadda multiplier consumes less power and has less delay compared to the conventional Dadda multiplier.

**Similar Documents**: This paper presents the design and analysis of an efficient Dadda multiplier for low power consumption, utilizing a novel hybrid full adder (HFA) in 0.18 μm CMOS technology. The HFA is a fusion of the carry select adder (CSA) and carry look ahead adder (CLA) techniques, designed to minimize both delay and power usage. The Dadda multiplier, incorporating this innovative HFA, is constructed using the standard cell library of 0.18 μm CMOS technology. The design was simulated using Hspice, and the results were compared against a traditional Dadda multiplier. The outcomes

This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of subpipelining can be further explored. Furthermore, composite field arithmetic is employed to reduce the area requirements, and different implementations for the inversion in subfield GF(2/sup 4/) are compared. In addition, an efficient key expansion architecture suitable for the subpipelined round units is also presented. Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV1000 e-8 bg560 device in non-feedback modes, which is faster and is 79% more efficient in terms of equivalent throughput/slice than the fastest previous FPGA implementation known to date.

This paper presents a second-order /spl Delta//spl Sigma/ modulator for audio-band analog-to-digital conversion implemented in a 3.3-V, 0.5-/spl mu/m, single-poly CMOS process using metal-metal capacitors that achieves 98-dB peak signal-to-noise-and-distortion ratio and 105-dB peak spurious-free dynamic range. The design uses a low-complexity, first-order mismatch shaping 33-level digital-to-analog converter and a 33-level flash analog-to-digital converter with digital common-mode rejection and dynamic element matching of comparator offsets. These signal-processing innovations, combined with established circuit techniques, enable state-of-the art performance in CMOS technology optimized for digital circuits.

In the design of high speed Flash ADC selection of Thermometer to Binary decoder plays an important role. This paper describes different decoder topologies suitable for Flash ADCs. Comparative analysis between them is presented in terms of hardware required, propagation delay & power consumption. Result shows that fat tree & Mux based topologies are suitable for high speed conversions, but Mux based topology is effective in terms of power consumption. Presence of bubble error reduces output correction capability. In this paper advance scheme is proposed for correction of bubble error in Mux based decoder.

A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.

As silicon feature sizes decrease, more complex circui try arrays can now be contrived on a single die. This increase in the number of on-chip devices per unit area results in increased power dissipation per unit area. In order to meet certain power and operating temperature specifications, circuit design necessitates a focus on power efficiency, which is especially important in systems employing hundreds or thousands of instances of the same device. In large arrays, a slight increase in the power efficiency of a single component is heightened by the number of instances of the device in the system. This paper proposes a fully differential, low-power current-starving inverter-based amplifier topology designed in a commercial 0.18μm process. This design achieves 46dB DC gain and a 464 kHz uni ty gain frequency with a power consumption of only 145.32nW at 700mV power supply vol tage for ultra-low power, low bandwidth applications. Higher bandwidth designs are also proposed, including a 48dB DC gain, 2.4 MHz unity-gain frequency amplifier operating at 900mV wi th only 3.74μW power consumption.

Comparator is one of the most widely used building block for analog and mixed signal systems. For the implementation of high-performance CMOS A/D converters, low offset comparators are essential. In this paper, dynamic comparator offset is calculated to the extent of high accuracy. The offset so calculated has been reduced by the charge storage techniques to achieve an efficient design. In addition to the offset, propagation delay and power dissipation, being the important parameter of the comparator, has been analyzed. It is observed that offset voltage in the comparator has been reduced to 350μV for output offset storage technique and 400μV for input offset storage techniques from 91mV. In this paper, BPTM model has been used in analyze the dynamic comparator. KeywordsDynamic comparator, offset voltage, storage capacitor, input offset storage, output offset storage.

Current compression schemes for floating-point data commonly take fixed-precision values and compress them to a variable-length bit stream, complicating memory management and random access. We present a fixed-rate, near-lossless compression scheme that maps small blocks of 4d values in d dimensions to a fixed, user-specified number of bits per block, thereby allowing read and write random access to compressed floating-point data at block granularity. Our approach is inspired by fixed-rate texture compression methods widely adopted in graphics hardware, but has been tailored to the high dynamic range and precision demands of scientific applications. Our compressor is based on a new, lifted, orthogonal block transform and embedded coding, allowing each per-block bit stream to be truncated at any point if desired, thus facilitating bit rate selection using a single compression scheme. To avoid compression or decompression upon every data access, we employ a software write-back cache of uncompressed blocks. Our compressor has been designed with computational simplicity and speed in mind to allow for the possibility of a hardware implementation, and uses only a small number of fixed-point arithmetic operations per compressed value. We demonstrate the viability and benefits of lossy compression in several applications, including visualization, quantitative data analysis, and numerical simulation.

A 256 144-bit TCAM is designed in 0.18m CMOS. The proposed TCAM cell uses 4T static storage for increased density. The proposed match-line (ML) sense scheme reduces power consumption by minimizing switching activity of search-lines and limiting voltage swing of MLs. The scheme achieves a match-time of 3 ns and operates at a minimum supply voltage of 1.2 V.

This paper presents a digital nonlinearity calibration technique for ADCs with strong input–output discontinuities between adjacent codes, such as pipeline, algorithmic, and SAR ADCs with redundancy. In this kind of converter, the ADC transfer function often involves multivalued regions, where conventional integral-nonlinearity (INL)-based calibration methods tend to miscalibrate, negatively affecting the ADC’s performance. As a solution to this problem, this paper proposes a novel INL-based calibration which incorporates information from the ADC’s internal signals to provide a robust estimation of static nonlinear errors for multivalued ADCs. The method is fully generalizable and can be applied to any existing design as long as there is access to internal digital signals. In pipeline or subranging ADCs, this implies access to partial subcodes before digital correction; for algorithmic or SAR ADCs, conversion bit/bits per cycle are used. As a proof-of-concept demonstrator, the experimental results for a 1.2 V 23 mW 130 nm-CMOS pipeline ADC with a SINAD of 58.4 dBc (in nominal conditions without calibration) is considered. In a stressed situation with 0.95 V of supply, the ADC has SINAD values of 47.8 dBc and 56.1 dBc, respectively, before and after calibration (total power consumption, including the calibration logic, being 15.4 mW).

In emerging embedded applications such as wireless sensor networks, the key metric is minimizing energy dissipation rather than processor speed. Minimum energy analysis of CMOS circuits estimates the optimal operating point of clock frequencies, supply voltage, and threshold voltage according to A. Chandrakasan et al. (see ibid., vol.27, no.4, p.473-84, Apr. 1992). The minimum energy analysis shows that the optimal power supply typically occurs in subthreshold (e.g., supply voltages that are below device thresholds). New subthreshold logic and memory design methodologies are developed and demonstrated on a fast Fourier transform (FFT) processor. The FFT processor uses an energy-aware architecture that allows for variable FFT length (128-1024 point), variable bit-precision (8 b and 16 b) and is designed to investigate the estimated minimum energy point. The FFT processor is fabricated using a standard 0.18-/spl mu/m CMOS logic process and operates down to 180 mV. The minimum energy point for the 16-b 1024-point FFT processor occurs at 350-mV supply voltage where it dissipates 155 nJ/FFT at a clock frequency of 10 kHz.


Question: Regarding the matching of latent fingerprints.

The impending transformation in the realm of forensic identification sciences is being catalyzed by a confluence of legal and scientific influences. The long-standing premise of inherent uniqueness, which has been the bedrock of forensic identification disciplines, is being challenged by mounting evidence of inaccuracies in both proficiency assessments and real-world cases. Legal reforms concerning the acceptance of expert testimony in courtrooms, coupled with the rise of DNA profiling as a benchmark for a scientifically robust method to address issues of identity concordance, are propelling the conventional forensic sciences toward the adoption of a novel scientific framework. This paradigm shift is necessitated by the need for enhanced reliability and scientific rigor in forensic identifications, aiming to rectify the shortcomings and inconsistencies that have marred the traditional practices.

We propose a new technique for direct visual matching of images for the purposes of face recognition and image retrieval, using a probabilistic measure of similarity, based primarily on a Bayesian (MAP) analysis of image differences. The performance advantage of this probabilistic matching technique over standard Euclidean nearest-neighbor eigenface matching was demonstrated using results from DARPA’s 1996 “FERET” face recognition competition, in which this Bayesian matching algorithm was found to be the top performer. In addition, we derive a simple method of replacing costly computation of nonlinear (on-line) Bayesian similarity measures by inexpensive linear (off-line) subspace projections and simple Euclidean norms, thus resulting in a significant computational speed-up for implementation with very large databases. Appears in: Pattern Recognition, Vol. 33, No. 11, pps. 1771-1782, November, 2000. This work may not be copied or reproduced in whole or in part for any commercial purpose. Permission to copy in whole or in part without payment of fee is granted for nonprofit educational and research purposes provided that all such whole or partial copies include the following: a notice that such copying is by permission of Mitsubishi Electric Research Laboratories, Inc.; an acknowledgment of the authors and individual contributions to the work; and all applicable portions of the copyright notice. Copying, reproduction, or republishing for any other purpose shall require a license with payment of fee to Mitsubishi Electric Research Laboratories, Inc. All rights reserved. Copyright c Mitsubishi Electric Research Laboratories, Inc., 2002 201 Broadway, Cambridge, Massachusetts 02139 Appears in: Pattern Recognition, Vol. 33, No. 11, pps. 1771-1782, November, 2000.

Ear classification refers to the process by which an input ear image is assigned to one of several pre-defined classes based on a set of features extracted from the image. In the context of large-scale ear identification, where the input probe image has to be compared against a large set of gallery images in order to locate a matching identity, classification can be used to restrict the matching process to only those images in the gallery that belong to the same class as the probe. In this work, we utilize an unsupervised clustering scheme to partition ear images into multiple classes (i.e., clusters), with each class being denoted by a prototype or a centroid. A given ear image is assigned class labels (i.e., cluster indices) that correspond to the clusters whose centroids are closest to it. We compare the classification performance of three different texture descriptors, viz. Histograms of Oriented Gradients, uniform Local Binary Patterns and Local Phase Quantization. Extensive experiments using three different ear datasets suggest that the Local Phase Quantization texture descriptor scheme along with PCA for dimensionality reduction results in a 96.89% hit rate (i.e., 3.11% pre-selection error rate) with a penetration rate of 32.08%. Further, we demonstrate that the hit rate improves to 99.01% with a penetration rate of 47.10% when a multi-cluster search strategy is employed.

In informational age there are many information crucial to a individual. To protect the data from the unwanted use we proposed the biometric system of vein recognition as today's world demand for a easy and accurate biometric system to protect our data. The biometric system is accurate and easy to use as every individual has a unique vein pattern. In this paper we have studied various method used by different people to achieve the goal to secure world and give the reader a brief prospective of this technology.

Despite new technologies that make face detection and recognition more sophisticated, long-recognized problems in security, privacy, and accuracy persist. Refining this technology and introducing it into new domains will require solving these problems through focused interdisciplinary efforts among developers, researchers, and policymakers.


Question: Regarding the matching of latent fingerprints.

This paper presents a new approach to minutiae-based fingerprint matching, addressing the twin challenges of establishing correspondence and calculating similarity. To tackle the correspondence issue, each minutia is assigned dual descriptors: one based on texture and the other on minutiae characteristics. An alignment-based greedy algorithm is then employed to determine the relationships between minutiae. For the similarity computation phase, a 17-dimensional feature vector is derived from the matching results. This vector is subsequently transformed into a matching score through the use of a support vector classifier. The effectiveness of the proposed algorithm is demonstrated through testing on the FVC2002 databases, where it outperforms competitors in terms of equal error rate. Notably, the algorithm achieves the top rank on DB3, the most challenging database in the FVC2002 set, and maintains an average second-place ranking across all four databases. © 2007 Pattern Recognition Society. Published by Elsevier Ltd. All rights reserved.

We think of Match as an operator which takes two graph-like structures (e.g., conceptual hierarchies or ontologies) and produces a mapping between those nodes of the two graphs that correspond semantically to each other. Semantic matching is a novel approach where semantic correspondences are discovered by computing, and returning as a result, the semantic information implicitly or explicitly codified in the labels of nodes and arcs. In this paper we present an algorithm implementing semantic matching, and we discuss its implementation within the S-Match system. We also test S-Match against three state of the art matching systems. The results, though preliminary, look promising, in particular for what concerns precision and recall.

Over the past few years, the evaluation of Electrocardio-graphic (ECG) signals as a prospective biometric modality has revealed promising results. Given the vital and continuous nature of this information source, ECG signals offer several advantages to the field of biometrics; yet, several challenges currently prevent the ECG from being adopted as a biometric modality in operational settings. These arise partially due to ECG signal's clinical tradition and intru-siveness, but also from the lack of evidence on the permanence of the ECG templates over time. The problem of in-trusiveness has been recently overcome with the “off-the-person” approach for capturing ECG signals. In this paper we provide an evaluation of the permanence of ECG signals collected at the fingers, with respect to the biometric authentication performance. Our experimental results on a small dataset suggest that further research is necessary to account for and understand sources of variability found in some subjects. Despite these limitations, “off-the-person” ECG appears to be a viable trait for multi-biometric or standalone biometrics, low user throughput, real-world scenarios.

We present randomized algorithms to solve the following string-matching problem and some of its generalizations: Given a string X of length n (the pattern) and a string Y (the text), find the first occurrence of X as a consecutive block within Y. The algorithms represent strings of length n by much shorter strings called fingerprints, and achieve their efficiency by manipulating fingerprints instead of longer strings. The algorithms require a constant number of storage locations, and essentially run in real time. They are conceptually simple and easy to implement. The method readily generalizes to higher-dimensional patternmatching problems.


Question:
Regarding the matching of latent fingerprints.

**Question**: An evolutionary algorithm for optimizing complex systems

**Similar Question**: An evolutionary algorithmic method for the optimization of intricate systems.

This paper delves into the Handbook of Fingerprint Recognition, exploring the strategies for integrating multiple biometric modalities, particularly focusing on fingerprint recognition systems. The integration of classifiers, akin to the fusion of multiple biometric sources, is a critical aspect in enhancing the accuracy and reliability of biometric systems. A key strategy discussed is the combination scheme, which involves merging the outputs of individual classifiers to make a final decision. Among the popular techniques, majority voting stands out, where an input pattern is assigned to the class with the highest number of votes. In scenarios with two classifiers, logical AND or OR operators are often employed, while in cases with more than two, these rules are combined. For instance, a biometric system might work on "fingerprint OR (face AND hand geometry)," requiring either a fingerprint or both face and hand geometry for identification.

Class set reduction, logistic regression, and Borda counts are prominent methods used in combining classifiers based on rank labels. Class set reduction aims to select a minimal subset of classes that includes the true class, often combining multiple subsets from various modalities using union or intersection operations. Logistic regression and Borda counts, collectively known as class set reordering methods, seek to create a consensus ranking of classes, ensuring the true class is ranked highest. This approach is particularly useful in indexing and retrieval systems, where a biometric system typically outputs an ordered list of candidates, with the top element being the most probable match.

When integrating multiple modalities, the combination of confidence values is crucial. Commonly used schemes include sum, mean, median, product, minimum, and maximum rules. The sum or mean rule is often favored, although normalization of confidences from different modalities is essential. This normalization process, which involves mapping confidence measures from various modalities into a common domain, can be as simple as inverting the sign of distance scores to ensure higher scores correlate with higher similarity. More complex non-linear normalization techniques can be learned from training data, translating and scaling scores to have zero mean, unit variance, and then mapping them to a fixed interval of (0,1) using a hyperbolic tangent function.

The paper also discusses the theoretical underpinnings of multimodal biometric integration strategies. Daugman (1999b) demonstrated that combining a strong biometric with a weak one using abstract level combination with AND or OR voting rules can degrade performance compared to the better individual biometric. Hong, Jain, and Pankanti (1999) further confirmed this finding, showing that

In this paper, we present an empirical comparison of some Differential Evolution variants to solve global optimization problems. The aim is to identify which one of them is more suitable to solve an optimization problem, depending on the problem's features and also to identify the variant with the best performance, regardless of the features of the problem to be solved. Eight variants were implemented and tested on 13 benchmark problems taken from the specialized literature. These variants vary in the type of recombination operator used and also in the way in which the mutation is computed. A set of statistical tests were performed in order to obtain more confidence on the validity of the results and to reinforce our discussion. The main aim is that this study can help both researchers and practitioners interested in using differential evolution as a global optimizer, since we expect that our conclusions can provide some insights regarding the advantages or limitations of each of the variants studied.

Page ii Complex Adaptive Systems John H. Holland, Christopher Langton, and Stewart W. Wilson, advisors Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control, and Artificial Intelligence, MIT Press edition John H. Holland Toward a Practice of Autonomous Systems: Proceedings of the First European Conference on Artificial Life edited by Francisco J. Varela and Paul Bourgine Genetic Programming: On the Programming of Computers by Means of Natural Selection John R. Koza

Fingerprint is one of the well accepted biometric traits for building automatic human recognition system. These systems mainly involves matching of two fingerprints based on their minutiae points. Therefore, extraction of reliable or true minutiae from the fingerprint image is critically important. This paper proposed an novel algorithm for automatic extraction of highly reliable minutiae points from a fingerprint image. It utilizes frequency domain image enhancement and heuristics. Experiments have been conducted on two databases. FVC2002 which is a publicly available fingerprint database containing 800 fingerprint images of 100 persons and IITK-Sel500FP which is an in-house database containing 1000 fingerprint images of 500 persons. Minutiae points extracted by the proposed algorithm are benchmarked against the manually marked ones and the comparison is done with an open source minutiae extractor mindtct of NIST. Experimental results have shown that the proposed algorithm has significantly higher confidence of extracted minutiae points being true.

The purpose of this paper is to outline a theory of automata appropriate to the properties, requirements and questions of adaptation. The conditions that such a theory should satisfy come from not one but several fields: It should be possible to formulate, at least in an abstract version, some of the key hypotheses and problems from relevant parts of biology, particularly the areas concerned with molecular control and neurophysiology. The work in theoretical genetics initiated by R. A. Fisher [5] and Sewall Wright [24] should find a natural place in the theory. At the same time the rigorous methods of automata theory should be brought to bear (particularly those parts concerned with growing automata [1, 2, 3, 7, 8, 12, 15, 18, 23]). Finally the theory should include among its models abstract counterparts of artificial adaptive systems currently being studied, systems such as Newell-Shaw-Simon's "General Problem Solver" [13], Selfridge's "Pandemonium" [17], von Neumann's self-reproducing automata [22] and Turing's morphogenetic systems [19, 20]. The theory outlined here (which is intended as a theory and not the theory) is presented in four main parts. Section 2 discusses the study of adaptation via generation procedures and generated populations. Section 3 defines a continuum of generation procedures realizable in a reasonably direct fashion. Section 4 discusses the realization of generation procedures as populations of interacting programs in an iterative circuit computer. Section 5 discusses the process of adaptation in the context of the earlier sections. The paper concludes with a discussion of the nature of the theorems of this theory. Before entering upon the detailed discussion, one general feature of the theory should be noted. The interpretations or models of the theory divide into two broad categories: "complete" models and "incomplete" models. The "complete" models comprise the artificial systems--systems with properties and specifications completely delimited at the outset (cf. the rules of a game). One set of "complete" models for the theory consists of various programmed parallel computers. The "incomplete" models encompass natural systems. Any natural system involves an unlimited number of factors and, inevitably, the theory can handle only a selected few of these. Because there will always be variables which do not have explicit counterparts in the theory, the derived statements must be approximate relative to natural systems. For this reason it helps greatly that

A combination of distributed computation, positive feedback and constructive greedy heuristic is proposed as a new approach to stochastic optimization and problem solving. Positive feedback accounts for rapid discovery of very good solutions, distributed computation avoids premature convergence, and greedy heuristic helps the procedure to find acceptable solutions in the early stages of the search process. An application of the proposed methodology to the classical travelling salesman problem shows that the system can rapidly provide very good, if not optimal, solutions. We report on many simulation results and discuss the working of the algorithm. Some hints about how this approach can be applied to a variety of optimization problems are also given.

Ant System, the first Ant Colony Optimization algorithm, showed to be a viable method for attacking hard combinatorial optimization problems. Yet, its performance, when compared to more fine-tuned algorithms, was rather poor for large instances of traditional benchmark problems like the Traveling Salesman Problem. To show that Ant Colony Optimization algorithms could be good alternatives to existing algorithms for hard combinatorial optimization problems, recent research in this ares has mainly focused on the development of algorithmic variants which achieve better performance than AS. In this article, we present – Ant System, an Ant Colony Optimization algorithm derived from Ant System. – Ant System differs from Ant System in several important aspects, whose usefulness we demonstrate by means of an experimental study. Additionally, we relate one of the characteristics specific to AS — that of using a greedier search than Ant System — to results from the search space analysis of the combinatorial optimization problems attacked in this paper. Our computational results on the Traveling Salesman Problem and the Quadratic Assignment Problem show that – Ant System is currently among the best performing algorithms for these problems.

Biometric systems that use a single biometric trait have to contend with noisy data, restricted degrees of freedom, failureto-enroll problems, spoof attacks, and unacceptable error rates. Multibiometric systems that use multiple traits of an individual for authentication, alleviate some of these problems while improving verification performance. We demonstrate that the performance of multibiometric systems can be further improved by learning user-specific parameters. Two types of parameters are considered here. (i) Thresholds that are used to decide if a matching score indicates a genuine user or an impostor, and (ii) weights that are used to indicate the importance of matching scores output by each biometric trait. User-specific thresholds are computed using the cumulative histogram of impostor matching scores corresponding to each user. The user-specific weights associated with each biometric are estimated by searching for that set of weights which minimizes the total verification error. The tests were conducted on a database of 50 users who provided fingerprint, face and hand geometry data, with 10 of these users providing data over a period of two months. We observed that user-specific thresholds improved system performance by ∼ 2%, while user-specific weights improved performance by ∼ 3%.

Abstract: This paper generalises the golden section optimal search method to higher dimensional optimisation problem. The method is applicable to a strict quasi-convex function of N-variables over an N-dimensional hyper rectangle. An algorithm is proposed in N-dimension. The algorithm is illustrated graphically in two dimensions and verified through several test functions in higher dimension using MATLAB.

This paper aims at incorporating immune operators in genetic algorithms as an advanced method for solving the problem of test data generation. The new proposed hybrid algorithm is called immune genetic algorithm (IGA). A full description of this algorithm is presented before investigating its application in the context of software test data generation using some benchmark programs. Moreover, the algorithm is compared with other evolutionary algorithms.

In this paper we will address the problem of planning optimal grasps. Two general optimality criteria, that consider the total finger force and the maximum finger force will be introduced and discussed. Moreover their formalization, using various metrics on a space of generalized forces, will be detailed. The geometric interpretation of the two criteria will lead to an efficient planning algorithm. An example of its use in a robotic environment equipped with two-jaw and three-jaw grippers will also be shown.


Question: Regarding the matching of latent fingerprints.

This paper introduces an innovative minutiae matching technique that employs a thin-plate spline model to characterize elastic deformations in fingerprints. The model is estimated through a dual matching process, involving both local and global stages, to accurately align the fingerprints. Post-registration, the algorithm can then precisely count the number of matching minutiae using stringent matching criteria. In scenarios involving deformed fingerprints, this method significantly outperforms rigid matching algorithms, delivering enhanced matching scores. Notably, the computational time required for this process is a mere 100 milliseconds on a 1 GHz P-III computer. Additionally, the paper highlights that the observed deformations in fingerprints do not align with those predicted by theoretical models previously proposed in the literature. Copyright ? 2003 Pattern Recognition Society. Reproduced with permission from Elsevier Science Ltd. All rights reserved.

Multimodal biometrics has recently attracted substantial interest for its high performance in biometric recognition system. In this paper we introduce multimodal biometrics for face and palmprint images using fusion techniques at the feature level. Gabor based image processing is utilized to extract discriminant features, while principal component analysis (PCA) and linear discriminant analysis (LDA) are used to reduce the dimension of each modality. The output features of LDA are serially combined and classified by a Euclidean distance classifier. The experimental results based on ORL face and Poly-U palmprint databases proved that this fusion technique is able to increase biometric recognition rates compared to that produced by single modal biometrics.

Changing procedures in the handling of rare and precious documents in museums and elsewhere, based on assumptions about constituents of latent fingerprints, have led the author to an examination of available data. These changes appear to have been triggered by one paper using general biological data regarding eccrine sweat production to infer that deposited fingerprints are mostly water. Searching the fingerprint literature has revealed a number of reference works similarly quoting figures for average water content of deposited fingerprints of 98% or more. Whilst accurate estimation is difficult there is no evidence that the residue on fingers could be anything like 98% water, even if there were no contamination from sebaceous glands. Consideration of published analytical data of real fingerprints, and several theoretical considerations regarding evaporation and replenishment rates, indicates a probable initial average water content of a fingerprint, soon after deposition, of 20% or less.

This paper presents a novel audio fingerprinting method that is highly robust to a variety of audio distortions. It is based on an unconventional audio fingerprint generation scheme. The robustness is achieved by generating different versions of the spectrogram matrix of the audio signal by using a threshold based on the average of the spectral values to prune this matrix. We transform each version of this pruned spectrogram matrix into a 2-D binary image. Multiple versions of these 2-D images suppress noise to a varying degree. This varying degree of noise suppression improves likelihood of one of the images matching a reference image. To speed up matching, we convert each image into an n-dimensional vector, and perform a nearest neighbor search based on this n-dimensional vector. We give results with two different feature parameters and their combination. We test this method on TRECVID 2010 content-based copy detection evaluation dataset, and we validate the performance on TRECVID 2009 dataset also. Experimental results show the effectiveness of these features even when the audio is distorted. We compare the proposed method to two state-of-the-art audio copy detection systems, namely NN-based and Shazam systems. Our method by far outperforms Shazam system for all audio transformations (or distortions) in terms of detection performance, number of missed queries and localization accuracy. Compared to NN-based system, our approach reduces minimal Normalized Detection Cost Rate (min NDCR) by 23 % and improves localization accuracy by 24 %.

A facial recognition system is a computer application for automatically identifying or verifying a person from a digital image or a video frame from a video source. One of the way is to do this is by comparing selected facial features from the image and a facial database. It is typically used in security systems and can be compared to other biometrics such as fingerprint or eye iris recognition systems. In this paper we focus on 3-D facial recognition system and biometric facial recognition system. We do critics on facial recognition system giving effectiveness and weaknesses. This paper also introduces scope of recognition system in India. Face recognition has received substantial attention from researchers in biometrics, pattern recognition field and computer vision communities. Face recognition can be applied in Security measure at Air ports, Passport verification, Criminals list verification in police department, Visa processing, Verification of Electoral identification and Card Security measure at ATM’s. Principal Component Analysis (PCA) is a technique among the most common feature extraction techniques used in Face Recognition. In this paper, a face recognition system for personal identification and verification using Principal Component Analysis with different distance classifiers is proposed. The test results in the ORL face database produces interesting results from the point of view of recognition success, rate, and robustness of the face recognition algorithm. Different classifiers were used to match the image of a person to a class (a subject) obtained from the training data. These classifiers are: the City-Block Distance Classifier, the Euclidian distance classifier, the Squared Euclidian Distance Classifier, and the Squared Chebyshev distance Classifier.


Question: Regarding the matching of latent fingerprints.

This paper introduces a sophisticated real-time matching system designed to efficiently search and query extensive fingerprint databases, addressing the pressing demand created by the rapid advancement of multimedia technology. Unlike conventional digital libraries, image databases, including fingerprints, require specialized handling due to their unique characteristics and contextual complexities. The intricate nature of two-dimensional image data and the presence of contextual dependencies pose significant challenges for representation and indexing techniques. Despite ongoing research, developing a universally effective content-based retrieval method for images remains an open issue. Existing approaches that focus on shape, texture, and color have achieved only limited success and have not been rigorously tested under conditions of noise and distortion. In specific application domains, however, such constraints can be leveraged to enhance retrieval performance. Fingerprint databases, in particular, are marked by their vast size and the frequent presence of noise and distortion in query images, often due to the skin's elasticity. In this context, the paper presents a novel method for indexing large fingerprint databases. The proposed approach combines domain-specific high-level features, such as pattern class and ridge density, with elastic structural feature-based matching at lower levels. This multilevel indexing strategy significantly narrows down the search space, making the process more efficient. To further enhance performance, the search engine has been implemented on a Splash 2 field-programmable gate array (FPGA)-based array processor, achieving near-ASIC level matching speeds. The effectiveness of the system has been validated through testing on both a local test dataset and the National Institute of Standards and Technology (NIST) database NIST-9, a comprehensive resource for fingerprint data.

This paper proposes a new powerful distance measure called Normalized Unmatched Points (NUP). This measure can be used in a face recognition system to discriminate facial images. It works by counting the number of unmatched pixels between query and database images. A face recognition system has been proposed which makes use of this proposed distance measure for taking the decision on matching. This system has been tested on four publicly available databases, viz. ORL, YALE, BERN and CALTECH databases. Experimental results show that the proposed measure achieves recognition rates more than 98.66% for the first five likely matched faces. It is observed that the NUP distance measure performs better than other existing similar variants on these databases.

This paper presents a novel audio fingerprinting method that is highly robust to a variety of audio distortions. It is based on an unconventional audio fingerprint generation scheme. The robustness is achieved by generating different versions of the spectrogram matrix of the audio signal by using a threshold based on the average of the spectral values to prune this matrix. We transform each version of this pruned spectrogram matrix into a 2-D binary image. Multiple versions of these 2-D images suppress noise to a varying degree. This varying degree of noise suppression improves likelihood of one of the images matching a reference image. To speed up matching, we convert each image into an n-dimensional vector, and perform a nearest neighbor search based on this n-dimensional vector. We give results with two different feature parameters and their combination. We test this method on TRECVID 2010 content-based copy detection evaluation dataset, and we validate the performance on TRECVID 2009 dataset also. Experimental results show the effectiveness of these features even when the audio is distorted. We compare the proposed method to two state-of-the-art audio copy detection systems, namely NN-based and Shazam systems. Our method by far outperforms Shazam system for all audio transformations (or distortions) in terms of detection performance, number of missed queries and localization accuracy. Compared to NN-based system, our approach reduces minimal Normalized Detection Cost Rate (min NDCR) by 23 % and improves localization accuracy by 24 %.

Security concerns increase as the technology for falsification advances. There are strong evidences that a difficult to falsify biometric trait, the human heartbeat, can be used for identity recognition. Existing solutions for biometric recognition from electrocardiogram (ECG) signals are based on temporal and amplitude distances between detected fiducial points. Such methods rely heavily on the accuracy of fiducial detection, which is still an open problem due to the difficulty in exact localization of wave boundaries. This paper presents a systematic analysis for human identification from ECG data. A fiducial-detection-based framework that incorporates analytic and appearance attributes is first introduced. The appearance-based approach needs detection of one fiducial point only. Further, to completely relax the detection of fiducial points, a new approach based on autocorrelation (AC) in conjunction with discrete cosine transform (DCT) is proposed. Experimentation demonstrates that the AC/DCT method produces comparable recognition accuracy with the fiducial-detection-based approach.

The electrocardiogram (ECG) is an emerging biometric modality that has seen about 13 years of development in peer-reviewed literature, and as such deserves a systematic review and discussion of the associated methods and findings. In this paper, we review most of the techniques that have been applied to the use of the electrocardiogram for biometric recognition. In particular, we categorize the methodologies based on the features and the classification schemes. Finally, a comparative analysis of the authentication performance of a few of the ECG biometric systems is presented, using our inhouse database. The comparative study includes the cases where training and testing data come from the same and different sessions (days). The authentication results show that most of the algorithms that have been proposed for ECG-based biometrics perform well when the training and testing data come from the same session. However, when training and testing data come from different sessions, a performance degradation occurs. Multiple training sessions were incorporated to diminish the loss in performance. That notwithstanding, only a few of the proposed ECG recognition algorithms appear to be able to support performance improvement due to multiple training sessions. Only three of these algorithms produced equal error rates (EERs) in the single digits, including an EER of 5.5% using a method proposed by us.


Question: Regarding feature selection, framing it as a single participant game.

In the realm of machine learning, Classification and Regression Trees (CART) have emerged as a pivotal technique for addressing complex data problems. This method, which transforms the feature selection process into a strategic game for a single player, offers a unique approach to model building. In CART, the game is played on a tree-like graph, where nodes represent features and edges represent decisions or outcomes. The objective of the player, akin to a data scientist, is to construct a tree that optimally predicts the target variable, be it categorical or continuous. This is achieved through a series of splits, each of which maximizes the information gain or minimizes the impurity at a node. The game's complexity lies in balancing the tree's depth to prevent overfitting, while ensuring that the model captures the underlying patterns in the data effectively. The player must judiciously select features at each step, akin to making strategic moves, to ensure that the tree is both robust and interpretable. This game-like perspective not only makes the learning process more engaging but also aids in understanding the intricate relationship between features and outcomes in a structured manner.

As the number of features in pattern recognition applications continuously grows, new algorithms are necessary to reduce the dimensionality of the feature space while producing comparable results. For example, a dynamic area of research, activity recognition, produces large quantities of high-velocity, high-dimensionality data that require real time classification. While dimensionality reduction approaches such as principle component analysis (PCA) and feature selection work well for datasets of reasonable size and dimensionality, they fail on big data. A possible approach to classification of high-dimensionality datasets is to combine a typical classifier, fuzzy k-nearest neighbor in our case (FKNN), with feature reduction by random projection (RP). As opposed to PCA where one projection matrix is computed based on least square optimality, in RP, a projection matrix is chosen at random multiple times. As the random projection procedure is repeated many times, the question is how to aggregate the values of the classifier obtained in each projection. In this paper we present a fusion strategy for RP FKNN, denoted as RPFKNN. The fusion strategy is based on the class membership values produced by FKNN and classification accuracy in each projection. We test RPFKNN on several synthetic and activity recognition datasets.

Language games represent one of the most fascinating challenges of research in artificial intelligence. In this paper we give an overview of WebCrow, a system that tackles crosswords using the Web as a knowledge base. This appears to be a novel approach with respect to the available literature. It is also the first solver for nonEnglish crosswords and it has been designed to be potentially multilingual. Although WebCrow has been implemented only in a preliminary version, it already displays very interesting results reaching the performance of a human beginner: crosswords that are “easy” for expert humans are solved, within competition time limits, with 80% of correct words and over 90% of correct letters. Introduction Crosswords are probably the most played language puzzles worldwide. Until recently, the research in artificial intelligence focused its interest only on the NP-complete crossword generation problem (Mazlack 1976) (Ginsberg et al. 1990) which can now be solved in a few seconds for reasonable dimensions (Ginsberg 1993). Conversely, problems like solving crosswords from clues have been defined as AI-complete (Littman 2000) and are extremely challenging for machines since there is no closedworld assumption and they require human-level knowledge. Interestingly, AI has nowadays the opportunity to exploit a stable nucleus of technology, such as search engines, information retrieval and machine learning techniques, that can enable computers to enfold with semantics real-life concepts. We will present here a software system, called WebCrow, whose major assumption is to attack crosswords making use of the Web as its primary source of knowledge, being this an extremely rich and self-updating repository of human knowledge1. This paper gives a general overview of the modules and the subproblems present in the project. Copyright c © 2005, American Association for Artificial Intelligence (www.aaai.org). All rights reserved. 1The WebCrow project, with the emphasis on the power coming from searching the Web, was briefly described in the Nature magazine(News-Nature 2004) and mentioned in the AAAI Web site concerning games and puzzles http://www.aaai.org/AITopics/html/crosswd.html To the best of our knowledge the only significant attempt reported in the literature to tackle this problem is the Proverb system, which has reached human-like performances (Keim, Shazeer, & Littman 1999). Unlike Proverb, WebCrow does not possess any knowledge-specific expert module nor a crossword database of great dimensions. WebCrow, instead, in order to stress the generality of its knowledge and language-independence, has in its core a module performing a special form of question answering on the Web that we shall call clue-answering. The second goal of the system, that is filling the crossword grid with the best set of candidate answers, has been tackled as a Probabilistic-CSP. Italian crosswords are structurally similar to Americans, but they differ in two aspects: two-letter words2 are allowed and, more importantly, they contain stronger and more ambiguous references to socio-cultural and political topics. The latter is a phenomenon especially present in newspapers and it introduces an additional degree of complexity in crossword solving, since it requires the possession of a knowledge that is extremely broad, fresh and also robust to volunteer vagueness and ambiguity. Neologisms and compound words are often present. We have collected 685 examples of Italian crosswords. The majority was obtained from two sources: the main Italian crossword magazine La Settimana Enigmistica and the main on-line newspaper’s crossword section La Repubblica. 60 puzzles were randomly chosen to form the experimental test suite. The remaining part constituted a database of clue-answer pairs used as an aid in the answering process. In this paper the challenge of WebCrow is to solve Italian crosswords within a 15 minutes time limit (running the program on a common laptop), as in real competitions. The version of WebCrow that is discussed here is preliminary but it has already given very promising results. WebCrow averaged around 70% words correct and 80% letters correct in the overall test set. On the examples that expert players consider “easy” WebCrow performed with 80% words correct (100% in one case) and over 90% letters correct. Architectural overview WebCrow has been designed as a modular and data-driven system. Two are the main sources that it applies to: Web 2Name initials, acronyms, abbreviations or portions of a word.

Coco (“cooperative/competitive”) values are a solution concept for two-player normalform games with transferable utility, when binding agreements and side payments between players are possible. In this paper, we show that coco values can also be defined for stochastic games and can be learned using a simple variant of Q-learning that is provably convergent. We provide a set of examples showing how the strategies learned by the Coco-Q algorithm relate to those learned by existing multiagent Q-learning algorithms.

We present an approach to structured prediction from bandit feedback, called Bandit Structured Prediction, where only the value of a task loss function at a single predicted point, instead of a correct structure, is observed in learning. We present an application to discriminative reranking in Statistical Machine Translation (SMT) where the learning algorithm only has access to a 1 − BLEU loss evaluation of a predicted translation instead of obtaining a gold standard reference translation. In our experiment bandit feedback is obtained by evaluating BLEU on reference translations without revealing them to the algorithm. This can be thought of as a simulation of interactive machine translation where an SMT system is personalized by a user who provides single point feedback to predicted translations. Our experiments show that our approach improves translation quality and is comparable to approaches that employ more informative feedback in learning.

Evaluating whether machines improve on human performance is one of the central questions of machine learning. However, there are many domains where the data is selectively labeled, in the sense that the observed outcomes are themselves a consequence of the existing choices of the human decision-makers. For instance, in the context of judicial bail decisions, we observe the outcome of whether a defendant fails to return for their court appearance only if the human judge decides to release the defendant on bail. This selective labeling makes it harder to evaluate predictive models as the instances for which outcomes are observed do not represent a random sample of the population. Here we propose a novel framework for evaluating the performance of predictive models on selectively labeled data. We develop an approach called contraction which allows us to compare the performance of predictive models and human decision-makers without resorting to counterfactual inference. Our methodology harnesses the heterogeneity of human decision-makers and facilitates effective evaluation of predictive models even in the presence of unmeasured confounders (unobservables) which influence both human decisions and the resulting outcomes. Experimental results on real world datasets spanning diverse domains such as health care, insurance, and criminal justice demonstrate the utility of our evaluation metric in comparing human decisions and machine predictions.

In the context of machine learning from examples this paper deals with the problem of estimating the quality of attributes with and without dependencies among them. Kira and Rendell (1992a,b) developed an algorithm called RELIEF, which was shown to be very eecient in estimating attributes. Original RELIEF can deal with discrete and continuous attributes and is limited to only two-class problems. In this paper RELIEF is analysed and extended to deal with noisy, incomplete, and multi-class data sets. The extensions are veriied on various artiicial and one well known real-world problem.

Procedural content generation via Machine Learning (PCGML) is the umbrella term for approaches that generate content for games via machine learning. One of the benefits of PCGML is that, unlike search or grammar-based PCG, it does not require hand authoring of initial content or rules. Instead, PCGML relies on existing content and black box models, which can be difficult to tune or tweak without expert knowledge. This is especially problematic when a human designer needs to understand how to manipulate their data or models to achieve desired results. We present an approach to Explainable PCGML via Design Patterns in which the design patterns act as a vocabulary and mode of interaction between user and model. We demonstrate that our technique outperforms non-explainable versions of our system in interactions with five expert designers, four of whom lack any machine learning expertise.

This paper deals with the problem of tracking football players in a football match using data from a single moving camera. Tracking footballers from a single video source is di cult: not only do the football players occlude each other, but they frequently enter and leave the camera's eld of view, making initialisation and destruction of a player's tracking a di cult task. The system presented here uses particle lters to track players. The multiple state estimates used by a particle lter provide an elegant method for maintaining tracking of players following an occlusion. Automated tracking can be achieved by creating and stopping particle lters depending on the input player data.

This article presents an algorithm for inducing multiclass decision trees with multivariate tests at internal decision nodes. Each test is constructed by training a linear machine and eliminating variables in a controlled manner. Empirical results demonstrate that the algorithm builds small accurate trees across a variety of tasks.

This paper provides new insight into kernel methods by using data selection. The kernel trick is used to select from the data a relevant subset forming a basis in a feature space F . Thus the selected vectors de,ne a subspace in F . Then, the data is projected onto this subspace where classical algorithms are applied. We show that kernel methods like generalized discriminant analysis (Neural Comput. 12 (2000) 2385) or kernel principal component analysis (Neural Comput. 10 (1998) 1299) can be expressed more easily. Moreover, it will turn out that the size of the basis is related to the complexity of the model. Therefore, the data selection leads to a complexity control and thus to a better generalization. The approach covers a wide range of algorithms. We investigate the function approximation on real classi,cation problems and on a regression problem. c © 2003 Elsevier B.V. All rights reserved.