Question: Compact circularly polarized patch antenna with reduced rearward radiation for GPS satellite communications.

In this work, we present a dual-band circularly polarized ring antenna designed, constructed, and tested, leveraging the principles of composite right and left handed (CRLH) metamaterials. By harnessing the unique properties of CRLH metamaterials, we achieve consistent phase constants and current distributions on the ring antenna across two distinct frequency bands. This results in similar radiation patterns at both operating bands, ensuring consistent performance. The circular polarization is realized through the dual-port feeding technique, where power dividers supply equal amplitude excitations with a 90-degree phase difference to the vertical ports. This design ensures the antenna's suitability for dual-band operation while maintaining circular polarization, making it an ideal candidate for various applications requiring dual-band functionality with circular polarization, including GPS satellite communications.

**Question**: A Novel Method for the Synthesis of Multifunctional Nanomaterials for Environmental Applications

**Documents**: Synthesis and characterization of magnetite nanomaterials for environmental applications
Abstract—In this paper, we report the synthesis and characterization of magnetite (Fe3O4) nanomaterials via a co-precipitation method. The synthesized nanomaterials were characterized by X-ray diffraction (XRD), Fourier transform infrared spectroscopy (FTIR), scanning electron microscopy (SEM), and transmission electron microscopy (TEM). The results show that the nanomaterials have a cubic spinel structure and are in the size range of 20-30 nm. The magnetite nanomaterials exhibit superparamagnetic behavior at room temperature, which makes them suitable for environmental applications such as water purification and magnetic separation.

**Similar Documents**: This study focuses on the development and analysis of magnetite (Fe3O4) nanomaterials through a co-precipitation synthesis technique. Comprehensive characterization of the synthesized nanomaterials was conducted using X-ray diffraction (XRD), Fourier transform infrared spectroscopy (FTIR), scanning electron microscopy (SEM), and transmission electron microscopy (TEM). The analysis reveals that the nanomaterials possess a cubic spinel structure and are uniformly sized within the 20-30 nm range. Notably, these magnetite nanomaterials display superparamagnetic properties at room temperature, a characteristic that significantly enhances their potential for environmental applications, particularly in the areas of water treatment and magnetic separation processes. This research contributes to the growing body of knowledge on multifunctional nanomaterials and their environmental remediation capabilities.

In this paper, a low-cost planar dipole array antenna with an omnidirectional radiation characteristic is presented. The proposed omnidirectional planar dipole array antenna comprises two 1/spl times/2 dipole arrays arranged back to back, and can be easily constructed by printing on both sides of a dielectric substrate. By selecting the central ground plane to have a small width (about 6 mm for operating at about 2.4 GHz), the proposed array antenna can have a good omnidirectional radiation pattern in the azimuthal plane (gain variations less than 2 dBi). Prototypes of the proposed antenna for WLAN operation in the 2.4 GHz band (2400-2484 MHz) were constructed and studied.

A two-port pattern reconfigurable three-layered Yagi-Uda patch antenna with ±45° dual-polarization characteristic is presented. A driven patch (DP) and two large parasitic patches (LPPs) are printed on the top side of the middle layer, and the middle and bottom layers share a common metal ground. Two microstrip feedlines printed orthogonally on the bottom side of the bottom layer are used to feed the DP through two H-shaped slots etched in the ground. The LPPs are connected to/disconnected from the ground controlled by switches. By adjusting the connection states of the LPPs, one wide-beam mode and three narrow-beam modes can be obtained in both polarizations. A small parasitic patch is printed on the top side of the top layer to improve the pattern coherence of the two polarizations. This antenna is studied by both simulation and measurement. The measured common bandwidth of the four modes in both polarizations is 3.32–3.51 GHz, and the isolations between two polarizations in all the modes are higher than 20 dB. The low-profile antenna is very suitable for microbase-station applications.

INMARSAT allocated frequencies are 1.525 GHz to 1.559 GHz as downlink and 1.625 GHz to 1.6605 GHz as uplink GPS allocated frequencies 1.57542 GHz in L1 band. In this paper we design two types of Helix antenna as PQHA to operate in allocated frequencies for INMARSAT and GPS application. We used for their optimum design Electromagnetic simulations and were verified by fabrication and VSWR measurement.

A 2D-periodic leaky-wave antenna for a Ka-band satcom-on-the-move ground user terminal is presented. The antenna panel operates at the 20 GHz downlink as well as the 30 GHz uplink bands with the respective circular polarizations, using a common radiation aperture and a common phase centre. The dual-band performance is achieved by a carefully designed stacked dual-layer frequency selective surface, with one layer operating at 20 GHz and being transparent at 30 GHz, and the second layer acting vice versa. The paper describes the design of the circularly polarized primary feed, the dual-layer structures, and the complete compact leaky-wave antenna panel. The measured radiation performance reveals realized-gain values above 22 dBi and efficiencies above 60%. The cross-polarization discrimination and sidelobe level are suitable to meet the power spectral requirements for satellite communications at Ka-band.

Radiation characteristics of a spiral antenna over a high-impedance surface (HIS) are analyzed. The HIS consists of fan-shaped patch cells. The fan-shaped patches are arranged homogeneously in the circumferential direction but are set non-homogeneously in the radial direction. The analysis is performed using method of moment. Radiation characteristics of a spiral antenna with a perfect electric conductor (PEC) reflector are analyzed. It is reaffirmed that wideband radiation characteristics, including input impedance and axial ratio are deteriorate. Subsequently, Radiation characteristics of a spiral antenna with a fan-shaped HIS reflector are analyzed. It is revealed that input impedance and axial ratio are mitigated by replacing the PEC reflector with the fan-shaped HIS reflector.

A new dual-band circularly polarized microstrip antenna is presented experimentally. In this paper, using dual-radiator a new design dual-band antenna can be obtained. The frequency ratio of this design is flexible which more than 1.4.

A compact 24-GHz Yagi-Uda antenna has been developed using standard design tables and simple scaling to take into account the added capacitance due to the supporting dielectric substrate. The antenna results in a directivity of 9.3 dB, a front-to-back ratio of 11 dB, and a bandwidth of 2.5-3%. The Yagi-Uda antenna has been implemented in an 11-beam system using a planar array and a 2-inch Teflon spherical lens. The measured patterns show a 22 dB gain beam, a cross-polarization level of -24 dB, and a crossover level of -6 dB. The design method presented in this paper is quite straightforward, and can be used to develop low-, medium-, and even high-gain endfire Yagi-Uda antennas.

In this paper planar circular Electromagnetic Band Gap (EBG) structures have been implemented in the Butler matrix fed antenna array system to improve the radiation performance of the system. Initially a conventional 4×4 Butler matrix fed antenna array system has been designed at 14.5 GHz. Asymmetricity in the gain values of major beams of the antenna array system has been observed both in simulation and measurement. Generally due to the design simplicity, light weight and compactness, the rectangular patch microstrip antenna has been used as the radiating element in the Butler matrix fed antenna array system. At higher frequencies microstrip antenna suffers from losses due to surface wave excitation. It degrades the radiation efficiency of the antenna array system and also increases the level of mutual coupling between the radiating elements in the antenna array. EBG (Electromagnetic Band Gap) units are used to improve the radiation performance of the system by the generation of stop band. The propagation of surface wave will be suppressed in this stop band region and may improve the performance of the system. To fulfill this requirement, 3 × 1 planar circular EBG unit has been designed. A stop band of 2.15 GHz with the centre frequency of 14.5 GHz has been obtained by the proposed EBG unit. The 3×1 planar circular EBG unit has been integrated between the radiating elements of the antenna array system. As a result the gain enhancement has been achieved for the 1R, 2L, 2R and 1L beams both in simulation and measurement at 14.5 GHz.

A novel periodic leaky-wave antenna for broadside radiation with horizontally polarized omnidirectional pattern is proposed, designed and demonstrated experimentally. The objective is to achieve a horizontally polarized omnidirectional antenna array with highly directive beam. The proposed structure is based on combining the rotating electric field method and a leaky-wave antenna design. By properly designing a unit cell with a pair of crossed dipoles spaced at a distance approximately equal to λg/4 at the center frequency, not only omnidirectional radiation pattern with horizontal polarization is obtained by crossed dipoles fed in phase quadrature, but also the open-stopband effect exhibited at broadside scan is significantly reduced. The analysis and design of this structure are performed on the basis of a simple equivalent network model. A finite structure formed by 16-unit cell (32-element) for broadside beam is developed at the 2.4 GHz band, which offers a horizontally polarized omnidirectional radiation pattern with enhanced gain of 9.9-10.6 dBi and measured radiation efficiency of 90% for the covering bands.

This paper presents the design, implementation and interport isolation performance evaluation of three dual port, dual polarized 2.4GHz microstrip patch antennas. Input matching and interport isolation (both DC and RF) performance of implemented antennas has been compared by measuring the input return losses (Sii, S22) and interport isolation (S12) respectively at 2.4GHz. Two implemented single layer antennas provide around 40dB RF interport isolation while the multilayer antenna has 60dB isolation between transmit and receive ports at centre frequency with DC isolated ports. The multilayer antenna provides more than 55dB interport isolation for antenna's 10 dB input impedance bandwidth of 50MHz.


Question: Compact circularly polarized patch antenna with reduced back radiation for GPS satellite communications.

This paper introduces a compact, circularly polarized patch antenna that incorporates metamaterial structures to achieve low-profile design and improved performance for GPS satellite communications. The antenna features a single-fed configuration and is enhanced with composite right/left-handed (CRLH) mushroom-like structures and a reactive impedance surface (RIS) to facilitate miniaturization. The circular polarization is achieved by simultaneously exciting two orthogonally polarized modes within the left-handed (LH) region. The paper provides a detailed examination of the antenna's radiation characteristics, supported by both simulation and experimental data. The circularly polarized performance can be adjusted using various methods. The proposed antenna measures 0.177λ0 × 0.181λ0 × 0.025λ0 at 2.58 GHz and demonstrates a radiation efficiency of approximately 72%. As an extension of this work, a compact dual-band, dual linearly polarized patch antenna has been designed and manufactured, yielding promising experimental outcomes. This innovative design represents a significant advancement in antenna technology, particularly for applications requiring low back radiation and miniaturization.

Automotive radar systems utilizing the millimeterwave band have been developed 2) since they can detect targets even in bad weather. In the automotive radar systems, linear polarization inclined 45 degrees is utilized in order to avoid mutual radio interference between them. The antenna for the automotive radar systems is required to have high efficiency, which means high gain against for an aperture area determined by the size of a radar sensor, in order to detect the targets at a long distance. In addition, low profile is required not to spoil the appearance of a car. Ease of manufacturing is also one of the significant factors in order to install the automotive radar systems in popular cars. As candidate antennas for the automotive radar systems, a slotted waveguide array antenna and a triplate-type array antenna have been studied. These antennas have low profile and high efficiency 7

An ultra-wideband horizontally polarized omnidirectional antenna is proposed. The connected Vivaldi antenna array mechanism is exploited to achieve the ultra-wide bandwidths of both the impedance and the radiation patterns simultaneously. Sixteen Vivaldi antenna elements are connected with each other and distributed along a circular substrate to form the proposed antenna. The designed antenna exhibits a relative impedance bandwidth of 159.97% (1.28–11.51 GHz) for <inline-formula> <tex-math notation="LaTeX">$\vert S_{11}\vert <-10$ </tex-math></inline-formula> dB. Meanwhile, uniform omnidirectional radiation patterns with a gain variation of less than 1.5 dB have been obtained within the frequency band of 1.25–7.6 GHz (142.73%).

Circularly polarized single-layer U-slot microstrip patch antenna has been proposed. The suggested asymmetrical U-slot can generate the two orthogonal modes for circular polarization without chamfering any corner of the probe-fed square patch microstrip antenna. A parametric study has been carried out to investigate the effects caused by different arm lengths of the U-slot. The thickness of the foam substrate is about 8.5% of the wavelength at the operating frequency. The 3 dB axial ratio bandwidth of the antenna is 4%. Both experimental and theoretical results of the antenna have been presented and discussed. Circular polarization, printed antennas, U-slot.

A new wideband ±45° dual-polarized metal loop dielectric resonator magnetoelectric antenna is proposed in this communication. The antenna consists of two orthogonal dielectric bars that support two orthogonal electric dipoles and two cross interlaced metal semi-loops that are equivalent to two orthogonal magnetic dipoles above the ground. With a legitimate combination of the electric and magnetic dipoles, a unidirectional radiation with low backward radiation and equal E-plane and H-plane radiation patterns can be achieved. The antenna can be made of a monolithic dielectric block with simple installation. To validate the new antenna configuration, a prototype is designed, manufactured, and measured. The prototype antenna using ceramic with the electrical size of <inline-formula> <tex-math notation="LaTeX">$0.33\lambda _{o} \times 0.33\lambda _{o} \times 0.21\lambda _{o}$ </tex-math></inline-formula> demonstrates that an impedance bandwidth of 11.4% (<inline-formula> <tex-math notation="LaTeX">$\vert S_{11}\vert < -15$ </tex-math></inline-formula> dB) in the 3.5 GHz frequency band can be achieved with the measured forward/backward ratio of better than 22 dB. The proposed antenna is suitable as antenna element for massive-MIMO array antennas, where a large number of antenna elements need to be installed in a compact space.

For the synthetic aperture radar systems, there is an increasing demand for achieving resolutions of 0.2 mtimes0.2 m. As the range resolution and system bandwidth are inversely proportional, the system bandwidth is expected to be greater than 1 GHz. Thus an antenna with wider band needs to be developed. Waveguide slot antennas have been implemented on several SAR satellites due to its inherent advantages such as high efficiency and power handling capacity, but its bandwidth is quite limited. To avoid the manufacture difficulties of the ridge waveguide, which is capable of broadening the bandwidth of slot antennas, a novel antenna element with conventional waveguide is designed. The bandwidth of VSWR les1.5 is greater than 1 GHz at X-band. To reduce the mutual coupling of closely placed antenna elements, a decoupling method with cavity-like walls inserted between adjacent elements is adopted and their effects on the performance of the antenna are summarized.

In this letter, electromagnetic band-gap (EBG) structure is used to reduce the radar cross section (RCS) of the patch array antenna. The proposition of this method is based on the high impedance characteristic of the mushroom-like EBG structure. The basic patch array antenna is designed with a central frequency of 5.0 GHz while replacing the substrate of the array with the mushroom-like EBG structure. The frequency band in which RCS of the patch array antenna reduced significantly can be adjusted by parameters of the EBG. The backward RCS of the patch array antenna with EBG can be reduced as much as 10 dB compared to that of the conventional array antenna, and the degradation of the antenna performance is not significant.

A novel resonator-loaded wideband dual-polarized antenna is proposed for LTE700/GSM850/GSM900 applications. Four single-polarized miniaturized antenna elements are placed with square arrangement upon the reflector for dual polarization. One pair of parallel elements is for +45° polarization, and the other pair is for –45° polarization. The impedance bandwidth is greatly improved loaded with a resonator. Experimentally, the antenna exhibits a wide impedance bandwidth of 37.5% ranging from 0.67 to 0.98 GHz for |<inline-formula> <tex-math notation="LaTeX">$S$</tex-math></inline-formula>11|<–15 dB, high isolation of more than 40 dB, and stable gain of around 9.5 dBi over the whole operating band.

In this study, a compact wideband slot antenna with band notch performance is designed. An M-shaped slot on the feed line increases the impedance bandwidth of the square slot antenna. A stop-band notch can be achieved by using two L-shaped protruded strip inside the square-ring stub. The designed slot antenna has a compact size of 20×20 mm, showing wideband characteristics in the frequency band of 4.4 to over 10.7 GHz with a band rejection performance in the frequency band of 5.0 to 5.4 GHz.

A novel printed monopole antenna with constant gain over a wide bandwidth for ultra wideband applications with desired notch-band characteristic is presented. The proposed antenna consists of a square-ring radiating patch with a pair of T-shaped strips protruded inside the square ring and a coupled T-shaped strip and a ground plane with a protruded strip, which provides a wide us able fractional bandwidth of more than 130% (3.07-14.6 GHz). By using the square-ring radiating patch with a pair of T-shaped strips protruded inside it, the frequency bandstop performance is generated, and we can control its characteristics such as band-notch frequency and its bandwidth by electromagnetically adjusting coupling between a pair of T-shaped strips protruded inside the square ring. The designed antenna has a small size of 12 × 18 mm2, or about 0.15λ × 0.25λ at 4.2 GHz, while showing the band-rejection performance in the frequency band of 5.05-5.95 GHz.

In this letter, a single-fed low-profile high-gain circularly polarized slotted cavity antenna using a high-order cavity mode, i.e., TE440 mode, is proposed. The proposed antenna has a simple structure that consists of a radiating linearly polarized slotted cavity antenna and a linear-to-circular polarization converter. An antenna prototype operating at WLAN 5.8-GHz band fabricated with low-cost standard printed circuit board (PCB) process is exemplified to validate the proposed concept. Measured results compared to their simulated counterparts are presented, and a good agreement between simulation and measurement is obtained.


Question: Compact circularly polarized patch antenna with reduced rearward radiation for GPS satellite communications.

This paper presents a novel omnidirectional circularly polarized (CP) antenna design, featuring a circular mushroom configuration with curved branches. The antenna's operation is centered around the zeroth-order resonance (ZOR) mode of an epsilon negative (ENG) transmission line (TL), which facilitates the generation of a vertical polarization and an omnidirectional radiation pattern. The curved branches, on the other hand, are responsible for the horizontal polarization. A notable feature of this antenna is its inherent provision of a 90° phase difference between the orthogonal polarizations, courtesy of the zeroth-order resonator. Consequently, the antenna exhibits an omnidirectional CP radiation pattern in the azimuthal plane. One of the key advantages of this design is its simplicity; it is a planar antenna that does not require a complex dual feeding structure or a 90° phase shifter. Performance-wise, the antenna demonstrates an average axial ratio of 2.03 dB and a left-hand (LH) circularly polarized (CP) gain of -0.40 dBic in the azimuthal plane, showcasing its potential for use in various wireless communication systems.

**Question**: A Comparative Study on the Performance of Different Types of Neural Networks for Speech Recognition

**Documents**: Comparative Study of Artificial Neural Network Architectures for Speech Recognition
This paper presents a comparative study of different artificial neural network (ANN) architectures for speech recognition. The architectures under investigation include feedforward neural networks (FNNs), recurrent neural networks (RNNs), and convolutional neural networks (CNNs). The study evaluates the performance of these networks on a standard speech recognition dataset. The results show that CNNs outperform FNNs and RNNs in terms of accuracy and robustness. The study also highlights the importance of selecting the appropriate network architecture for speech recognition tasks.

**Similar Documents**: This paper delves into a detailed comparative analysis of various artificial neural network (ANN) architectures for their application in speech recognition. Among the architectures scrutinized are feedforward neural networks (FNNs), recurrent neural networks (RNNs), and convolutional neural networks (CNNs). The performance of these networks is rigorously evaluated using a benchmark speech recognition dataset. The findings indicate that CNNs surpass both FNNs and RNNs in terms of both accuracy and reliability. Moreover, the study underscores the critical role of selecting the most suitable network architecture for enhancing the effectiveness of speech recognition systems.

The antenna characteristics are described of a single-arm spiral (SAS) antenna. A balun circuit, required for a conventional two-arm balanced-mode spiral (TAS), is not necessary for feeding this SAS. First, the radiation pattern of an SAS having a disc/ground-plane is investigated. When the radius of the disc is smaller than the radius of the first-mode active region on the spiral and the spacing between the disc and spiral plane is small, the SAS is found to radiate a circularly polarized (CP) bidirectional beam, whose radiation pattern is almost symmetric with respect to the antenna axis normal to the spiral plane. Second, from a practical standpoint, the CP bidirectional beam is transformed into a CP unidirectional beam by placing a conducting cavity behind an SAS with a disc. It is revealed that the SAS has a good VSWR (less than 2) and a good axial ratio (less than 3 dB) over a design frequency range of 3 GHz to 10 GHz, where a cavity/antenna height of 7 mm (0.07 wavelength at the lowest design frequency) is chosen. The frequency response of the gain for the SAS is found to be similar to that for a conventional TAS, and the radiation efficiency for the SAS is slightly larger than that for the TAS. It is concluded that the SAS with a small disc backed by a cavity realizes a circularly polarized, low-profile, wideband antenna with a simple feed system that does not require a balun circuit.

We have designed and tested a novel electronic tracking antenna array that is formed by 2 × 2 microstrip sub-arrays. Through time sequence phase weighting on each sub-array, the amplitude and phase on each sub-array can be recovered from the output of the resultant single channel. The amplitude and phase on each array can be used to produce the sum and difference radiation pattern by digital signal processing. In comparison with the monopulse system, the RF comparator is eliminated and the number of the receiver channels is reduced from 3 to 1. A proof-of-concept prototype was fabricated and tested. The measured results confirmed the validity and advantages of the proposed scheme. The procedure of channel correction is given.

A novel design of a high-gain reconfigurable sectoral antenna using an active cylindrical frequency selective surface (FSS) structure is presented. The FSS structure consists of metallic discontinuous strips with PIN diodes in their discontinuities, and it is placed cylindrically around an omnidirectional electromagnetically coupled coaxial dipole (ECCD) array. The cylindrical FSS structure is divided into two semi-cylinders. By controlling the state of diodes in each semi-cylinder, a directive radiation pattern is obtained that can be swept in the entire azimuth plane. The effect of the diode-state configuration and the radius of the cylindrical structure are carefully studied to obtain an optimum sectoral radiation pattern. In addition, a solution for increasing the matching bandwidth of the antenna is also proposed. An experimental prototype was fabricated, and the measured results show a beamwidth of 20° in elevation and 70° in the azimuth plane at 2.1 GHz with a gain of 13 dBi. With these features, the proposed antenna is suitable for base-station applications in wireless communication systems.

A combination of slots and series-fed patch antenna array is introduced leading to an array antenna with wide bandwidth, low sidelobe level (SLL), and high front-to-back ratio (F/B). Three structures are analyzed. The first, the reference structure, is the conventional series-fed microstrip antenna array that operates at 16.26 GHz with a bandwidth of 3%, SLL of -24 dB, and F/B of 23 dB. The second is similar to the reference structure, but a large slot that covers the patch array is removed from the ground plane. This results in a wide operating bandwidth of over 72% for , with a 3 dB gain bandwidth of over 15.9%. The SLL of this structure is improved to more than at 16.26 GHz, and stable SLL of over 15.5-16.4 GHz band is also exhibited. This structure has a bi-directional radiation pattern. To make the pattern uni-directional and increase the F/B, a third structure is analyzed. In this structure, rather than one single large slot, an array of slots is used and a reflector is placed above the series-fed patch array. This increases the F/B to 40 dB. The simulated and measured results are presented and discussed.

The majority of RFID tags are linearly polarized dipole antennas, but a few use a planar, dual-dipole antenna that facilitates circular polarization, but requires a three-terminal IC. In this paper, we present a novel way to achieve circular polarization with a planar antenna using a two-terminal IC. We present an intuitive methodology for design, and perform experiments that validate circular polarization. The results show that the tag exhibits strong circular polarization, but the precise axial ratio of the tag remains uncertain due to lack of precision in the experimental system.

Massive multiple input and multiple output (MIMO) has attracted significant interests in both academia and industry. It has been considered as one of most promising technologies for 5G wireless systems. The large-scale antenna array for base stations naturally becomes the key to deploy the Massive MIMO technologies. In this communication, we present a dual-polarized antenna array with 144 ports for Massive MIMO operating at 3.7 GHz. The proposed array consists of 18 low profile subarrays. Each subarray consists of four single units. Each single antenna unit consists of one vertically polarized port and one horizontally polarized port connected to power splitters, which serve as a feeding network. A stacked patch design is used to construct the single unit with the feeding network, which gives higher gain and lower mutual coupling within the size of a conversional dual-port patch antenna. Simulation results of the proposed single antenna unit, sub-array, and Massive MIMO array are verified by measurement.

A compact high directive EBG resonator antenna operating in two frequency bands is described. Two major contributions to this compact design are using single layer superstrate and using artificial surface as ground plane. To obtain only the lower operating frequency band using superstrate layer is enough, but to extract the upper operating frequency band both superstrate layer and artificial surface as ground plane are necessary. Therefore, design of a superstrate to work in two frequency bands is very important. Initially, using appropriate frequency selective surface (FSS) structure with square loop elements, we design an optimum superstrate layer for each frequency band separately to achieve maximum directivity. Also, to design an artificial surface to work in the upper frequency band we use a suitable FSS structure over dielectric layer backed by PEC. Next, by using the idea of FSS structure with double square loop elements we propose FSS structure with modified double square loop elements, so that it operates in both of the desired operating frequency bands simultaneously. Finally, the simulation results for two operating frequency bands are shown to have good agreement with measurements.

A simple circularly polarized (CP) loop tag antenna is proposed to overcome the polarization mismatch problem between reader antenna and tag antenna. Good CP radiation can be achieved by introducing an open gap onto the square loop. Also, the technique of loading a matching stub across the RFID chip is applied to the proposed loop tag antenna, and desirable impedance matching between the antenna and RFID chip can be realized by tuning the matching stub. The proposed loop tag antenna shows good reading distance performance, and its measured reading distance reaches to 17.6 m.

This paper presents the design, simulation, and measurement results of a 4-element uniform circular array (UCA) using dipole antenna elements with integrated microstrip tapered baluns to convert between balanced and unbalanced signals. These baluns are compact, integrated into the array support structure, and can provide a balanced signal over a relatively wide bandwidth. Simulation results are shown for the amplitude and phase balance of the balun from 1.6 GHz to 2.2 GHz. The array was fabricated and its manifold was measured in an anechoic chamber at a frequency of 1.7 GHz. The gain and phase responses of the array are presented and are compared to a simulated ideal dipole UCA in free-space.

For the synthetic aperture radar systems, there is an increasing demand for achieving resolutions of 0.2 mtimes0.2 m. As the range resolution and system bandwidth are inversely proportional, the system bandwidth is expected to be greater than 1 GHz. Thus an antenna with wider band needs to be developed. Waveguide slot antennas have been implemented on several SAR satellites due to its inherent advantages such as high efficiency and power handling capacity, but its bandwidth is quite limited. To avoid the manufacture difficulties of the ridge waveguide, which is capable of broadening the bandwidth of slot antennas, a novel antenna element with conventional waveguide is designed. The bandwidth of VSWR les1.5 is greater than 1 GHz at X-band. To reduce the mutual coupling of closely placed antenna elements, a decoupling method with cavity-like walls inserted between adjacent elements is adopted and their effects on the performance of the antenna are summarized.


Question: A 65-nm CMOS-based, 7.6 mW, 214-fs RMS jitter, 10-GHz phase-locked loop for a 40-Gb/s serial link transmitter utilizing a two-stage ring oscillator.

This paper offers an in-depth analysis of clock jitter and phase noise in both single-ended and differential ring oscillators. By employing impulse sensitivity functions, the authors derive mathematical expressions that elucidate the jitter and phase noise characteristics of ring oscillators. The study delves into how various factors, including the number of oscillator stages, power consumption, oscillation frequency, and short-channel effects, influence jitter and phase noise performance. Additionally, the impact of substrate and supply noise on these metrics is explored, with a particular focus on the role of symmetry in the upconversion of 1/f noise. The paper also presents novel design strategies aimed at minimizing jitter and phase noise. Experimental results confirm the accuracy of the theoretical predictions, showcasing the effectiveness of the proposed analysis.

**Question**: A Novel Approach for the Synthesis of Nanostructured Metal Oxides Using Microwave-Assisted Hydrothermal Synthesis

**Documents**: Microwave-assisted Hydrothermal Synthesis of Nanostructured Metal Oxides: A Review
This review article provides a comprehensive overview of the microwave-assisted hydrothermal synthesis technique for the production of nanostructured metal oxides. The advantages of using microwave energy for accelerating reactions and promoting the formation of uniform and well-crystallized nanostructures are discussed. The influence of various synthesis parameters, such as microwave power, reaction time, and precursor concentration, on the morphology, size, and crystallinity of the resulting metal oxide nanoparticles is analyzed. The review also highlights the importance of understanding the underlying reaction mechanisms and the role of microwave heating in the hydrothermal synthesis process. The potential applications of microwave-assisted hydrothermal synthesis in the field of materials science and nanotechnology are discussed, including its use in the production of catalysts, energy storage materials, and optical devices.

**Similar Documents**: This article offers an extensive review of microwave-assisted hydrothermal synthesis as a method for synthesizing nanostructured metal oxides. It delves into the benefits of utilizing microwave energy to expedite reactions and to facilitate the creation of uniformly sized and well-crystallized nanostructures. The paper explores how different synthesis conditions, such as microwave power intensity, reaction duration, and the concentration of precursors, affect the characteristics of the metal oxide nanoparticles, including their morphology, size, and crystalline structure. It also emphasizes the significance of gaining insight into the fundamental reaction mechanisms and the part played by microwave heating in the hydrothermal synthesis process. The review further discusses the potential of microwave-assisted hydrothermal synthesis in the materials science and nanotechnology sectors, particularly in the development of catalysts, energy storage

This letter presents a CMOS outphasing class-D power amplifier (PA) with a Chireix combiner. Two voltage-mode class-D amplifiers used in the outphasing system were designed and implemented with a 0.18-mum CMOS process. By applying the Chireix combiner technique, drain efficiency of the outphasing PA for CDMA signals was improved from 38.6% to 48% while output power was increased from 14.5 to 15.4 dBm with an adjacent channel power ratio of -45 dBc.

A high-speed SerDes must meet multiple challenges including high-speed operation, intensive equalization technique, low power consumption, small area and robustness. In order to meet new standards, such a OIF CEI-25G-LR, CEI-28G-MR/SR/VSR, IEEE802.3bj and 32G-FC, data-rates are increased to 25 to 28Gb/s, which is more than 75% higher than the previous generation of SerDes. For SerDes applications with several hundreds of lanes integrated in single chip, power consumption is very important factor while maintaining high performance. There are several previous works at 28Gb/s or higher data-rate [1-2]. They use an unrolled DFE to meet the critical timing margin, but the unrolled DFE structure increases the number of DFE slicers, increasing the overall power and die area. In order to tackle these challenges, we introduce several circuits and architectural techniques. The analog front-end (AFE) uses a single-stage architecture and a compact on-chip passive inductor in the transimpedance amplifier (TIA), providing 15dB boost. The boost is adaptive and its adaptation loop is decoupled from the decision-feedback equalizer (DFE) adaptation loop by the use of a group-delay adaptation (GDA) algorithm. DFE has a half-rate 1-tap unrolled structure with 2 total error latches for power and area reduction. A two-stage sense-amplifier-based slicer achieves a sensitivity of 15mV and DFE timing closure. We also develop a high-speed clock buffer that uses a new active-inductor circuit. This active-inductor circuit has the capability to control output-common-mode voltage to optimize circuit operating points.

A fully integrated step-down switched-capacitor dc–dc converter ring with 123 phases has been designed that could achieve fast dynamic voltage scaling for the microprocessor of wearable devices. The symmetrical multiphase converter ring surrounds its load in the square and supplies power to the on-chip power grid that is easily accessible at any point of the chip edges. The frequency of the <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula>-controlled oscillator is adjusted through its supply voltage <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula>, which allows the unity-gain frequency to be designed higher than the switching frequency. The converter ring has been fabricated in a low-leakage 65-nm CMOS process. This converter achieves a response time of 3 ns, a reference tracking speed of 2.5 V/<inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>, and a minimum output ripple of 2.2 mV. The peak efficiency is 80% at the power density of 66.6 mW/mm2, and the maximum power density is 180 mW/mm2.

This paper describes a single-channel, calibration-free Successive-Approximation-Register (SAR) ADC with a resolution of 10 bits at 240 MS/s. A DAC switching technique and an addition-only digital error correction technique based on the non-binary search are proposed to tackle the static and dynamic non-idealities attributed to capacitor mismatch and insufficient DAC settling. The conversion speed is enhanced, and the power and area of the DAC are also reduced by 40% as a result. In addition, a switching scheme lifting the input common mode of the comparator is proposed to further enhance the speed. Moreover, the comparator employs multiple feedback paths for an enhanced regeneration strength to alleviate the metastable problem. Occupying an active area of 0.003 mm 2 and dissipating 0.68 mW from 1 V supply at 240 MS/s in 28 nm CMOS, the proposed design achieves an SNDR of 57 dB with low-frequency inputs and 53 dB at the Nyquist input. This corresponds to a conversion efficiency of 4.8 fJ/c.-s. and 7.8 fJ/c.-s. respectively. The DAC switching technique improves the INL and DNL from +1.15/-1.01 LSB and +0.92/-0.28 LSB to within +0.55/-0.45 LSB and +0.45/-0.23 LSB, respectively. This ADC is at least 80% smaller and 32% more power efficient than reported state-of-the-art ADCs of similar resolutions and Nyquist bandwidths larger than 75 MHz.

A high-speed and high-resolution comparator intended to be implemented in a 12 bit 100 MHz pipeline analog-to-digital converter (ADC) for frequency wireless local area network application is proposed. The designed comparator presents a rail-to-rail input range preamplifier without any capacitance required. This comparator with a novel architecture of output stage achieves very high speed at a low kickback noise. The simulation results using a 0.35 mum TSMC CMOS process technology show that this comparator exhibits a propagation delay of 2.8 ns and has a very high resolution for a rail-to-rail input signal range, while consumes only 1.0 mW of power with 5.0 V voltage supply.

Phase, frequency, and amplitude of single-phase voltages are the most important and basic information required for single-phase grid-connected applications. This paper proposes a method for instantly and robustly estimating the phase, frequency, and amplitude of frequency-varying single-phase signals for such applications, which is a phase-locked loop (PLL) method based on a structure. The proposed method has the following attractive features: 1) the estimation system results in a nonlinear system, but it can be stabilized; 2) all subsystems constructing the system can be easily designed; 3) "two-phase signal generator"; can autotune a single system parameter in response to varying frequency of the injected signal; 4) high-order "PLL-Controllers" allowing fast tracking can be stably used; and 5) even in hostile envelopments, favorable instant estimates can be obtained. This paper proposes the estimation method and verifies its usefulness by extensive numerical experiments.

To realize a high-efficiency terahertz signal source, a varactor-based frequency-doubler topology is proposed. The structure is based on a compact partially coupled ring that simultaneously achieves isolation, matching, and harmonic filtering for both input and output signals at f0 and 2f0. The optimum varactor pumping/loading conditions for the highest conversion efficiency are also presented analytically along with intuitive circuit representations. Using the proposed circuit, a passive 480-GHz frequency doubler with a measured minimum conversion loss of 14.3 dB and an unsaturated output power of 0.23 mW is reported. Within 20-GHz range, the fluctuation of the measured output power is less than 1.5 dB, and the simulated 3-dB output bandwidth is 70 GHz (14.6%). The doubler is fabricated using 65-nm low-power bulk CMOS technology and consumes near zero dc power.

This paper presents a direct-conversion receiver for FCC-compliant ultra-wideband (UWB) Gaussian-shaped pulses that are transmitted in one of fourteen 500-MHz-wide channels within the 3.1-10.6-GHz band. The receiver is fabricated in 0.18-mum SiGe BiCMOS. The packaged chip consists of an unmatched wideband low-noise amplifier (LNA), filter, phase-splitter, 5-GHz ISM band switchable notch filter, 3.1-10.6-GHz local oscillator (LO) amplifiers, mixers, and baseband channel-select filters/buffers. The required quadrature single-ended LO signals are generated externally. The average conversion gain and input P1dB are 32 dB and -41 dBm, respectively. The unmatched LNA provides a system noise figure of 3.3 to 5 dB over the entire band. The chip draws 30 mA from 1.8 V. To verify the unmatched LNA's performance in a complete system, wireless testing of the front-end embedded in a full receiver at 100 Mbps reveals a 10-3 bit-error rate (BER) at -80 dBm sensitivity. The notch filter suppresses out-of-band interferers and reduces the effects of intermodulation products that appear in the baseband. BER improvements of an order of magnitude and greater are demonstrated with the filter

Two novel level shifters that are suitable for block-level dynamic voltage scaling environment (namely, V/sub DD/-hopping) are proposed. In order to achieve reduction in power consumption and delay, the first proposed level shifter which is called contention mitigated level shifter (CMLS) uses a contention-reduction technique. The simulation results with 65-nm CMOS model show 24% reduction in power and 50% decrease in delay with 4% area increase compared with the conventional level shifter. The second proposed level shifter which is called bypassing enabled level shifter (BELS) implements a bypass function and it is fabricated using 0.35/spl mu/m CMOS technology. The measurement results show that the power and delay of the proposed BELS are reduced by 50% and 65%, respectively with 60% area overhead over the conventional level shifter.

The synthesis of linear frequency sweeps or chirps is required, among others, in frequency-modulated continuous-wave radar systems for object position estimation. Low phase and frequency errors in sweeps with high bandwidth are a prerequisite for good accuracy and resolution, but, in certain applications where high measurement rates are desired, the additional demand for short sweep cycles has to be met. Transient phenomena in dynamic synthesizers as well as nonlinear system behavior usually cause unknown phase errors in the system output. For the class of phase-locked-loop (PLL)-based frequency synthesizers, a novel output phase-measurement method and dedicated circuitry are proposed that allow significant reduction of phase errors by adaptive input predistortion. The measurement procedure is implemented within the PLL control circuitry and does not require external equipment. The application of this method to PLL system identification and linearization of extremely short frequency sweeps is shown


Question: A 65-nm CMOS-based 7.6 mW, 214-fs RMS jitter, 10-GHz phase-locked loop for a 40-Gb/s serial link transmitter utilizing a two-stage ring oscillator.

This paper introduces a comprehensive model for injection-locked LC oscillators (LC-ILOs), applicable across various tank quality factors and injection strengths. The model elucidates key characteristics of LC-ILOs, including lock-range, phase shift, bandwidth, and their response to input jitter. The practical application of this model is demonstrated through the implementation of an LC-ILO in conjunction with a half-rate data sampler, forming a forwarded-clock I/O receiver in 45-nm CMOS technology. By employing a strongly-injected low-Q LC oscillator, the receiver achieves effective clock deskew across 1UI and successfully mitigates high-frequency clock jitter. The complete 27 Gb/s data receiver, based on this LC-ILO design, exhibits an impressive overall power efficiency of 1.6 mW/Gb/s, showcasing the model's utility in real-world high-speed communication systems.

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without lowthreshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 0.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

Fractional-N phase-locked loop frequency synthesizers based on time-to-digital converters (TDC-PLLs) have been proposed to reduce the area and linearity requirements of conventional PLLs based on delta-sigma modulation and charge pumps (ΔΣ-PLLs). Although TDC-PLLs with good performance have been demonstrated, TDC quantization noise has so far kept their phase noise and spurious tone performance below that of the best comparable ΔΣ-PLLs. An alternative approach is to use a delta-sigma frequency-to-digital converter (ΔΣ FDC) in place of a TDC to retain the benefits of TDC-PLLs and ΔΣ-PLLs. This paper proposes a practical ΔΣ FDC based PLL in which the quantization noise is equivalent to that of a ΔΣ-PLL. It presents a linearized model of the PLL, design criteria to avoid spurious tones in the ΔΣFDC quantization noise, and a design methodology for choosing the loop parameters in terms of standard PLL target specifications.

In this work, a miniature ultra-wideband (UWB) power divider (PD) is proposed. By implementing the transmission lines of a two-stage Wilkinson PD using bridged T-coils, very compact size with no reduction in bandwidth can be achieved. Specifically, a proposed UWB two-way PD with a center frequency f0=5.5 GHz is implemented using the commercial GaAs pHEMT process. The circuit size without pads is only 1.45 mm × 0.84 mm, which is about 0.027λ0 × 0.016λ0 at f0. The fractional bandwidth for 15-dB input/output return loss and isolation is 110%, and the in-band insertion loss is within 1.3 ± 0.36 dB.

The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 μm2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.

In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL

Demand for system-on-chip solutions has increased the interest in low drop-out (LDO) voltage regulators which do not require a bulky off-chip capacitor to achieve stability, also called capacitor-less LDO (CL-LDO) regulators. Several architectures have been proposed; however comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This paper compares CL-LDOs in a unified matter. We designed, fabricated, and tested five illustrative CL-LDO regulator topologies under common design conditions using 0.6?m CMOS technology. We compare the architectures in terms of (1) line/load regulation, (2) power supply rejection, (3) line/load transient, (4) total on-chip compensation capacitance, (5) noise, and (6) quiescent power consumption. Insights on what optimal topology to choose to meet particular LDO specifications are provided.

Recent advances in MEMS-based oscillators have resulted in their proliferation in timing applications that were once exclusive to quartz-based devices [1]. For applications requiring low phase noise - e.g., cellular, GPS and high-speed serial links - one possible approach is to bias the MEMS resonator at a higher DC voltage to reduce its motional impedance and increase signal energy [2]. Realizing high-voltage charge pumps in bulk CMOS technology is limited by the breakdown voltage of the well/substrate diodes shown in Fig. 23.8.1(a) and Fig. 23.8.1(b). This breakdown limit is even lower with technology scaling and is <;10V in a 22nm CMOS node. Systems with high-voltage requirements often resort to older, high-voltage-tolerant nodes or exotic technologies that limit MEMS integration into SoCs. This work demonstrates a charge pump design in 65nm technology with a three-fold increase in the output voltage range. Highvoltage tolerance is enabled by the proposed well-biasing arrangement and oxide isolation. The pump achieves 34V output by using three different charge pump cells that tradeoff achievable voltage range and power efficiency to achieve a peak efficiency of 38%. Additionally, finger capacitors are optimized to ensure reliability while maintaining efficiency.

A 1.8-GHz CMOS power amplifier for a polar transmitter is implemented with a 0.18- RF CMOS process. The matching components, including the input and output transformers, were integrated. A dual-primary transformer is proposed in order to increase the efficiency in the low power region of the amplifier. The loss induced by the matching network for the low-output power region is minimized using the dual-primary transformer. The amplifier achieved a power-added efficiency of 40.7% at a maximum output power of 31.6 dBm. The dynamic range was 34 dB for a supply voltage that ranged from 0.5 to 3.3 V. The low power efficiency was 32% at the output power of 16 dBm.

Linear time-invariant (LTI) phase noise theories provide important qualitative design insights but are limited in their quantitative predictive power. Part of the difficulty is that device noise undergoes multiple frequency translations to become oscillator phase noise. A quantitative understanding of this process requires abandoning the principle of time invariance assumed in most older theories of phase noise. Fortunately, the noise-to-phase transfer function of oscillators is still linear, despite the existence of the nonlinearities necessary for amplitude stabilization. In addition to providing a quantitative reconciliation between theory and measurement, the time-varying phase noise model presented in this tutorial identifies the importance of symmetry in suppressing the upconversion of 1/f noise into close-in phase noise, and provides an explicit appreciation of cyclostationary effects and AM-PM conversion. These insights allow a reinterpretation of why the Colpitts oscillator exhibits good performance, and suggest new oscillator topologies. Tuned LC and ring oscillator circuit examples are presented to reinforce the theoretical considerations developed. Simulation issues and the accommodation of amplitude noise are considered in appendixes.

A 1.8V CMOS chopper four-quadrant analog multiplier, intending to serve as an autonomous IC block for low-frequency signal processing, is presented. Particular emphasis is laid upon achieving low output noise by means of chopper stabilization, while the multiplier's operation is based on the MOS Translinear Principle. The proposed design has been implemented and simulated in TSMC 0.18 µm CMOS process.


Question: A 65-nm CMOS-based phase-locked loop operating at 10 GHz with a 7.6 mW power consumption, 214-fs RMS jitter, and utilizing a two-stage ring oscillator for 40-Gb/s serial link transmitter applications.

This paper delves into the investigation of injection locking and pulling phenomena in oscillators, offering a comprehensive analysis that elucidates these effects in both time and frequency domains. By employing an identity derived from phase and envelope equations, the paper explicates the inherent nonlinearity of oscillators and its role in phase noise suppression. Moreover, it provides insights into the dynamics of phase-locked oscillators when subjected to injection pulling, thereby contributing to a deeper understanding of their behavior under such conditions.

In the context of a high-performance 40-Gb/s serial link transmitter, a 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop (PLL) is designed and implemented using a two-stage ring oscillator in 65-nm CMOS technology. The PLL's exceptional jitter performance is achieved through careful optimization of the ring oscillator stages and the phase-frequency detector, showcasing the effectiveness of the design in achieving low jitter operation. This work highlights the importance of understanding injection locking and pulling in oscillators, particularly in the design of high-speed serial link transmitters, where minimizing phase noise and jitter is crucial for reliable data transmission.

This paper describes a transmitter driver based on a CMOS inverter with a resistive feedback. By employing the proposed driver topology, the pre-driver can be greatly simplified, resulting in a remarkable reduction of the overall driver power consumption. It also offers another advantage that the implementation of equalization is straightforward, compared with a conventional voltage-mode driver. Furthermore, the output impedance remains relatively constant while the data is being transmitted, resulting in good signal integrity. For evaluation of the driver performance, a fully functional 20 Gb/s transmitter is implemented, including a PRBS generator, a serializer, and a half-rate clock generator. In order to enhance the overall speed of the digital circuits for 20 Gb/s data transmission, the resistive feedback is applied to the time-critical inverters, which enables shorter rise/fall times. The prototype chip is fabricated in a 65 nm CMOS technology. The implemented driver circuit operates up to the data rate of 20 Gb/s, exhibiting an energy efficiency of 0.4 pJ/b for the output swing of 250 mVpp,diff.

A novel multiple-event Time to Digital Converter (TDC) with direct to histogram output is implemented in a 65nm Xilinx Virtex 5 FPGA. The delay-line based architecture achieves 16.3 ps temporal accuracy over a 2.86ns dynamic range. The measured maximum conversion rate of 6.17 Gsamples/s and the sampling rate of 61.7 Gsamples/s are the highest published in the literature. The system achieves a linearity of -0.9/+3 LSB DNL and -1.5/+5 LSB INL. The TDC is demonstrated in a direct time of flight optical ranging application with 12mm error over a 350mm range.

We report a 107 GHz baseband differential transimpedance amplifier IC for high speed optical communication links. The amplifier, comprised of two Darlington resistive feedback stages, was implemented in a 500 nm InP HBT process and demonstrates 55 dBΩ differential transimpedance gain, 30 ps group delay, P1dB = 1 dBm, and is powered by a 5.2 V supply. Differential input and output impedances are 50Ω. The IC interfaces to -2V DC at the input for connections to high-speed photodiodes and -450 mV DC at the output for interfaces to Gilbert-cell mixers and to ECL logic.

In this paper a design and comparison between a fully differential RC Miller compensated CMOS op-amp and conventional op-amp is presented. High gain enables the circuit to operate efficiently in a closed loop feedback system, whereas high bandwidth makes it suitable for high speed applications. A novel RC Miller compensation technique is used to optimize the parameters of gain and bandwidth for high speed applications are illustrated in this research work. The design is also able to address any fluctuation in supply or dc input voltages and stabilizes the operation by nullifying. The design is implemented on TSMC 0.18 m CMOS process at 3.3 V as supply voltage under room temperature 27 C. The simulated result shows that a unity gain bandwidth of 136.8 MHz with a high gain of 92.27 dB is achieved for the proposed op-amp circuit. The total areas of the layouts are 0.000158 mm and 0.000532 mm for conventional and proposed respectively. Key wrods: Two-Stage Op-amp, fully differential, high gain, high bandwidth

This paper demonstrates a 16-element phased-array transmitter in a standard 0.18-mum SiGe BiCMOS technology for Q-band satellite applications. The transmitter array is based on the all-RF architecture with 4-bit RF phase shifters and a corporate-feed network. A 1:2 active divider and two 1:8 passive tee-junction dividers constitute the corporate-feed network, and three-dimensional shielded transmission-lines are used for the passive divider to minimize area. All signals are processed differentially inside the chip except for the input and output interfaces. The phased-array transmitter results in a 12.5 dB of average power gain per channel at 42.5 GHz with a 3-dB gain bandwidth of 39.9-45.6 GHz. The RMS gain variation is < 1.3 dB and the RMS phase variation is < for all 4-bit phase states at 35-50 GHz. The measured input and output return losses are < -10 dB at 36.6-50 GHz, and <-10 dB at 37.6-50 GHz, respectively. The measured peak-to-peak group delay variation is plusmn 20 ps at 40-45 GHz. The output P-1dB is -5plusmn1.5 dBm and the maximum saturated output power is - 2.5plusmn1.5 dBm per channel at 42.5 GHz. The transmitter shows <1.8 dB of RMS gain mismatch and < 7deg of RMS phase mismatch between the 16 different channels over all phase states. A - 30 dB worst-case port-to-port coupling is measured between adjacent channels at 30-50 GHz, and the measured RMS gain and phase disturbances due to the inter-channel coupling are < 0.15 dB and < 1deg, respectively, at 35-50 GHz. All measurements are obtained without any on-chip calibration. The chip consumes 720 mA from a 5 V supply voltage and the chip size is 2.6times3.2 mm2.

In this paper a class-D audio amplifier for mobile applications is presented realized in a 0.14 μm CMOS technology tailored for mobile applications. The amplifier has a simple PDM-based digital interface for audio and control that requires only two pins and enables assembly in 9-bump WL-CSP. The complete audio path is discussed that consists of a Parser, Digital PWM controller, 1-bit DA-converters, analog feedback loop and the Class-D power stage. A reconfigurable gate driver is used that reduces quiescent current consumption and radiated emission.

A single-chip 65GHz Doppler radar transceiver with on-chip patch antenna is reported. Implemented in a production 0.18mum SiGe BiCMOS process, it features a differential output transmit power of 4.3dBm, 16.5dB single-ended down-conversion gain and a double-sideband noise figure of 12.8dB. The radar includes a 65GHz 2-stage cascode LNA with S 11<-15dB at 50-94GHz and 14dB gain at 65GHz, a double-balanced down-convert mixer, a SiGe HBT IF amplifier with low 1/f noise, a VCO and a 65GHz output buffer. The LO is provided by an integrated varactor-tuned 61-67GHz VCO optimized for low phase noise. The patch antenna is designed to be impedance-matched for dual-band operation at 62.8 and 64.6GHz. The use of lumped inductors in all blocks and a vertically-stacked transformer for single-ended to differential conversion in the receive path help reduce the transceiver area to 1mm times 1mm

This letter presents a CMOS outphasing class-D power amplifier (PA) with a Chireix combiner. Two voltage-mode class-D amplifiers used in the outphasing system were designed and implemented with a 0.18-mum CMOS process. By applying the Chireix combiner technique, drain efficiency of the outphasing PA for CDMA signals was improved from 38.6% to 48% while output power was increased from 14.5 to 15.4 dBm with an adjacent channel power ratio of -45 dBc.

This paper reports a full-rate direct decision-feedback-equalization (DFE) receiver with circuit techniques to widen the data eye opening with competitive power and area efficiencies. Specifically, a current-reuse active-inductor (AI) linear equalizer is merged into a clocked-one-tap DFE core for joint-elimination of pre-cursor and long-tail post-cursors. Unlike the passive-inductor designs that are bulky and untunable, the AI linear equalizer offers orthogonally tunable low- and high-frequency de-emphasis. The clocked-one-tap DFE resolves the first post-cursor via return-to-zero feedback data patterns for sharper data transition (i.e., horizontal eye opening), and is followed by a D-flip-flop slicer to maximize the data height (i.e., vertical eye opening). A 10-Gb/s DFE receiver was fabricated in 65-nm CMOS. Measured over an 84-cm printed circuit board differential trace with 23.3-dB channel loss at Nyquist frequency (5 GHz), the achieved figure-of-merit is 0.027 pJ/bit/dB (power consumption/date rate/channel loss). At 10-12 bit error rate under 27-1 pseudorandom binary sequence, the horizontal and vertical eye opening are 59.6% and 189.3 mV, respectively. The die size is 0.002 mm2.

This paper presents the co-design of 0.5V operational band-gap reference (BGR) and 32kHz crystal oscillator (XO) in 40nm CMOS process. The proposed BJT-based BGR offers 10× resistor area reduction compared to the conventional BGR. The proposed XO provides trans-conductance enhancement without the need for large coupling capacitor and uses a feedback loop to regulate its bias current, oscillation amplitude across PVT. The total power consumption is less than 49nW from −40°C to 120°C. Without any trimming, the BGR achieves temperature coefficients of 8ppm/°C and XO has temperature coefficient of 0.25ppm/°C. The BGR offers 5× lower area, 2× lower power consumption at 120°C compared to prior work on resistor-based, non-duty cycled BGR. The XO improves power consumption by at least 2× compared to prior work at 120°C, 0.5V supply.


Question: A 65-nm CMOS-based, 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for a 40-Gb/s serial link transmitter using a two-stage ring oscillator.

This study delves into the phase noise characteristics of two inductorless CMOS oscillators, providing a comprehensive analysis of their noise behavior. By applying a first-order examination of a linear oscillatory system, we derive a noise shaping function and propose an innovative definition of Q. A linear model is employed to assess the phase noise of CMOS ring oscillators, leading to the identification and formulation of three distinct phase noise phenomena: additive noise, high-frequency multiplicative noise, and low-frequency multiplicative noise. Drawing parallels, the phase noise of a CMOS relaxation oscillator is also analyzed using the same foundational concepts. The paper further discusses the methodologies and challenges associated with time-domain noise simulation. Two experimental models, fabricated using a 0.5m CMOS technology, are utilized to validate the theoretical predictions. When compared to empirical results, the calculated phase noise values of a 2-GHz ring oscillator and a 900-MHz relaxation oscillator at a 5 MHz offset exhibit an error margin of approximately 4 dB, demonstrating the accuracy of the theoretical analysis.

A two-stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. With the common-gate configuration employed as the input stage, the broad-band input matching is obtained and the noise does not rise rapidly at higher frequency. By combining the common-gate and common-source stages, the broad-band characteristic and small area are achieved by using two inductors. This LNA has been fabricated in a 0.18-mum CMOS process. The measured power gain is 11.2-12.4 dB and noise figure is 4.4-6.5 dB with -3-dB bandwidth of 0.4-10 GHz. The measured IIP3 is -6 dBm at 6 GHz. It consumes 12 mW from a 1.8-V supply voltage and occupies only 0.42 mm2

A high-speed SerDes must meet multiple challenges including high-speed operation, intensive equalization technique, low power consumption, small area and robustness. In order to meet new standards, such a OIF CEI-25G-LR, CEI-28G-MR/SR/VSR, IEEE802.3bj and 32G-FC, data-rates are increased to 25 to 28Gb/s, which is more than 75% higher than the previous generation of SerDes. For SerDes applications with several hundreds of lanes integrated in single chip, power consumption is very important factor while maintaining high performance. There are several previous works at 28Gb/s or higher data-rate [1-2]. They use an unrolled DFE to meet the critical timing margin, but the unrolled DFE structure increases the number of DFE slicers, increasing the overall power and die area. In order to tackle these challenges, we introduce several circuits and architectural techniques. The analog front-end (AFE) uses a single-stage architecture and a compact on-chip passive inductor in the transimpedance amplifier (TIA), providing 15dB boost. The boost is adaptive and its adaptation loop is decoupled from the decision-feedback equalizer (DFE) adaptation loop by the use of a group-delay adaptation (GDA) algorithm. DFE has a half-rate 1-tap unrolled structure with 2 total error latches for power and area reduction. A two-stage sense-amplifier-based slicer achieves a sensitivity of 15mV and DFE timing closure. We also develop a high-speed clock buffer that uses a new active-inductor circuit. This active-inductor circuit has the capability to control output-common-mode voltage to optimize circuit operating points.

The push for 100Gb/s optical transport and beyond necessitates electronic components at higher speed and integration level in order to drive down cost, complexity and size of transceivers [1-2]. This requires parallel multi-channel optical transceivers each operating at 25Gb/s and beyond. Due to variations in the output power of transmitters and in some cases different optical paths the parallel receivers have to operate at different input optical power levels. This trend places increasing strain to the acceptable inter-channel crosstalk in integrated multi-channel receivers [3]. Minimizing this cross-talk penalty when all channels are operational is becoming increasingly important in ultra-high throughput optical links.

In this article, the large-signal, small-signal, and noise performance of the Cherry-Hooper amplifier with emitter-follower feedback are analyzed from a design perspective. A method for choosing the component values to obtain a low group delay distortion or Bessel transfer function is given. The design theory is illustrated with an implementation of the circuit in a 47-GHz SiGe process. The amplifier has 19.7-dB gain, 13.7-GHz bandwidth, and /spl plusmn/10-ps group delay distortion. The amplifier core consumes 34 mW from a -3.3-V supply.

We have developed a flip-chip interconnection technique to solve the problem of the degradation of the modulation bandwidth of an optical transmitter due to the parasitic inductance of bonding wire. And we have fabricated an LE-EA-DFB laser module that has a 3-dB bandwidth of 59 GHz thanks to our flip-chip interconnection technique. The fabricated optical receiver, which includes a wideband electrical amplifier, has a 3-dB bandwidth of 51 GHz. Using these optical modules with a 3-dB bandwidth of more than 50 GHz, we have obtained a bit-error rate of less than 2 × 10-4, which is an error-free condition using KP4 forward error correction, under 53.2-Gbaud 4-level pulse amplitude modulation (4-PAM) operation without an equalizer even after a 2-km transmission through single-mode fiber.

This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10-100× smaller than the noise generated by a static CMOS circuit. Unlike static CMOS, whose dominant dynamic power is proportional to the frequency, MCML circuits dissipate a constant power independent of clock frequency. Although these traits make MCML highly energy efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at the modest clock rate and with a low activity factor. To address this challenge, a single-core microarchitecture for MCML is explored that exploits the C-slow retiming technique, and operates at a high frequency with low complexity to save energy. This design principle contrasts with the contemporary multicore design paradigm for static CMOS that relies on a large number of gates operating in parallel at the modest speeds. The proposed architecture generates 10-40× lower power and ground noise, and operates within 13% of the performance (i.e., 1/ExecutionTime) of a conventional, eight-core static CMOS processor while exhibiting 1.6× lower energy and 9% less area. Moreover, the operation of an MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length.

A CMOS low noise amplifier (LNA) for ultra-wideband (UWB) systems is presented. The proposed LNA achieve wide operating bandwidth for 3–10.6 GHz by using resistive shunt feedback topology. Two stage amplifiers and an inter stage circuit are designed to achieve wider gain bandwidth. The shunt resistive feedback are employed in input and output stage to provide wideband input matching with low noise figure (NF). This work is designed and fabricated in TSMC 0.18µm CMOS process. The proposed UWB LNA achieves a measured flat gain 15 dB and has a noise figure of 4 dB over the entire band while consuming 21.5 mW of power. The measured third order intercept point IIP3 is 2.5 dBm.

Phase, frequency, and amplitude of single-phase voltages are the most important and basic information required for single-phase grid-connected applications. This paper proposes a method for instantly and robustly estimating the phase, frequency, and amplitude of frequency-varying single-phase signals for such applications, which is a phase-locked loop (PLL) method based on a structure. The proposed method has the following attractive features: 1) the estimation system results in a nonlinear system, but it can be stabilized; 2) all subsystems constructing the system can be easily designed; 3) "two-phase signal generator"; can autotune a single system parameter in response to varying frequency of the injected signal; 4) high-order "PLL-Controllers" allowing fast tracking can be stably used; and 5) even in hostile envelopments, favorable instant estimates can be obtained. This paper proposes the estimation method and verifies its usefulness by extensive numerical experiments.

This paper presents a 64 GHz transmit/receive communication link between two 32-element SiGe-based phased arrays. The antenna element is a series-fed patch array, which provides directivity in the elevation plane. The transmit array results in an EIRP of 42 dBm, while the receive array provides an electronic gain of 33 dB and a system NF < 8 dB including the T/R switch and antenna losses. The arrays can be scanned to +/−50° in the azimuth using a 5-bit phase shifter on the SiGe chip, while keeping very low sidelobes and a near-ideal pattern. The communication link uses one array on the transmit side and another array on the receive side, together with external mixers and IF amplifiers. A Keysight M8195A arbitrary waveform generator is used to generate the modulated waveforms on the transmit side and a Keysight DSO804A oscilloscope is used to demodulate the received IF signal. The link performance was measured for different scan angles and modulation formats. Data rates of 1 Gbps using 16-QAM and 2 Gbps using QPSK are demonstrated at 300 m. The system also results in > 4 Gbps data rate at 100 meters, and ∼ 500 Mbps data rate at 800 meters.

Low frequency noise of NMOS and PMOS transistors in a 0.25 /spl mu/m foundry CMOS process with a pure SiO/sub 2/ gate oxide layer is characterized for the entire range of MOSFET operation. Surprisingly, the measurement results showed that surface channel PMOS transistors have about an order of magnitude lower 1/f noise than NMOS transistors especially at V/sub GS/-V/sub TH/ less than /spl sim/0.4 V The data were used to show that a VCO using all surface channel PMOS transistors can have /spl sim/14 dB lower close-in phase noise compared to that for a VCO using all surface channel NMOS transistors.


Question: A 65-nm CMOS-based, 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for a 40-Gb/s serial link transmitter using a two-stage ring oscillator design.

This paper introduces a 27Gb/s forwarded-clock I/O receiver that employs a differential injection-locked LC-DCO for filtering and deskewing the link clock, showcasing its operation at high-speed data transmission rates. The design leverages a novel technique to effectively manage clock synchronization and filtering, making it suitable for high-speed serial links. By utilizing an injection-locked LC-DCO, the receiver achieves robust performance at 27 Gb/s, demonstrating its capability to handle high data rates in advanced communication systems.

**Question**: A Direct Search Method to solve Economic Dispatch Problem with Valve-Point Effect

**Documents**: A novel hybrid GA-PSO algorithm for economic dispatch problem with valve-point effect
A novel hybrid algorithm combining genetic algorithm (GA) and particle swarm optimization (PSO) is proposed for solving the economic dispatch problem with valve-point effect. The proposed algorithm, named HGA-PSO, incorporates the global search ability of GA with the local search capability of PSO to efficiently explore the solution space. In HGA-PSO, the initial population is generated using GA, and then the best individuals are refined using PSO. This hybrid approach ensures a balance between exploration and exploitation, which is crucial for solving complex optimization problems like the economic dispatch with valve-point effect. The proposed HGA-PSO algorithm is tested on several benchmark problems and its performance is compared with that of standard GA and PSO algorithms. The results show that HGA-PSO outperforms the conventional algorithms in terms of solution quality and convergence speed.

**Similar Documents**: This paper presents a hybrid GA-PSO algorithm, termed HGA-PSO, specifically designed to tackle the economic dispatch problem in the presence of valve-point effect. The algorithm integrates the strengths of genetic algorithms (GA) for global search with the precision of particle swarm optimization (PSO) for local search, creating a powerful tool for navigating the solution space. HGA-PSO begins with an initial population generated by GA, followed by the refinement of top-performing individuals using PSO. This dual approach ensures a harmonious blend of exploration and exploitation, essential for addressing intricate optimization challenges such as the economic dispatch with valve-point effect. The effectiveness of HGA-PSO is validated through its application to various benchmark problems, where it demonstrates superior performance compared to traditional GA and PSO algorithms in terms of solution quality and convergence rate.

A half-rate decision feedback equalizer (DFE) with two infinite impulse response (IIR) filters and one discrete-time tap is presented. The two IIR filters have different time constants to cancel the long tail of the pulse response. The discrete-tap cancels the first post-cursor inter-symbol interference term. The system can operate with a low transmit swing of 150mVpp-diff and 24 dB channel loss at the Nyquist frequency while consuming 4.1mW at 10 Gb/s. The receiver, including the DFE, clock buffers and clock phase adjustment, occupies an area of 8,760 μm2 and was fabricated in an ST 28nm LP CMOS process.

A 1.8V CMOS chopper four-quadrant analog multiplier, intending to serve as an autonomous IC block for low-frequency signal processing, is presented. Particular emphasis is laid upon achieving low output noise by means of chopper stabilization, while the multiplier's operation is based on the MOS Translinear Principle. The proposed design has been implemented and simulated in TSMC 0.18 µm CMOS process.

(ABSTRACT) Analogcircuit/IC design for high speed optical fiber communication is a fairly new research area in Dr. Ha's group. In the first project sponsored by ETRI (Electronics and Telecommunication Research Institute) we started to design the building blocks of receiver for next generation 400 Gb/s optical fiber communication. In this thesis research a transceiver architecture based on 4x100 Gb/s parallel communication is proposed. As part of the receiver, a transimpedance amplifier for 100 Gb/s optical communication is designed, analyzed and simulated. Simulation results demonstrate the excellent feasibility of proposed architecture. always dominated the high speed optical transceiver design because of their inherent properties of high mobility and low noise. But they are power hungry and bulky in size which made them less attractive for highly integrated circuit design. On the contrary, CMOS technology always drew attraction because of low cost, low power dissipation and high level of integration facility. But their notorious parasitic characteristic and inferior noise performance makes high speed transceiver design very challenging. The emergence of nano-scale CMOS offer highly scaled feature sized transistors with transition frequencies exceeding 200 GHz and can improve optical receiver performance significantly. Increasing bandwidth to meet the target data rate is the most challenging task of TIA design especially in CMOS technology. Several CMOS TIA architectures have been published recently [6]-[11] for 40 Gb/s data rate having bandwidth no more than 40 GHz. In contrast to existing works, the goal of this research is to step further and design a single channel stand-alone iii TIA compatible in serial 100 Gb/s data rate with enhanced bandwidth and optimized transimpedance gain, input referred noise and group delay variation. A 100 Gb/s transimpedance amplifier (TIA) for optical receiver front end is designed in this work. To achieve wide bandwidth and low group delay variation a differential TIA with active feedback network is proposed. Proposed design also combines regulated cascode front end, peaking inductors and capacitive degeneration to have wide band response. Simulation results show 70 GHz bandwidth, 42 dBΩ transimpedance gain and 2.8 ps of group delay variation for proposed architecture. Input referred noise current density is 26 pA/√ while the total power dissipation from 1.2V supply is 24mW. Performance of the proposed TIA is compared with other existing TIAs, and the proposed TIA shows significant improvement in bandwidth and group delay variation compared to other existing TIA architectures. iv To my parents v Acknowledgements First …

A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35nm while not scaling the gate oxide as a means to improve performance and reduce power. Increased NMOS and PMOS drive currents are achieved by enhanced channel strain and junction engineering. 193nm lithography along with APSM mask technology is used on critical layers to provide aggressive design rules and a 6-T SRAM cell size of 0.57/spl mu/m/sup 2/. Process yield, performance and reliability are demonstrated on a 70 Mbit SRAM test vehicle with >0.5 billion transistors.

A CMOS low noise amplifier (LNA) for ultra-wideband (UWB) systems is presented. The proposed LNA achieve wide operating bandwidth for 3–10.6 GHz by using resistive shunt feedback topology. Two stage amplifiers and an inter stage circuit are designed to achieve wider gain bandwidth. The shunt resistive feedback are employed in input and output stage to provide wideband input matching with low noise figure (NF). This work is designed and fabricated in TSMC 0.18µm CMOS process. The proposed UWB LNA achieves a measured flat gain 15 dB and has a noise figure of 4 dB over the entire band while consuming 21.5 mW of power. The measured third order intercept point IIP3 is 2.5 dBm.

We developed 1.3 μm, EML module built in EML driver IC for both 50 and 56 Gbit/s. 40-km SMF transmission with clear eye openings under 56 Gbit/s operation were demonstrated for the first time.

The design of a 12.77-MHz on-chip RC relaxation oscillator with digital compensation technique is presented. To maintain the frequency stability versus temperature and supply voltage variations, loop delay tuning by a digital feedback loop is developed in this system. In order to generate an on-chip reference for digital calibration, a replica comparator is added. The on-chip relaxation oscillator is fabricated in 0.18-μm CMOS process. The measured output frequency variation is 31 ppm/°C across -30 to 120 °C temperature range after compensation. The frequency variation over the supply voltage from 0.6 V to 1.1 V is ±0.5%/V. The measured total power consumption is 56.2 μW at 0.9-V supply voltage when the digital compensation blocks are enabled. After digital compensation, the compensation blocks can be shutdown for power saving, and the main oscillator consumes only 12.8 μW.

In this work, we present a novel ultra-low power timer designed using the gate leakage of MOS capacitors. The test chip was fabricated in a 0.13 mum CMOS technology and the total circuit area is 480 mum2. Measurement results show that the circuit functions correctly at a wide range of supply voltages from 300 mV to 1.2 V, making it particularly suitable for subthreshold systems. The temperature sensitivity is 0.16%/degC at 600 mV and 0.6%/degC at 300 mV. The power dissipation is less than 1pW running at 20degC and 300 mV.

This paper presents a recursive digital low-dropout (RLDO) regulator that improves response time, quiescent power, and load regulation dynamic range over prior digital LDO designs by 1–2 orders of magnitude. The proposed RLDO enables a practical digital replacement to analog LDOs by using an SAR-like binary search algorithm in a coarse loop and a sub-LSB pulse width modulation duty control scheme in a fine loop. A proportional-derivative compensation scheme is employed to ensure stable operation independent of load current, the size of the output decoupling capacitor, and clock frequency. Implemented in 0.0023 mm2 in 65 nm CMOS, the 7-bit RLDO achieves, at a 0.5-V input, a response time of 15.1 ns with a figure of merit of 199.4 ps, along with stable operation across a 20 000 $\times $  dynamic load range.

Traditional YIG tuned oscillators use negative resistance type circuits and large magnetic structure to produce excellent phase noise with octave plus tuning ranges, but at the expense of size and weight. This paper describes a revolutionary approach to YIG tuned oscillator design which makes use of a unique combination of a miniaturized magnetic structure, and a GaAs HBT ring oscillator circuit topology, working through a YIG tuned filter to produce octave tuning ranges in X and Ku bands with phase noise less than -125 dBC per Hz at 100 KHz. Frequency pulling is less than 10 KHz into a 2:1 VSWR load over all phases. Simulations and measured data are in excellent agreement