Question: Advancing towards brain-activity-driven information search: interpreting image relevance from MEG signals.

This paper offers a comprehensive tutorial on the application of machine learning classifiers to functional Magnetic Resonance Imaging (fMRI) data for the purpose of decoding stimuli, mental states, behaviors, and other variables of interest. The analysis of complex, multivariate data from brain imaging experiments has increasingly turned to machine learning algorithms to train classifiers capable of extracting meaningful information from fMRI datasets. The paper delves into the critical decisions involved in this process, as well as the methodology for achieving statistically significant outcomes. Using a case study as an illustrative example, the authors highlight how classifiers can not only determine whether information about a variable of interest exists (pattern discrimination) but also address more nuanced questions such as where this information is located within the brain (pattern localization) and the nature of its encoding (pattern characterization). This approach expands the scope of fMRI analysis, offering insights into the neural mechanisms underlying various cognitive and behavioral processes.

This paper surveys the use of Spreading Activation techniques onSemantic Networks in Associative Information Retrieval. The majorSpreading Activation models are presented and their applications toIR is surveyed. A number of works in this area are criticallyanalyzed in order to study the relevance of Spreading Activation forassociative IR.

This paper describes a brain-machine interface for the online control of a powered lower-limb exoskeleton based on electroencephalogram (EEG) signals recorded over the user’s sensorimotor cortical areas. We train a binary decoder that can distinguish two different mental states, which is applied in a cascaded manner to efficiently control the exoskeleton in three different directions: walk front, turn left and turn right. This is realized by first classifying the user’s intention to walk front or change the direction. If the user decides to change the direction, a subsequent classification is performed to decide turn left or right. The user’s mental command is conditionally executed considering the possibility of obstacle collision. All five subjects were able to successfully complete the 3-way navigation task using brain signals while mounted in the exoskeleton. We observed on average 10.2% decrease in overall task completion time compared to the baseline protocol. August 25, 2016 DRAFT

Functional near infrared spectroscopy (NIRS) is a promising new tool for research in human-robot interaction (HRI). The use of NIRS in HRI has already been demonstrated both as a means for investigating brain activity during human-robot interactions, as well as in the development of brain-robot interfaces that passively monitor a person’s cognitive state to adapt robots’ behaviors accordingly. In this paper, we survey the utility of NIRS and its range of applications in HRI. We discuss both some exemplary applications as well as several pressing challenges to the deployment of NIRS in more realistic settings.

Both physiological and behavioral studies have suggested that stimulus-driven neural activity in the sensory pathways can be modulated in amplitude during selective attention. Recordings of event-related brain potentials indicate that such sensory gain control or amplification processes play an important role in visual-spatial attention. Combined event-related brain potential and neuroimaging experiments provide strong evidence that attentional gain control operates at an early stage of visual processing in extrastriate cortical areas. These data support early selection theories of attention and provide a basis for distinguishing between separate mechanisms of attentional suppression (of unattended inputs) and attentional facilitation (of attended inputs).

New imaging techniques in cognitive neuroscience have produced a deluge of information correlating cognitive and neural phenomena. Yet our understanding of the inter-relationship between brain and mind remains hampered by the lack of a theoretical language for expressing cognitive functions in neural terms. We propose an approach to understanding operational laws in cognition based on principles of coordination dynamics that are derived from a simple and experimentally verified theoretical model. When applied to the dynamical properties of cortical areas and their coordination, these principles support a mechanism of adaptive inter-area pattern constraint that we postulate underlies cognitive operations generally.

The average evoked-potential waveforms to sound and light stimuli recorded from scalp in awake human subjects show differences as a function of the subject's degree of uncertainty with respect to the sensory modality of the stimulus to be presented. Differences are also found in the evoked potential as a function of whether or not the sensorymodality of the stimulus was anticipated correctly. The major waveform alteration is in the amplitude of a positive-going component which reaches peak amplitude at about 300 milliseconds.

The central problem for cognitive neuroscience is to describe how cognitive processes arise from brain processes. This review summarizes the recent evidence that synchronous neural oscillations reveal much about the origin and nature of cognitive processes such as memory, attention and consciousness. Memory processes are most closely related to theta and gamma rhythms, whereas attention seems closely associated with alpha and gamma rhythms. Conscious awareness may arise from synchronous neural oscillations occurring globally throughout the brain rather than from the locally synchronous oscillations that occur when a sensory area encodes a stimulus. These associations between the dynamics of the brain and cognitive processes indicate progress towards a unified theory of brain and cognition.

Neuroimaging data emphasize that older adults often show greater extent of brain activation than younger adults for similar objective levels of difficulty. A possible interpretation of this finding is that older adults need to recruit neuronal resources at lower loads than younger adults, leaving no resources for higher loads, and thus leading to performance decrements [Compensation-Related Utilization of Neural Circuits Hypothesis; e.g., Reuter-Lorenz, P. A., & Cappell, K. A. Neurocognitive aging and the compensation hypothesis. Current Directions in Psychological Science, 17, 177–182, 2008]. The Compensation-Related Utilization of Neural Circuits Hypothesis leads to the prediction that activation differences between younger and older adults should disappear when task difficulty is made subjectively comparable. In a Sternberg memory search task, this can be achieved by assessing brain activity as a function of load relative to the individual's memory span, which declines with age. Specifically, we hypothesized a nonlinear relationship between load and both performance and brain activity and predicted that asymptotes in the brain activation function should correlate with performance asymptotes (corresponding to working memory span). The results suggest that age differences in brain activation can be largely attributed to individual variations in working memory span. Interestingly, the brain activation data show a sigmoid relationship with load. Results are discussed in terms of Cowan's [Cowan, N. The magical number 4 in short-term memory: A reconsideration of mental storage capacity. Behavioral and Brain Sciences, 24, 87–114, 2001] model of working memory and theories of impaired inhibitory processes in aging.

User's examination of search results is a key concept involved in all the click models. However, most studies assumed that eye fixation means examination and no further study has been carried out to better understand user's examination behavior. In this study, we design an experimental search engine to collect both the user's feedback on their examinations and the eye-tracking/click-through data. To our surprise, a large proportion (45.8%) of the results fixated by users are not recognized as being "read". Looking into the tracking data, we found that before the user actually "reads" the result, there is often a "skimming" step in which the user quickly looks at the result without reading it. We thus propose a two-stage examination model which composes of a first "from skimming to reading" stage (Stage 1) and a second "from reading to clicking" stage (Stage 2). We found that the biases (e.g. position bias, domain bias, attractiveness bias) considered in many studies impact in different ways in Stage 1 and Stage 2, which suggests that users make judgments according to different signals in different stages. We also show that the two-stage examination behaviors can be predicted with mouse movement behavior, which can be collected at large scale. Relevance estimation with the two-stage examination model also outperforms that with a single-stage examination model. This study shows that the user's examination of search results is a complex cognitive process that needs to be investigated in greater depth and this may have a significant impact on Web search.

Image retrieval is an important problem for researchers in computer vision and content-based image retrieval (CBIR) fields. Over the last decades, many image retrieval systems were based on image representation as a set of extracted low-level features such as color, texture and shape. Then, systems calculate similarity metrics between features in order to find similar images to a query image. The disadvantage of this approach is that images visually and semantically different may be similar in the low level feature space. So, it is necessary to develop tools to optimize retrieval of information. Integration of vector space models is one solution to improve the performance of image retrieval. In this paper, we present an efficient and effective retrieval framework which includes a vectorization technique combined with a pseudo relevance model. The idea is to transform any similarity matching model (between images) to a vector space model providing a score. A study on several methodologies to obtain the vectorization is presented. Some experiments have been undertaken on Wang, Oxford5k and Inria Holidays datasets to show the performance of our proposed framework.


Question: Creation of an FPGA-based SPWM generator for high-frequency switching DC/AC inverters.

This document introduces an innovative power filter topology, specifically tailored for grid-tethered voltage-source inverters, termed the LLCL filter. This design involves the strategic insertion of a miniature inductor into the capacitor's branch loop within the conventional LCL filter framework, thereby forming a series resonant circuit at the switching frequency. The LLCL filter exhibits a superior capability to mitigate the current ripple components at the switching frequency, significantly more effective than the standard LCL filter. This results in a reduction in the overall inductance and the physical dimensions of the filter. Moreover, by minimizing the inductance of the inductor connected to the grid, the LLCL filter elevates the characteristic resonance frequency, a feature advantageous for enhancing the control of the inverter system. The paper also delves into the parameters required for designing the LLCL filter. Comparative assessments and discourse on the performance of the traditional LCL filter vis-à-vis the proposed LLCL filter are provided, supported by experimental data gathered from a 1.8-kW single-phase grid-connected inverter prototype. This study underscores the LLCL filter's potential for achieving improved performance and compactness in grid-tied inverter systems.

Question: Development of an FPGA-Based SPWM Generator for High Switching Frequency DC/AC Inverters

Documents: An FPGA-Based Real-Time Control System for High-Power DC-DC Converters

In this paper, a novel real-time control system is presented, designed for high-power DC-DC converters using a Field-Programmable Gate Array (FPGA). The proposed system integrates an FPGA for the generation of control signals, enabling high-speed processing capabilities essential for real-time control. This approach offers several advantages over conventional microcontroller-based systems, including faster switching frequencies, improved efficiency, and enhanced reliability. The FPGA-based control system is capable of generating precise control signals for the converter's power switches, resulting in reduced switching losses and improved overall converter efficiency. The system's high switching frequency also contributes to a reduction in the size and weight of passive components, such as inductors and capacitors, which are crucial for the compactness and portability of the converter. The paper details the design and implementation of the FPGA-based control system, including the digital signal processing algorithms used for generating the control signals. Experimental results from a high-power DC-DC converter prototype demonstrate the effectiveness of the proposed control system in achieving high switching frequencies, reduced switching losses, and improved efficiency. The study concludes that the FPGA-based control system is a viable and advantageous alternative for real

A time-domain-control-based quasi-<inline-formula> <tex-math notation="LaTeX">$V^{2}$ </tex-math></inline-formula> buck converter with small area, fast transient response, wide load current range, and constant switching frequency is proposed in this paper. The proposed time-domain-based controller achieves compact core area and simplified constant switching frequency control by replacing the conventional voltage-domain comparator with a phase detector having an adaptive detection window. Moreover, a coupling-based inductor current emulator is also proposed to support the discontinuous conduction mode operation in the light load. The proposed buck converter is implemented using 0.35-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. The core area of the proposed buck converter is only 0.293 mm2. The measured peak efficiency in the continuous conduction mode is 92% and the end-to-end efficiency in the load current range of 25–700 mA is 73%. The undershoot/overshoot and recovery time with the up/down load current steps of 510 mA are 38/20 mV and 2.5/2.6 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>, respectively.

A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wireless RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed dithering. Other imperfections of analog circuits are compensated through digital means. The presented ideas enable the employment of fully-digital frequency synthesizers using sophisticated signal processing algorithms, realized in the most advanced deep-submicrometer digital CMOS processes which allow almost no analog extensions. They also promote costeffective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13m CMOS process together with a DSP, which acts as a digital baseband processor with a large number of digital gates in order to investigate noise coupling. The phase noise is112 dBc/Hz at 500-kHz offset. The close-in spurious tones are below 62 dBc, while the far-out spurs are below 80 dBc. The presented ideas have been incorporated in a commercial Bluetooth transceiver.

A multilevel inverter is a power electronic device that is used for high voltage and high power applications and has many advantages like, low switching stress, low total harmonic distortion (THD). Hence, the size and bulkiness of passive filters can be reduced. This paper proposes two new topologies of a 7-level cascaded multilevel inverter with reduced number of switches than that of conventional type which has 12 switches. The topologies consist of circuits with 9 switches and 7 switches for the same 7-level output. Therefore with less number of switches, there will be a reduction in gate drive circuitry and also very few switches will be conducting for specific intervals of time. The SPWM technique is implemented using multicarrier wave signals. Level Shifted triangular waves are used in comparison with sinusoidal reference to generate Sine PWM switching sequence. The number of level shifted triangular waves depends on the number of levels in the output. i.e. for n levels, n-1 number of carrier waves. This paper uses 1 KHz SPWM pulses with a modulation index of 0.8. The circuits are simulated using SPWM technique and the effect of the harmonic spectrum is analyzed. A comparison is made for the topologies with 9 switches and 7 switches and an effective reduction in THD has been observed for the circuits with less number of switches. The THD for 9 switches is 14% and the THD for 7 switches is 12.5%. The circuits are modeled and simulated with the help of MATLAB/SIMULINK.

Although the concept of variable-speed drives, based on utilization of multiphase machines, dates back to the late 1960s, it was not until the mid- to late 1990s that multiphase drives became serious contenders for various applications. These include electric ship propulsion, locomotive traction, electric and hybrid electric vehicles, ldquomore-electricrdquo aircraft, and high-power industrial applications. As a consequence, there has been a substantial increase in the interest for such drive systems worldwide, resulting in a huge volume of work published during the last ten years. An attempt is made in this paper to provide a brief review of the current state of the art in the area. After addressing the reasons for potential use of multiphase rather than three-phase drives and the available approaches to multiphase machine designs, various control schemes are surveyed. This is followed by a discussion of the multiphase voltage source inverter control. Various possibilities for the use of additional degrees of freedom that exist in multiphase machines are further elaborated. Finally, multiphase machine applications in electric energy generation are addressed.

An inverter control design in DQ reference frame takes 3-phase sinusoidal signals and converts them to the DQ-frame to make a 2-phase based DC variable control. The error is calculated by subtracting the feedback from reference and then feedding it to PI controllers. The outputs of PI controllers are of the voltage form and transferred back to the ABC frame and fed to SPWM modules. P+Resonant controllers suggest establishing the control strategy in stationary (alpha-beta) frame. In this frame the axis are fix and three phase variables are mapped in a rotating vector with the same angular speed of the original signals. The P+Resonant controller has zero steady state error at the resonant frequency. This paper explains how to apply DQ-frame and P+Resonant for inverter controller design for grid connected single-phase Voltage Source Inverters (VSI). To evaluate the effectiveness of both control techniques, it is also presented simulated results with application of these controllers.

This work presents new three-level unidirectional single-phase PFC rectifier topologies well-suited for applications targeting high efficiency and/or high power density. The characteristics of a selected novel rectifier topology, including its principles of operation, modulation strategy, PID control scheme, and a power circuit design related analysis are presented. Finally, a 220-V/3-kW laboratory prototype is constructed and used in order to verify the characteristics of the new converter, which include remarkably low switching losses and single ac-side boost inductor, that allow for a 98.6% peak efficiency with a switching frequency of 140 kHz.

Improved back EMF detection circuits for low voltage/low speed and high voltage sensorless BLDC motor drives are presented in this paper. The improvements are based on the direct back EMF sensing method from our previous research work described in reference, which describes a technique for directly extracting phase back EMF information without the need to sense or re-construct the motor neutral. The reference method is not sensitive to switching noise and requires no filtering, achieving much better performance than traditional back EMF sensing scheme. A complementary PWM (synchronous rectification) is proposed to reduce the power dissipation in power devices for low voltage applications. In order to further extend the sensorless BLDC system to lower speed, a pre-conditioning circuit is proposed to amplify the back EMFs at very low speed. As a result, the brushless DC motor can run at lower speed with the improved back EMF sensing scheme. On the other hand, another improved detection circuit is presented for high voltage applications to overcome the delaying problem caused by large sensing resistors. The detailed circuit models are analyzed and experimental results verify the analysis.

An interleaved active clamp flyback inverter using a synchronous rectifier for a photovoltaic AC module system is proposed. In a conventional single flyback inverter for the photovoltaic AC module system, this inverter has drawbacks of a conduction losses of each switch, transformer copper and high ripple current of capacitor. To overcome these problems, two flyback converter modules with interleaved pulse-width modulation (PWM) are connected in parallel at the input and output sides reducing the ripple current on the input and output capacitors and decrease the current stress on the transformer windings. Thus, the transformer copper losses and the conduction losses on the switches are reduced. Also, reliability and life of capacitor are increased due to reducing the ripple current of input and output capacitors. In order to verify these, theoretical analysis and simulation are performed.

This paper proposes a compact field weakening controller (FWC). The FWC was developed during the development of an electrically driven rear axle for a hybrid electric car. The overall control system of the vehicle, the hybrid controller (HC), delivers a reference torque for the rear drive unit (RDU). Depending on the torque reference, instantaneous vehicle speed and battery voltage the task of the FWC is to produce current references for the current controller. The references are chosen to give an optimal current, optimal in the sense that the torque-per-current ratio is maximized, under the restriction of keeping the stator voltage and current limited. The FWC is based on comprehensive measurements of the machine. An algorithm is used to process the data from the measurements. The output from the algorithm is look-up tables. Implementation of the look-up tables is also discussed in the paper

In this paper, a new current source gate drive circuit is proposed for high efficiency synchronous buck VRMs. The proposed circuit achieves quick turn-on and turn-off transition times to reduce switching loss and conduction loss in power MOSFETS. The driver circuit consists of two sets of four control switches and two very small inductors (typically 50 nH-300 nH each at 1 MHz). It drives both the control MOSFET and synchronous MOSFET in synchronous buck VRMs. An analysis, design procedure, optimization procedure and experimental results are presented for the proposed circuit. Experimental results demonstrate an efficiency of 86.6% at 15 A load and 81.9% at 30 A load for 12 V input and 1.3 V output at 1 MHz.


Question: Creation of an FPGA-based SPWM generator for high-frequency switching DC/AC inverters.

This paper details the design and development of a fully integrated silicon carbide (SiC)-based six-pack power module, specifically tailored for high-performance inverter applications. The module, rated at 1200V and 100A, features four paralleled SiC junction gate field-effect transistors (JFETs) per switching element, alongside two antiparallel SiC Schottky barrier diodes. Rigorous testing, including 1000 cycles of thermal shock tests ranging from -40°C to +200°C, confirms the robustness and stability of the module assembly. Static characteristic evaluations reveal a phase leg on-state resistance of 55 mΩ at a junction temperature of 200°C. Switching performance analysis, conducted with a 650V voltage and 60A current, indicates a decrease in module switching loss as the junction temperature rises to 150°C. The paper also outlines the test setup for a broad temperature range, discussing factors such as the impact of SiC JFET internal capacitance and package parasitic inductances on shoot-through. Furthermore, a compact liquid-cooled three-phase inverter, measuring 22.9 cm × 22.4 cm × 7.1 cm and weighing 3.53 kg, is designed using this power module, targeting electric and hybrid electric vehicle applications. At a 10 kHz switching frequency and 5 kW output power, the inverter achieves a conversion efficiency of 98.5%, demonstrating its high efficiency even when the coolant temperature reaches 95°C.

**Question**: A Direct Search Method to solve Economic Dispatch Problem with Valve-Point Effect

**Documents**: A Novel Approach for Solving Economic Dispatch Problem Using Adaptive Harmony Search Algorithm
In this paper, a novel approach for solving the economic dispatch problem (EDP) with valve-point effect is proposed. The proposed method is based on the adaptive harmony search (AHS) algorithm, which is a metaheuristic optimization algorithm inspired by the musical improvisation process. The AHS algorithm is modified to adaptively update the harmony memory considering rate (HMCR) and the pitch adjusting rate (PAR) parameters based on the objective function value and the iteration number. The proposed AHS algorithm is tested on three standard test systems with valve-point effect, namely the 6-generator, 13-generator, and 40-generator systems. The results show that the proposed AHS algorithm can effectively solve

This paper deals with a power factor correction (PFC)-based Cuk converter-fed brushless dc motor (BLDC) drive as a cost-effective solution for low-power applications. The speed of the BLDC motor is controlled by varying the dc-bus voltage of a voltage source inverter (VSI) which uses a low frequency switching of VSI (electronic commutation of the BLDC motor) for low switching losses. A diode bridge rectifier followed by a Cuk converter working in a discontinuous conduction mode (DCM) is used for control of dc-link voltage with unity power factor at ac mains. Performance of the PFC Cuk converter is evaluated under four different operating conditions of discontinuous and continuous conduction modes (CCM) and a comparison is made to select a best suited mode of operation. The performance of the proposed system is simulated in a MATLAB/Simulink environment and a hardware prototype of the proposed drive is developed to validate its performance over a wide range of speed with unity power factor at ac mains.

10-kV silicon carbide (SiC) MOSFETs are currently being developed by a number of organizations in the U.S. with prospective applications in high-voltage and high-frequency power-electronic systems. The aim of this paper is to demonstrate the high-frequency and high-temperature capability of 10-kV SiC MOSFETs in the application of a dc/dc boost converter. In this study, 10-kV SiC MOSFET and junction barrier Schottky (JBS) diode were characterized and modeled in SPICE. Following this, a dc/dc boost converter based on a 10-kV 10-A MOSFET and a 10-kV 5-A JBS diode was designed and tested under continuous operation for frequencies up to 25 kHz. The boost converter had an output voltage of 4 kV, an output power of 4 kW, and operated with a junction temperature of 174degC for the SiC MOSFET. The fast-switching speed, low losses, and high-temperature operation capability of 10-kV SiC MOSFETs demonstrated in the dc/dc boost converter make them attractive for high-frequency and high-voltage power-conversion applications.

This work reports on the design and test of a CMOS-based Switched Capacitor (SC) DC-DC conversion integrated circuit (IC) for the point-of-load (POL) application conventionally addressed with the buck converter. A 12V-to-1.5V converter is fabricated in a 0.18µm technology, with an active die area of 3mm2. There is a significant reduction in printed circuit board (PCB) footprint, passive component height and cost when compared to surveyed buck converters. The converter achieves 93% peak efficiency and an efficiency of 80% over an output current range of 7mA to 1A. This work demonstrates the vast potential of SC converters for wide-range voltage conversion in deep-submicron CMOS technologies, when cost and efficiency are of critical importance.

In this paper, a simplified optimal trajectory control (SOTC) for the LLC resonant converter is proposed. During the steady state, a linear compensator such as proportional-integral or proportional-integral-derivative (PID) is used, controlling the switching frequency fs to eliminate the steady-state error. However, during load transients, the SOTC method takes over, immediately changing the pulse widths of the gate-driving signals. Using the state-plane analysis, the pulse widths are estimated, letting the state variables track the optimal trajectory locus in the minimum period of time. The proposed solution is implemented in a digital controller, and experimental results show that while the digital logic requirement is very small, the performance improvement is significant.

High-resolution Time-to-Digital converter (TDC) is one of the crucial blocks in Highenergy nuclear physics time of flight experiments. The contemporary time interval measurement techniques rely on employing methods like Time-to-Amplitude Conversion, Vernier method, Delay Locked Loops (DLL), Tapped Delay Lines (TDL), Differential Delay Lines (DDL) etc. Recently, FPGA based TDC designs with merits of low cost, fast development cycle and re-programmability are reported [1]. The TDC implementation in FPGA have design challenges and issues like, lack of direct control over the propagation delays, unpredictable Place & Route (P&R) delays and delay variations due to Process, Voltage & Temperature (PVT) variations. In the TDC design presented here, the resolution below the minimum gate delay is achieved by employing differential (Vernier oscillator) technique. The predictable P&R is achieved by manual P&R of the critical elements and avoiding the use of digital synthesis tools. Further, in order to compensate for the delay variations due to PVT, a calibration methodology is developed and implemented. By implementing the design in a Flash-based FPGA, the low power design objective is achieved.

Hard-switching-induced switching loss can contribute significantly to the power loss of an isolated bidirectional dual-active-bridge (DAB) dc–dc converter operating at high frequency. An <inline-formula> <tex-math notation="LaTeX">$LC$</tex-math></inline-formula>-type series resonant DAB converter based on a switch-controlled-inductor (SCI) is proposed to mitigate the loss arising from hard switching under wide-range variations in output voltage and current. Zero-voltage switching is achieved at the primary side (high voltage), while at the secondary side (low voltage), zero-current switching is preferred to reduce excessive ringing due to circulating current and switching loss. In order to achieve reduced conduction loss, a nominal operating point is chosen where the root-mean-square resonant tank current is the minimum. To validate the proposed topology and modulation scheme, an <inline-formula><tex-math notation="LaTeX">$LC$</tex-math></inline-formula>-type series resonant DAB converter based on SCI operating at 100 kHz is designed to interface a 400-V dc bus to a supercapacitor-based energy storage. Simulation and experimental results validate the effectiveness of the proposed topology for charging/discharging a supercapacitor with an output voltage variation of between 10 and 48 V and a maximum rated power of 480 W. A maximum efficiency of 94.6% is achieved using the proposed topology and modulation scheme.

AC/DC converter systems generally have two stages: an input power factor correction (PFC) boost ac/dc stage that converts input ac voltage to an intermediate dc voltage while reducing the input current harmonics injected to the grid, followed by a dc/dc converter that steps up or down the intermediate dc-bus voltage as required by the output load and provides high-frequency galvanic isolation. Since a low-frequency ripple (second harmonic of the input ac line frequency) exists in the output voltage of the PFC ac/dc boost converter due to the power ripple, the voltage loop in the conventional control system must have a very low bandwidth in order to avoid distortions in the input current waveform. This results in the conventional PFC controller having a slow dynamic response against load variations with adverse overshoots and undershoots. This paper presents a new control approach that is based on a novel discrete energy function minimization control law that allows the front-end ac/dc boost PFC converter to operate with faster dynamic response than the conventional controllers and simultaneously maintain near unity input power factor. Experimental results from a 3-kW ac/dc converter built for charging traction battery of a pure electric vehicle are presented in this paper to validate the proposed control method and its superiority over conventional controllers.

This paper describes a MOSFET switched pulser, which is composed of 30 series connections of pulse generating modules (PGMs) that can produce a 700 V/500 A/100 ns pulse with the rising time of 60 ns or less. All PGMs are connected in series through the specially designed pulse transformers to obtain 20 kV/500 A/100 ns pulses at repetition rates up to 20 kHz. To obtain the fast rising time pulse, it is essential to minimize the leakage inductance of the pulse transformer and the wiring inductance between pulse transformers. In this paper, two kinds of layout for the series connection of pulse transformers are introduced and compared to the conventional methods. Also, the authors minimized the losses by adopting an energy recovery circuit that returns to the source the stored energy in the clamp circuit of the primary windings of the pulse transformers. Experimental results are given for the proposed pulser under the resistor load and the wire-cylinder plasma reactor load, respectively.

This paper deals with doubly fed induction generator control strategy. This paper includes the results performed in PSIM-9 software such as Performance comparison of output voltage under different loading conditions and output power. Keywords— Doubly Fed Induction Generator (DFIG), variable speed wind turbine

In this paper, a new medium voltage power converter topology using a diode rectifier, three-level boost (TLB) converter, and neutral-point-clamped (NPC) inverter is proposed for a high-power permanent magnet synchronous generator-based wind energy conversion system. The generator-side TLB converter performs the maximum power point tracking and balancing of dc-link capacitor voltages, while the grid-side NPC inverter regulates the net dc-bus voltage and reactive power to the grid. A significant improvement in the grid power quality is accomplished as the NPC inverter no longer controls the dc-link neutral point voltage. A model predictive strategy is proposed to control the complete system where the discrete-time models of the proposed power electronic converters are used to predict the future behavior of control variables. These predictions are evaluated using two independent cost functions, and the switching states which minimize these cost functions are selected and applied to the generator- and grid-side converters directly. In order to comply with the high-power application, the switching frequencies of the TLB converter and NPC inverter are minimized and maintained below 1.5 and 1 kHz, respectively. The proposed topology and control strategy are verified through MATLAB simulations on a 3-MW/3000-V/577-A system and dSPACE DS1103-based experiments on 3.6-kW/208-V/10-A prototype.


Question: Creation of an FPGA-based SPWM generator for high-frequency switching DC/AC inverters.

This article delves into the stability concerns associated with grid-connected inverters utilized in distributed power generation systems, focusing on the challenges posed by the broad spectrum of grid impedance values. To counteract the low-frequency grid voltage distortions, intricate control strategies, such as those employing multiple rotating dq-frames or resonant-based techniques, are frequently implemented. Meanwhile, an LCL-filter is typically deployed to address high-frequency disturbances. However, the diverse grid impedance values, characteristic of remote areas with radial distribution networks, present significant hurdles to the stability and efficacy of the LCL-filter-based current control system. The study highlights the pivotal role of active damping in enhancing system stability across a multitude of resonance types. Active damping facilitates the seamless integration of the generation system into a wide array of grid conditions, thereby enabling more adaptable system operations capable of handling abrupt grid fluctuations. The findings are substantiated through an extensive measurement campaign conducted on both single-phase and three-phase systems, serving as scaled models for photovoltaic and wind turbine applications, respectively. The empirical data effectively corroborates the analytical insights presented.

The objective of this research is to investigate the stability issues encountered in grid-connected inverters that are integral to distributed generation systems, particularly in light of the extensive variation in grid impedance values. Such inverters often necessitate sophisticated control methodologies, including the use of multiple rotating dq-frames or resonant-based designs, to mitigate low-frequency grid voltage distortions. Additionally, an LCL-filter is typically employed to manage high-frequency distortions. The wide range of grid impedance values, typical in remote regions with radial distribution networks, poses significant challenges to the stability and performance of LCL-filter-based current control systems. This paper demonstrates that the implementation of active damping significantly contributes to system stabilization across various resonance scenarios. Active damping ensures the system's compatibility with a broad range of grid conditions, offering enhanced operational flexibility to accommodate sudden grid changes. The analysis is supported by comprehensive experimental data gathered from tests on both single-phase and three-phase systems, which serve as scaled models for photovoltaic and wind turbine systems, respectively. The empirical evidence validates the theoretical conclusions, highlighting the effectiveness of active damping in stabilizing grid-connected inverters under diverse grid conditions.

This paper describes a MOSFET switched pulser, which is composed of 30 series connections of pulse generating modules (PGMs) that can produce a 700 V/500 A/100 ns pulse with the rising time of 60 ns or less. All PGMs are connected in series through the specially designed pulse transformers to obtain 20 kV/500 A/100 ns pulses at repetition rates up to 20 kHz. To obtain the fast rising time pulse, it is essential to minimize the leakage inductance of the pulse transformer and the wiring inductance between pulse transformers. In this paper, two kinds of layout for the series connection of pulse transformers are introduced and compared to the conventional methods. Also, the authors minimized the losses by adopting an energy recovery circuit that returns to the source the stored energy in the clamp circuit of the primary windings of the pulse transformers. Experimental results are given for the proposed pulser under the resistor load and the wire-cylinder plasma reactor load, respectively.

The paper describes switched-capacitor dc-dc converters (charge pumps) suitable for on-chip, low-power applications. The proposed configurations are based on connecting two identical but opposite-phase SC converters in parallel, thus eliminating the need for separate bootstrap gate drivers. We focus on emerging very low-power VLSI applications such as batterypowered or self-powered signal processors where high power conversion efficiency is important and where power levels are in the milliwatt range. Conduction and switching losses are considered to allow design optimization in terms of switching frequency and component sizes. Open-loop and closed-loop operation of an experimental, fully integrated, 10MHz voltage doubler is described. The doubler has 2V or 3V input and generates 3.3V or 5V output at up to 5mW load. The converter circuit fabricated in a standard 1.2μ CMOS technology takes 0.7mm of the chip area.

This paper investigates the soft start-up for high frequency LLC resonant converter with optimal trajectory control. Two methods are proposed to realize soft start-up for high frequency LLC converter by commercial low-cost microcontrollers (MCU). Both methods can achieve soft start-up with minimum stress and optimal energy delivery. One method is mixed-signal implementation by sensing resonant tank to minimize the digital delay. Another method is digital implementation with look-up table. Experimental results are demonstrated on 500kHz 1kW 400V/12V LLC converter.

Conventional dead-time compensation methods, for pulsewidth-modulated (PWM) inverters, improve the current output waveforms; however, the zero-current crossing effect is still apparent. This letter proposes a new method, based on angle domain repetitive control, to reduce the distortions in the PWM inverters output waveforms caused by the dead time and the zero-crossing problem.

Hard-switching-induced switching loss can contribute significantly to the power loss of an isolated bidirectional dual-active-bridge (DAB) dc–dc converter operating at high frequency. An <inline-formula> <tex-math notation="LaTeX">$LC$</tex-math></inline-formula>-type series resonant DAB converter based on a switch-controlled-inductor (SCI) is proposed to mitigate the loss arising from hard switching under wide-range variations in output voltage and current. Zero-voltage switching is achieved at the primary side (high voltage), while at the secondary side (low voltage), zero-current switching is preferred to reduce excessive ringing due to circulating current and switching loss. In order to achieve reduced conduction loss, a nominal operating point is chosen where the root-mean-square resonant tank current is the minimum. To validate the proposed topology and modulation scheme, an <inline-formula><tex-math notation="LaTeX">$LC$</tex-math></inline-formula>-type series resonant DAB converter based on SCI operating at 100 kHz is designed to interface a 400-V dc bus to a supercapacitor-based energy storage. Simulation and experimental results validate the effectiveness of the proposed topology for charging/discharging a supercapacitor with an output voltage variation of between 10 and 48 V and a maximum rated power of 480 W. A maximum efficiency of 94.6% is achieved using the proposed topology and modulation scheme.

A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wireless RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed dithering. Other imperfections of analog circuits are compensated through digital means. The presented ideas enable the employment of fully-digital frequency synthesizers using sophisticated signal processing algorithms, realized in the most advanced deep-submicrometer digital CMOS processes which allow almost no analog extensions. They also promote costeffective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13m CMOS process together with a DSP, which acts as a digital baseband processor with a large number of digital gates in order to investigate noise coupling. The phase noise is112 dBc/Hz at 500-kHz offset. The close-in spurious tones are below 62 dBc, while the far-out spurs are below 80 dBc. The presented ideas have been incorporated in a commercial Bluetooth transceiver.

In this paper, a new current source gate drive circuit is proposed for high efficiency synchronous buck VRMs. The proposed circuit achieves quick turn-on and turn-off transition times to reduce switching loss and conduction loss in power MOSFETS. The driver circuit consists of two sets of four control switches and two very small inductors (typically 50 nH-300 nH each at 1 MHz). It drives both the control MOSFET and synchronous MOSFET in synchronous buck VRMs. An analysis, design procedure, optimization procedure and experimental results are presented for the proposed circuit. Experimental results demonstrate an efficiency of 86.6% at 15 A load and 81.9% at 30 A load for 12 V input and 1.3 V output at 1 MHz.

Switching regulators with ripple-based control (i.e., ¿ripple regulators¿) are conceptually simple, have fast transient responses to both line and load perturbations, and some versions operate with a switching frequency that is proportional to the load current under the discontinuous conduction mode. These characteristics make the ripple regulators well-suited, especially for power management applications in computers and portable electronic devices. Ripple regulators also have some drawbacks, including (in some versions) a poorly defined switching frequency, noise-induced jitter, inadequate dc regulation, and a tendency for fast-scale instability. This paper presents an overview of the various ripple-based control techniques, discusses their merits and limitations, and introduces techniques for reducing the noise sensitivity and the sensitivity to capacitor parameters, improving the frequency stability and the dc regulation, and avoiding fast-scale instability.

The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realization of fast and secure implementations of cryptographic algorithms. Under this work, such an implementation has been done for Advanced Encryption Standard (AES) on fast, efficient and low power Field Programmable Gate Arrays (FPGAs) whereby computational intensive cryptographic processes are offloaded from the main processor thus results in achieving highspeed secure wireless connectivity. The dedicated resources of Spartan-3 FPGAs have been effectively utilized to develop wider logic function which minimizes the critical paths by confining logic to single Configurable Logic Block (CLB), thus improving the performance, density and power consumption of the design. The resultant design consumes only 4 Block RAMs and 487 Slices to fit both AES cores and its key scheduling.

Multilevel inverters require a large number of power semiconductors. The gate driver for each power semiconductor requires its own floating or isolated DC voltage source. Traditional methods on meeting the requirement are expensive and bulky. This paper presents a gate driver design for floating voltage source type multilevel inverters. Bootstrap capacitors are used to form the floating voltage sources in the design, which allows a single DC power supply to be used by all the gate drivers. Specially configured diode plus the proper charging cycles maintain adequate capacitor voltage levels. Such a simple and low cost solution allows user to utilize the easy accessible single-channel gate drivers for multilevel inverter applications without the extra cost on the bulky isolated DC power supplies for each gate driver. A prototype 3-cell 8-level floating voltage source inverter using the method illustrates the technique


Question: Creation of an FPGA-based SPWM generator for high-frequency switching DC/AC inverters.

This document explores the advancement of Silicon Carbide (SiC) power technology to higher voltage applications, specifically focusing on 10 kV/10 A SiC DMOSFETs and SiC JBS diodes. The paper details the development of a novel 10 kV/120 A SiC power module that incorporates these cutting-edge SiC devices. This module facilitates the creation of a compact, high-performance 13.8 kV to 465/√3 solid state power substation (SSPS) with a substantial 1 MVA rating. This innovation marks a significant step in the evolution of solid state power substations, showcasing the potential of SiC technology in enhancing the efficiency and reliability of high-voltage power conversion systems.

**Question**: An Investigation into the Effectiveness of a Novel Control Algorithm for Wind Turbine Systems

**Documents**: A new control algorithm for variable speed wind turbine systems based on a nonlinear controller
A new control algorithm for variable speed wind turbine systems is proposed in this paper. The algorithm is based on a nonlinear controller which is designed to achieve maximum power point tracking (MPPT) under varying wind conditions. The proposed controller is designed using a backstepping approach and is able to handle nonlinearities and uncertainties in the wind turbine system. The effectiveness of the proposed control algorithm is demonstrated through simulations on a 2 MW wind turbine system.

**Similar Documents**: This paper presents an innovative control algorithm tailored for variable speed wind turbine systems, focusing on maximizing power generation under fluctuating wind conditions. The algorithm leverages a sophisticated nonlinear controller, specifically engineered using a backstepping technique, to adeptly manage the inherent nonlinearities and uncertainties prevalent in wind turbine operations. This approach ensures robust performance and adaptability, crucial for optimal power extraction. To substantiate the efficacy of the proposed control strategy, comprehensive simulations were conducted on a 2 MW wind turbine system, yielding promising results that underscore its potential in enhancing wind turbine efficiency and reliability.

This paper describes a newly developed novel repetitive impulse voltage generator using a boost converter array. To solve problems such as short life time, low operating frequency, and the fixed pulse width of conventional generators, the proposed generator is designed with a boost converter array that employs series-connected capacitors and insulated gate bipolar transistors. The circuit can easily obtain a high-voltage pulse without any high-voltage direct current source and pulse transformer. Thus, the proposed circuit not only allows elimination of the expensive high-frequency transformer but also allows operation at a frequency up to several kilohertz with high reliability and longer life span. To validate the proposed circuit, two pulse generators rated at 1.8 kV, 40 A and 20 kV, 300 A are implemented and tested.

Improved back EMF detection circuits for low voltage/low speed and high voltage sensorless BLDC motor drives are presented in this paper. The improvements are based on the direct back EMF sensing method from our previous research work described in reference, which describes a technique for directly extracting phase back EMF information without the need to sense or re-construct the motor neutral. The reference method is not sensitive to switching noise and requires no filtering, achieving much better performance than traditional back EMF sensing scheme. A complementary PWM (synchronous rectification) is proposed to reduce the power dissipation in power devices for low voltage applications. In order to further extend the sensorless BLDC system to lower speed, a pre-conditioning circuit is proposed to amplify the back EMFs at very low speed. As a result, the brushless DC motor can run at lower speed with the improved back EMF sensing scheme. On the other hand, another improved detection circuit is presented for high voltage applications to overcome the delaying problem caused by large sensing resistors. The detailed circuit models are analyzed and experimental results verify the analysis.

IEC 1000-3-2 regulations impose a reduced harmonic content on any converter with an input power higher than 75 W. However, if the power architecture of the system is based on small on-board converters, and the total power is higher than 75 W, IEC regulations must be fulfilled although each individual converter need not comply with the regulations. In this paper, one of the different possible solutions is presented. Each on-board converter has an active input current shaper (AICS) in order to reduce the input current harmonic content of each converter and, hence, to comply with IEC 1000-3-2 regulations. Moreover, two different types of AICSs were compared: the conventional one and a new type of AICS based on a full-wave rectifier.

This study addresses a grid-connected photovoltaic (PV) generation system. In order to make the PV generation system more flexible and expandable, the backstage power circuit is composed of a high step-up converter and a pulsewidth-modulation (PWM) inverter. In the dc-dc power conversion, the high step-up converter is introduced to improve the conversion efficiency of conventional boost converters and to allow the parallel operation of low-voltage PV modules. Moreover, an adaptive total sliding-mode control system is designed for the current control of the PWM inverter to maintain the output current with a higher power factor and less variation under load changes. In addition, an adaptive step-perturbation method is proposed to achieve the objective of maximum power point tracking, and an active sun tracking scheme without any light sensors is investigated to make PV plates face the sun directly in order to capture maximum irradiation and enhance system efficiency. Experimental results are given to verify the validity of the high step-up converter, the PWM inverter control, the ASP method, and the active sun tracker for a grid-connected PV generation system.

The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realization of fast and secure implementations of cryptographic algorithms. Under this work, such an implementation has been done for Advanced Encryption Standard (AES) on fast, efficient and low power Field Programmable Gate Arrays (FPGAs) whereby computational intensive cryptographic processes are offloaded from the main processor thus results in achieving highspeed secure wireless connectivity. The dedicated resources of Spartan-3 FPGAs have been effectively utilized to develop wider logic function which minimizes the critical paths by confining logic to single Configurable Logic Block (CLB), thus improving the performance, density and power consumption of the design. The resultant design consumes only 4 Block RAMs and 487 Slices to fit both AES cores and its key scheduling.

This study investigates a phase-locked loop (PLL) controlled parallel resonant converter (PRC) for a pulse power capacitor charging application. The dynamic nature of the capacitor charging is such that it causes a shift in the resonant frequency of the PRC. Using the proposed control method, the PRC can be optimized to operate with its maximum power capability and guarantee ZVS operation, even when the input voltage and resonant tank parameters vary. The detailed implementation of the PLL controller, as well as the determination of dead-time and leading time, is presented in this paper. Simulation and experimental results verify the performance of the proposed control method.

This work presents a 1.3 kW, single phase, AC-DC converter with power factor correction based on a 7-level flying capacitor multilevel converter. The topology features a tradeoff of active circuit complexity for dramatic reduction on the magnetic component size, while maintaining a high efficiency. In this work, we demonstrate these features through theoretical analysis as well as a hardware prototype. It has been experimentally demonstrated that the prototype can operate at an universal AC input from 90–230 VRMS and frequencies from 47–63 Hz with an output voltage of 400 V, achieving a box power density of 1.21 W/cm3 (19.8 W/in3) and a peak efficiency of 97.6%. This prototype is the first successful demonstration of a 7-level flying capacitor multilevel boost topology as an AC-DC converter with fully implemented digital PFC control and self-powered start-up from a universal AC input.

Standard squirrel cage induction motors are subjected to nonsinusoidal wave shapes, when supplied from adjustable frequency inverters. In addition to causing increased heating, these wave patterns can be destructive to the insulation. Pulse width modulated (PWM) inverter output amplitudes and risetimes are investigated, and motor insulation capabilities are discussed. Voltage reflections are simulated for various cable lengths and risetimes and are presented graphically. Simulations confirm potential problems with long cables and short risetimes. Application precautions are also discussed.<<ETX>>

Although the concept of variable-speed drives, based on utilization of multiphase machines, dates back to the late 1960s, it was not until the mid- to late 1990s that multiphase drives became serious contenders for various applications. These include electric ship propulsion, locomotive traction, electric and hybrid electric vehicles, ldquomore-electricrdquo aircraft, and high-power industrial applications. As a consequence, there has been a substantial increase in the interest for such drive systems worldwide, resulting in a huge volume of work published during the last ten years. An attempt is made in this paper to provide a brief review of the current state of the art in the area. After addressing the reasons for potential use of multiphase rather than three-phase drives and the available approaches to multiphase machine designs, various control schemes are surveyed. This is followed by a discussion of the multiphase voltage source inverter control. Various possibilities for the use of additional degrees of freedom that exist in multiphase machines are further elaborated. Finally, multiphase machine applications in electric energy generation are addressed.

This paper deals with a synthesis of space-vector pulsewidth modulation (SVPWM) control methods applied for an H-bridge inverter feeding a three-phase permanent-magnet synchronous machine (PMSM) in electric-vehicle (EV) applications. First, a short survey of existing architectures of power converters, particularly those adapted to degraded operating modes, is presented. Standard SVPWM control methods are compared with three innovative methods using EV drive specifications in the normal operating mode. Then, a rigorous analysis of the margins left in the control strategy is presented for a semiconductor switch failure to fulfill degraded operating modes. Finally, both classic and innovative strategies are implemented in numerical simulation; their results are analyzed and discussed.


Question: Creation of an FPGA-based SPWM generator for high-frequency switching DC/AC inverters.

This document explores the evolving landscape of Distributed Power Generation Systems (DPGSs), particularly those leveraging renewable energy sources such as wind, solar, and hydroelectric power. With a growing global focus on sustainability, countries like Germany, Denmark, Japan, and the United States are leading the charge in developing and implementing DPGSs. As the integration of DPGSs into the electrical grid increases, there arises a need for more stringent regulations concerning power quality, operational safety, and protection against islanding. To align with these new standards, the control mechanisms of distributed generation systems must be refined to ensure seamless grid interconnection.

The paper provides a comprehensive review of DPGS architectures, specifically focusing on those utilizing fuel cells, photovoltaic systems, and wind turbines. It also delves into the control strategies employed by grid-side converters, highlighting their role in mitigating low-order harmonic distortions. Furthermore, the document discusses control methodologies for managing grid faults, a critical aspect in maintaining the stability and reliability of the electrical grid.

Finally, the paper concludes with an analysis of synchronization techniques, emphasizing their significance in the effective control of DPGSs. These methods are crucial for ensuring that renewable energy sources are integrated smoothly and efficiently into the existing grid infrastructure, thereby facilitating a transition towards a more sustainable and resilient energy system.

The eGaN HEMTs with ZVS technique have emerged in high frequency converters to reduce the switching loss. This paper investigates an eGaN HEMT ZVS isolated SEPIC converter running up to 2 MHz. Furthermore, an inductor optimization method is proposed to ensure ZVS and reduce reverse conduction loss of the SR. The efficiency curve is optimized based on the trade-off method between the switching and conduction losses. Moreover, the embedded inductor is proposed to reduce the conduction loss of the inductor. Finally, two 2 MHz eGaN HEMT prototypes with the commercial and embedded inductor with 18–36 V input and 5 V/2 A output are built respectively to verify the effectiveness of the proposed methods. The converters achieve a peak efficiency of over 88.2% and power density of 52.9 W/in3, outperforming the state-of-art power module products.

Traditional two-level high-frequency pulse width modulation (PWM) inverters for motor drives have several problems associated with their high frequency switching which produces common-mode voltage and high voltage change (dV/dt) rates to the motor windings. Multilevel inverters solve these problems because their devices can switch at a much lower frequency. Two different multilevel topologies are identified for use as a converter for electric drives, a cascade inverter with separate dc sources and a back-to-back diode clamped converter. The cascade inverter is a natural fit for large automotive allelectric drives because of the high VA ratings possible and because it uses several levels of dc voltage sources which would be available from batteries or fuel cells. The back-to-back diode clamped converter is ideal where a source of ac voltage is available such as a hybrid electric vehicle. Simulation and experimental results show the superiority of these two converters over PWM based drives.

In this paper, a simplified optimal trajectory control (SOTC) for the LLC resonant converter is proposed. During the steady state, a linear compensator such as proportional-integral or proportional-integral-derivative (PID) is used, controlling the switching frequency fs to eliminate the steady-state error. However, during load transients, the SOTC method takes over, immediately changing the pulse widths of the gate-driving signals. Using the state-plane analysis, the pulse widths are estimated, letting the state variables track the optimal trajectory locus in the minimum period of time. The proposed solution is implemented in a digital controller, and experimental results show that while the digital logic requirement is very small, the performance improvement is significant.

A new single-phase 7-level pulse-width modulation (PWM) inverter using T-type Neutral-point-clamped (TNPC) celIs is presented to obtain high quality output voltage minimizing the number of switching devices. It includes two TNPC cells series-connected together and connected to with different voltage levels. To avoid inherent problems caused by voltage unbalance, modified Buck-boost converters are added at DC-link side to make DC voltage sources for the proposed inverter. Operational principles and the switching pattern are analyzed in this paper. To verify the performance of the proposed inverter, PSIM simulation and experimental results are also shown in this paper.

In this paper the selective harmonic elimination pulse width modulation (SHE-PWM) technique is proposed to control the three-level four-leg neutral point clamped (NPC) inverter in order to have both advantages of low switching frequency of SHE and neutral point of fourth leg in four wire systems. In this proposed method, the obtained switching angles of inverter phase legs are used to eliminate the non-triplen, 5th to 23th harmonics orders from the output voltage. As well, switching angles calculated for the fourth leg are considered to eliminate the triplen harmonics containing 3th, 9th, 15th, 21th and 27th orders from phase voltage. The efficiency of the proposed modulation technique is verified by simulations of a four leg NPC inverter as an UPS feeding different types of dynamic and unbalanced loads.

This work presents a 1.3 kW, single phase, AC-DC converter with power factor correction based on a 7-level flying capacitor multilevel converter. The topology features a tradeoff of active circuit complexity for dramatic reduction on the magnetic component size, while maintaining a high efficiency. In this work, we demonstrate these features through theoretical analysis as well as a hardware prototype. It has been experimentally demonstrated that the prototype can operate at an universal AC input from 90–230 VRMS and frequencies from 47–63 Hz with an output voltage of 400 V, achieving a box power density of 1.21 W/cm3 (19.8 W/in3) and a peak efficiency of 97.6%. This prototype is the first successful demonstration of a 7-level flying capacitor multilevel boost topology as an AC-DC converter with fully implemented digital PFC control and self-powered start-up from a universal AC input.

This paper focuses on a new three-phase high power current-fed DC/DC converter with an active clamp. A three-phase DC/DC converter with high efficiency and voltage boosting capability is designed for use in the interface between a low-voltage fuel-cell source and a high-voltage DC bus for inverters. Zero-voltage switching in all active switches is achieved through using a common active clamp branch, and zero current switching in the rectifier diodes is achieved through discontinuous current conduction in the secondary side. Further, the converter is capable of increased power transfer due to its three-phase power configuration, and it reduces the RMS current per phase, thus reducing conduction losses. Moreover, a delta-delta connection on the three-phase transformer provides parallel current paths and reduces conduction losses in the transformer windings. An efficiency of above 93% is achieved through both improvements in the switching and through reducing conduction losses. A high voltage ratio is achieved by combining inherent voltage boost characteristics of the current-fed converter and the transformer turns ratio. The proposed converter and three-phase PWM strategy is analyzed, simulated, and implemented in hardware. Experimental results are obtained on a 500-W prototype unit, with all of the design verified and analyzed.

In this paper, a five-level inverter is developed and applied for injecting the real power of the renewable power into the grid to reduce the switching power loss, harmonic distortion, and electromagnetic interference caused by the switching operation of power electronic devices. Two dc capacitors, a dual-buck converter, a full-bridge inverter, and a filter configure the five-level inverter. The input of the dual-buck converter is two dc capacitor voltage sources. The dual-buck converter converts two dc capacitor voltage sources to a dc output voltage with three levels and balances these two dc capacitor voltages. The output voltage of the dual-buck converter supplies to the full-bridge inverter. The power electronic switches of the full-bridge inverter are switched in low frequency synchronous with the utility voltage to convert the output voltage of the dual-buck converter to a five-level ac voltage. The output current of the five-level inverter is controlled to generate a sinusoidal current in phase with the utility voltage to inject into the grid. A hardware prototype is developed to verify the performance of the developed renewable power generation system. The experimental results show that the developed renewable power generation system reaches the expected performance.

Multilevel inverters brought a tremendous revolution in high power superior performance industrial drive applications. Minimizing harmonic distortion is a challenging issue for power electronic drive. This problem can be solved by developing suitable modulation technique. There are number of modulation techniques established in the last decade. Among them, the space vector pulse width modulation (SVPWM) is extensively used because of their easier digital realization, better DC bus utilization and lower THD. Conventional SVPWM requires different number of logical computations of on time calculations and different number of lookup table for each triangle due to having their different number of switching states. In this paper, a simple SVPWM is presented where proposed only four logical computations of on time calculation, four active switching states and four lookup table for each triangle. Five level cascaded h-bridge inverter (CHBI) based on SVPWM technique are modeled and analyzed by using MATLAB/Simulink and origin 6.1 with a passive R-L load that can be extended to any level. These results are compared with other lower levels of inverter and with previous established results. From these results, five level CHBI based on SVPWM shows better performance compared to others in terms of THD.

In this paper, a new current source gate drive circuit is proposed for high efficiency synchronous buck VRMs. The proposed circuit achieves quick turn-on and turn-off transition times to reduce switching loss and conduction loss in power MOSFETS. The driver circuit consists of two sets of four control switches and two very small inductors (typically 50 nH-300 nH each at 1 MHz). It drives both the control MOSFET and synchronous MOSFET in synchronous buck VRMs. An analysis, design procedure, optimization procedure and experimental results are presented for the proposed circuit. Experimental results demonstrate an efficiency of 86.6% at 15 A load and 81.9% at 30 A load for 12 V input and 1.3 V output at 1 MHz.


Question: A full-duplex assisted user virtualization scheme for mobile edge computing in 5G networks.

This paper delineates the advanced progression of Network Functions Virtualization (NFV) from its initial phase, independent of Software-Defined Networking (SDN), to a fully integrated SDN-enabled NFV framework. This evolution signifies that SDN not only serves as a foundational support but also significantly influences the design and functionality of virtual network functions (VNFs). In the current iteration, where feasible, the stateless processing in VNFs is shifted from the computational component to the networking component. To substantiate this claim, the paper details the implementation of a flow-centric network access control solution, incorporating an SDN-enabled VNF based on IEEE 802.1x. This system defines services through a set of flow rules, authorized following an end-user authentication procedure. Network access control is enforced at the network level, whereas authentication and authorization status is maintained at the computational level. The deployment of this SDN-enhanced NFV strategy leads to enhanced performance and minimized control channel traffic. This integrated SDN-NFV approach paves the way for expanding the application of NFV, particularly in scenarios requiring extensive stateless packet processing.

Fog computing is an emerging paradigm of cloud computing which to meet the growing computation demand of mobile application. It can help mobile devices to overcome resource constraints by offloading the computationally intensive tasks to cloud servers. The challenge of the cloud is to minimize the time of data transfer and task execution to the user, whose location changes owing to mobility, and the energy consumption for the mobile device. To provide satisfactory computation performance is particularly challenging in the fog computing environment. In this paper, we propose a novel fog computing model and offloading policy which can effectively bring the fog computing power closer to the mobile user. The fog computing model consist of remote cloud nodes and local cloud nodes, which is attached to wireless access infrastructure. And we give task offloading policy taking into account executi+on, energy consumption and other expenses. We finally evaluate the performance of our method through experimental simulations. The experimental results show that this method has a significant effect on reducing the execution time of tasks and energy consumption of mobile devices.

Cellular networks have been engineered and optimized to carrying ever-increasing amounts of mobile data, but over the last few years, a new class of applications based on machine-centric communications has begun to emerge. Automated devices such as sensors, tracking devices, and meters, often referred to as machine-to-machine (M2M) or machine-type communications (MTC), introduce an attractive revenue stream for mobile network operators, if a massive number of them can be efficiently supported. The novel technical challenges posed by MTC applications include increased overhead and control signaling as well as diverse application-specific constraints such as ultra-low complexity, extreme energy efficiency, critical timing, and continuous data intensive uploading. This article explains the new requirements and challenges that large-scale MTC applications introduce, and provides a survey of key techniques for overcoming them. We focus on the potential of 4.5G and 5G networks to serve both the high data rate needs of conventional human-type communication (HTC) subscribers and the forecasted billions of new MTC devices. We also opine on attractive economic models that will enable this new class of cellular subscribers to grow to its full potential.

Nowadays, mobile operators face the challenge to sustain the future data tsunami. In fact, today's increasing data and control traffic generated by new kinds of network usage puts strain on mobile operators', without creating any corresponding equivalent revenue. In our previous work, we analyzed the 3GPP LTE/EPC architecture and showed that a redesign of this architecture is needed to suit future network usages and to provide new revenue generating services. Moreover, we proposed a new control plane based on the OpenFlow (OF) protocol for the LTE/EPC architecture that enables flexibility and programmability aspects. In this paper, we are interested in the programmability aspect. We show how the data plane can be easily configured thanks to OF. In addition, we evaluate the signaling load of our proposed architecture and compare it to that of 3GPP LTE/EPC architecture. The preliminary findings suggest that managing the data plane with OF has little impact on the signaling load while the network programmability is improved.

In this paper we propose HyFog, a novel hybrid task offloading framework in fog computing, where device users have the flexibility of choosing among multiple options for task executions, including local mobile execution, Device-to-Device (D2D) offloaded execution, and Cloud offloaded execution. We further develop a novel three-layer graph matching algorithm for efficient hybrid task offloading among the devices. Specifically, we first construct a three-layer graph to capture the choice space enabled by these three execution approaches, and then the problem of minimizing the total task execution cost is recast as a minimum weight matching problem over the constructed three-layer graph, which can be efficiently solved using the Edmonds's Blossom algorithm. Numerical results demonstrate that the proposed three-layer graph matching solution can achieve superior performance, with more than 50% cost reduction over the case of local task executions by all the devices.

The integration of Device-to-Device (D2D) communication into a cellular network improves system spectral efficiency, increases capacity, reduces power consumption and also reduces traffic to the evolved NodeB (eNB). However, D2D communication generates interference to the conventional cellular network which deteriorates the system performance. In this paper, we propose a radio resource allocation and power control scheme to mitigate the interference using cell sectorization scheme while reusing uplink cellular resources by the D2D pairs. By simulations, we show that our proposed scheme improves the overall system performance compared with the existing methods.

Network Function Virtualization has received a large amount of research and recent efforts have been made to further leverage the cloud to enhance NFV. However, since there are privacy and security issues with using cloud computing, work has been done to allow for operating on encrypted data, which introduces a large amount of overhead in both computation and data, while only providing a limited set of operations, since these encryption schemes are not fully homomorphic. We propose using trusted computing to circumvent these limitations by having hardware enforce data privacy and provide guaranteed computation. Prior work has shown that Intel's Software Guard Extensions can be used to protect the state of network functions, but there are still questions about the usability of SGX in arbitrary NFV applications and the performance of SGX in these applications. We extend prior work to show how SGX can be used in network deployments by extending the Click modular router to perform secure packet processing with SGX. We also present a performance evaluation of SGX on real hardware to show that processing inside of SGX has a negligible performance impact, compared to performing the same processing outside of SGX.

The level of demand for bare-metal cloud services has increased rapidly because such services are cost-effective for several types of workloads, and some cloud clients prefer a single-tenant environment due to the lower security vulnerability of such enviornments. However, as the bare-metal cloud does not utilize a virtualization layer, it cannot use live migration. Thus, there is a lack of manageability with the bare-metal cloud. Live migration support can improve the manageability of bare-metal cloud services significantly.
 This paper suggests an on-demand virtualization technique to improve the manageability of bare-metal cloud services. A thin virtualization layer is inserted into the bare-metal cloud when live migration is requested. After the completion of the live migration process, the thin virtualization layer is removed from the host. We modified BitVisor [19] to implement on-demand virtualization and live migration on the x86 architecture.
 The elapsed time of on-demand virtualization was negligible. It takes about 20 ms to insert the virtualization layer and 30 ms to remove the one. After removing the virtualization layer, the host machine works with bare-metal performance.

This paper presents a quantitative study on the energy-traffic tradeoff problem from the perspective of entire Wireless Local Area Network (WLAN). We propose a novel Energy-Efficient Cooperative Offloading Model (E2COM) for energy-traffic tradeoff, which can ensure the fairness of energy consumption of mobile devices and reduce the computation repetition and eliminate the Internet data traffic redundancy through cooperative execution and sharing computation results. We design an Online Task Scheduling Algorithm (OTS) based on a pricing mechanism and Lyapunov optimization to address the problem without predicting future information on task arrivals, transmission rates and so on. OTS can achieve a desirable tradeoff between the energy consumption and Internet data traffic by appropriately setting the tradeoff coefficient. Simulation results demonstrate that E2COM is more efficient than no offloading and cloud offloading for a variety of typical mobile devices, applications and link qualities in WLAN.

Vehicle-to-vehicle (V2V) communication has the potential to improve road safety significantly by providing connectivity between vehicles to exchange information messages. V2V has recently gained considerable attention in part due to the standardization work that has started for Long Term Evolution (LTE) under the Third Generation Partnership Project (3GPP). Efficient and reliable distributed allocation of time-frequency resources among different vehicle user equipments (VUEs) remains a challenge particularly in dense urban environments. In this work, a new autonomous resource selection scheme for urban V2V communication scenario is proposed. Specifically, the proposed scheme relies on resource partitioning based on VUE heading direction along with a sensing-based collision avoidance mechanism, which aims to alleviate the potential interference between VUEs due to resource collision and in-band emission (IBE). The performance of the two-stage autonomous resource selection scheme is evaluated by system-level simulations in urban scenarios, where the results show a significant performance gain in comparison to existing approaches.

Service Function Chains (SFCs) comprise a sequence of Network Functions (NFs) that are typically traversed in-order by data flows. Consequently, SFC delay grows linearly with the length of the SFC. Yet, for highly latency sensitive applications, this delay may be unacceptable---particularly when the constituent NFs are virtualized, running on commodity servers. In this paper, we investigate how SFC latency may be reduced by exploiting opportunities for parallel packet processing across NFs. We propose ParaBox, a novel hybrid packet processing architecture that, when possible, dynamically distributes packets to VNFs in parallel and merges their outputs intelligently to ensure the preservation of correct sequential processing semantics. To demonstrate the feasibility of our approach, we implement a ParaBox prototype on top of the DPDK-enabled Berkeley Extensible Software Switch. Our preliminary experiment results show that ParaBox can not only significantly reduce the service chaining latency, but also improve throughput.