Question: Image analysis in a DSP setting utilizing OpenCV technology.

In the realm of digital signal processing (DSP), the integration of OpenCV for image processing tasks is rapidly advancing, paving the way for real-time computer vision applications. As technology evolves, mobile computer vision is poised to become as commonplace as touch interfaces, transforming the way we interact with digital devices. This trend is significantly influenced by the capabilities of OpenCV, a powerful library that streamlines the development of computer vision projects, making it easier for developers to incorporate sophisticated image processing features into their DSP environments. The widespread adoption of mobile computer vision, facilitated by tools like OpenCV, promises to revolutionize various sectors, from consumer electronics to industrial automation, by enabling devices to interpret and respond to visual information in real-time, akin to the seamless integration of touch interfaces in today's smartphones and tablets.

217  Abstract-Steganography is the technique of hiding the fact that communication is taking place, by hiding data in other data. Many different carrier file formats can be used, but digital images are the most popular because of their frequency on the Internet. For hiding secret information in images, there exist a large variety of steganographic techniques some are more complex than others and all of them have respective strong and weak points. Steganalysis, the detection of this hidden information, is an inherently difficult problem and requires a thorough investigation so we are using " Edge detection Filter ". In this paper search how the edges of the images can be used to hiding text message in Steganography .It give the depth view of image steganography and Edge detection Filter techniques. Method: In this paper search how the edges of the images can be used to hiding text message in Steganography. For that gray image has been presented. In this method tried to find binary value of each character of text message and then in the next stage, tried to find dark places of gray image (black) by converting the original image to binary image for labeling each object of image by considering on 8 pixel connectivity. Then these images have been converted to RGB image in order to find dark places. Because in this way each sequence of gray color turns into RGB color and dark level of grey image is found by this way if the Gary image is very light the histogram must be changed manually to find just dark places. In the final stage each 8 pixels of dark places has been considered as a byte and binary value of each character has been put in low bit of each byte that was created manually by dark places pixels for increasing security of the main way of least Significant bit steganography. Steganalysis then used to evaluate the hiding process to ensure the data can be hidden in best possible way.

A general technique for the recovery of signi cant image features is presented. The technique is based on the mean shift algorithm, a simple nonparametric procedure for estimating density gradients. Drawbacks of the current methods (including robust clustering) are avoided. Feature space of any nature can be processed, and as an example, color image segmentation is discussed. The segmentation is completely autonomous, only its class is chosen by the user. Thus, the same program can produce a high quality edge image, or provide, by extracting all the signi cant colors, a preprocessor for content-based query systems. A 512 512 color image is analyzed in less than 10 seconds on a standard workstation. Gray level images are handled as color images having only the lightness coordinate.

We present our region-based image retrieval tool, finding region in the picture (FRIP), that is able to accommodate, to the extent possible, region scaling, rotation, and translation. Our goal is to develop an effective retrieval system to overcome a few limitations associated with existing systems. To do this, we propose adaptive circular filters used for semantic image segmentation, which are based on both Bayes' theorem and texture distribution of image. In addition, to decrease the computational complexity without losing the accuracy of the search results, we extract optimal feature vectors from segmented regions and apply them to our stepwise Boolean AND matching scheme. The experimental results using real world images show that our system can indeed improve retrieval performance compared to other global property-based or region-of-interest-based image retrieval methods.

Transport-based techniques for signal and data analysis have recently received increased interest. Given their ability to provide accurate generative models for signal intensities and other data distributions, they have been used in a variety of applications, including content-based retrieval, cancer detection, image superresolution, and statistical machine learning, to name a few, and they have been shown to produce state-of-the-art results. Moreover, the geometric characteristics of transport-related metrics have inspired new kinds of algorithms for interpreting the meaning of data distributions. Here, we provide a practical overview of the mathematical underpinnings of mass transport-related methods, including numerical implementation, as well as a review, with demonstrations, of several applications. Software accompanying this article is available from [43].

Reliable, fast and efficient optic disc localization and blood-vessel detection are the primary tasks in computer analyses of retinal image. Most of the existing algorithms suffer due to inconsistent image contrast, varying individual condition, noises and computational complexity. This paper presents an algorithm to automatically detect landmark features of retinal image, such as optic disc and blood vessel. First, optic disc and blood vessel pixels are detected from blue plane of the image. Then, using OD location the vessel pixels are connected. The detection scheme utilizes basic operations like edge detection, binary thresholding and morphological operation. This method was evaluated on standard retinal image databases, such as STARE and DRIVE. Experimental results demonstrate that the high accuracy achieved by the proposed method is comparable to that reported by the most accurate methods in literature, alongside a substantial reduction of execution time. Thus the method may provide a reliable solution in automatic mass screening and diagnosis of the retinal diseases.

Drowsiness detection is vital in preventing traffic accidents. Eye state analysis - detecting whether the eye is open or closed - is critical step for drowsiness detection. In this paper, we propose an easy algorithm for pupil center and iris boundary localization and a new algorithm for eye state analysis, which we incorporate into a four step system for drowsiness detection: face detection, eye detection, eye state analysis, and drowsy decision. This new system requires no training data at any step or special cameras. Our eye detection algorithm uses Eye Map, thus achieving excellent pupil center and iris boundary localization results on the IMM database. Our novel eye state analysis algorithm detects eye state using the saturation (S) channel of the HSV color space. We analyze our eye state analysis algorithm using five video sequences and show superior results compared to the common technique based on distance between eyelids.

Based on a multi-step process, an automatic hair segmentation method is created and tested on a database of 115 manually segmented hair images. By extracting various information components from an image, including background color, face position, hair color, skin color, and skin mask, a heuristic-based method is created for the detection and segmentation of hair that can detect hair with an accuracy of approximately 75% and with a false hair overestimation error of 34%. Furthermore, it is shown that downsampling the image down to a face width of 25px results in a 73% reduction in computation time with insignificant change in detection accuracy.

Two new, cost-effective thresholding algorithms for use in extracting binary images of characters from machineor hand-printed documents are described. The creation of a binary representation from an analog image requires such algorithms to determine whether a point is converted into a binary one because it falls within a character stroke or a binary zero because it does not. This thresholding is a critical step in Optical Character Recognition (OCR). I t is also essential for other Character Image Extraction (CIEJ applications, such as the processing of machine-printed or handwritten characters from carbon copy forms or bank checks, where smudges and scenic backgrounds, for example, may have to be suppressed. The first algorithm, a nonlinear, adaptive procedure, is implemented with a minimum of hardware and is intended for many CIE applications. The second is a more aggressive approach directed toward specialized, high-volume applications which justify extra complexity.

Computer vision can be understood as the ability to perform inference on image data. Breakthroughs in computer vision technology are often marked by advances in inference techniques, as even the model design is often dictated by the complexity of inference in them. This thesis proposes learning based inference schemes and demonstrates applications in computer vision. We propose techniques for inference in both generative and discriminative computer vision models. Despite their intuitive appeal, the use of generative models in vision is hampered by the difficulty of posterior inference, which is often too complex or too slow to be practical. We propose techniques for improving inference in two widely used techniques: Markov Chain Monte Carlo (MCMC) sampling and message-passing inference. Our inference strategy is to learn separate discriminative models that assist Bayesian inference in a generative model. Experiments on a range of generative vision models show that the proposed techniques accelerate the inference process and/or converge to better solutions. A main complication in the design of discriminative models is the inclusion of prior knowledge in a principled way. For better inference in discriminative models, we propose techniques that modify the original model itself, as inference is simple evaluation of the model. We concentrate on convolutional neural network (CNN) models and propose a generalization of standard spatial convolutions, which are the basic building blocks of CNN architectures, to bilateral convolutions. First, we generalize the existing use of bilateral filters and then propose new neural network architectures with learnable bilateral filters, which we call ‘Bilateral Neural Networks’. We show how the bilateral filtering modules can be used for modifying existing CNN architectures for better image segmentation and propose a neural network approach for temporal information propagation in videos. Experiments demonstrate the potential of the proposed bilateral networks on a wide range of vision tasks and datasets. In summary, we propose learning based techniques for better inference in several computer vision models ranging from inverse graphics to freely parameterized neural networks. In generative vision models, our inference techniques alleviate some of the crucial hurdles in Bayesian posterior inference, paving new ways for the use of model based machine learning in vision. In discriminative CNN models, the proposed filter generalizations aid in the design of new neural network architectures that can handle sparse high-dimensional data as well as provide a way for incorporating prior knowledge into CNNs.

Motion detection is very important in image processing. One way of detecting motion is using optical flow. Optical flow cannot be computed locally, since only one independent measurement is available from the image sequence at a point, while the flow velocity has two components. A second constraint is needed. The method used for finding the optical flow in this project is assuming that the apparent velocity of the brightness pattern varies smoothly almost everywhere in the image. This technique is later used in developing software for motion detection which has the capability to carry out four types of motion detection. The motion detection software presented in this project also can highlight motion region, count motion level as well as counting object numbers. Many objects such as vehicles and human from video streams can be recognized by applying optical flow technique. Keywords—Background modeling, Motion detection, Optical flow, Velocity smoothness constant, motion trajectories.


Question: Implementing image processing techniques in a DSP environment with OpenCV.

This paper offers an in-depth comparison between two prominent libraries, NumPy/SciPy and OpenCV with Python bindings, which are extensively utilized for image processing and computer vision tasks. Python's popularity in the scientific community stems from its clear syntax and rich ecosystem of specialized packages. When it comes to image processing, these two libraries stand out. Our study evaluates both libraries based on performance and ease of use. Additionally, we explore the efficiency of using OpenCV through Python bindings compared to employing its native C implementation directly. This analysis aims to guide developers and researchers in making informed decisions about which tool to use for their computer vision projects, particularly in environments where Python is preferred for its rapid prototyping capabilities.

VLFeat is an open and portable library of computer vision algorithms. It aims at facilitating fast prototyping and reproducible research for computer vision scientists and students. It includes rigorous implementations of common building blocks such as feature detectors, feature extractors, (hierarchical) k-means clustering, randomized kd-tree matching, and super-pixelization. The source code and interfaces are fully documented. The library integrates directly with MATLAB, a popular language for computer vision research.

The advantages of Convolutional Neural Networks (CNNs) with respect to traditional methods for visual pattern recognition have changed the field of machine vision. The main issue that hinders broad adoption of this technique is the massive computing workload in CNN that prevents real-time implementation on low-power embedded platforms. Recently, several dedicated solutions have been proposed to improve the energy efficiency and throughput, nevertheless the huge amount of data transfer involved in the processing is still a challenging issue. This work proposes a new CNN accelerator exploiting a novel memory access scheme which significantly improves data locality in CNN related processing. With this scheme, external memory access is reduced by 50% while achieving similar or even better throughput. The accelerator is implemented using 28nm CMOS technology. Implementation results show that the accelerator achieves a performance of 102GOp/s @800MHz while consuming 0.303mm2 in silicon area. Power simulation shows that the dynamic power of the accelerator is 68mW. Its flexibility is demonstrated by running various different CNN benchmarks.

Solid freeform fabrication (SFF) processes based on mask image projection such as digital micro-mirror devices (DMD) have the potential to be fast and inexpensive. More and more research and commercial systems have been developed based on such digital devices. However, a digital light processing (DLP) projector based on DMD has limited resolution and certain image blurring. In order to use a DLP projector in the large-area mask projection stereolithography, it is critical to plan mask images in order to achieve high accuracy and resolution. Based on our previous work on optimized pixel blending, we present a calibration method for capturing the non-uniformity of a projection image by a low cost off-the-shelf DLP projector. Our method is based on two calibration systems, a geometric calibration system that can calibrate the position, shape, size, and orientation of a pixel and an energy calibration system that can calibrate the light intensity of a pixel. Based on both results, the light intensity at various grayscale levels can be approximated for each pixel. Developing a library of such approximation functions is critical for the optimized pixel blending to generate a better mask image plan. Experimental results verify our calibration results.

In this paper, a fast and flexible algorithm for computing watersheds in digital grayscale images is introduced. A review of watersheds and related notion is first presented, and the major methods to determine watersheds are discussed. The present algorithm is based on an immersion process analogy, in which the flooding of the water in the picture is efficiently simulated using a queue of pixels. It is described in detail and provided in a pseudo C language. We prove the accuracy of this algorithm is superior to that of the existing implementations. Furthermore, it is shown that its adaptation to any kind of digital grid and its generalization to n-dimensional images and even to graphs are straightforward. In addition, its strongest point is that it is faster than any other watershed algorithm. Applications of this algorithm with regard to picture segmentation are presented for MR imagery and for digital elevation models. An example of 3-D watershed is also provided. Lastly, some ideas are given on how to solve complex segmentation tasks using watersheds on graphs. Zndex Terms-Algorithm, digital image, FIFO structure, graph, grid, mathematical morphology, picture segmentation, watersheds.

A 352 288 pixel CMOS image sensor chip with perpixel single-slope ADC and dynamic memory in a standard digital 0.18m CMOS process is described. The chip performs “snapshot” image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10 000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4 9.4 m with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 V/e . At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization.

In this paper we consider the problem of obtaining a picture with improved resolution from an ensemble of K spatially shifted low-resolution pictures. We show that it can be done and provide a procedure for its implementations. The framework and scheme utilized in the generalized multichannel sampling theorem of Papoulis and Brown was found to be an appropriate representation for our problem. The linear channels of this scheme correspond to the processes that produce the low-resolution pictures (by blur and shifts) and to the process of reconstruction. The total process is shown to consist of two distinct degradation-restoration pairs: blurring-deblurring and undersampling-merging. This paper discusses merging. Deblurring (deconvolution) can be done by any desired scheme independent of merging. It is shown that the procedure achieves the claims of super resolution schemes but, unlike many of them, is well posed and robust. This procedure holds for a selected ensemble so that K is not too large and no two of the pictures practially coincide. The number of multiplications per pixel of the improved picture can be reduced to O(K2). o ESJZ

In this paper, we propose a framework for both gradient descent image and object alignment in the Fourier domain. Our method centers upon the classical Lucas & Kanade (LK) algorithm where we represent the source and template/model in the complex 2D Fourier domain rather than in the spatial 2D domain. We refer to our approach as the Fourier LK (FLK) algorithm. The FLK formulation is advantageous when one preprocesses the source image and template/model with a bank of filters (e.g., oriented edges, Gabor, etc.) as 1) it can handle substantial illumination variations, 2) the inefficient preprocessing filter bank step can be subsumed within the FLK algorithm as a sparse diagonal weighting matrix, 3) unlike traditional LK, the computational cost is invariant to the number of filters and as a result is far more efficient, and 4) this approach can be extended to the Inverse Compositional (IC) form of the LK algorithm where nearly all steps (including Fourier transform and filter bank preprocessing) can be precomputed, leading to an extremely efficient and robust approach to gradient descent image matching. Further, these computational savings translate to nonrigid object alignment tasks that are considered extensions of the LK algorithm, such as those found in Active Appearance Models (AAMs).

We introduce a parallel GPU implementation of the Simple Linear Iterative Clustering (SLIC) superpixel segmentation. Using a single graphic card, our implementation achieves speedups of up to 83× from the standard sequential implementation. Our implementation is fully compatible with the standard sequential implementation and the software is now available online and is open source.

This paper presents a complete Optical Character Recognition (OCR) system for camera captured image/graphics embedded textual documents for handheld devices. At first, text regions are extracted and skew corrected. Then, these regions are binarized and segmented into lines and characters. Characters are passed into the recognition module. Experimenting with a set of 100 business card images, captured by cell phone camera, we have achieved a maximum recognition accuracy of 92.74%. Compared to Tesseract, an open source desktop-based powerful OCR engine, present recognition accuracy is worth contributing. Moreover, the developed technique is computationally efficient and consumes low memory so as to be applicable on handheld devices.

Today, the characterization of the technological age is done by the digital images spread. They are the most common form of conveying information whether through internet, newspapers, magazines, or scientific journals. They are used as a strong proof of various crimes and as evidence used for various purposes. The modification, capturing or creating of the image has become easier and available with the emergence of means of image editing and processing tools. One of the most important and popular types of image forgery is a copy-move forgery in which an image part is copied and then pasted into the same image that has the intention of hiding something important or showing a false scene. Because the important properties of the copied parts come from the same image, such as brightness, noise, and texture which will be compatible with the entire image that makes more difficult for experts for the detection and distinguishing the alteration. Usually, the detecting copy move forgery conventional techniques suffer severely from the time-consuming problem. The evaluation of the improved method had been done using (150) images that were selected from two different datasets, “CoMoFoD” and “MICC-F2000”. Experimental results show that the improved method can accurately and quickly reveal the doubled regions of a tampered image. In addition, greatly reducing the processing time in comparison to the Khan algorithm, and the accuracy is kept at the same level. Owing to the availability and technological advancement of the image editing sophisticated tools, there is an increase in the loss of authentication in digital images. Thus, this led us to the proposal of different detection techniques that checks whether the digital images are forged or authentic. The specific type of forgery technique is copy move forgery in which widely used research topic is detection under digital image forensics. In this thesis, an enhancement of copy move image forgery classification is done by implementing hybrid features with classification algorithms like SIFT with SVM and EM algorithm and ORB with SVM and EM.The technique works by applying Firstly the DCT on an image and then on a resultant image, SIFT is obtained after applying DCT. A supervised learning method is proposed for classifying a copy-move image forgery of TIFF, JPEG, and BMP. The process starts with reducing the color of the photos. Achieve the accuracy more than 90%.


Question: Image analysis in a DSP setting utilizing the OpenCV library.

Python as a Powerful Tool for Scientific Computing and Engineering
Python has proven to be a versatile language that can effectively manage and direct scientific codes developed in other languages. Yet, with the integration of fundamental tools, Python evolves into a sophisticated high-level language, perfectly suited for scientific and engineering applications. This language is not only capable of delivering results swiftly enough for immediate utility but also offers the flexibility to enhance performance through additional extensions, making it a preferred choice for many computational tasks in these fields.

**Question**: The Role of Blockchain in Enhancing Supply Chain Transparency

**Documents**: The Impact of Blockchain on Supply Chain Management
The implementation of blockchain technology has the potential to revolutionize supply chain management by providing an unprecedented level of transparency and trust. Blockchain, with its decentralized ledger, ensures that all transactions are recorded in a tamper-proof manner, allowing for real-time tracking of goods and verification of their authenticity. This technology can significantly reduce fraud, improve efficiency, and enhance customer trust in the products they purchase.

**Similar Documents**: Blockchain: A Catalyst for Transparency in Supply Chain Operations
The integration of blockchain technology into supply chain management systems can significantly enhance transparency and foster a greater degree of trust among stakeholders. By offering a decentralized, immutable ledger, blockchain enables the secure recording of all transactions, facilitating real-time monitoring of product movement and confirming their legitimacy. This approach not only minimizes the risk of fraudulent activities but also streamlines operational processes, ultimately leading to increased customer confidence in the authenticity and quality of goods.

Nonlinear image reconstruction based upon sparse representations of images has recently received widespread attention with the emerging framework of compressed sensing (CS). This theory indicates that, when feasible, judicious selection of the type of distortion induced by measurement systems may dramatically improve our ability to perform image reconstruction. However, applying compressed sensing theory to practical imaging systems poses a key challenge: physical constraints typically make it infeasible to actually measure many of the random projections described in the literature, and therefore, innovative and sophisticated imaging systems must be carefully designed to effectively exploit CS theory. In video settings, the performance of an imaging system is characterized by both pixel resolution and field of view. In this work, we propose compressive imaging techniques for improving the performance of video imaging systems in the presence of constraints on the focal plane array size. In particular, we describe a novel yet practical approach that combines coded aperture imaging to enhance pixel resolution with superimposing subframes of a scene onto a single focal plane array to increase field of view. Specifically, the proposed method superimposes coded observations and uses wavelet-based sparsity recovery algorithms to reconstruct the original subframes. We demonstrate the effectiveness of this approach by reconstructing with high resolution the constituent images of a video sequence.

This work investigated two different machine learning techniques: Cascade Learning and Deep Learning, to find out which algorithm performs better to detect the number plate of vehicles registered in Bangladesh. To do this, we created a dataset of about 1000 images collected from a security camera of Independent University, Bangladesh. Each image in the dataset were then labelled manually by selecting the Region of Interest (ROI). In the Cascade Learning approach, a sliding window technique was used to detect objects. Then a cascade classifier was employed to determine if the window contained object of interest or not. In the Deep Learning approach, CIFAR-10 dataset was used to pre-train a 15-layer Convolutional Neural Network (CNN). Using this pretrained CNN, a Regions with CNN (R-CNN) was then trained using our dataset. We found that the Deep Learning approach (maximum accuracy 99.60% using 566 training images) outperforms the detector constructed using Cascade classifiers (maximum accuracy 59.52% using 566 positive and 1022 negative training images) for 252 test images.

In this paper we present a comprehensive and critical survey of face detection algorithms. Face detection is a necessary first-step in face recognition systems, with the purpose of localizing and extracting the face region from the background. It also has several applications in areas such as content-based image retrieval, video coding, video conferencing, crowd surveillance, and intelligent human–computer interfaces. However, it was not until recently that the face detection problem received considerable attention among researchers. The human face is a dynamic object and has a high degree of variability in its apperance, which makes face detection a difficult problem in computer vision. A wide variety of techniques have been proposed, ranging from simple edge-based algorithms to composite high-level approaches utilizing advanced pattern recognition methods. The algorithms presented in this paper are classified as either feature-based or image-based and are discussed in terms of their technical approach and performance. Due to the lack of standardized tests, we do not provide a comprehensive comparative evaluation, but in cases where results are reported on common datasets, comparisons are presented. We also give a presentation of some proposed applications and possible application areas. c © 2001 Academic Press

The goal of face detection is to locate all regions that contain a face. This paper has a simple face detection procedure which has two major steps, first to segment skin region from an image, and second, to decide these regions contain human face or not. Our procedure is based on skin color segmentation and human face features (knowledge-based approach). In this paper, we used RGB, YCbCr, CEILAB (L*a*b) and HSV color models for skin color segmentation. These color models with thresholds, help to remove non skin like pixels from an image. We tested each skin region, that skin region is actually represents a human face or not, by using human face features based on knowledge of geometrical properties of human face. The experiment result shows that, the algorithm gives hopeful results. At last, we concluded this paper and proposed future work.

Face recognition systems play a vital role in many applications including surveillance, biometrics and security. In this work, we present a {\textit complete} real-time face recognition system consisting of a face detection, a recognition and a down sampling module using an FPGA. Our system provides an end-to-end solution for face recognition, it receives video input from a camera, detects the locations of the face(s) using the Viola-Jones algorithm, subsequently recognizes each face using the Eigenface algorithm, and outputs the results to a display. Experimental results show that our complete face recognition system operates at 45 frames per second on a Virtex-5 FPGA.

Image registration finds a variety of applications in computer vision. Unfortunately, traditional image registration techniques tend to be costly. We present a new image registration technique that makes use of the spatial intensity gradient of the images to find a good match using a type of Newton-Raphson iteration. Our technique is faster because it examines far fewer potential matches between the images than existing techniques. Furthermore, this registration technique can be generalized to handle rotation, scaling and shearing. We show show our technique can be adapted for use in a stereo vision system.

Image and geometry registration algorithms are essential components of many computer graphics and computer vision systems. With recent technological advances in RGB-D sensors, robust algorithms that combine 2D image and 3D geometry registration have become an active area of research.
 This course introduces the basics of 2D/3D registration algorithms and provides theoretical explanations and practical tools for designing computer vision and computer graphics systems based on RGB-D devices such as the Microsoft Kinect or Asus Xtion Live. To illustrate the theory and demonstrate practical relevance, the course briefly discusses three applications: rigid scanning, non-rigid modeling, and real-time face tracking.

Stereo vision is an active research topic in computer vision. Point Grey® Bumblebee® and digital single-lens reflex camera (DSLR) are normally found in the stereo vision research, they are robust but expensive. Open source electronic prototyping platforms such as Arduino and Raspberry Pi are interesting products, which allows students or researchers to custom made inexpensive experimental equipment for their research projects. This paper describes the intelligent stereo camera mobile platform developed in our research using Pi and camera modules and presents the concept of using inexpensive open source parts for robotic stereo vision research work in details.

This paper presents an algorithm implemented in real time in a laboratory robot, designed to trace and detect the color of an object in an indoor environment using the Kalman filter. The image capture is done by a kinect camera installed in the robot. The algorithm is programmed into a single board computer, BeagleBone Black that uses the ROS — OpenCV system in image processing.

The state-of-the-art ARM processors provide multiple cores and SIMD instructions. OpenCL is a promising programming model for utilizing such parallel processing capability because of its SPMD programming model and built-in vector support. Moreover, it provides portability between multicore ARM processors and accelerators in embedded systems. In this paper, we introduce the design and implementation of an efficient OpenCL framework for multicore ARM processors. Computational tasks in a program are implemented as OpenCL kernels and run on all CPU cores in parallel by our OpenCL framework. Vector operations and built-in functions in OpenCL kernels are optimized using the NEON SIMD instruction set. We evaluate our OpenCL framework using 37 benchmark applications. The result shows that our approach is effective and promising.


Question: Image analysis in a DSP setting utilizing OpenCV.

This tutorial offers a comprehensive overview of image alignment and stitching techniques. Image alignment methodologies excel at identifying the correspondence among images that have varying levels of overlap, making them indispensable for applications like video stabilization, summarization, and the creation of panoramic images. Image stitching algorithms take the alignment estimations generated by these registration techniques and merge the images into a single, coherent scene, while addressing potential issues such as blurring, ghosting from parallax and scene motion, and differences in image exposure. This tutorial delves into the foundational motion models that underpin alignment and stitching processes. It then outlines efficient direct (pixel-based) and feature-based alignment algorithms, followed by a detailed explanation of blending techniques used to create seamless panoramic images. The tutorial concludes with an exploration of ongoing research challenges in the field of image alignment and stitching.

**Question**: A Direct Search Method to solve Economic Dispatch Problem with Valve-Point Effect

**Documents**: An efficient particle swarm optimization for economic dispatch
This paper presents an efficient particle swarm optimization (EPSO) algorithm for solving economic dispatch (ED) problems. The proposed EPSO algorithm is designed to handle the non-smooth cost function and the valve-point effect, which are common in ED problems. The EPSO algorithm is a modified version of the standard PSO algorithm that incorporates an efficient local search technique to improve the search efficiency and convergence speed. The proposed algorithm is tested on several standard test systems and compared with other optimization algorithms. The results show that the EPSO algorithm can solve ED problems with a high degree of accuracy and efficiency.

**Similar Documents**: This paper introduces an enhanced particle swarm optimization (EPSO) approach for addressing economic dispatch (ED) issues, specifically focusing on non-smooth cost functions and the valve-point effect prevalent in ED scenarios. The EPSO algorithm is an optimized variant of the conventional particle swarm optimization technique, featuring an integrated efficient local search mechanism to boost search effectiveness and accelerate convergence. The proposed methodology is evaluated on a series of benchmark test systems and its performance is contrasted against alternative optimization techniques. The findings highlight the EPSO algorithm's capability to accurately and efficiently tackle economic dispatch problems.

End-to-end Optical Character Recognition (OCR) systems are heavily used to convert document images into machine-readable text. Commercial and open-source OCR systems (like Abbyy, OCRopus, Tesseract etc.) have traditionally been optimized for contemporary documents like books, letters, memos, and other end-user documents. However, these systems are difficult to use equally well for digitizing historical document images, which contain degradations like non-uniform shading, bleed-through, and irregular layout; such degradations usually do not exist in contemporary document images.
 The open-source anyOCR is an end-to-end OCR pipeline, which contains state-of-the-art techniques that are required for digitizing degraded historical archives with high accuracy. However, high accuracy comes at a cost of high computational complexity that results in 1) long runtime that limits digitization of big collection of historical archives and 2) high energy consumption that is the most critical limiting factor for portable devices with constrained energy budget. Therefore, we are targeting energy efficient and high throughput acceleration of the anyOCR pipeline. Generalpurpose computing platforms fail to meet these requirements that makes custom hardware design mandatory. In this paper, we are presenting a new concept named iDocChip. It is a portable hybrid hardware-software FPGA-based accelerator that is characterized by low footprint meaning small size, high power efficiency that will allow using it in portable devices, and high throughput that will make it possible to process big collection of historical archives in real time without effecting the accuracy.
 In this paper, we focus on binarization, which is the second most critical step in the anyOCR pipeline after text-line recognizer that we have already presented in our previous publication [21]. The anyOCR system makes use of a Percentile Based Binarization method that is suitable for overcoming degradations like non-uniform shading and bleed-through. To the best of our knowledge, we propose the first hardware architecture of the PBB technique. Based on the new architecture, we present a hybrid hardware-software FPGA-based accelerator that outperforms the existing anyOCR software implementation running on i7-4790T in terms of runtime by factor of 21, while achieving energy efficiency of 10 Images/J that is higher than that achieved by low power embedded processors with negligible loss of recognition accuracy.

We study an energy functional for computing optical flow that combines three assumptions: a brightness constancy assumption, a gradient constancy assumption, and a discontinuity-preserving spatio-temporal smoothness constraint. In order to allow for large displacements, linearisations in the two data terms are strictly avoided. We present a consistent numerical scheme based on two nested fixed point iterations. By proving that this scheme implements a coarse-to-fine warping strategy, we give a theoretical foundation for warping which has been used on a mainly experimental basis so far. Our evaluation demonstrates that the novel method gives significantly smaller angular errors than previous techniques for optical flow estimation. We show that it is fairly insensitive to parameter variations, and we demonstrate its excellent robustness under noise. In Proc. 8th European Conference on Computer Vision, Springer LNCS 3024, T. Pajdla and J. Matas (Eds.), vol. 4, pp. 25-36, Prague, Czech Republic, May 2004 c © Springer-Verlag Berlin Heidelberg 2004 Received The Longuet-Higgins Best Paper Award.

This supplement provides additional details on the bilateral solver and its extensions in Sections 1–4, and a plethora of experiments and comparisons to prior work in Section 5. In Section 1 we derive the bilateral-space quadratic objective at the core of the bilateral solver. Section 2 details the bilateral-space pyramid representation used for faster initialization and preconditioning. Section 3 extends the bilateral solver to use a robust error function to cope with outliers. Section 4 improves the performance of the bilateral solver when applied to multiple output channels. Finally, in Section 5 we provide additional evaluation of the bilateral solver and extensively compare it to numerous existing and novel baseline techniques.

In this paper, we have derived analytic expressions for the phase correlation of downsampled images. We have shown that for downsampled images the signal power in the phase correlation is not concentrated in a single peak, but rather in several coherent peaks mostly adjacent to each other. These coherent peaks correspond to the polyphase transform of a filtered unit impulse centered at the point of registration. The analytic results provide a closed-form solution to subpixel translation estimation, and are used for detailed error analysis. Excellent results have been obtained for subpixel translation estimation of images of different nature and across different spectral bands.

In the past few years the data produced all over the internet has increased with an exponential rate. The storage costs have been rising immensely. But, in the field of Computer Science, the introduction of new technologies has resulted in reduction of storage costs. This led to a rampant rise in the data generation rates. This huge amount of data that is so vast and complex such that classical methods are insufficient for processing is termed as ‘Big Data’. There are various tools in Hadoop to analyze the textual data such as Pig, HBase, etc. But the data present on the Internet as well as the Social Networking sites comprises of unstructured media. The maximum spectrum of the media files is covered by Image data. The major concern is not about the storage of images, but the processing of images being generated with the speed of light. Every day around 350 million pictures are being uploaded on social network. Until now, over 200 billion photos have been uploaded only on Facebook. This accounts to an average of around 200 photos per user. This whole amount of data generated round the globe can be classified into three formats-Structured, Semi-Structured, and Unstructured. The Image data contains not only the pictures but also the data defining those pictures such as the resolution, source of the image, capture device, etc. To fetch all this information in a structured format HIPI (Hadoop Image Processing Interface) tools are used. In this paper image processing is performed on a MultiNode Hadoop Cluster and its performance is measured.

We integrate the cascade-of-rejectors approach with the Histograms of Oriented Gradients (HoG) features to achieve a fast and accurate human detection system. The features used in our system are HoGs of variable-size blocks that capture salient features of humans automatically. Using AdaBoost for feature selection, we identify the appropriate set of blocks, from a large set of possible blocks. In our system, we use the integral image representation and a rejection cascade which significantly speed up the computation. For a 320 × 280 image, the system can process 5 to 30 frames per second depending on the density in which we scan the image, while maintaining an accuracy level similar to existing methods.

Conventional weed control system is usually used by spraying herbicides uniformly throughout the land. Excessive use of herbicides on an ongoing basis can produce chemical waste that is harmful to plants and soil. The application of precision agriculture farming in the detection process in order to control weeds using Computer Vision On Farm becomes interesting, but it still has some problems due to computer size and power consumption. Raspberry Pi is one of the minicomputer with low price and low power consumption. Having computing like a desktop computer with the open source Linux operating system can be used for image processing and weed fractal dimension processing using OpenCV library and C programming. This research results the best fractal computation time when performing the image with dimension size of 128 x 128 pixels. It is about 7 milliseconds. Furthermore, the average speed ratio between personal computer and Raspberry Pi is 0.04 times faster. The use of Raspberry Pi is cost and power consumption efficient compared to personal computer.

This paper presents a novel and efficient texture-based method for modeling the background and detecting moving objects from a video sequence. Each pixel is modeled as a group of adaptive local binary pattern histograms that are calculated over a circular region around the pixel. The approach provides us with many advantages compared to the state-of-the-art. Experimental results clearly justify our model.

Computational techniques involving contrast enhancement and noise filtering on two-dimensional image arrays are developed based on their local mean and variance. These algorithms are nonrecursive and do not require the use of any kind of transform. They share the same characteristics in that each pixel is processed independently. Consequently, this approach has an obvious advantage when used in real-time digital image processing applications and where a parallel processor can be used. For both the additive and multiplicative cases, the a priori mean and variance of each pixel is derived from its local mean and variance. Then, the minimum mean-square error estimator in its simplest form is applied to obtain the noise filtering algorithms. For multiplicative noise a statistical optimal linear approximation is made. Experimental results show that such an assumption yields a very effective filtering algorithm. Examples on images containing 256 × 256 pixels are given. Results show that in most cases the techniques developed in this paper are readily adaptable to real-time image processing.

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Question: Evaluating conflicts in the equitable distribution of indivisible items through a spectrum of criteria.

This paper presents a novel solution to the combinatorial assignment problem, focusing on the distribution of indivisible goods such as course schedules among students. Traditional impossibility theorems suggest that only dictatorships can achieve both efficiency and strategyproof mechanisms in such scenarios, but these are often deemed unfair due to the unequal distribution of goods among participants. The proposed solution involves a series of steps to address the dilemma between efficiency, incentive, and fairness.

First, two new criteria for outcome fairness are introduced: the maximin share guarantee and envy bounded by a single good. These criteria are designed to be more accommodating of indivisibilities in goods, formalizing the notion that dictatorships are inherently unfair.

Second, the existence of an approximation to Competitive Equilibrium from Equal Incomes (CEEI) is demonstrated, where incomes are unequal but can be made arbitrarily close together. This approximation also allows for a small margin of error in market clearing, which diminishes as the problem size grows, making it particularly applicable to real-world scenarios.

Third, it is shown that this Approximate CEEI meets the proposed fairness criteria, ensuring a more equitable distribution of goods.

Finally, a mechanism based on Approximate CEEI is developed that is strategyproof for agents who are traditionally considered price takers by economists. This mechanism is tested against real-world data and compared with other theoretical and practical mechanisms. The results indicate that most alternative mechanisms either fail to be strategyproof for these agents or are unfair ex-post, often suffering from both shortcomings. The proposed solution, therefore, offers a significant improvement in balancing efficiency, fairness, and strategyproofness in the combinatorial assignment of indivisible goods.


Question: Using a criteria scale to identify conflicts in the fair division of indivisible items.

This document explores a variant of the Santa Claus problem, focusing on the equitable distribution of n gifts among m children. Each child assigns a subjective value to each gift, denoted as pij, representing child i's valuation of gift j. The objective is to maximize the happiness of the least fortunate child by optimizing the minimum total value of gifts received by any child, expressed as mini=1,...,m sumj ∈ Si pij, where Si is the set of gifts given to the i-th child. The main contribution is an approximation algorithm with a performance guarantee of O(log log m/log log log m) for the restricted assignment scenario, where pij ∈ pj,0, indicating that gift j is either valued at pj or has no value to each child. The algorithm is devised through the rounding of a large linear programming relaxation, commonly known as the configuration LP. Additionally, the analysis reveals that the configuration LP has an integrality gap of Ω(m1/2) in more general scenarios, when pij can assume arbitrary values. This study provides a nuanced understanding of fair allocation challenges and their algorithmic solutions in the context of gift distribution.


Question: Using a scale of criteria to identify conflicts in the fair division of indivisible items.

This paper delves into the issue of allocating indivisible goods in a manner that is perceived as fair by all parties involved, from an algorithmic standpoint. The concept of fair division has been widely explored in economic theory, leading to the proposal of various fairness criteria. Among these, envy-freeness stands out as a pivotal concept. In our study, each player is assigned a monotone utility function that quantifies their valuation of any subset of goods. An allocation is deemed envy-free if every participant prefers their allocated share over any other player's share. While envy-free allocations are guaranteed to exist when goods are divisible, the presence of indivisibilities complicates the scenario. Our findings reveal that there are allocations in which envy is limited by the maximum marginal utility, and we provide a straightforward algorithm to compute such allocations. We then tackle the optimization challenge of identifying an allocation that minimizes envy. We prove that, in the general case, the problem is intractable and cannot be approximated in polynomial time unless P equals NP. To circumvent this, we examine specific instances (for instance, additive utilities) that are closely linked to a category of job scheduling problems. Here, we derive approximation algorithms and establish inapproximability results. Additionally, we explore the development of truthful mechanisms aimed at achieving allocations with bounded envy, a critical aspect in practical applications of fair division.


Question: Using a criteria scale to identify conflicts in the equitable distribution of indivisible items.

This paper delves into the intricate challenge of allocating indivisible goods among players, a topic that has received less attention compared to the division of divisible goods, which has been extensively explored in mathematics and economics. The focus here is on the Max-Min Fairness problem, a fairness criterion for allocating m indivisible items among k players. Each player has a distinct valuation function for subsets of goods, and the objective is to distribute the items to maximize the lowest valuation among players. Adopting a game-theoretic viewpoint, the paper demonstrates that, for two players with additive valuations, the randomized cut-and-choose mechanism yields an expected minimum valuation that is a 1/2-approximation of the optimum. To further this analysis, it is shown that no truthful mechanism can compute the exact optimum. From an algorithmic standpoint, when the true additive valuation functions are part of the input, a simple algorithm is introduced that offers a 1/(m - k + 1) approximation ratio, ensuring each player receives at least 1/k of the value of all but the k - 1 most valuable items. Additionally, an algorithm with an additive error against the fractional optimum, bounded by the value of the largest item, is presented. These two approximation algorithms have distinct strengths, with instances where one outperforms the other, highlighting the complexity and nuances of allocating indivisible goods under fairness constraints.


Question: Using a scale of criteria to characterize conflicts in the fair division of indivisible goods.

This paper introduces a novel technique, the Polynomial-Time Approximation Scheme (PTAS), aimed at maximizing the minimum machine completion time in a scheduling context. Unlike traditional scheduling methods that may not efficiently handle large-scale problems, the PTAS offers a scalable solution by approximating the optimal solution within a guaranteed factor of accuracy. Central to the PTAS is its ability to balance the trade-off between computational complexity and solution quality. By focusing on maximizing the minimum completion time, the PTAS ensures a fair distribution of workload across machines, which is particularly beneficial in scenarios where resource allocation needs to be equitable. The application of PTAS to scheduling problems demonstrates its effectiveness in achieving near-optimal solutions in a reasonable amount of time, making it a valuable tool for managing complex scheduling tasks in industries such as manufacturing and logistics. Comparative analysis against exact algorithms and other heuristic methods highlights the superior performance of PTAS in terms of solution quality and computational efficiency, especially for problems of significant size.


Question: Handling hardware device failures through software tolerance mechanisms.

This paper introduces the Microdrivers framework, an innovative solution for enhancing the reliability and ease of development for device drivers while maintaining high performance. Traditionally, drivers operate in the kernel to ensure optimal efficiency and direct access to kernel services, but this approach compromises reliability and increases complexity for developers. Kernel driver faults can lead to system-wide crashes, and developers lack the user-mode tools necessary for efficient coding, instead relying on less user-friendly kernel tools.

Microdrivers addresses these challenges by partitioning driver functions between the kernel and user mode. Critical path code, crucial for I/O performance, remains in the kernel to ensure high-speed data handling. Conversely, non-critical tasks such as initialization and configuration are shifted to a user-mode process, improving reliability and developer experience. To ensure compatibility with existing drivers without necessitating a complete rewrite, the paper presents DriverSlicer, a tool that facilitates the division of kernel drivers into kernel- and user-level components with minimal programmer intervention. Through experimentation, it is demonstrated that up to 65% of driver code can be relocated to user mode without impacting typical performance, and only a small percentage (1-6%) of the code requires annotations for this process. This approach not only enhances driver reliability and developer productivity but also preserves performance, making it a promising solution for mitigating the risks associated with kernel driver failures.

Autonomous or semi-autonomous systems are deployed in environments where contact with programmers or technicians is infrequent or undesirable. To operate reliably, such systems should be able to adapt to new circumstances on their own. This paper describes our combined approach for adaptable software architecture and task synthesis from high-level goals, which is based on a three-layer model. In the uppermost layer, reactive plans are generated from goals expressed in a temporal logic. The middle layer is responsible for plan execution and assembling a configuration of domain-specific software components, which reside in the lowest layer. Moreover, the middle layer is responsible for selecting alternative components when the current configuration is no longer viable for the circumstances that have arisen. The implementation demonstrates that the approach enables us to handle non-determinism in the environment and unexpected failures in software components.

Malicious modification of hardware in untrusted fabrication facilities, referred to as hardware Trojan, has emerged as a major security concern. Comprehensive detection of these Trojans during postmanufacturing test has been shown to be extremely difficult. Hence, it is important to develop design techniques that provide effective countermeasures against hardware Trojans by either preventing Trojan attacks or facilitating detection during test. Obfuscation is a technique that is conventionally employed to prevent piracy of software and hardware intellectual property (IP). In this work, we propose a novel application of key-based circuit structure and functionality obfuscation to achieve protection against hardware Trojans triggered by rare internal circuit conditions. The proposed obfuscation scheme is based on judicious modification of the state transition function, which creates two distinct functional modes: normal and Responsible Editor: S. T. Chakradhar A preliminary version of this work has been published in the International Conference on Computer Aided Design (ICCAD), 2009. R. S. Chakraborty (B) Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, West Bengal 721302, India e-mail: rschakraborty@cse.iitkgp.ernet.in S. Bhunia Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, OH 44106, USA e-mail: skb21@case.edu obfuscated. A circuit transitions from the obfuscated to the normal mode only upon application of a specific input sequence, which defines the key. We show that it provides security against Trojan attacks in two ways: (1) it makes some inserted Trojans benign, i.e. they become effective only in the obfuscated mode; and (2) it prevents an adversary from exploiting the true rare events in a circuit to insert hard-to-detect Trojans. The proposed design methodology can thus achieve simultaneous protection from hardware Trojans and hardware IP piracy. Besides protecting ICs against Trojan attacks in foundry, we show that it can also protect against malicious modifications by untrusted computeraided design (CAD) tools in both SoC and FPGA design flows. Simulation results for a set of benchmark circuits show that the scheme is capable of achieving high levels of security against Trojan attacks at modest area, power and delay overhead.

Several recent studies have reported & examined the phenomenon that long-running software systems show an increasing failure rate and/or a progressive degradation of their performance. Causes of this phenomenon, which has been referred to as "software aging", are the accumulation of internal error conditions, and the depletion of operating system resources. A proactive technique called "software rejuvenation" has been proposed as a way to counteract software aging. It involves occasionally terminating the software application, cleaning its internal state and/or its environment, and then restarting it. Due to the costs incurred by software rejuvenation, an important question is when to schedule this action. While periodic rejuvenation at constant time intervals is straightforward to implement, it may not yield the best results. The rate at which software ages is usually not constant, but it depends on the time-varying system workload. Software rejuvenation should therefore be planned & initiated in the face of the actual system behavior. This requires the measurement, analysis, and prediction of system resource usage. In this paper, we study the development of resource usage in a web server while subjecting it to an artificial workload. We first collect data on several system resource usage & activity parameters. Non-parametric statistical methods are then applied toward detecting & estimating trends in the data sets. Finally, we fit time series models to the data collected. Unlike the models used previously in the research on software aging, these time series models allow for seasonal patterns, and we show how the exploitation of the seasonal variation can help in adequately predicting the future resource usage. Based on the models employed here, proactive management techniques like software rejuvenation triggered by actual measurements can be built

Hardware/software codesign investigates the concurrent design of hardware and software components of complex electronic systems. It tries to exploit the synergy of hardware and software with the goal to optimize and/or satisfy design constraints such as cost, performance, and power of the final product. At the same time, it targets to reduce the time-to-market frame considerably. This paper presents major achievements of two decades of research on methods and tools for hardware/software codesign by starting with a historical survey of its roots, by highlighting its major research directions and achievements until today, and finally, by predicting in which direction research in codesign might evolve in the decades to come.

In the last few years, many different attacks against computing platform targeting hardware or low level firmware have been published. Such attacks are generally quite hard to detect and to defend against as they target components that are out of the scope of the operating system and may not have been taken into account in the security policy enforced on the platform. In this paper, we study the case of remote attacks against network adapters. In our case study, we assume that the target adapter is running a flawed firmware that an attacker may subvert remotely by sending packets on the network to the adapter. We study possible detection techniques and their efficiency. We show that, depending on the architecture of the adapter and the interface provided by the NIC to the host operating system, building an efficient detection framework is possible. We explain the choices we made when designing such a framework that we called NAVIS and give details on our proof of concept implementation.

Flexible and reliable connection is critical for self-reconfiguration, self-assembly, or self-healing. However, most existing connection mechanisms suffer from a deficiency that a connection would seize itself if one end malfunctions or is out of service. To mitigate this limitation on self-healing, this paper presents a new SINGO connector that can establish or disengage a connection even if one end of the connection is not operational. We describe the design and the prototype of the connector and demonstrate its performance by both theoretical analysis and physical experimentations.

Custom instruction set extensions can substantially boost performance of reconfigurable softcore CPUs. While this approach is commonly tailored to one specific FPGA system, we are presenting a fine-grained FPGA-like overlay architecture which can be implemented in the user logic of various FPGA families from different vendors. This allows the execution of a portable application consisting of a program binary and an overlay configuration in a completely heterogeneous environment. Furthermore, we are presenting different optimizations for dramatically reducing the implementation cost of the proposed overlay architecture. In particular, this includes the mapping of the overlay interconnection network directly into the switch fabric of the hosting FPGA. Our case study demonstrates an overhead reduction of an order of magnitude as compared to related approaches.

Cloud computing is an increasingly important solution for providing services deployed in dynamically scalable cloud networks. Services in the cloud computing networks may be virtualized with specific servers which host abstracted details. Some of the servers are active and available, while others are busy or heavy loaded, and the remaining are offline for various reasons. Users would expect the right and available servers to complete their application requirements. Therefore, in order to provide an effective control scheme with parameter guidance for cloud resource services, failure detection is essential to meet users' service expectations. It can resolve possible performance bottlenecks in providing the virtual service for the cloud computing networks. Most existing Failure Detector (FD) schemes do not automatically adjust their detection service parameters for the dynamic network conditions, thus they couldn't be used for actual application. This paper explores FD properties with relation to the actual and automatic fault-tolerant cloud computing networks, and find a general non-manual analysis method to self-tune the corresponding parameters to satisfy user requirements. Based on this general automatic method, we propose specific and dynamic Self-tuning Failure Detector, called SFD, as a major breakthrough in the existing schemes. We carry out actual and extensive experiments to compare the quality of service performance between the SFD and several other existing FDs. Our experimental results demonstrate that our scheme can automatically adjust SFD control parameters to obtain corresponding services and satisfy user requirements, while maintaining good performance. Such an SFD can be extensively applied to industrial and commercial usage, and it can also significantly benefit the cloud computing networks.

Defining a processor micro-architecture for a targeted productspace involves multi-dimensional optimization across performance, power and reliability axes. A key decision in sucha definition process is the circuit-and technology-driven parameterof the nominal (voltage, frequency) operating point. This is a challenging task, since optimizing individually orpair-wise amongst these metrics usually results in a designthat falls short of the specification in at least one of the threedimensions. Aided by academic research, industry has nowadopted early-stage definition methodologies that considerboth energy-and performance-related metrics. Reliabilityrelatedenhancements, on the other hand, tend to get factoredin via a separate thread of activity. This task is typically pursuedwithout thorough pre-silicon quantifications of the energyor even the performance cost. In the late-CMOS designera, reliability needs to move from a post-silicon afterthoughtor validation-only effort to a pre-silicon definitionprocess. In this paper, we present BRAVO, a methodologyfor such reliability-aware design space exploration. BRAVOis supported by a multi-core simulation framework that integratesperformance, power and reliability modeling capability. Errors induced by both soft and hard fault incidence arecaptured within the reliability models. We introduce the notionof the Balanced Reliability Metric (BRM), that we useto evaluate overall reliability of the processor across soft andhard error incidences. We demonstrate up to 79% improvementin reliability in terms of this metric, for only a 6% dropin overall energy efficiency over design points that maximizeenergy efficiency. We also demonstrate several real-life usecaseapplications of BRAVO in an industrial setting.

This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.


Question: Handling hardware device failures through software tolerance mechanisms.

XFI: A Protective Shield for System Address Spaces through Software Guards

XFI is a pioneering security framework designed to provide robust protection and flexible access control for system address spaces, applicable across privilege levels and compatible with legacy code in off-the-shelf systems. To achieve this, XFI integrates static analysis techniques with inline software guards and a dual-stack execution model. Our implementation of XFI on the Windows platform for the x86 architecture employs binary rewriting and a standalone verifier; the integrity of the implementation hinges on the verifier, but not on the rewriter. We have successfully applied XFI to various software components, including device drivers and multimedia codecs, ensuring their secure operation within both the kernel and user-mode address spaces, all while incurring minimal performance overhead.

Pipelining has become a common technique to increase throughput of the instruction fetch, instruction decode, and instruction execution portions of modern computers. Branch instructions disrupt the flow of instructions through the pipeline, increasing the overall execution cost of branch instructions. Three schemes to reduce the cost of branches are presented in the context of a general pipeline model. Ten realistic Unix domain programs are used to directly compare the cost and performance of the three schemes and the results are in favor of the software-based scheme. For example, the software-based scheme has a cost of 1.65 cycles/branch vs. a cost of 1.68 cycles/branch of the best hardware scheme for a highly pipelined processor (11-stage pipeline). The results are 1.19 (software scheme) vs. 1.23 cycles/branch (best hardware scheme) for a moderately pipelined processor (5-stage pipeline).

Increasingly many systems have to run all the time with no downtime allowed. Consider, for example, systems controlling electric power plants and e-banking servers. Nevertheless, security patches and a constant stream of new operating system versions need to be deployed without stopping running programs. These factors naturally lead to a pressing demand for live update---upgrading all or parts of the operating system without rebooting. Unfortunately, existing solutions require significant manual intervention and thus work reliably only for small operating system patches.
 In this paper, we describe an automated system for live update that can safely and automatically handle major upgrades without rebooting. We have implemented our ideas in Proteos, a new research OS designed with live update in mind. Proteos relies on system support and nonintrusive instrumentation to handle even very complex updates with minimal manual effort. The key novelty is the idea of state quiescence, which allows updates to happen only in safe and predictable system states. A second novelty is the ability to automatically perform transactional live updates at the process level, ensuring a safe and stable update process. Unlike prior solutions, Proteos supports automated state transfer, state checking, and hot rollback. We have evaluated Proteos on 50 real updates and on novel live update scenarios. The results show that our techniques can effectively support both simple and complex updates, while outperforming prior solutions in terms of flexibility, security, reliability, and stability of the update process.

We study the resilience to Byzantine failures of distributed implementations of Stochastic Gradient Descent (SGD). So far, distributed machine learning frameworks have largely ignored the possibility of failures, especially arbitrary (i.e., Byzantine) ones. Causes of failures include software bugs, network asynchrony, biases in local datasets, as well as attackers trying to compromise the entire system. Assuming a set of n workers, up to f being Byzantine, we ask how resilient can SGD be, without limiting the dimension, nor the size of the parameter space. We first show that no gradient aggregation rule based on a linear combination of the vectors proposed by the workers (i.e, current approaches) tolerates a single Byzantine failure. We then formulate a resilience property of the aggregation rule capturing the basic requirements to guarantee convergence despite f Byzantine workers. We propose Krum, an aggregation rule that satisfies our resilience property, which we argue is the first provably Byzantine-resilient algorithm for distributed SGD. We also report on experimental evaluations of Krum.

Counterfeiting of goods and electronic devices is a growing problem that has a huge economic impact on the electronics industry. Sometimes the consequences are even more dramatic, when critical systems start failing due to the use of counterfeit lower quality components. Hardware Intrinsic security (i.e. security systems built on the unique electronic fingerprint of a device) offers the potential to reduce the counterfeiting problem drastically. In this paper we will show how Hardware Intrinsic Security (HIS) can be used to prevent various forms of counterfeiting and over-production. HIS technology can also be used to bind software or user data to specific hardware devices, which provides additional security to both soft- and hardware vendors as well as consumers using HIS-enabled products. Besides showing the benefits of HIS, we will also provide an extensive overview of the results (both scientific and industrial) that Intrinsic-ID has achieved studying and implementing HIS.

Predicting the reliability of a system in its actual life-cycle conditions and estimating its time to failure is helpful in decision making to mitigate system risks. There are three approaches to prognostics: the physics-of-failure approach, the data-driven approach, and the fusion approach. A key requirement in all these approaches is identification of the appropriate parameter(s) to monitor to gather data that can be used to assess impending failure. This paper presents a physics-of-failure approach, which uses failure modes, mechanisms and effects analysis (FMMEA) to enhance prognostics planning and implementation. This paper also presents the fusion approach to prognostics and the applicability of FMMEA to this approach. An example case of generating FMMEA information and using that to identify appropriate parameters to monitor is presented.

In this paper we work on the balance between hardware and software implementation of a machine learning algorithm, which belongs to the area of statistical learning theory. We use system-on-chip technology to demonstrate the potential usefulness of moving the critical sections of an algorithm into HW: the so-called hardware/software balance. Our experiments show that the approach can achieve speedups using a complex machine learning algorithm called a support vector machine. The experiments are conducted on a real-time Java virtual machine named Java optimized processor

We present results of a systematic investigation of leakage of compromising information via electromagnetic (EM) emanations from CMOS devices. These emanations are shown to consist of a multiplicity of signals, each leaking somewhat different information about the underlying computation. We show that not only can EM emanations be used to attack cryptographic devices where the power side–channel is unavailable, they can even be used to break power analysis countermeasures.

As the complexity of distributed computing systems increases, systems management tasks require significantly higher levels of automation; examples include diagnosis and prediction based on real-time streams of computer events, setting alarms, and performing continuous monitoring. The core of autonomic computing, a recently proposed initiative towards next-generation IT-systems capable of 'self-healing', is the ability to analyze data in real-time and to predict potential problems. The goal is to avoid catastrophic failures through prompt execution of remedial actions.This paper describes an attempt to build a proactive prediction and control system for large clusters. We collected event logs containing various system reliability, availability and serviceability (RAS) events, and system activity reports (SARs) from a 350-node cluster system for a period of one year. The 'raw' system health measurements contain a great deal of redundant event data, which is either repetitive in nature or misaligned with respect to time. We applied a filtering technique and modeled the data into a set of primary and derived variables. These variables used probabilistic networks for establishing event correlations through prediction algorithms. We also evaluated the role of time-series methods, rule-based classification algorithms and Bayesian network models in event prediction.Based on historical data, our results suggest that it is feasible to predict system performance parameters (SARs) with a high degree of accuracy using time-series models. Rule-based classification techniques can be used to extract machine-event signatures to predict critical events with up to 70% accuracy.

There are two basic models for the on-chip memory in CMP systems:hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison of the two modelsunder the same set of assumptions about technology, area, and computational capabilities. The goal is to quantify how and when they differ in terms of performance, energy consumption, bandwidth requirements, and latency tolerance for general-purpose CMPs. We demonstrate that for data-parallel applications, the cache-based and streaming models perform and scale equally well. For certain applications with little data reuse, streaming scales better due to better bandwidth use and macroscopic software prefetching. However, the introduction of techniques such as hardware prefetching and non-allocating stores to the cache-based model eliminates the streaming advantage. Overall, our results indicate that there is not sufficient advantage in building streaming memory systems where all on-chip memory structures are explicitly managed. On the other hand, we show that streaming at the programming model level is particularly beneficial, even with the cache-based model, as it enhances locality and creates opportunities for bandwidth optimizations. Moreover, we observe that stream programming is actually easier with the cache-based model because the hardware guarantees correct, best-effort execution even when the programmer cannot fully regularize an application's code.

Applicationservicesfor theend-userareall importantin today’scommunicationnetworks,andcoulddictatethesuccessor failureof technologyor serviceproviders[39]. It is importantto develop and deploy applicationfunctionality quickly [18]. The ability to compose servicesfrom independentprovidersprovidesa flexible way to quickly build new end-to-endfunctionality. Suchcompositionof services acrossthe network and acrossdifferent serviceproviders becomesespeciallyimportant in the context of growing popularityandheterogeneityin 3G+ accessnetworks and devices[25]. In this work, we provide a framework for constructing such composed services on the Internet. Robustnessandhigh-availability arecrucial for Internet services.While cluster-basedmodelsfor resilienceto failureshave beenbuilt for web-servers[27] aswell asproxy services[11, 4], theseareinadequatein thecontext of composedservices.This is especiallyso whenthe application sessionis long-lived, andfailureshaveto behandledduring asession. In the context of composed services, we address the important and challenging issues of resilience to failures, and adapting to changes in overall performance during longlived sessions. Our framework is basedon a connection-orientedoverlay network of compute-clusterson theInternet.Theoverlay network provides the context for composingservices over the wide-area,and monitoring for livenessand performanceof a session. We have performedinitial analysesof the feasibility of network failure detectionover the wide-areaInternet. And we have a preliminaryevaluation of the overheadassociatedwith suchan overlay network. We presentour plansfor furtherevaluationandrefinement of thearchitecture;andfor examiningissuesrelatedto the creationof theoverlaytopology. 1 Intr oduction Application functionality for the end-useris thedriving force behinddevelopmentof technologyandits adoption. It is importantto be ableto developanddeploy new functionality quickly [18]. Compositionof existing servicesto achieve new functionalityenablessuchquick development throughreuseof alreadydeployed components.Consider for example,thescenarioshown in Figure1. Video-on-demand server Replicated instances Service Provider A


Question: Handling hardware device failures through software tolerance mechanisms.

CuriOS: Enhancing System Reliability through Innovative Operating System Architecture

In a microkernel operating system, an error in a service can lead to state corruption and failure, affecting all clients utilizing that service. Simply restarting the service may not be an optimal solution for reliability, as it can result in the loss of crucial client-related state, such as session information. CuriOS, a pioneering OS design, addresses this challenge by employing lightweight distribution, isolation, and persistence of OS service state to minimize state loss during restarts. Moreover, the design significantly curtails error propagation within client-related state maintained by OS services.

This is achieved by encapsulating services within separate protection domains and only granting access to client-related state during the processing of requests. Such an approach ensures that errors are contained within the service, preventing them from cascading to other parts of the system and affecting multiple clients.

Experiments involving fault injection have demonstrated that CuriOS can recover from 87% to 100% of manifested errors in various OS services, including file systems, network services, timers, and schedulers, while maintaining low performance overheads. This highlights the effectiveness of CuriOS in enhancing system reliability without compromising on performance.

Cloud computing is pervasive, but cloud service outages still take place. One might say that the computing forecast for tomorrow is “cloudy with a chance of failure.” One main reason why major outages still occur is that there are many unknown large-scale failure scenarios in which recovery might fail. We propose a new type of cloud service, Failure as a Service (FaaS), which allows cloud services to routinely perform large-scale failure drills in real deployments.

We present results of a systematic investigation of leakage of compromising information via electromagnetic (EM) emanations from CMOS devices. These emanations are shown to consist of a multiplicity of signals, each leaking somewhat different information about the underlying computation. We show that not only can EM emanations be used to attack cryptographic devices where the power side–channel is unavailable, they can even be used to break power analysis countermeasures.

Chain replication is a new approach to coordinating clusters of fail-stop storage servers. The approach is intended for supporting large-scale storage services that exhibit high throughput and availability without sacrificing strong consistency guarantees. Besides outlining the chain replication protocols themselves, simulation experiments explore the performance characteristics of a prototype implementation. Throughput, availability, and several objectplacement strategies (including schemes based on distributed hash table routing) are discussed.

Many kinds of memory safety vulnerabilities have been endangering software systems for decades. Amongst other approaches, fuzzing is a promising technique to unveil various software faults. Recently, feedback-guided fuzzing demonstrated its power, producing a steady stream of security-critical software bugs. Most fuzzing efforts—especially feedback fuzzing—are limited to user space components of an operating system (OS), although bugs in kernel components are more severe, because they allow an attacker to gain access to a system with full privileges. Unfortunately, kernel components are difficult to fuzz as feedback mechanisms (i.e., guided code coverage) cannot be easily applied. Additionally, non-determinism due to interrupts, kernel threads, statefulness, and similar mechanisms poses problems. Furthermore, if a process fuzzes its own kernel, a kernel crash highly impacts the performance of the fuzzer as the OS needs to reboot. In this paper, we approach the problem of coverageguided kernel fuzzing in an OS-independent and hardware-assisted way: We utilize a hypervisor and Intel’s Processor Trace (PT) technology. This allows us to remain independent of the target OS as we just require a small user space component that interacts with the targeted OS. As a result, our approach introduces almost no performance overhead, even in cases where the OS crashes, and performs up to 17,000 executions per second on an off-the-shelf laptop. We developed a framework called kernel-AFL (kAFL) to assess the security of Linux, macOS, and Windows kernel components. Among many crashes, we uncovered several flaws in the ext4 driver for Linux, the HFS and APFS file system of macOS, and the NTFS driver of Windows.

When systems fail in the field, logged error or warning messages are frequently the only evidence available for assessing and diagnosing the underlying cause. Consequently, the efficacy of such logging—how often and how well error causes can be determined via postmortem log messages—is a matter of significant practical importance. However, there is little empirical data about how well existing logging practices work and how they can yet be improved. We describe a comprehensive study characterizing the efficacy of logging practices across five large and widely used software systems. Across 250 randomly sampled reported failures, we first identify that more than half of the failures could not be diagnosed well using existing log data. Surprisingly, we find that majority of these unreported failures are manifested via a common set of generic error patterns (e.g., system call return errors) that, if logged, can significantly ease the diagnosis of these unreported failure cases. We further mechanize this knowledge in a tool called Errlog , that proactively adds appropriate logging statements into source code while adding only 1.4% performance overhead. A controlled user study suggests that Errlog can reduce diagnosis time by 60.7%.

In recent years, hardware Trojans have drawn the attention of governments and industry as well as the scientific community. One of the main concerns is that integrated circuits, e.g., for military or criticalinfrastructure applications, could be maliciously manipulated during the manufacturing process, which often takes place abroad. However, since there have been no reported hardware Trojans in practice yet, little is known about how such a Trojan would look like, and how difficult it would be in practice to implement one. In this paper we propose an extremely stealthy approach for implementing hardware Trojans below the gate level, and we evaluate their impact on the security of the target device. Instead of adding additional circuitry to the target design, we insert our hardware Trojans by changing the dopant polarity of existing transistors. Since the modified circuit appears legitimate on all wiring layers (including all metal and polysilicon), our family of Trojans is resistant to most detection techniques, including fine-grain optical inspection and checking against “golden chips”. We demonstrate the effectiveness of our approach by inserting Trojans into two designs — a digital post-processing derived from Intel’s cryptographically secure RNG design used in the Ivy Bridge processors and a side-channel resistant SBox implementation — and by exploring their detectability and their effects on security.

ion-Based Livelock/Deadlock Checking for Hardware Verification In-Ho Moon and Kevin Harer Synopsys Inc. {mooni, kevinh}@synopsys.com

Monitoring is an essential part of many program development tools, and plays a central role in debugging, optimization, status reporting, and reconfiguration. Traditional monitoring techniques are inadequate when monitoring complex systems such as multiprocessors or distributed systems. A new approach is described in which a historical database forms the conceptual basis for the information processed by the monitor. This approach permits advances in specifying the low-level data collection, specifying the analysis of the collected data, performing the analysis, and displaying the results. Two prototype implementations demonstrate the feasibility of the approach.

With the increasing clock rate and transistor count of today’s microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and power-delivery issues are becoming especially critical for high-performance computing systems. In this work, we investigate dynamic thermal management as a technique to control CPUpower dissipation. With the increasing usage of clock gating techniques, the average power dissipation typically seen by common applications is becoming much less than the chip’s rated maximum power dissipation. However; system designers still must design thermal heat sinks to withstand the worst-case scenario. We define and investigate the major components of any dynamic thermal management scheme. Specijcally we explore the tradeoffs between several mechanisms for responding to periods of thermal trauma and we consider the effects of hardware and sofnyare implementations. With appropriate dynamic thermal management, the CPU can be designed for a much lower maximum power rating, with minimal performance impact for typical applications.

As robots become more common in everyday life it will be increasingly important to understand how non-experts will view robot failure. In this study, we found that severity of failure seems to be tightly coupled with perceived risk to self rather than risk to the robot's task and object. We initially thought perceived severity would be tied to the cost of damage. Instead, participants placed falling drinking glasses above a laptop when rating the severity of the failure. Related results reinforce the primacy of personal safety over the financial cost of damage and suggest the results were tied to proximity to breaking glass.