Question: A comparative analysis of Dickson and Fibonacci charge pump performances.

This paper explores the theoretical boundaries of two-phase switched-capacitor (SC) dc-dc converters, delving into the achievable performance metrics for a designated capacitor count, k. The research reveals that the maximum attainable step-up or step-down conversion ratio aligns with the kth Fibonacci number. Furthermore, it establishes a ceiling on the number of switches required in any SC circuit, which is determined by the formula 3k^2. The practical applications of these findings are significant, as they enable the optimization of component usage for specific applications and facilitate the design of SC converters capable of sustaining output voltage regulation and high conversion efficiency across a broad spectrum of input voltage fluctuations. The identified constraints on output resistance and efficiency serve as valuable tools for the selection and comparative analysis of SC converters, illustrating their potential for enhancing system performance under varying conditions.

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without lowthreshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 0.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

The efficient and fast control of electric power forms part of the key technologies of modern automated production. It is performed using electronic power converters. The converters transfer energy from a source to a controlled process in a quantized fashion, using semiconductor switches which are turned on and off at fast repetition rates. The algorithms which generate the switching functions – pulsewidth modulation techniques – are manifold. They range from simple averaging schemes to involved methods of real-time optimization. This paper gives an overview.

The architecture, design, and implementation of two clock-free analog class D audio power amplifiers using 0.5 ¿m CMOS standard technology are introduced. The amplifiers are designed to consume significantly less power than former implementations. Both designs operate with a 2.7 V single voltage supply and deliver a maximum output power of 250 mW into an 8 ¿ speaker. The two class-D amplifiers are based on a hysteretic sliding mode controller, which avoids the complex task of generating the highly linear triangle carrier signal used in conventional architectures. The first design generates a two-level modulated signal, known as binary modulated amplifier (BMA); the second topology implements a three-level modulated signal, also called ternary modulated amplifier (TMA). The architectures and implementations are simple and compact, providing very low quiescent power consumption. Experimental results of the BMA/TMA yield an efficiency of 89/90% and a total harmonic distortion plus noise (THD+N) of 0.02/0.03%, respectively. The efficiency and linearity is comparable to state-of-the-art amplifiers but the static power consumption is less than one tenth of previous proposed architectures. Both class D amplifiers achieve a power supply rejection ratio greater than 75 dB at 217 Hz, and a signal-to-noise ratio (SNR) higher than 90 dB within the whole audio band. Each amplifier occupies less than 1.5 mm2.

A 1.8V CMOS chopper four-quadrant analog multiplier, intending to serve as an autonomous IC block for low-frequency signal processing, is presented. Particular emphasis is laid upon achieving low output noise by means of chopper stabilization, while the multiplier's operation is based on the MOS Translinear Principle. The proposed design has been implemented and simulated in TSMC 0.18 µm CMOS process.

A high efficient LLCC-type resonant dc-dc converter is discussed in this paper for a low-power photovoltaic application. Emphasis is put on the different design mechanisms of the resonant tank. At the same time soft switching of the inverter as well as the rectifier bridge are regarded. Concerning the design rules, a new challenge is solved in designing a LLCC-converter with voltage-source output. Instead of the resonant elements, ratios of them, e.g. the ratio of inductances Ls/Lp is considered as design parameters first. Furthermore, the derived design rule for the transformer-inductor device fits directly into the overall LLCC-design. Due to the nature of transformers, i.e. the relation of the inductances Ls/Lp is only a function of geometry, this design parameter is directly considered by geometry. Experimental results demonstrate the high efficiency.

The amount of stored energy is an important issue in the low-droop and high-precision pulse generation. Pulse forming network (PFN) simulating an open-ended transmission line seems to be useful due to its minimum stored energy. The drawbacks of the PFN include low-output pulse quality and constant pulsewidth, which limit their applications. Another limitation of generating rectangular pulses using PFN is that half of the charged voltage appears in the output when delivering the entire stored energy to the matched load. This paper proposes a structure of PFN-based pulse generator that overcomes the above-mentioned limitations. For continuous pulsewidth adjustment, a lossless scheme is presented. By increasing the ratio of the load magnitude to the characteristic impedance, the amplitude of the output pulse voltage would be approximately equal to that of the charged voltage. Therefore, the semiconductor switches can be utilized in the PFN pulse generator easily. In addition, the pulse quality is enhanced and faster rising time is obtained in comparison with the conventional PFNs. In this proposal, the stored energy quantity is limited to three times the energy needed for the output pulse in the case of  $R_{L}=10Z_{0}$ . To verify the proposed structure, a prototype is simulated using PSPICE software, and the experimental results are presented.

Operating a bridge-type PWM (pulse width modulation) switch mode power converter with asymmetrical duty ratios can eliminate switching losses with no increase in conduction loss. This circuit topology combines the best features of resonant (zero switching loss) and switch mode (low conclusion loss) circuits. Design equations are presented for just such a circuit.<<ETX>>

This paper discusses application of direct charge measurement (DCM) on characterizing on-chip interconnect capacitance. Measurement equipment and techniques are leveraged from Flat Panel Display testing. On-chip active device is not an essential necessity for DCM test structure and it is easy to implement parallel measurements. Femto-Farad measurement sensitivity is achieved without having on-chip active device. Measurement results of silicon and glass substrates, including parallel measurements, are presented.

Power consumption from logic circuits, interconnections, dock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between ~ I I ~ I T O M ~ C ~ ~ O I W , clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom design. Also comparisons between static and dynamic logic are given. Results show that the power consumption of all interconnections and off chip driving can be up to 20% and 65% of the total power consumption respectively. Compared to cell library design, gate array designed chips consume about 10% more power, and power reduction in full custom designed chips could be 15%.

A zero-voltage switching (ZVS) flyback-boost (FB) converter with a voltage-doubler rectifier (VDR) has been proposed. By combining the common part between a flyback converter and a boost converter as a parallel-input/series-output (PISO) configuration, this proposed circuit can increase a step-up ratio and clamp the surge voltage of switches. The secondary VDR provides a further extended step-up ratio as well as its voltage stress to be clamped. An auxiliary switch instead of a boost diode enables all switches to be turned on under ZVS conditions. The zero-current turn-off of the secondary VDR alleviates its reverse-recovery losses. The operation principles, the theoretical analysis, and the design consideration are investigated. The experimental results from a 250W and 42V-to-400V prototype are shown to verify the proposed scheme.


Question: A comparative analysis of Dickson and Fibonacci charge pump performances.

This paper introduces an analytical framework for assessing and optimizing the performance of switched-capacitor (SC) dc-dc converters by evaluating their output impedance. This methodology has been validated through both simulation and experimental testing, ensuring its reliability. The developed formulation enables the straightforward optimization of capacitor dimensions to adhere to constraints like total capacitance or energy storage limits. Additionally, it facilitates the optimization of switch sizes while accounting for total switch conductances or volt-ampere (V-A) product constraints. This approach not only allows for the comparison of various SC topologies but also contrasts SC converters with traditional magnetic-based dc-dc circuits in diverse application contexts. Notably, the analysis reveals that ladder-type SC converters outperform conventional magnetic-based converters in terms of conduction loss for conversion ratios in the medium to high range. This comprehensive analysis provides valuable insights for the design and optimization of SC dc-dc converters in practical scenarios, emphasizing their efficiency advantages in specific applications.

An analytical investigation of a dual-mode ring oscillator is presented. The ring oscillator is designed using a CMOS 0.18-μm technology with differential eight-stage delay cells employing auxiliary input devices. With a proper startup control, the oscillator operates in two different modes covering two different frequency bands. A nonlinear model, along with the linearization method, is used to obtain the transient and steady-state behaviors of the dual-mode ring oscillator. The analytical derivations are verified through HSPICE simulation. The oscillator operates at the frequency bands from 2-5 GHz and from 0.1-2 GHz, respectively.

The eGaN HEMTs with ZVS technique have emerged in high frequency converters to reduce the switching loss. This paper investigates an eGaN HEMT ZVS isolated SEPIC converter running up to 2 MHz. Furthermore, an inductor optimization method is proposed to ensure ZVS and reduce reverse conduction loss of the SR. The efficiency curve is optimized based on the trade-off method between the switching and conduction losses. Moreover, the embedded inductor is proposed to reduce the conduction loss of the inductor. Finally, two 2 MHz eGaN HEMT prototypes with the commercial and embedded inductor with 18–36 V input and 5 V/2 A output are built respectively to verify the effectiveness of the proposed methods. The converters achieve a peak efficiency of over 88.2% and power density of 52.9 W/in3, outperforming the state-of-art power module products.

As the precision of the capacitance ratios among binary-weighted capacitors is the key to accuracy/performance of charge-scaling digital-to-analog converters, it is very important to generate a highly matched common-centroid layout with minimum routing-induced parasitics. However, most of the previous works only focused on common-centroid placement optimization with the consideration of random and systematic mismatch. This paper introduces a novel common-centroid capacitor layout generation approach to minimize the parasitic impact on circuit accuracy/performance. Experimental results show that, compared with the manual layout, the layout generated by the presented approach can achieve even smaller layout area and better circuit accuracy/performance within much shorter time.

A novel, accurate, compact, and power-efficient lithium-ion (Li-Ion) battery charger designed to yield maximum capacity, cycle life, and therefore runtime is presented and experimentally verified. The proposed charger uses a diode to smoothly (i.e., continuously) transition between two high-gain linear feedback loops and control a single power MOS device, automatically charging the battery with constant current and then constant voltage. An adaptive power-efficient charging scheme in the form of a cascaded switching regulator supply ensures the voltage across the charging power-intensive pMOS remains low, thereby reducing its power losses and yielding up to 27% better overall power efficiency. An 83% power-efficient printed circuit board prototype was built and used to charge several Li-Ion batteries to within plusmn0.43% of their optimum full-charge voltage and therefore within a negligibly small fraction of their full capacity

Adapting power-electronic converters that are used in pulsed-power application attracted considerable attention during recent years. In this paper, a modular bipolar high-voltage pulse generator is proposed based on the voltage multipliers and half-bridge converters concept by using power electronics switches. This circuit is capable to generate repetitive high voltage bipolar pulses with a flexible output pattern, by using low voltage power supply and elements. The proposed topology was simulated in MATLAB/Simulink. To verify the circuit operation a four-stage laboratory prototype has been assembled and tested. The results confirm the theoretical analysis and show the validity of the converter scheme.

Modern system-on-chip (SoC) environments are swamped in high frequency noise that is generated by RF and digital circuits and propagated onto supply rails through capacitive coupling. In these systems, linear regulators are used to shield noise-sensitive analog blocks from high frequency fluctuations in the power supply. The paper presents a low dropout regulator that achieves power supply rejection (PSR) better than -40 dB over the entire frequency spectrum. The system has an output voltage of 1.0 V and a maximum current capability of 10 mA. It consists of operational amplifiers (op amps), a bandgap reference, a clock generator, and a charge pump and has been designed and simulated using BSIM3 models of a 0.5 /spl mu/m CMOS process obtained from MOSIS.

Recently, LLC resonant converters are gaining more and more interest in DC/DC conversion due to their high efficiency and power density. Usually, they are used in low power applications, i.e. in the range of few hundred Watt and with constant output load, however they are very appealing in high power and renewable energy applications as well as in many other applications affected by wide variations of the load and/or the source voltage. This paper presents and discusses a novel half bridge DC/DC resonant converter with digital control and fuzzy logic. The proposed system is compared with a more traditional PID controller. A variable frequency control algorithms are implemented using a low cost, high performance Texas Instrument TMS320F28069 DSP for the regulation of the output voltage. Simulation results using MATLAB are presented to evaluate the quality of the obtained result. A laboratory prototype has been realized and experimental results obtained using both PID and Fuzzy controllers are shown and discussed.

In this paper a design and comparison between a fully differential RC Miller compensated CMOS op-amp and conventional op-amp is presented. High gain enables the circuit to operate efficiently in a closed loop feedback system, whereas high bandwidth makes it suitable for high speed applications. A novel RC Miller compensation technique is used to optimize the parameters of gain and bandwidth for high speed applications are illustrated in this research work. The design is also able to address any fluctuation in supply or dc input voltages and stabilizes the operation by nullifying. The design is implemented on TSMC 0.18 m CMOS process at 3.3 V as supply voltage under room temperature 27 C. The simulated result shows that a unity gain bandwidth of 136.8 MHz with a high gain of 92.27 dB is achieved for the proposed op-amp circuit. The total areas of the layouts are 0.000158 mm and 0.000532 mm for conventional and proposed respectively. Key wrods: Two-Stage Op-amp, fully differential, high gain, high bandwidth

A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than two V/sub GS/ drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The op amp is characterized by low static power consumption and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5-/spl mu/m CMOS technology verify the scheme operating with /spl plusmn/0.9-V supplies and close to rail-to-rail input and output swing.

This paper introduces a fully integrated RF energy-harvesting system. The system can simultaneously deliver the current demanded by external dc loads and store the extra energy in external capacitors, during periods of extra output power. The design is fabricated in 0.18- $\mu \text{m}$  CMOS technology, and the active chip area is 1.08 mm2. The proposed self-startup system is reconfigurable with an integrated LC matching network, an RF rectifier, and a power management/controller unit, which consumes 66–157 nW. The required clock generation and the voltage reference circuit are integrated on the same chip. Duty cycle control is used to operate for the low input power that cannot provide the demanded output power. Moreover, the number of stages of the RF rectifier is reconfigurable to increase the efficiency of the available output power. For high available power, a secondary path is activated to charge an external energy storage element. The measured RF input power sensitivity is −14.8 dBm at a 1-V dc output.


Question: A comparative analysis of Dickson and Fibonacci charge pump performances.

Innovative MOS Charge Pumps for Enhanced Low-Voltage Functionality

This paper presents advanced MOS charge pumps, which employ charge transfer switches (CTS's) to orchestrate charge flow and amplify output voltage, specifically tailored for low-voltage applications. By harnessing the internally generated boosted voltage to regulate the CTS of preceding stages, these charge pumps are optimized for operation under low-voltage conditions. The incorporation of dynamic control over the CTS's effectively curtails the reverse charge sharing effect, leading to an augmentation in voltage pumping efficiency. Moreover, the constraints associated with diode-configured output stages are alleviated through the utilization of a high-amplitude clock signal for pumping. Through the implementation of these novel circuit strategies, the feasibility of a 1.2-V-to-3.5-V charge pump and a 2-V-to-16-V charge pump is successfully demonstrated, showcasing the versatility and efficacy of the proposed design in low-voltage environments.

A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications.

In this paper, a gain-boosting preamplifier-latch comparator with minimum input referred offset voltage is proposed. The preamplifier utilizes telescope structure with cross-coupled active loading, which enhances the gain of preamplifier. In order to minimize the delay time of comparator, the input DC range and the ratio of PMOS/NMOS are selected carefully. The circuit is fabricated in TSMC 0.18um with 1.8V power supply.

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulkdriven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) based on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 μW. PSpice simulation results using the 0.18 μm CMOS technology from TSMC are included to verify the design functionality and correspondence with theory.

This brief presents an energy-efficient level shifter (LS) to convert a subthreshold input signal to an above-threshold output signal. In order to achieve a wide range of conversion, a dual current mirror (CM) structure consisting of a virtual CM and an auxiliary CM is proposed. The circuit has been implemented and optimized in SMIC 40-nm technology. The postlayout simulation demonstrates that the new LS can achieve voltage conversion from 0.2 to 1.1 V. Moreover, at the target voltage of 0.3 V, the proposed LS exhibits an average propagation delay of 66.48 ns, a total energy per transition of 72.31 fJ, and a static power consumption of 88.4 pW, demonstrating an improvement of <inline-formula> <tex-math notation="LaTeX">$6.0\times $ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$13.1\times $ </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">$89.0\times $ </tex-math></inline-formula>, respectively, when compared with Wilson CM-based LS.

In this paper, a systematic review of bridgeless power factor correction (PFC) boost rectifiers, also called dual boost PFC rectifiers, is presented. Performance comparison between the conventional PFC boost rectifier and a representative member of the bridgeless PFC boost rectifier family is performed. Loss analysis and experimental efficiency evaluation for both CCM and DCM/CCM boundary operations are provided.

This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in the charge pump. The architecture maintains high signal integrity while each port consumes only 7.5 mW/Gb/s. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.

The aim of this study is to develop a high-efficiency single-input multiple-output (SIMO) dc-dc converter. The proposed converter can boost the voltage of a low-voltage input power source to a controllable high-voltage dc bus and middle-voltage output terminals. The high-voltage dc bus can take as the main power for a high-voltage dc load or the front terminal of a dc-ac inverter. Moreover, middle-voltage output terminals can supply powers for individual middle-voltage dc loads or for charging auxiliary power sources (e.g., battery modules). In this study, a coupled-inductor-based dc-dc converter scheme utilizes only one power switch with the properties of voltage clamping and soft switching, and the corresponding device specifications are adequately designed. As a result, the objectives of high-efficiency power conversion, high step-up ratio, and various output voltages with different levels can be obtained. Some experimental results via a kilowatt-level prototype are given to verify the effectiveness of the proposed SIMO dc-dc converter in practical applications.

In this work, we present a novel ultra-low power timer designed using the gate leakage of MOS capacitors. The test chip was fabricated in a 0.13 mum CMOS technology and the total circuit area is 480 mum2. Measurement results show that the circuit functions correctly at a wide range of supply voltages from 300 mV to 1.2 V, making it particularly suitable for subthreshold systems. The temperature sensitivity is 0.16%/degC at 600 mV and 0.6%/degC at 300 mV. The power dissipation is less than 1pW running at 20degC and 300 mV.

Demand for system-on-chip solutions has increased the interest in low drop-out (LDO) voltage regulators which do not require a bulky off-chip capacitor to achieve stability, also called capacitor-less LDO (CL-LDO) regulators. Several architectures have been proposed; however comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This paper compares CL-LDOs in a unified matter. We designed, fabricated, and tested five illustrative CL-LDO regulator topologies under common design conditions using 0.6?m CMOS technology. We compare the architectures in terms of (1) line/load regulation, (2) power supply rejection, (3) line/load transient, (4) total on-chip compensation capacitance, (5) noise, and (6) quiescent power consumption. Insights on what optimal topology to choose to meet particular LDO specifications are provided.

The low power VLSI design has an important role in designing of many electronic systems. While designing any combinational or sequential circuits, the important parameters like power consumption, implementation area, voltage leakage and performance of the circuit are to be considered. Design of area, high speed and powerefficient data path logic systems forms the largest areas of research in VLSI system design. This paper presents a low power Carry look ahead adder design using Full swing Gate diffusion (FS-GDI) technique. The proposed CLA implementation utilizes improved full-swing GDI F1 and F2 gates, which are the counterparts of standard CMOS NAND and NOR gates. The basic Gate Diffusion Input (GDI) logic style suffers from some practical limitations like swing degradation, fabrication complexity in standard CMOS process and bulk connections. These limitations can be overcome by Full swing GDI technique. The proposed technique utilizes a single swing restoration (SR) transistor to improve the output swing of F1 and F2 GDI gates. A 16-bit CLA is designed and Simulations are performed by Mentor graphics 130nm CMOS technology ELDO simulator. Simulation results have shown a greater reduction in delay, power dissipation and area.


Question: A comparative analysis of Dickson and Fibonacci charge pump performance.

This paper presents a comprehensive analytical and practical assessment of switched-capacitor DC-DC converters, highlighting their suitability as an alternative to inductor-based converters in low-power and medium-power applications. The research introduces a simplified methodology for analyzing the output impedance of a switched-capacitor converter, which serves as a critical indicator of performance and power loss. This impedance, characterized by its resistive nature, exhibits two distinct asymptotic behaviors: one at high switching frequencies, where resistive elements predominantly influence impedance, and another at low switching frequencies, where charge transfer among ideal capacitors becomes the dominant factor. An optimization technique is proposed to enhance converter performance by determining optimal component sizes, taking into account practical limitations. A comparative study is conducted on various switched-capacitor converter configurations within these two asymptotic scenarios. The performance of these converters, evaluated through conduction loss metrics, is juxtaposed against two inductor-based DC-DC converters. Notably, at moderate to high conversion ratios, switched-capacitor converters exhibit considerably lower conduction losses compared to inductor-based buck converters. The paper delves into practical considerations of converter implementation, including the impact of device parasitics on power loss and strategies for transistor control. Both integrated and discrete device implementations are discussed. With the application of appropriate analysis techniques, switched-capacitor DC-DC converters emerge as a compelling alternative to traditional power converters, offering significant advantages in certain operational scenarios.

This paper describes an integrated frequency multiplier, implemented as a Gilbert cell based frequency doubler in a 130 nm SiGe BiCMOS technology. The circuit demonstrates a 3 dB bandwidth of 97–134GHz with peak output power of 1 dBm for 1 dBm input power. The fundamental suppression, measured at the single-ended output, is better than 21 dBc while the frequency doubler consumes 69mW from a 3.3V supply. The doubler is preceded by a differential amplifier functioning as an active balun to generate a differential signal for the Gilbert cell.

This paper proposes new step-up DC-DC converters with high ratio capability. The proposed DC-DC converters are derived using combination of boost converters and buck-boost converters. A high ratio capability is achieved by parallel input and series output combination so that the efficiency is better than the one that is achieved by using a conventional boost converter. A method to reduce the input and output ripples are also proposed in this paper. Simulated and experimental results are included to show the validity of the proposed converters.

The self-oscillating flyback converter is a popular circuit for cost-sensitive applications due to its simplicity and low component count. This paper presents self-oscillating fly-back converter for mobile batteries charging applications. The converter is designed to step-down the high voltage input to an acceptable level from 220 VAC to 7VDC. By adding indictor and capacitor the power factor and input currant increased, and became 500mA, where the old input currant was 250mA, Diode was connected between Emitter and collector, so the output voltage was improved, and has less ripple, in addition to the soft switching was obtained, simulation model is developed by using MULTISIM software. The operation principle of this converter is described using some operating waveforms based on simulation results and a detailed circuit operation analysis. Analytical results are verified by laboratory experiment. With an input of 220 VAC, 500mA and an output of 7V DC, the efficiency of circuit was75%.

An auto-zero and chopper operational amplifier with a 4.5-60 V supply voltage range is realized, using a 0.18 μm CMOS process augmented by 5 V CMOS and 60 V DMOS transistors. It achieves a maximum offset voltage drift of 0.02 μV/°C, a minimum CMRR of 145 dB, a noise PSD of 6.8 nV/√Hz, and a 3.1 MHz unity gain bandwidth, while dissipating 840 μA of current. Up-modulated chopper ripple is suppressed by auto- zeroing. Furthermore, glitches from the charge injection of the input switches are mitigated by employing six parallel input stages with 800 kHz interleaved clocks. This moves the majority of the glitch energy up to 4.8 MHz, while leaving little energy at 800 kHz. As a result, the requirements on an external low-pass glitch filter is relaxed, and a wider usable signal bandwidth can be obtained. Maximum input bias current due to charge injection mismatch is reduced from 1.5 nA to 150 pA by post production trimming with an on-chip charge mismatch compensation circuit.

This paper presents an inductive DC-DC boost converter for energy harvesting using a thermoelectric generator with a minimum startup voltage of 70 mV and a regulated output voltage of 1.25 V. With a typical generator resistance of 40 Ω, an output power of 17 μW can be provided, which translates to an end-to-end efficiency of 58%. The converter employs Schmitt-trigger logic startup control circuitry and an ultra-low voltage charge pump using modified Schmitt-trigger driving circuits optimized for driving capacitive loads. Together with a novel ultra-low leakage power switch and the required control scheme, to the best of the authors' knowledge, this enables the lowest minimum voltage with fully integrated startup.

In this paper, modified circuit topologies of a differential voltage-controlled oscillator (VCO) and a quadrature VCO (QVCO) in a standard bulk 90-nm CMOS process are presented for low dc power and low phase-noise applications. By utilizing current-reuse and transformer-feedback techniques, the proposed VCO and QVCO can be operated at reduced dc power consumption while maintaining extraordinary circuit performance in terms of low phase-noise and low amplitude/phase errors. The VCO circuit topology is investigated to obtain the design procedure. The VCO is further applied to the QVCO design with a bottom-series coupling technique. The coupling network between two differential VCOs and device size are properly designed based on our proposed design methodology to achieve low amplitude and phase errors. Moreover, the VCO and the QVCO are fully characterized with amplitude and phase errors via a four-port vector network analyzer. With a dc power of 3 mW, the VCO exhibits a frequency tuning range from 20.3 to 21.3 GHz, a phase noise of - 116.4 dBc/Hz at 1-MHz offset, a figure-of-merit (FOM) of -198 dBc/Hz, a phase error of 3.8° , and an amplitude error of 0.9 dB. With a dc power of 6 mW, the QVCO demonstrates a phase noise of -117.4 dBc/Hz, a FOM of -195.6 dBc/Hz, a phase error of 4° , and an amplitude error of 0.6 dB. The proposed VCO and QVCO can be compared with the previously reported state-of-the-art VCOs and QVCOs in silicon-based technologies.

This brief presents a power-efficient voltage level-shifter architecture that is capable of converting extremely low levels of input voltages to higher levels. In order to avoid the static power dissipation, the proposed structure uses a current generator that turns on only during the transition times, in which the logic level of the input signal is not corresponding to the output logic level. Moreover, the strength of the pull-up device is decreased when the pull-down device is pulling down the output node in order for the circuit to be functional even for the input voltage lower than the threshold voltage of a MOSFET. The operation of the proposed structure is also analytically investigated. Post-layout simulation results of the proposed structure in a 0.18-μm CMOS technology show that at the input low supply voltage of 0.4 V and the high supply voltage of 1.8 V, the level shifter has a propagation delay of 30 ns, a static power dissipation of 130 pW, and an energy per transition of 327 fJ for a 1-MHz input signal.

In this paper, we present a methodology to enhance the operating range of a Miller frequency divider. Conventionally Miller frequency dividers are visualized as mixers. We present how injection locking portrait of Miller dividers helps us to understand the dynamics of Miller frequency dividers. Further, we discuss how to enhance the operating range while optimizing the divider between power dissipation and operating range. The Miller divider with the proposed methodology has been designed in a standard CMOS 65 nm (low leakage) process. Post layout simulation results show that Miller divider with optimization techniques presented in this paper can operate over the frequency range of 13 GHz for 0dBm input power at center frequency of 61.5 GHz.

An analytical investigation of a dual-mode ring oscillator is presented. The ring oscillator is designed using a CMOS 0.18-μm technology with differential eight-stage delay cells employing auxiliary input devices. With a proper startup control, the oscillator operates in two different modes covering two different frequency bands. A nonlinear model, along with the linearization method, is used to obtain the transient and steady-state behaviors of the dual-mode ring oscillator. The analytical derivations are verified through HSPICE simulation. The oscillator operates at the frequency bands from 2-5 GHz and from 0.1-2 GHz, respectively.

In this paper, a high-conversion-ratio bidirectional dc-dc converter with coupled inductor is proposed. In the boost mode, two capacitors are parallel charged and series discharged by the coupled inductor. Thus, high step-up voltage gain can be achieved with an appropriate duty ratio. The voltage stress on the main switch is reduced by a passive clamp circuit. Therefore, the low resistance RDS(ON) of the main switch can be adopted to reduce conduction loss. In the buck mode, two capacitors are series charged and parallel discharged by the coupled inductor. The bidirectional converter can have high step-down gain. Aside from that, all of the switches achieve zero voltage-switching turn-on, and the switching loss can be improved. Due to two active clamp circuits, the energy of the leakage inductor of the coupled inductor is recycled. The efficiency can be further improved. The operating principle and the steady-state analyses of the voltage gain are discussed. Finally, a 24-V-input-voltage, 400-V-output-voltage, and 200-W-output-power prototype circuit is implemented in the laboratory to verify the performance.


Question: A comparative analysis of Dickson and Fibonacci charge pump performance.

This article presents an investigation into switched-capacitor DC-DC converters, specifically charge pumps, designed for on-chip, low-power applications. The novel configurations introduced here are built upon the parallel connection of two identical SC converters operating in opposite phases, thereby eliminating the necessity for individual bootstrap gate drivers. The focus is on very low-power VLSI applications, such as battery-powered or self-powered signal processors, where achieving high power conversion efficiency is crucial, especially in scenarios where power consumption is in the milliwatt range. The paper comprehensively addresses conduction and switching losses, facilitating design optimization in terms of switching frequency and component dimensions. The experimental section details the open-loop and closed-loop operation of a fully integrated 10MHz voltage doubler. This doubler, with a 2V or 3V input, is capable of generating a 3.3V or 5V output, sustaining loads up to 5mW. The converter, fabricated using a standard 1.2μ CMOS technology, occupies just 0.7mm of the chip area, demonstrating its suitability for space-constrained on-chip applications.

The efficient and fast control of electric power forms part of the key technologies of modern automated production. It is performed using electronic power converters. The converters transfer energy from a source to a controlled process in a quantized fashion, using semiconductor switches which are turned on and off at fast repetition rates. The algorithms which generate the switching functions – pulsewidth modulation techniques – are manifold. They range from simple averaging schemes to involved methods of real-time optimization. This paper gives an overview.

In this paper, a new low-energy switching technique with low common-mode voltage variation is proposed for successive-approximation analog-to-digital converters (SA-ADCs). In the proposed scheme, not only the switching energy consumed within the first three comparisons is less than zero, but also other comparisons are made with the low-power monotonic method. Therefore, the switching energy of the capacitive array, including the consumed energy during the sampling phase, is reduced by 90.68% compared with the conventional counterpart. Moreover, since the variation of the input common-mode voltage of the employed comparator is only 0.125Vref, where Vref is the reference voltage of the ADC, the required comparator’s performance can be much more relaxed leading to more power saving. Post-layout simulation results of a 10-bit 1-MS/s SA-ADC in a 0.18-μm CMOS technology show a signal-to-noise-and-distortion ratio (SNDR) of 61 dB, a spurious-free dynamic range (SFDR) of 79.8 dB, and an effective number of 9.84 bits. The ADC consumes 35.3 μW with a 1.8-V supply and achieves a Figure-of-Merit (FoM) of 38.5 fJ/conversion-step.

We propose a maximum power point tracking (MPPT) circuit for micro-scale sensor systems that measures ripple voltages in a switched capacitor energy harvester. Compared to conventional current mirror type MPPT circuits, this design incurs no voltage drop and does not require high bandwidth amplifiers. Using correlated double sampling, high accuracy is achieved with a power overhead of 5%, even at low harvested currents of 1.4uA based on measured results in 180nm CMOS.

An ultra low-power, precise voltage reference using a switched-capacitor technique in 0.35-μm CMOS is presented in this paper. The temperature dependence of the carrier mobility and channel length modulation effect can be effectively minimized by using 3.3 and 5 V N-type transistors to operate in the saturation and subthreshold regions, respectively. In place of resistors, a precise reference voltage with flexible trimming capability is achieved by using capacitors. When the supply voltage is 1 V and the temperature is 80°C, the supply current is 250 nA. The line sensitivity is 0.76%/V; the PSRR is -41 dB at 100 Hz and -17 dB at 10 MHz. Moreover, the occupied die area is 0.049 mm2.

With the emergence of nanoscale material-based energy harvesters such as thermoelectric generator and microbial fuel cells, energy-harvesting-assisted self-powered electronics systems are gaining popularity. The state-of-the-art low-voltage CMOS boost converter, a critical voltage converter circuit for low power energy harvesting sources will be reviewed in this paper. Fundamentals of the boost converter circuit startup problem are discussed and recent circuit solutions to solve this problem are compared and analyzed. Necessary design considerations and trade-offs regarding circuit topology, component and CMOS process are also addressed.

We present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both non-pipelined and functionally pipelined data-paths. The scheduling problem refers to the assignment of a supply voltage level to each operation in a data ow graph so as to minimize the average energy consumption for given computation time or throughput constraints or both. The energy model is accurate and accounts for the input pattern dependencies, re-convergent fanout induced dependencies, and the energy cost of level shifters. Experimental results show that using four supply voltage levels on a number of standard benchmarks, an average energy saving of 53% (with a computation time constraint of 1.5 times the critical path delay) can be obtained compared to using one fixed supply voltage level.

Switching losses are reduced by gallium nitride (GaN) technology, which allows faster device switching speeds. At the same time, the weight and size of converters utilizing these devices are greatly reduced in several applications by using high frequency (HF) transformers. A new, low voltage high current, GaN-based AC/DC topology for battery charging applications is simulated, modeled, and investigated in this paper. The proposed topology is designed to operate at 1 MHz for 120Vac to 48Vdc/60Vdc conversion for 1.4 kW load. The integration of GaN totem-pole power factor correction rectifier (TP-PFC), high-frequency series-resonant converter (SRC), and current doubler rectifier (CDR) presents an opportunity to further increase the efficiency and compactness of this GaN battery charging system. In this work, a new GaN topology to combine the advantages of TP-PFC and SRC with CDR in a battery charging converter is investigated, simulated, and modelled. Loss analysis of the proposed topology is addressed.

This paper presents a new fully differential operational transconductance amplifier (OTA) for low-voltage and fast-settling switched-capacitor circuits in digital CMOS technology. The proposed two-stage OTA is a hybrid class A/AB that combines a folded cascode as the first stage with active current mirrors as the second stage. It employs a hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling.

The charge and discharge characteristics of lead-acid battery and LiFePO4 battery is proposed in this paper. The purpose of this paper lies in offering the pulse current charger of higher peak value which can shorten the charging time to reach the goal of charging fast and also avoids the polarization phenomena produced while charging the voltage and current signal simultaneously, supervising whole charging course of the battery, avoiding the situation of excessive charging, and ensuring the life of battery. The hardware circuit of this pulse current charger adopts the power electronic elements for the main structure, uses Digital Signal Processor as the core of the controller, and substantially decreases the volume of charger and the loss of circuit. Besides, the input power supply of this charger is utility, greatly facilitating its using or carrying, which contributes to the development of variety of electric equipments in the future.

This study investigates a phase-locked loop (PLL) controlled parallel resonant converter (PRC) for a pulse power capacitor charging application. The dynamic nature of the capacitor charging is such that it causes a shift in the resonant frequency of the PRC. Using the proposed control method, the PRC can be optimized to operate with its maximum power capability and guarantee ZVS operation, even when the input voltage and resonant tank parameters vary. The detailed implementation of the PLL controller, as well as the determination of dead-time and leading time, is presented in this paper. Simulation and experimental results verify the performance of the proposed control method.


Question: Data Clustering: 50 Years After the Introduction of K-means

This paper presents a parallel data-clustering algorithm designed for distributed memory multiprocessors, specifically targeting the processing of large-scale data sets prevalent in data and text mining. Our approach is a parallelized version of the k-means clustering algorithm, utilizing the message passing model to harness the inherent data-parallelism of the k-means method. We provide a theoretical analysis demonstrating that as the volume of data points escalates, the speedup and scaleup of our algorithm approach optimal levels. To validate our algorithm's performance, we conducted experiments on an IBM POWERparallel SP2 system, utilizing up to 16 nodes. Our results showcase nearly linear relative speedups, exemplified by a 15.62 speedup on 16 nodes, alongside linear scaleup in both data set size and the number of clusters sought. Notably, our implementation achieved a processing rate of over 1.8 gigaflops when tested on a 2 gigabyte data set.

Clustering methods are among the most commonly used tools for exploratory data analysis. However, using clustering to perform data analysis can be challenging for modern datasets that contain a large number of dimensions, are complex in nature, and lack a ground-truth labeling. Traditional tools, like summarization and plotting of clusters, are of limited benefit in a high-dimensional setting. On the other hand, while many clustering methods have been studied theoretically, such analysis often has limited instructive value for practical purposes due to unverifiable assumptions, oracle-dependent tuning parameters, or unquantified finite-sample effects.

Ensembles for unsupervised outlier detection is an emerging topic that has been neglected for a surprisingly long time (although there are reasons why this is more difficult than supervised ensembles or even clustering ensembles). Aggarwal recently discussed algorithmic patterns of outlier detection ensembles, identified traces of the idea in the literature, and remarked on potential as well as unlikely avenues for future transfer of concepts from supervised ensembles. Complementary to his points, here we focus on the core ingredients for building an outlier ensemble, discuss the first steps taken in the literature, and identify challenges for future research.

Clustering methods based on deep neural networks have proven promising for clustering real-world data because of their high representational power. In this paper we propose a systematic taxonomy of clustering methods that utilize deep neural networks. We base our taxonomy on a comprehensive review of recent work and validate the taxonomy in a case study. In this case study, we show that the taxonomy enables researchers and practitioners to systematically create new clustering methods by selectively recombining and replacing distinct aspects of previous methods with the goal of overcoming their individual limitations. The experimental evaluation confirms this and shows that the method created for the case study achieves state-of-the-art clustering quality and surpasses it in some cases.

Fast and high-quality document clustering algorithms play an important role in providing intuitive navigation and browsing mechanisms by organizing large amounts of information into a small number of meaningful clusters. In particular, clustering algorithms that build meaningful hierarchies out of large document collections are ideal tools for their interactive visualization and exploration as they provide data-views that are consistent, predictable, and at different levels of granularity. This paper focuses on document clustering algorithms that build such hierarchical solutions and (i) presents a comprehensive study of partitional and agglomerative algorithms that use different criterion functions and merging schemes, and (ii) presents a new class of clustering algorithms called constrained agglomerative algorithms, which combine features from both partitional and agglomerative approaches that allows them to reduce the early-stage errors made by agglomerative methods and hence improve the quality of clustering solutions. The experimental evaluation shows that, contrary to the common belief, partitional algorithms always lead to better solutions than agglomerative algorithms; making them ideal for clustering large document collections due to not only their relatively low computational requirements, but also higher clustering quality. Furthermore, the constrained agglomerative methods consistently lead to better solutions than agglomerative methods alone and for many cases they outperform partitional methods, as well.

Evaluation of clustering results (or cluster validation) is an important and necessary step in cluster analysis, but it is often time-consuming and complicated work. We present a visual cluster validation tool, the Cluster Validity Analysis Platform (CVAP), to facilitate cluster validation. The CVAP provides necessary methods (e.g., many validity indices, several clustering algorithms and procedures) and an analysis environment for clustering, evaluation of clustering results, estimation of the number of clusters, and performance comparison among different clustering algorithms. It can help users accomplish their clustering tasks faster and easier and help achieve good clustering quality when there is little prior knowledge about the cluster structure of a data set.

Basing cluster analysis on mixture models has become a classical and powerful approach. It enables some classical criteria such as the well-known k-means criterion to be explained. To classify the rows or the columns of a contingency table, an adapted version of k-means known as Mndki2, which uses the chi-square distance, can be used. Unfortunately, this simple, effective method which can be used jointly with correspondence analysis based on the same representation of the data, cannot be associated with a mixture model in the same way as the classical k-means algorithm. In this paper we show that the Mndki2 algorithm can be viewed as an approximation of a classifying version of the EM algorithm for a mixture of multinomial distributions. A comparison of the algorithms belonging in this context are experimentally investigated using Monte Carlo simulations. 2006 Elsevier B.V. All rights reserved.

The assignment of alternatives (observations/objects) into predefined homogenous groups is a problem of major practical and research interest. This type of problem is referred to as classification or sorting, depending on whether the groups are nominal or ordinal. Methodologies for addressing classification and sorting problems have been developed from a variety of research disciplines, including statistics/econometrics, artificial intelligent and operations research. The objective of this paper is to review the research conducted on the framework of the multicriteria decision aiding (MCDA). The review covers different forms of MCDA classification/sorting models, different aspects of the model development process, as well as real-world applications of MCDA classification/sorting techniques and their software implementations. 2002 Elsevier Science B.V. All rights reserved.

Various educational oriented problems are resolved through Educational Data Mining, which is the most prevalent applications of data mining. One of the crucial goals of this paper is to study the most recent works carried out on EDM and analyze their merits and drawbacks. This paper also highlights the cumulative results of the various data mining practices and techniques applied in the surveyed articles, and thereby suggesting the researchers on the future directions on EDM. In addition, an experiment was also conducted to evaluate, certain classification and clustering algorithms to observe the most reliable algorithms for future researches.

The problem this paper is concerned with is that of unsupervised learning. Mainly, what does it mean to learn a probability distribution? The classical answer to this is to learn a probability density. This is often done by defining a parametric family of densities (Pθ)θ∈Rd and finding the one that maximized the likelihood on our data: if we have real data examples {x}i=1, we would solve the problem


Question: Data Clustering: 50 Years of Advancements Since K-means

This paper introduces novel spectral techniques for addressing ratio cut partitioning and clustering problems, which are crucial in various stages of Very Large Scale Integration (VLSI) design, including layout, testing, and hardware simulation. The ratio cut objective function, known for encompassing both the mincut and equipartition objectives, has been a focal point in partitioning algorithms. Our research reveals that the second smallest eigenvalue of a matrix derived from the circuit netlist can serve as an accurate approximation of the optimal ratio cut partition cost. We further illustrate that efficient Lanczos-type methods for solving sparse symmetric eigenvalue problems provide a solid foundation for developing heuristic ratio cuts based on the eigenvector associated with the second eigenvalue. The computation of the second eigenvector also leads to effective clustering methods, which perform exceptionally well on challenging input cases as identified in the Computer-Aided Design (CAD) literature. We explore the use of the intersection graph representation of the circuit netlist as a starting point for partitioning and propose a heuristic based on the spectral ratio cut partitioning of this graph. Our partitioning algorithms were evaluated on industry-standard benchmark suites, and the outcomes show significant improvements in solution quality and runtime efficiency compared to previous methods, such as those proposed by Wei and Cheng. The paper concludes with a discussion on potential algorithmic optimizations and directions for future research in this area.

This paper focuses on a new clustering task, called self-taught clustering. Self-taught clustering is an instance of unsupervised transfer learning, which aims at clustering a small collection of target unlabeled data with the help of a large amount of auxiliary unlabeled data. The target and auxiliary data can be different in topic distribution. We show that even when the target data are not sufficient to allow effective learning of a high quality feature representation, it is possible to learn the useful features with the help of the auxiliary data on which the target data can be clustered effectively. We propose a co-clustering based self-taught clustering algorithm to tackle this problem, by clustering the target and auxiliary data simultaneously to allow the feature representation from the auxiliary data to influence the target data through a common set of features. Under the new data representation, clustering on the target data can be improved. Our experiments on image clustering show that our algorithm can greatly outperform several state-of-the-art clustering methods when utilizing irrelevant unlabeled auxiliary data.

The use of general descriptive names, registered names, trademarks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. I dedicate this book to my grandchildren. Preface The intent of this book is to describe some recent data mining tools that have proven effective in dealing with data sets which often involve uncertain description or other complexities that cause difficulty for the conventional approaches of logistic regression, neural network models, and decision trees. Among these traditional algorithms, neural network models often have a relative advantage when data is complex. We will discuss methods with simple examples, review applications, and evaluate relative advantages of several contemporary methods. Our intent is to cover the fundamental concepts of data mining, to demonstrate the potential of gathering large sets of data, and analyzing these data sets to gain useful business understanding. We have organized the material into three parts. Part I introduces concepts. Part II contains chapters on a number of different techniques often used in data mining. Part III focuses on business applications of data mining. Not all of these chapters need to be covered, and their sequence could be varied at instructor design. The book will include short vignettes of how specific concepts have been applied in real practice. A series of representative data sets will be generated to demonstrate specific methods and concepts. References to data mining software and sites such as www.kdnuggets.com will be provided. Chapter 1 gives an overview of data mining, and provides a description of the data mining process. An overview of useful business applications is provided. Chapter 2 presents the data mining process in more detail. It demonstrates this process with a typical set of data. Visualization of data through data mining software is addressed. Chapter 3 presents memory-based reasoning methods of data mining. Major real applications are described. Algorithms are demonstrated with prototypical data based on real applications. Chapter 4 discusses association rule methods. Application in the form of market basket analysis is discussed. A real data set is described, and a simplified version used to demonstrate association rule methods. Chapter 5 presents fuzzy data mining approaches. Fuzzy decision tree approaches are described, as well as fuzzy association rule applications. Real data mining applications are described and demonstrated Chapter 6 presents Rough …

Spatial data clustering is one of the important data mining techniques for extracting knowledge from large amount of spatial data collected in various applications, such as remote sensing, GIS, computer cartography, environmental assessment and planning, etc. Several useful and popular spatial data clustering algorithms have been proposed in the past decade. DBSCAN is one of them, which can discover clusters of any arbitrary shape and can handle the noise points effectively. However, DBSCAN requires large volume of memory support because it operates on the entire database. This paper presents an improved sampling-based DBSCAN which can cluster large-scale spatial databases effectively. Experimental results included to establish that the proposed sampling-based DBSCAN outperforms DBSCAN as well as its other counterparts, in terms of execution time, without losing the quality of clustering.

We describe AutoClass, an approach to unsupervised classiication based upon the classical mixture model, supplemented by a Bayesian method for determining the optimal classes. We include a moderately detailed exposition of the mathematics behind the AutoClass system. We emphasize that no current unsupervised classiication system can produce maximally useful results when operated alone. It is the interaction between domain experts and the machine searching over the model space, that generates new knowledge. Both bring unique information and abilities to the database analysis task, and each enhances the others' eeectiveness. We illustrate this point with several applications of AutoClass to complex real world databases, and describe the resulting successes and failures. 6.1 Introduction This chapter is a summary of our experience in using an automatic classiication program (AutoClass) to extract useful information from databases. It also gives an outline of the principles that underlie automatic classiication in general, and AutoClass in particular. We are concerned with the problem of automatic discovery of classes in data (sometimes called clustering, or unsupervised learning), rather than the generation of class descriptions from labeled examples (called supervised learning). In some sense, automatic classiication aims at discovering the \natural" classes in the data. These classes reeect basic causal mechanisms that makes some cases look more like each other than the rest of the cases. The causal mechanisms may be as boring as sample biases in the data, or could reeect some major new discovery in the domain. Sometimes, these classes were well known to experts in the eld, but unknown to AutoClass, and other times

In most parallel DBSCAN algorithms, neighboring points are assigned to the same data partition for parallel processing to facilitate calculation of the density of the neighbors. This data partitioning scheme causes a few critical problems including load imbalance between data partitions, especially in a skewed data set. To remedy these problems, we propose a cell-based data partitioning scheme, pseudo random partitioning , that randomly distributes small cells rather than the points themselves. It achieves high load balance regardless of data skewness while retaining the data contiguity required for DBSCAN. In addition, we build and broadcast a highly compact summary of the entire data set, which we call a two-level cell dictionary , to supplement random partitions. Then, we develop a novel parallel DBSCAN algorithm, Random Partitioning-DBSCAN (shortly, RP-DBSCAN), that uses pseudo random partitioning together with a two-level cell dictionary. The algorithm simultaneously finds the local clusters to each data partition and then merges these local clusters to obtain global clustering. To validate the merit of our approach, we implement RP-DBSCAN on Spark and conduct extensive experiments using various real-world data sets on 12 Microsoft Azure machines (48 cores). In RP-DBSCAN, data partitioning and cluster merging are very light, and clustering on each split is not dragged out by a specific worker. Therefore, the performance results show that RP-DBSCAN significantly outperforms the state-of-the-art algorithms by up to 180 times.

It is already true that Big Data has drawn huge attention from researchers in information sciences, policy and decision makers in governments and enterprises. As the speed of information growth exceeds Moore’s Law at the beginning of this new century, excessive data is making great troubles to human beings. However, there are so much potential and highly useful values hidden in the huge volume of data. A new scientific paradigm is born as dataintensive scientific discovery (DISD), also known as Big Data problems. A large number of fields and sectors, ranging from economic and business activities to public administration, from national security to scientific researches in many areas, involve with Big Data problems. On the one hand, Big Data is extremely valuable to produce productivity in businesses and evolutionary breakthroughs in scientific disciplines, which give us a lot of opportunities to make great progresses in many fields. There is no doubt that the future competitions in business productivity and technologies will surely converge into the Big Data explorations. On the other hand, Big Data also arises with many challenges, such as difficulties in data capture, data storage, data analysis and data visualization. This paper is aimed to demonstrate a close-up view about Big Data, including Big Data applications, Big Data opportunities and challenges, as well as the state-of-the-art techniques and technologies we currently adopt to deal with the Big Data problems. We also discuss several underlying methodologies to handle the data deluge, for example, granular computing, cloud computing, bio-inspired computing, and quantum computing. 2014 Elsevier Inc. All rights reserved.

Geospatial clustering is a very important research topic in the field of „Geospatial Knowledge Discovery.‟ Its main purpose is to group similar objects, from large geospatial datasets, into clusters, based on the objects‟ spatial and non-spatial attributes. This capability is very useful for better understanding the patterns and distributions of geographical phenomena. With the emerging availability of large amounts of geospatial data on the Internet, the demand for powerful methods of extracting meaningful information from large amounts of web-based geospatial data is thus also rapidly increasing. In this chapter, we present a geospatial clustering web service called GeoClustering. With this service, users are able to cluster online data sources easily and to then conveniently visualize the clustering results through a friendly map-centric user interface. Since it is web-based, GeoClustering offers a platform that can be accessed by anyone from anywhere at any time. To achieve better interoperability, GeoClustering offers an API and follows the OGC standard data format for spatial data exchange.

Here the problem of selecting the number of clusters in cluster analysis is considered. Recently, the concept of clustering stability, which measures the robustness of any given clustering algorithm, has been utilized in Wang (2010) for selecting the number of clusters through cross validation. In this manuscript, an estimation scheme for clustering instability is developed based on the bootstrap, and then the number of clusters is selected so that the corresponding estimated clustering instability is minimized. The proposed selection criterion’s effectiveness is demonstrated on simulations and real examples.

Consensus clustering emerges as a promising solution to find cluster structures from data. As an efficient approach for consensus clustering, the Kmeans based method has garnered attention in the literature, but the existing research is still preliminary and fragmented. In this paper, we provide a systematic study on the framework of K-meansbased Consensus Clustering (KCC). We first formulate the general definition of KCC, and then reveal a necessary and sufficient condition for utility functions that work for KCC, on both complete and incomplete basic partitionings. Experimental results on various real-world data sets demonstrate that KCC is highly efficient and is comparable to the state-of-the-art methods in terms of clustering quality. In addition, KCC shows high robustness to incomplete basic partitionings with substantial missing values.

Learning application-specific distance metrics from labeled data is critical for both statistical classification and information retrieval. Most of the earlier work in this area has focused on finding metrics that simultaneously optimize compactness and separability in a global sense. Specifically, such distance metrics attempt to keep all of the data points in each class close together while ensuring that data points from different classes are separated. However, particularly when classes exhibit multimodal data distributions, these goals conflict and thus cannot be simultaneously satisfied. This paper proposes a Local Distance Metric (LDM) that aims to optimize local compactness and local separability. We present an efficient algorithm that employs eigenvector analysis and bound optimization to learn the LDM from training data in a probabilistic framework. We demonstrate that LDM achieves significant improvements in both classification and retrieval accuracy compared to global distance learning and kernel-based KNN. Introduction Distance metric learning has played a significant role in both statistical classification and information retrieval. For instance, previous studies (Goldberger et al. 2005; Weinberger, Blitzer, & Saul 2006) have shown that appropriate distance metrics can significantly improve the classification accuracy of the K Nearest Neighbor (KNN) algorithm. In multimedia information retrieval, several papers (He et al. 2003; 2004; Muller, Pun, & Squire 2004) have shown that appropriate distance metrics, learned either from labeled or unlabeled data, usually result in substantial improvements in retrieval accuracy compared to the standard Euclidean distance. Most of the work in distance metrics learning can be organized into the following two categories: • Unsupervised distance metric learning, or manifold learning. The main idea is to learn a underlying low-dimensional manifold where geometric relationships (e.g., distance) between most of the observed data points are preserved. Popular algorithms in this category include ISOMAP (Tenenbaum, de Silva, & Langford 2000), Local Linear Embedding (Saul & Roweis 2003), and the Laplacian Eigenmap (Belkin & Niyogi 2003). Copyright c © 2006, American Association for Artificial Intelligence (www.aaai.org). All rights reserved. −5 0 5 10 −8 −6 −4 −2 0 2 4 6 8 10 12 Class A Class B (a) −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 −0.25 −0.2 −0.15 −0.1 −0.05 0 0.05 0.1 Class A Class B


Question: Data Clustering: 50 Years of Advancements Since K-means

Enhancing Text Document Clustering with Ontologies: A Comparative Study

Text document clustering is a critical technique for structuring and navigating large collections of documents, effectively condensing them into coherent clusters. However, traditional clustering methods often fall short due to their reliance on a simplistic 'bag of words' representation, which fails to capture the nuanced relationships between significant terms that may not appear together verbatim. To address this limitation, we introduce the integration of core ontologies as a source of background knowledge into the clustering process of text documents. This approach enriches the clustering methodology by leveraging semantic relationships encoded in ontologies, enhancing the precision of document categorization.

Our study evaluates the efficacy of incorporating ontologies into text clustering through a series of experiments. We analyze the impact of this enhancement on both a large dataset sourced from Reuters newsfeeds and a smaller, more specialized corpus related to an eLearning course on Java programming. By comparing the outcomes of clustering techniques with and without the use of background knowledge, our results consistently demonstrate a marked improvement in cluster quality when ontologies are utilized. This underscores the potential of ontologies to significantly boost the performance of text document clustering, offering a more refined and accurate means of organizing textual data.

The density-based clustering algorithm DBSCAN is a state-of-the-art data clustering technique with numerous applications in many fields. However, DBSCAN requires neighborhood queries for all objects and propagation of labels from object to object. This scheme is time consuming and thus limits its applicability for large datasets. In this paper, we propose a novel anytime approach to cope with this problem by reducing both the range query and the label propagation time of DBSCAN. Our algorithm, called AnyDBC, compresses the data into smaller density-connected subsets called primitive clusters and labels objects based on connected components of these primitive clusters to reduce the label propagation time. Moreover, instead of passively performing range queries for all objects as in existing techniques, AnyDBC iteratively and actively learns the current cluster structure of the data and selects a few most promising objects for refining clusters at each iteration. Thus, in the end, it performs substantially fewer range queries compared to DBSCAN while still satisfying the cluster definition of DBSCAN. Moreover, by processing queries in block and merging the results into the current cluster structure, AnyDBC can be efficiently parallelized on shared memory architectures to further accelerate the performance, uniquely making it a parallel and anytime technique at the same time. Experiments show speedup factors of orders of magnitude compared to DBSCAN and its fastest variants as well as a high parallel scalability on multicore processors for very large real and synthetic complex datasets.

We study a suitable class of well-clustered graphs that admit good k-way partitions and present the first almost-linear time algorithm for with almost-optimal approximation guarantees partitioning such graphs. A good k-way partition is a partition of the vertices of a graph into disjoint clusters (subsets) {Si}i=1, such that each cluster is better connected on the inside than towards the outside. This problem is a key building block in algorithm design, and has wide applications in community detection and network analysis. Key to our result is a theorem on the multi-cut and eigenvector structure of the graph Laplacians of these well-clustered graphs. Based on this theorem, we give the first rigorous guarantees on the approximation ratios of the widely used k-means clustering algorithms. We also give an almost-linear time algorithm based on heat kernel embeddings and approximate nearest neighbor data structures.

Automatic grouping and segmentation of images remains a challenging problem in computer vision. Recently, a number of authors have demonstrated good performance on this task using methods that are based on eigenvectors of the a nity matrix. These approaches are extremely attractive in that they are based on simple eigendecomposition algorithms whose stability is well understood. Nevertheless, the use of eigendecompositions in the context of segmentation is far from well understood. In this paper we give a unied treatment of these algorithms, and show the close connections between them while highlighting their distinguishing features. We then prove results on eigenvectors of block matrices that allow us to analyze the performance of these algorithms in simple grouping settings. Finally, we use our analysis to motivate a variation on the existing methods that combines aspects from di erent eigenvector segmentation algorithms. We illustrate our analysis with results on real and synthetic images. Human perceiving a scene can often easily segment it into coherent segments or groups. There has been a tremendous amount of e ort devoted to achieving the same level of performance in computer vision. In many cases, this is done by associating with each pixel a feature vector (e.g. color, motion, texture, position) and using a clustering or grouping algorithm on these feature vectors. Perhaps the cleanest approach to segmenting points in feature space is based on mixture models in which one assumes the data were generated by multiple processes and estimates the parameters of the processes and the number of components in the mixture. The assignment of points to clusters can then be easily performed by calculating the posterior probability of a point belonging to a cluster. Despite the elegance of this approach, the estimation process leads to a notoriously di cult optimization. The frequently used EM algorithm [3] often converges to a local maximum that depends on the initial conditions.

In this paper, we present an improved k-medoids clustering algorithm based on CF-Tree. The algorithm based on the clustering features of BIRCH algorithm, the concept of k-medoids algorithm has been improved. We preserve all the training sample data in an CF-Tree, then use k-medoids method to cluster the CF in leaf nodes of CF-Tree. Eventually, we can get k clusters from the root of the CF-Tree. This algorithm improves obviously the drawbacks of the k-medoids algorithm, such as the time complexity, scalability on large dataset, and can't find the clusters of sizes different very much and the convex shapes. Experiments show that this algorithm enhances the quality and scalability of clustering.

The Internet is emerging as a new marketing channel, so understanding the characteristics of online customers’ needs and expectations is considered a prerequisite for activating the consumer-oriented electronic commerce market. In this study, we propose a novel clustering algorithm based on genetic algorithms (GAs) to effectively segment the online shopping market. In general, GAs are believed to be effective on NP-complete global optimization problems, and they can provide good near-optimal solutions in reasonable time. Thus, we believe that a clustering technique with GA can provide a way of finding the relevant clusters more effectively. The research in this paper applied K-means clustering whose initial seeds are optimized by GA, which is called GA K-means, to a real-world online shopping market segmentation case. In this study, we compared the results of GA K-means to those of a simple K-means algorithm and self-organizing maps (SOM). The results showed that GA K-means clustering may improve segmentation performance in comparison to other typical clustering algorithms. In addition, our study validated the usefulness of the proposed model as a preprocessing tool for recommendation systems. 2007 Elsevier Ltd. All rights reserved.

In recent years, uncertain data management applications have grown in importance because of the large number of hardware applications which measure data approximately. For example, sensors are typically expected to have considerable noise in their readings because of inaccuracies in data retrieval, transmission, and power failures. In many cases, the estimated error of the underlying data stream is available. This information is very useful for the mining process, since it can be used in order to improve the quality of the underlying results. In this paper we will propose a method for clustering uncertain data streams. We use a very general model of the uncertainty in which we assume that only a few statistical measures of the uncertainty are available. We will show that the use of even modest uncertainty information during the mining process is sufficient to greatly improve the quality of the underlying results. We show that our approach is more effective than a purely deterministic method such as the CluStream approach. We will test the approach on a variety of real and synthetic data sets and illustrate the advantages of the method in terms of effectiveness and efficiency.

Data mining technology has attracted significant interest as a means of identifying patterns and trends from large collections of data. It is however evident that the collection and analysis of data that include personal information may violate the privacy of the individuals to whom information refers. Privacy protection in data mining is then becoming a crucial issue that has captured the attention of many researchers. In this chapter, we first describe the concept of k-anonymity and illustrate different approaches for its enforcement. We then discuss how the privacy requirements characterized by k-anonymity can be violated in data mining and introduce possible approaches to ensure the satisfaction of k-anonymity in data mining.

Data mining (DM) methodology has a tremendous contribution for researchers to extract the hidden knowledge and information which have been inherited in the data used by researchers. This study has proposed a new procedure, based on expanded RFM model by including one additional parameter, joining WRFM-based method to K-means algorithm applied in DM with K-optimum according to Davies– Bouldin Index, and then classifying customer product loyalty in under B2B concept. The developed methodology has been implemented for SAPCO Co. in Iran. The result shows a tremendous capability to the firm to assess his customer loyalty in marketing strategy designed by this company in comparing with random selection commonly used by most companies in Iran. 2009 Elsevier Ltd. All rights reserved.

We propose in this correspondence a new method to perform two-class clustering of 2-D data in a quick and automatic way by preserving certain features of the input data. The method is analytical, deterministic, unsupervised, automatic, and noniterative. The computation time is of order n if the data size is n, and hence much faster than any other method which requires the computation of an n-by-n dissimilarity matrix. Furthermore, the proposed method does not have the trouble of guessing initial values. This new approach is thus more suitable for fast automatic hierarchical clustering or any other fields requiring fast automatic two-class clustering of 2-D data. The method can be extended to cluster data in higher dimensional space. A 3-D example is included.

Nowadays companies increasingly derive revenue from the creation and sustenance of long-term relationships with their customers. In such an environment, marketing serves the purpose of maximizing customer lifetime value (CLV) and customer equity, which is the sum of the lifetime values of the company’s customers. A frequently-encountered difficulty for companies wishing to measure customer profitability is that management accounting and reporting systems have tended to reflect product profitability rather than customer profitability. But in spite of these difficulties, Companies looking for methods to know how calculate their customers's CLV. In this paper, we used K-Mean clustering approach to determine customers's CLV and segment them based on recency, frequency and monetary (RFM) measures. We also used Discriminant analysis to approve clustering results. Data required applying this method gathered from one branch of an Iranian private bank which is established newly. Finally, in terms of this segmentation, we proposed customer retention strategies for treating with the bank customers.


Question: Data Clustering: 50 Years of Advancements Since K-means

This paper delves into the application of thesauri and lexical resources for Word Sense Disambiguation (WSD), highlighting the evolution of techniques over the past few decades. Thesauri, such as Roget's International Thesaurus, have been pivotal in understanding and categorizing word senses due to their systematic structuring of synonyms and semantic relationships. Unlike dictionaries, which can be inconsistent and lack the pragmatic context crucial for WSD, thesauri provide a more coherent framework for word meanings. For instance, Roget's thesaurus, with its eight levels of concept hierarchy, allows for nuanced classification of word senses. This hierarchical structure often aligns with the different senses of a word, making it a valuable tool for WSD. Early applications of Roget's for WSD include the work of Masterman (1957) and Patrick (1985), who utilized the thesaurus to discriminate verb senses by examining semantic clusters formed by "e-chains." This method, involving the examination of closely related word groups in low-level semicolon groups and words connected via chains, demonstrated high reliability in distinguishing between senses of verbs like "inspire" and "question." Additionally, thesauri have been used to derive classes of words by extracting context from corpora, as seen in Yarowsky's (1992) work. While dictionaries offer detailed lexical information, they often fall short in providing the pragmatic context necessary for sense determination. As a result, corpora have become a primary source of information for WSD, offering real-world usage patterns that dictionaries may not capture. In contrast, thesauri, with their systematic structure and emphasis on semantic relationships, have proven to be a robust resource for WSD, complementing corpora in providing the contextual and relational information crucial for accurate word sense disambiguation. This paper underscores the importance of leveraging thesauri in WSD, showcasing their historical significance and ongoing relevance in the field of natural language processing.

Often users receive search results which contain a wide range of documents, only some of which are relevant to their information needs. To address this problem, ever more systems not only locate information for users, but also organise that information on their behalf. We look at two main automatic approaches to information organisation: interactive clustering of search results and pre-categorising documents to provide hierarchical browsing structures. To be feasible in real world applications, both of these approaches require accurate yet efficient algorithms. Yet, both suffer from the curse of dimensionality — documents are typically represented by hundreds or thousands of words (features) which must be analysed and processed during clustering or classification. In this paper, we discuss feature reduction techniques and their application to document clustering and classification, showing that feature reduction improves efficiency as well as accuracy. We validate these algorithms using human relevance assignments and categorisation.

The Internet is emerging as a new marketing channel, so understanding the characteristics of online customers’ needs and expectations is considered a prerequisite for activating the consumer-oriented electronic commerce market. In this study, we propose a novel clustering algorithm based on genetic algorithms (GAs) to effectively segment the online shopping market. In general, GAs are believed to be effective on NP-complete global optimization problems, and they can provide good near-optimal solutions in reasonable time. Thus, we believe that a clustering technique with GA can provide a way of finding the relevant clusters more effectively. The research in this paper applied K-means clustering whose initial seeds are optimized by GA, which is called GA K-means, to a real-world online shopping market segmentation case. In this study, we compared the results of GA K-means to those of a simple K-means algorithm and self-organizing maps (SOM). The results showed that GA K-means clustering may improve segmentation performance in comparison to other typical clustering algorithms. In addition, our study validated the usefulness of the proposed model as a preprocessing tool for recommendation systems. 2007 Elsevier Ltd. All rights reserved.

Machine Learning research has been making great progress in many directions This article summarizes four of these directions and discusses some current open problems The four directions are a improving classi cation accuracy by learning ensembles of classi ers b methods for scaling up supervised learning algorithms c reinforcement learning and d learning complex stochastic models

As an important technique of data analysis, clustering plays an important role in finding the underlying pattern structure embedded in unlabeled data. Clustering algorithms that need to store all the data into the memory for analysis become infeasible when the dataset is too large to be stored. To handle such large data, incremental clustering approaches are proposed. The key idea behind these approaches is to find representatives (centroids or medoids) to represent each cluster in each data chunk, which is a packet of the data, and final data analysis is carried out based on those identified representatives from all the chunks. In this paper, we propose a new incremental clustering approach called incremental multiple medoids-based fuzzy clustering (IMMFC) to handle complex patterns that are not compact and well separated. We would like to investigate whether IMMFC is a good alternative to capturing the underlying data structure more accurately. IMMFC not only facilitates the selection of multiple medoids for each cluster in a data chunk, but also has the mechanism to make use of relationships among those identified medoids as side information to help the final data clustering process. The detailed problem formulation, updating rules derivation, and the in-depth analysis of the proposed IMMFC are provided. Experimental studies on several large datasets that include real world malware datasets have been conducted. IMMFC outperforms existing incremental fuzzy clustering approaches in terms of clustering accuracy and robustness to the order of data. These results demonstrate the great potential of IMMFC for large-data analysis.

Data mining [Chen et al. 1996] is the process of extracting interesting (non-trivial, implicit, previously unknown and potentially useful) information or patterns from large information repositories such as: relational database, data warehouses, XML repository, etc. Also data mining is known as one of the core processes of Knowledge Discovery in Database (KDD). Many people take data mining as a synonym for another popular term, Knowledge Discovery in Database (KDD). Alternatively other people treat Data Mining as the core process of KDD. The KDD processes are shown in Figure 1 [Han and Kamber 2000]. Usually there are three processes. One is called preprocessing, which is executed before data mining techniques are applied to the right data. The preprocessing includes data cleaning, integration, selection and transformation. The main process of KDD is the data mining process, in this process different algorithms are applied to produce hidden knowledge. After that comes another process called postprocessing, which evaluates the mining result according to users’ requirements and domain knowledge. Regarding the evaluation results, the knowledge can be presented if the result is satisfactory, otherwise we have to run some or all of those processes again until we get the satisfactory result. The actually processes work as follows. First we need to clean and integrate the databases. Since the data source may come from different databases, which may have some inconsistences and duplications, we must clean the data source by removing those noises or make some compromises. Suppose we have two different databases, different words are used to refer the same thing in their schema. When we try to integrate the two sources we can only choose one of them, if we know that they denote the same thing. And also real world data tend to be incomplete and noisy due to the manual input mistakes. The integrated data sources can be stored in a database, data warehouse or other repositories. As not all the data in the database are related to our mining task, the second process is to select task related data from the integrated resources and transform them into a format that is ready to be mined. Suppose we want to find which items are often purchased together in a supermarket, while the database that records the purchase history may contains customer ID, items bought, transaction time, prices, number of each items and so on, but for this specific task we only need items bought. After selection of relevant data, the database that we are going to apply our data mining techniques to will be much smaller, consequently the whole process will be

In this paper, we present an approach based on the K-Nearest Neighbors algorithms for policies clustering that aims to reduce the ABAC policies dimensionality for high scale systems. Since ABAC considers a very large set of attributes for access decisions, it turns out that using such model for large scale systems might be very complicated. To date, researchers have proposed to use data mining techniques to discover roles for RBAC system construction. In this work in progress, we consider the usage of KNN-based techniques for the classification of ABAC policies based on similarity computations of rules in order to enhance the ABAC flexibility and to reduce the number of policy rules.

Nowadays, most data mining algorithms focus on clustering methods alone. Also, there are a lot of approaches designed for outlier detection. We observe that, in many situations, clusters and outliers are concepts whose meanings are inseparable to each other, especially for those data sets with noise. Thus, it is necessary to treat both clusters and outliers as concepts of the same importance in data analysis. In this paper, we present our continuous work on the cluster–outlier iterative detection algorithm (Shi in SubCOID: exploring cluster-outlier iterative detection approach to multi-dimensional data analysis in subspace. Auburn, pp. 132–135, 2008; Shi and Zhang in Towards exploring interactive relationship between clusters and outliers in multi-dimensional data analysis. IEEE Computer Society. Tokyo, pp. 518–519, 2005) to detect the clusters and outliers in another perspective for noisy data sets. In this algorithm, clusters are detected and adjusted according to the intra-relationship within clusters and the inter-relationship between clusters and outliers, and vice versa. The adjustment and modification of the clusters and outliers are performed iteratively until a certain termination condition is reached. This data processing algorithm can be applied in many fields, such as pattern recognition, data clustering, and signal processing. Experimental results demonstrate the advantages of our approach.

Many methods have been developed to recognize those progresses of technologies, and one of them is to analyze patent information. And visualization methods are considered to be proper for representing patent information and its analysis results. However, current visualization methods for patent analysis patent maps have some drawbacks. Therefore, we propose an alternative visualization method in this paper. With colleted keywords from patent documents of a target technology field, we cluster patent documents by the k-Means algorithm. With the clustering results, we form a semantic network of keywords without respect of filing dates. And then we build up a patent map by rearranging each keyword node of the semantic network according to its earliest filing date and frequency in patent documents. Our approach contributes to establishing a patent map which considers both structured and unstructured items of a patent document. Besides, differently from previous visualization methods for patent analysis, ours is based on forming a semantic network of keywords from patent documents. And thereby it visualizes a clear overview of patent information in a more comprehensible way. And as a result of those contributions, it enables us to understand advances of emerging technologies and forecast its trend in the future. 2007 Elsevier Ltd. All rights reserved.

While fuzzy c-means is a popular soft-clustering method, its effectiveness is largely limited to spherical clusters. By applying kernel tricks, the kernel fuzzy c-means algorithm attempts to address this problem by mapping data with nonlinear relationships to appropriate feature spaces. Kernel combination, or selection, is crucial for effective kernel clustering. Unfortunately, for most applications, it is uneasy to find the right combination. We propose a multiple kernel fuzzy c-means (MKFC) algorithm that extends the fuzzy c-means algorithm with a multiple kernel-learning setting. By incorporating multiple kernels and automatically adjusting the kernel weights, MKFC is more immune to ineffective kernels and irrelevant features. This makes the choice of kernels less crucial. In addition, we show multiple kernel k-means to be a special case of MKFC. Experiments on both synthetic and real-world data demonstrate the effectiveness of the proposed MKFC algorithm.

Now-a-days, diabetes disease is considered one of the key reasons of death among the people in the world. The availability of extensive medical information leads to the search for proper tools to support physicians to diagnose diabetes disease accurately. This research aimed at improving the diagnostic accuracy and reducing diagnostic missclassification based on the extracted significant diabetes features. Feature selection is critical to the superiority of classifiers founded through knowledge discovery approaches, thereby solving the classification problems relating to diabetes patients. This study proposed an integration approach between the SVM technique and K-means clustering algorithms to diagnose diabetes disease. Experimental results achieved high accuracy for differentiating the hidden patterns of the Diabetic and Nondiabetic patients compared with the modern diagnosis methods in term of the performance measure. The T-test statistical method obtained significant improvement results based on KSVM technique when tested on the UCI Pima Indian standard dataset. Keywords—K-means Clustering; Diabetes Patients; SVM;