Question: Creation and Verification of the Transgender Attitudes and Beliefs Scale.

This paper introduces a novel social desirability scale that is independent of psychopathology, addressing a critical gap in existing personality assessment tools. Historically, personality test scores have been influenced by various non-test-relevant factors, leading to concerns over response distortion. Wiggins and Rumrill (1959) outlined three primary approaches to mitigate this issue: statistical correction for "faking good" or "faking bad," analysis of response sets, and ratings of the social desirability of test items. However, a deeper distinction can be made that leads to a different categorization of approaches. The traditional approaches, including Meehl and Hathaway's corrections and Cronbach's response set analysis, primarily focus on the subject's test behavior. In contrast, Edwards primarily defines social desirability as a characteristic of test items, specifically their position on a social desirability scale.

The concept of statistical deviance underpins both approaches. For instance, in constructing the MMPI K scale, items were chosen based on their ability to differentiate between various subject groups, such as clinically normal individuals with abnormal test profiles and clinically abnormal individuals with normal profiles. These items, when responded to in a certain way, tend to be statistically deviant in the parent populations. Similarly, the Edwards Social Desirability Scale (SDS) was developed by selecting items that were unanimously agreed upon by judges as being either socially desirable or undesirable. These items, by necessity, have extreme social desirability scale positions, reflecting statistical deviance.

The strict adherence to the statistical deviance model in the development of social desirability scales has led to several unfortunate consequences. Items drawn from the MMPI, for example, may not only be scalable for social desirability but also have content with pathological implications. When such a scale is applied to a college student population, the interpretation of high social desirability scores becomes ambiguous. When subjects deny symptoms such as fitful sleep or excessive worry over possible misfortunes, it is unclear whether these responses are due to social desirability or the genuine absence of such symptoms. The probability of occurrence of symptoms represented in MMPI items (and incorporated into the SDS) is not always applicable to non-clinical populations.

To address these issues, the paper proposes a new social desirability scale that is developed without reliance on psychopathological items. This ensures that the scale can be used in various populations without the confounding effects of psychopathology. The new scale is designed to assess social desirability independent

Theory and research on self-monitoring have accumulated into a sizable literature on the impact of variation in the extent to which people cultivate public appearances in diverse domains of social functioning. Yet self-monitoring and its measure, the Self-Monitoring Scale, are surrounded by controversy generated by conflicting answers to the critical question, Is self-monitoring a unitary phenomenon? A primary source of answers to this question has been largely neglected--the Self-Monitoring Scale's relations with external criteria. We propose a quantitative method to examine the self-monitoring literature and thereby address major issues of the controversy. Application of this method reveals that, with important exceptions, a wide range of external criteria tap a dimension directly measured by the Self-Monitoring Scale. We discuss what this appraisal reveals about with self-monitoring is and is not.

Although adolescents are commonly assumed to be rebellious, risky and moody, two experiments demonstrate for the first time that these beliefs operate both explicitly and implicitly as stereotypes. In Experiment 1, participants (a) explicitly endorsed adolescent stereotypes and (b) implicitly associated adolescent stereotyped words more rapidly with the adolescent than the adult social category. Individual differences in the explicit endorsement of adolescent stereotypes predicted explicit perceptions of the rebelliousness of a 17-year-old but not a 71-year-old, although individual differences in implicit stereotyping did not. Identification with adults was associated with greater implicit stereotyping but not explicit stereotyping. In Experiment 2, subliminal exposure to adolescent stereotyped words increased subsequent perceptions of the rebelliousness of a 17-year-old but not a 71-year-old. Although individual differences in implicit adolescent stereotyping did not predict explicit evaluations of adolescents, stereotypes of adolescents nevertheless influenced explicit evaluations unconsciously and unintentionally.

Although dehumanizing women and male sexual aggression are theoretically aligned, the present research provides the first direct support for this assumption, using the Implicit Association Test to assess two forms of female dehumanization: animalization and objectification. In Study 1, men who automatically associated women more than men with primitive constructs (e.g., animals, instinct, nature) were more willing to rape and sexually harass women, and to report negative attitudes toward female rape victims. In Study 2, men who automatically associated women with animals (e.g., animals, paw, snout) more than with humans scored higher on a rape-behavioral analogue, as well as rape proclivity. Automatically objectifying women by associating them with objects, tools, and things was also positively correlated with men's rape proclivity. In concert, the research demonstrates that men who implicitly dehumanize women (as either animals or objects) are also likely to sexually victimize them.

This article describes the development of a questionnaire on metacognitive beliefs about procrastination. In Study 1 we performed a principal axis factor analysis that suggested a twofactor solution for the data obtained from the preliminary questionnaire. The factors identified were named positive and negative metacognitive beliefs about procrastination. The factor analysis reduced the questionnaire from 22 to 16 items, with each factor consisting of 8 items. In Study 2 we performed a confirmatory factor analysis that provided support for the twofactor solution suggested by the exploratory factor analysis. Both factors had adequate internal consistency. Concurrent validity was partially established through correlation analyses. These showed that positive metacognitive beliefs about procrastination were positively correlated with decisional procrastination, and that negative metacognitive beliefs about procrastination were positively correlated with both decisional and behavioral procrastination. The Metacognitive Beliefs About Procrastination Questionnaire may aid future research into procrastination and facilitate clinical assessment and case formulation.

This study compared the factor structure of the Sensation-Seeking Scale (SSS) in English and American samples, and a new form of the SSS, applicable to both samples, was constructed. Three of the four factors showed good crossnational and cross-sex reliability. English and American males did not differ on the total SSS score, but American females scored higher than English females. Males in both countries scored higher than females on the total SSS score and on the Thrill and Adventure-Seeking and Disinhibition subscales. Significant age declines occurred for both sexes, particularly on Thrill and Adventure Seeking and Disinhibition.

This study attempted to determine if anticipated moral reproach and cognitive dissonance explain negative attitudes toward vegans and vegetarians, and if vegans are subject to more negative attitudes than vegetarians. The sample consisted of 65 participants (women =41, men =24) who were randomly assigned into one of four conditions. Each participant read a vignette about a person who consumed either a vegan, vegetarian, plant-based or omnivore diet. They then completed a series of questionnaires that recorded their attitudes towards the person in the vignette, anticipated moral reproach, and cognitive dissonance. The results indicated that for the observed general attitudes for the vegan, vegetarian and plant-based diet conditions were more negative than for the omnivore condition, with plant-based diet being the most negative. For moral reproach the results indicated that higher levels of moral reproach contributed to more negative attitudes, but only in the omnivore condition. Whereas the liner regression indicated that cognitive dissonance was only significant predictor of attitudes in the vegan condition. The findings of this study indicated that diet can have an impact on attitudes, and that the diet its self may have a larger impact than the labels applied. DIET AND ATTITUDES 3 Attitudes Toward Vegans and Vegetarians: The Role of Anticipated Moral Reproach and Dissonance Although the majority of North Americans eat an omnivore diet, veganism and vegetarianism have in recent years experienced an increase in popularity (Duchene & Jackson, 2017). As a result, omnivores are believed to be more likely to discuss their attitudes towards vegans and vegetarians, due to the increased exposure to the groups, both in public dialogue and interpersonally among acquaintances. Cole (2011) examined all British newspapers published in the year 2007 that mentioned the words vegan, vegans or veganism. The results showed that the majority of papers published expressed a negative attitude towards veganism. Additionally, any positive papers published looked at only food suggesting that there is a limited perspective provided by the media on veganism. Cole (2011) provides evidence in support that there are systematic negative associations against vegans. The purpose of this study will be to look at possible explanatory theories that could explain why veganism is observed to be viewed more negatively then vegetarianism. The theories that will be used are moral reproach (Minson & Monin, 2012) and cognitive dissonance (Loughnan, Haslam, & Bastian, 2010). This is an important topic to research as veganism and vegetarianism are theorized to be concepts that are strongly tied to the individual’s identity and are seen to be as important to the individual as their sexual orientation, religion, and/ or ethnicity (Wright, 2015). Furthermore, this study may also help to explain why strategies that attempt to encourage people to adopt a vegetarian or vegan diet are often unsuccessful (Duchene & Jackson, 2017). It has been found that personal factors are the major contributor to choosing to become a vegetarian. These personal factors are altered by the perceptions held by the dominant group, omnivores (Hussar & Harris, 2010). By understanding why omnivores have these DIET AND ATTITUDES 4 perceptions about vegans and vegetarians, will lead to insight into why these negative attitudes are occurring. Comparing Veganism and Vegetarianism in Terms of Attitudes and Diet To explore the potential difference in attitudes toward vegetarians and vegans it is important to clarify what the difference is between the two groups. Vegetarianism is defined as a diet that doesn't involve the consumption of meat or by-products of animal slaughter (Wright, 2015). In comparison, veganism consists of a diet without any animal-based products, or any item containing an ingredient derived from an animal (Wright, 2015). Furthermore, vegans place more stress on the ethical tie to animal rights then vegetarians. Animal rights scholar, Carol Adams defines veganism as "an ethical stance based on compassion for all beings" (Adams, 2010, pp.113) and argues that being vegan is about more than adhering to a specific diet. Further evidence to support that veganism is distinctly different from vegetarianism can be found by looking at the groups’ origins. Historically, veganism was founded from a group of vegetarians, who no longer wanted to be seen as part of vegetarianism but rather as their own group (Adams, 2010). This supports the notion that veganism is distinctly different from vegetarianism, as it was created with the purpose to be different then vegetarianism. Evidently there are some clear differences between vegetarians and vegans. It is important to translate how these differences are believed to lead to differing attitudes towards vegans and vegetarians. To understand why vegetarianism may be viewed more positivity then veganism, one commonly offered explanation is that because vegetarians still consume dairy products, the group is viewed as having less polarizing views (Adams, 2010). Elaborating on this statement, Rothgerber found that 38% of people who identified as vegetarian reported consuming meat DIET AND ATTITUDES 5 products to some capacity (2014a). It has been theorised that the emergence of semivegetarianism has lead to vegetarianism being perceived as less negative then veganism. Semivegetarianism is a term that refers to an individual who identifies as being a vegetarian but still consumes meat (Adams, 2010; Rothgerber, 2014a; Ruby, 2012). The amount of meat consumed, and the degree of willingness varies among semi-vegetarians. The presence of semivegetarianism has lead to a blurred conceptualization of vegetarianism resulting in an increase in the perceived homogeneity between vegetarianism and omnivores (Adams, 2010). In support of this, Rothgerber found that semi-vegetarians were closer to omnivores than strict vegetarians regarding the level of disgust shown towards meat (2014a). In summary, this difference could alter the perception that the similarity between omnivores and vegetarians is greater than the similarity between omnivores and vegans. Previous research has been conducted looking at attitude differences between vegetarians and omnivores. The reasoning that a vegetarian gives for maintaining the diet has been found to influence omnivore attitudes towards the group. Generally, the reasons for vegetarianism have been grouped into one of two categories. Health vegetarians tend to cite personal reasons for their membership, such as citing the health benefits or a food allergy. In contrast, ethical vegetarians cite external reasons, such as animal welfare. It has been found that when vegetarians reported being morally motivated, it resulted in a harsher judgement then when the reason reported was personal motivation (Hussar & Harris, 2010). In summary, it is likely that the observed differences between health and ethical vegetarians may translate to comparing vegetarians and vegans, as veganism is tied more to morality then vegetarianism. Another area that is important to look at is difference between vegetarianism veganism, and conscious omnivores. As it is important to address if it is the association to DIET AND ATTITUDES 6 environmentalism or if it is the act of not eating meat that effects attitudes. Rothgerber (2015) states that vegetarianism is a specific form of environmentalism. As well, Bashir et. al (2013) found that individuals were less likely to affiliate with someone if they engaged in a stereotypical environmental activity such as engaging in environmental activism. However, research has shown that the diet that a person eats has a larger impact on attitudes then environmentalism. Rothgerber (2015) compared conscious omnivores to vegans and vegetarians to see how much of an effect the diet had on attitudes towards animals. Conscious omnivores are omnivores who limit their animal consumption and attempt to avoid consuming commercial meat and instead choose animals that are grass feed, or raised more humanely (Rothgerber,2015). The findings of the study were that conscious omnivores scored significantly lower than vegetarianism on both animal favourability and disgust towards meat. The findings also suggest that conscious omnivores conceptually aren’t a group of transitioning vegetarians but rather a separate group. Also, conscious omnivores were found not to put as much emphasis on their eating habits as being a part of their social identity, aligning with the attitudes of normal omnivores (Rothgerber, 2015). In conclusion, it is evident that there are some characteristics of vegetarianism and veganism that are different then omnivore environmentalists. These differences likely contribute to the differences in perceptions that are experienced by omnivores. To summarise it is evident that there is significant evidence to support that there is a difference in the perceptions of vegans and vegetarians that could contribute to a difference in attitudes between the two groups. This paper will now move to discuss some theories that have been applied to these groups in the past to potentially explain this phenomenon. Anticipated Moral Reproach Towards Vegans and Vegetarians DIET AND ATTITUDES 7 Anticipated moral reproach is defined as believing that an individual who holds a different moral stance is judging your own stance as being immoral (Minson & Monin, 2012). This perception of being judged leads to the individual developing a negative attitude towards the other group. In terms of group attitudes, anticipated moral reproach has been used to explain why, when a group stresses overly moral behaviour, it is given the derogatory label of a dogooder or goody-two-shoes. Though not inherently negative, terms such as do-gooder are applied to the individual in a derogatory manner to express their dislike of the group (Minson & Monin, 2012


Question: Creation and Verification of the Transgender Attitudes and Beliefs Scale.

This study involved the simultaneous use of the Rosenberg Self-Esteem Scale (RSES) in a comprehensive cross-cultural assessment across 53 nations, aiming to uncover both universal and culture-specific aspects of global self-esteem. The RSES, translated into 28 languages, was administered to a large sample of 16,998 individuals. The scale's factor structure was found to be consistent across the majority of nations, suggesting a strong cross-cultural equivalence. RSES scores consistently correlated with neuroticism, extraversion, and romantic attachment styles, reinforcing its validity in a global context. The data revealed that positive self-evaluation might be a culturally universal phenomenon, as evidenced by all nations scoring above the theoretical midpoint of the RSES. The variability in individual differences in self-esteem was observed to be culture-dependent, with a neutral response bias more common in collectivist cultures. The RSES's self-competence and self-liking subscales showed variation with cultural individualism. While positively and negatively worded items within the RSES were found to be correlated across cultures and related to external personality variables, the differences between the aggregates of positive and negative items were smaller in developed nations. The study highlighted that negatively worded items were subject to varied interpretations across nations, potentially limiting the direct comparability of cross-cultural data obtained using the RSES.

A questionnaire constructed to assess epistemic curiosity (EC) and perceptual curiosity (PC) curiosity was administered to 739 undergraduates (546 women, 193 men) ranging in age from 18 to 65. The study participants also responded to the trait anxiety, anger, depression, and curiosity scales of the State-Trait Personality Inventory (STPI; Spielberger et al., 1979) and selected subscales of the Sensation Seeking (SSS; Zuckerman, Kolin, Price, & Zoob, 1964) and Novelty Experiencing (NES; Pearson, 1970) scales. Factor analyses of the curiosity items with oblique rotation identified EC and PC factors with clear simple structure. Subsequent analyses of the EC items provided the basis for developing an EC scale, with Diversive and Specific Curiosity subscales. Moderately high correlations of the EC scale and subscales with other measures of curiosity provided strong evidence of convergent validity. Divergent validity was demonstrated by minimal correlations with trait anxiety and the sensation-seeking measures, and essentially zero correlations with the STPI trait anger and depression scales. Male participants had significantly higher scores on the EC scale and the NES External Cognition subscale (effect sizes of r =.16 and.21, respectively), indicating that they were more interested than female participants in solving problems and discovering how things work. Male participants also scored significantly higher than female participants on the SSS Thrill-and-Adventure and NES External Sensation subscales (r =.14 and.22, respectively), suggesting that they were more likely to engage in sensation-seeking activities.

My problem is that I have been persecuted by an integer. For seven years this number has followed me around, has intruded in my most private data, and has assaulted me from the pages of our most public journals. This number assumes a variety of disguises, being sometimes a little larger and sometimes a little smaller than usual, but never changing so much as to be unrecognizable. The persistence with which this number plagues me is far more than a random accident. There is, to quote a famous senator, a design behind it, some pattern governing its appearances. Either there really is something unusual about the number or else I am suffering from delusions of persecution. I shall begin my case history by telling you about some experiments that tested how accurately people can assign numbers to the magnitudes of various aspects of a stimulus. In the traditional language of psychology these would be called experiments in absolute


Question: Creation and Testing of the Transgender Attitudes and Beliefs Scale.

This study aimed to investigate antisocial traits among university students, focusing on the assessment of psychopathic attributes in a non-institutionalized setting. To achieve this, two scales were developed: one to measure primary psychopathy and the other for secondary psychopathy, both designed to evaluate a philosophy indicative of protopsychopathic tendencies. Additionally, an antisocial action scale was created for validation purposes. The primary, secondary, and antisocial action scales were analyzed for correlations with various factors, including boredom susceptibility and disinhibition, but not with experience seeking or thrill and adventure seeking. Notably, secondary psychopathy was linked to trait anxiety. Using multiple regression analysis, it was found that the key predictors of antisocial action were disinhibition, primary psychopathy, secondary psychopathy, and sex, whereas thrill and adventure seeking emerged as a negative predictor. These results challenge the notion of a singular behavioral inhibition system governing both antisocial and risk-taking behaviors, supporting the hypothesis that psychopathy exists on a continuous spectrum.

This study compared the factor structure of the Sensation-Seeking Scale (SSS) in English and American samples, and a new form of the SSS, applicable to both samples, was constructed. Three of the four factors showed good crossnational and cross-sex reliability. English and American males did not differ on the total SSS score, but American females scored higher than English females. Males in both countries scored higher than females on the total SSS score and on the Thrill and Adventure-Seeking and Disinhibition subscales. Significant age declines occurred for both sexes, particularly on Thrill and Adventure Seeking and Disinhibition.

The aim of this study was to translate into Spanish and to validate the Rosenberg Self-Esteem Scale (RSES), completed by 420 university students. Confirmatory factor analysis revealed that the model that best fit the data, both in the total sample and in the male and female subsamples, was the one-factor structure with method effects associated with positively worded items. The results indicated high, positive correlations between self-esteem and the five dimensions of self-concept. The scale showed satisfactory levels of internal consistency and temporal stability over a four-week period. Lastly, gender differences were obtained. These findings support the use of the RSES for the assessment of self-esteem in higher education.

Gender dysphoria (also known as "transsexualism") is characterized as a discrepancy between anatomical sex and gender identity. Research points towards neurobiological influences. Due to the sexually dimorphic characteristics of the human voice, voice gender perception provides a biologically relevant function, e.g. in the context of mating selection. There is evidence for a better recognition of voices of the opposite sex and a differentiation of the sexes in its underlying functional cerebral correlates, namely the prefrontal and middle temporal areas. This fMRI study investigated the neural correlates of voice gender perception in 32 male-to-female gender dysphoric individuals (MtFs) compared to 20 non-gender dysphoric men and 19 non-gender dysphoric women. Participants indicated the sex of 240 voice stimuli modified in semitone steps in the direction to the other gender. Compared to men and women, MtFs showed differences in a neural network including the medial prefrontal gyrus, the insula, and the precuneus when responding to male vs. female voices. With increased voice morphing men recruited more prefrontal areas compared to women and MtFs, while MtFs revealed a pattern more similar to women. On a behavioral and neuronal level, our results support the feeling of MtFs reporting they cannot identify with their assigned sex.


Question: An all-digital phase-locked loop operating at 0.6 volts and 800 megahertz with an integrated digital supply regulator.

This paper introduces the groundbreaking development of an all-digital Phase-Locked Loop (PLL) and polar transmitter specifically designed for mobile phones. These innovations are integral components of a single-chip GSM/EDGE transceiver System on Chip (SoC) manufactured using a 90 nm digital Complementary Metal-Oxide-Semiconductor (CMOS) process. The design philosophy revolves around creating circuits that seamlessly integrate with digital deep-submicron CMOS processes, facilitating direct integration with digital baseband and application processors. To achieve compatibility and optimize performance, the design capitalizes on the inherent advantages of deep-submicron CMOS processes, such as rapid transistor switching speeds, fine lithography, and precise device matching, while mitigating challenges associated with restricted voltage headroom.

The transmitter's architecture is entirely digital, leveraging the broad bandwidth direct frequency modulation capabilities of the all-digital PLL. Digital amplitude modulation is realized by dynamically adjusting the number of active NMOS transistor switches in response to instantaneous amplitude requirements. In a departure from conventional RF frequency synthesizer designs, which rely on voltage-controlled oscillators and phase/frequency detector and charge-pump combinations, this system employs a digitally controlled oscillator and a time-to-digital converter.

The performance of the transmitter is noteworthy, achieving Gaussian Minimum Shift Keying (GMSK) modulation with a root mean square (rms) phase error of less than 0.5 degrees, -165 dBc/Hz phase noise at a 20 MHz offset, and a settling time of 10 microseconds. For Enhanced Data rates for Global Evolution (EDGE) modulation, the transmitter meets the spectral mask with an Error Vector Magnitude (EVM) of 1.2%. The transmitter's footprint is compact at 1.5 mm² and it consumes 42 mA at a 1.2 V supply, delivering 6 dBm of RF output power.

This paper highlights the general trend towards further monolithic integration in power applications by enabling power management and interfacing solutions in advanced CMOS nodes. The need to combine high-density digital circuits, power-management circuits, and robust interfaces in a single technology platform requires the development of additional process options on top of baseline CMOS. Examples include high-voltage devices, devices to enable area-efficient ESD protection, and integrated capacitors and inductors with high quality factors. The use of bipolar devices in these technologies for protection and control purposes in power applications is also addressed.

This paper describes the first 32 kHz low-power MEMS-based oscillator in production. The primary goal is to provide a small form-factor oscillator (1.5 × 0.8 mm 2 ) for use as a crystal replacement in space-constrained mobile devices. The oscillator generates an output frequency of 32.768 kHz and its binary divisors down to 1 Hz. The frequency stability over the industrial temperature range (-40 °C to 85 °C) is ±100 ppm as an oscillator (XO) or ±3 ppm with optional calibration as a temperature compensated oscillator (TCXO). Supply currents are 0.9 μA for the XO and 1.0 μA for the TCXO at supply voltages from 1.4 V to 4.5 V. The MEMS resonator is a capacitively-transduced tuning fork at 524 kHz. The circuitry is fabricated in 180 nm CMOS and includes low power sustaining circuit, fractional-N PLL, temperature sensor, digital control, and low swing driver.

This brief presents an energy-efficient level shifter (LS) to convert a subthreshold input signal to an above-threshold output signal. In order to achieve a wide range of conversion, a dual current mirror (CM) structure consisting of a virtual CM and an auxiliary CM is proposed. The circuit has been implemented and optimized in SMIC 40-nm technology. The postlayout simulation demonstrates that the new LS can achieve voltage conversion from 0.2 to 1.1 V. Moreover, at the target voltage of 0.3 V, the proposed LS exhibits an average propagation delay of 66.48 ns, a total energy per transition of 72.31 fJ, and a static power consumption of 88.4 pW, demonstrating an improvement of <inline-formula> <tex-math notation="LaTeX">$6.0\times $ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$13.1\times $ </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">$89.0\times $ </tex-math></inline-formula>, respectively, when compared with Wilson CM-based LS.

Continuous conduction mode (CCM) boost converter is difficult to compensate due to the right half plane (RHP) zero. This paper presents a quasi fixed frequency constant on time (COT) controlled boost converter, it has no loop compensation requirement. With the proposed COT control, pulse frequency modulation (PFM) comes free at light load, which improves the light load efficiency compared with traditional PWM control. A compact on-time generator that controls the operation frequency is proposed. And a current sink based feedback circuit is used to improve the quality of feedback signal.The COT controller is designed with 1.5 mum BCD process. Simulation results demonstrate that the COT boost converter has fast load transient response and quasi fixed frequency operation.

This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low- and programmable-swing voltage-mode transmitter, software-controlled clock and data recovery (CDR) and adaptive equalization within the receiver, and a novel PLL-based phase rotator for the CDR. The design can operate with channel attenuation of -15 dB or greater at a bit-error rate of 10-15 or less, while consuming less than 2.25 mW/Gb/s per transceiver.

We propose a maximum power point tracking (MPPT) circuit for micro-scale sensor systems that measures ripple voltages in a switched capacitor energy harvester. Compared to conventional current mirror type MPPT circuits, this design incurs no voltage drop and does not require high bandwidth amplifiers. Using correlated double sampling, high accuracy is achieved with a power overhead of 5%, even at low harvested currents of 1.4uA based on measured results in 180nm CMOS.

This paper introduces a fully integrated RF energy-harvesting system. The system can simultaneously deliver the current demanded by external dc loads and store the extra energy in external capacitors, during periods of extra output power. The design is fabricated in 0.18- $\mu \text{m}$  CMOS technology, and the active chip area is 1.08 mm2. The proposed self-startup system is reconfigurable with an integrated LC matching network, an RF rectifier, and a power management/controller unit, which consumes 66–157 nW. The required clock generation and the voltage reference circuit are integrated on the same chip. Duty cycle control is used to operate for the low input power that cannot provide the demanded output power. Moreover, the number of stages of the RF rectifier is reconfigurable to increase the efficiency of the available output power. For high available power, a secondary path is activated to charge an external energy storage element. The measured RF input power sensitivity is −14.8 dBm at a 1-V dc output.

This paper describes a method for both filtering and deskewing a link clock using a differential injection-locked LC-DCO and demonstrates a forwarded-clock data receiver using this technique operating at 27 Gb/s.

This paper presents comparison of two control algorithms for DC/DC converters in vehicle chargers. It presents operation in phase-shifting algorithm and resonant LLC algorithm, their implementation, and test results.

The current paper presents low-power analog integrated circuits (ICs) for wireless electrocardiogram (ECG) detection in personal health monitoring. Considering the power-efficient communication in the body sensor network (BSN), the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. The proposed system comprises the design and implementation with three subsystems, namely, (1) the ECG acquisition node, (2) the protocol for standard IEEE 802.15.4 ZigBee system, and (3) the radio frequency (RF) transmitter circuits. A preamplifier, a low-pass filter, and a successive-approximation analog-to-digital converter (SA-ADC) are integrated to detect an ECG signal. For high integration, the ZigBee protocol is adopted for wireless communication. To transmit the ECG signal through wireless communication, a quadrature voltage-controlled oscillator and a 2.4 GHz low-IF transmitter with a power amplifier and up-conversion mixer are also developed. In the receiver, a 2.4 GHz fully integrated CMOS radio-frequency front-end with a low-noise amplifier, and a quadrature mixer is proposed. The low-power wireless bio-signal acquisition SoC (WBSA-SoC) has been implemented in TSMC 0.18-μm standard CMOS process. The measurement results on the human body reveal that the ECG signals can be acquired effectively by the proposed SoC.


Question: An all-digital phase-locked loop operating at 0.6 volts and 800 MHz with an integrated digital supply regulator.

This article outlines a comprehensive design methodology for a second-order all-digital phase-locked loop (ADPLL), drawing parallels with a type-II second-order analog phase-locked loop (PLL). The proposed design strategy aims to replicate the desirable frequency response and stability features of its analog counterpart within the digital domain. By leveraging the analog PLL analogy, the ADPLL design is endowed with the same performance attributes, ensuring a systematic and efficient design process that maintains stability and optimizes response characteristics.

In essence, the design procedure for the ADPLL is structured to mirror the established design principles of a type-II second-order analog PLL. This approach ensures that the ADPLL not only achieves a similar level of performance but also benefits from the inherent stability and response characteristics of the analog PLL. Through this method, designers can create ADPLLs that are well-suited for various applications, including high-frequency digital communications and clock synchronization, while maintaining the robustness and predictability of traditional analog PLL designs.

This paper1 presents a linear optical receiver designed using a 28nm CMOS technology suitable for 20Gbaud/s (40Gb/s) PAM-4 modulation. The optical receiver consists of a transimpedance amplifier (gain adjustable from 40dBΩ to 56dBO) followed by a variable gain amplifier (gain adjustable from 6dB to 17dB). Capacitive peaking is used to achieve a bandwidth of ~10GHz, thus avoiding the use of on-chip inductors which require large die area. A robust automatic gain control loop is used to ensure a constant differential output voltage swing of ~100mV for an input dynamic range of 20μA to 500μA (peak current). Over this same range, high linearity (total harmonic distortion less than 5%, 250MHz sinewave, 10harmonics taken into account) is obtained. The rms input referred noise current (integrated from 10MHz to 20GHz) was 2.5μArms. The linear optical receiver consumes 56mW from a 1.5V supply voltage.

A novel method adaptively controls the comparator bias current in a boost converter for sensor-data storage on Resistive Random Access Memory (ReRAM). ReRAM is ideal for low-power sensors because it is faster and lower voltage than NAND flash. However, ReRAM's voltage design needs to consider program current variation due to data pattern dependency and cell reliability is sensitive to small voltage fluctuations. The proposed control method of the boost converter architecture has three proposals. First, low program voltage ripple (VRIPPLE) and high program energy efficiency is obtained with an adaptive 2 to 8 μA comparator bias-current (ICMP) control method. ICMP is adjusted depending on the number of program bits (NBITS) in the SET data. In 2 cases of NBITS = 1 and 16, and compared to a conventional scheme (ICMP = 8 μA and 2 μA), respectively, VRIPPLE decreases by 41.2% and energy efficiency improves by 6.6%, respectively. Secondly, as NBITS decrease during SET verify, ICMP also decreases, which further reduces SET energy by 8.9 pJ. Thirdly, although the conventional boost converter fails in the `SS' process condition, an additional cross-coupled charge-pump boosts the buffer circuit, which provides full functional operation over the input range of 0.6 to 1.0 V.

An on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage bulk CMOS process is proposed in this work. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-mum 2.5-V standard CMOS process. The output voltage of the four-stage charge pump circuit with 2.5-V power-supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in a 0.25-mum 2.5-V bulk CMOS process

A systematic approach to designing high frequency and high power oscillators using activity condition is introduced. This method finds the best topology to achieve frequencies close to the fmax of the transistors. It also determines the maximum frequency of oscillation for a fixed circuit topology, considering the quality factor of the passive components. Using this technique, in a 0.13 μm CMOS process, we design and implement 121 GHz and 104 GHz fundamental oscillators with the output power of -3.5 dBm and -2.7 dBm, respectively. Next, we introduce a novel triple-push structure to realize 256 GHz and 482 GHz oscillators. The 256 GHz oscillator was implemented in a 0.13 μm CMOS process and the output power of -17 dBm was measured. The 482 GHz oscillator generates -7.9 dBm (0.16 mW) in a 65 nm CMOS process.

We present in this paper an overview of circuit techniques dedicated to design reliable low-voltage (1-V and below) analog functions in deep submicron standard CMOS processes. The challenges of designing such low-voltage and reliable analog building blocks are addressed both at circuit and physical layout levels. State-ofthe-art circuit topologies and techniques (input level shifting, bulk and current driven, DTMOS), used to build main analog modules (operational amplifier, analog CMOS switches) are covered with the implementation of MOS capacitors.

A low-distortion third-order class-D amplifier that is fully integrated into a 0.18-μ m CMOS process was designed for direct battery hookup in a mobile application. A class-D amplifier for direct battery hookup must have a sufficiently high power supply rejection ratio (PSRR) in preparation for noise, such as when a global system for mobile communications (GSM) bursts ripples through the system power line. This amplifier has a high PSRR of 88 dB for 217-Hz power supply ripples, using a third-order loop filter. System performance and stability are improved by applying the design technique of input-feedforward delta-sigma (ΔΣ) modulators to the pulse-width modulation (PWM) class-D amplifier. A filterless method that can remove the external LC filter is employed, which offers great advantages in terms of PCB space and system cost. This amplifier achieves a power efficiency of 85.5% while delivering an output power of 750 mW into an 8-Ω load from a 3.7-V supply voltage. Maximum achieved output power at 1% total harmonic distortion plus noise (THD+N) from a 4.9-V supply voltage into an 8-Ω load is 1.15 W. This class-D amplifier is designed to have a broad operational range of 2.7-4.9 V for the direct use of mobile phone battery power. It has a total area of 1.01 mm2 and achieves a THD+N of 0.018%.

A 1.8V CMOS chopper four-quadrant analog multiplier, intending to serve as an autonomous IC block for low-frequency signal processing, is presented. Particular emphasis is laid upon achieving low output noise by means of chopper stabilization, while the multiplier's operation is based on the MOS Translinear Principle. The proposed design has been implemented and simulated in TSMC 0.18 µm CMOS process.

A digital self-tuning control technique of DC-DC Buck converter is considered and thoroughly analyzed in this paper. The development of the small-signal model of the converter, which is the key of the control design presented in this work, is based on the state-space averaged (SSA) technique. Adaptive control has become a widely-used term in DC-DC conversion in recent years. A digital self-tuning Dahlin PID and a /Keviczky PID controller based on recursive leastsquares estimation are developed and designed to be applied to the voltage mode control (VMC) approach operating in a continuous conduction mode (CCM). A comparative study of these two digital self-tuning controllers for step change in input voltage magnitude or output load is also carried out. The simulation results obtained using a Matlab SimPowerSystems toolbox to validate the effectiveness of the proposed strategies are also given and discussed extensively.

A 1.8-V 12-bit 5MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented. To reduce DAC switching energy and chip area, a hybrid resistor-capacitor DAC is applied. To save energy, asynchronous control logic to drive the ADC is used. A pre-amplifier based comparator circuit is built to reduce the kickback noise from the dynamic latch designs. With 1.8 V supply voltage and 5.0 MHz sampling rate, measured results achieve -0.55/0.72 LSB (Least Significant Bit) of DNL (differential nonlinearity) and -0.78/0.92 LSB of integral nonlinearity (INL) respectively, and 10.76 bits of an effective number of bits (ENOB) at 1MHz input frequency. The chip area is 0.83 mm2 including pads and the power consumption is 490μW for optical and wireless communications.

This brief presents a power-efficient voltage level-shifter architecture that is capable of converting extremely low levels of input voltages to higher levels. In order to avoid the static power dissipation, the proposed structure uses a current generator that turns on only during the transition times, in which the logic level of the input signal is not corresponding to the output logic level. Moreover, the strength of the pull-up device is decreased when the pull-down device is pulling down the output node in order for the circuit to be functional even for the input voltage lower than the threshold voltage of a MOSFET. The operation of the proposed structure is also analytically investigated. Post-layout simulation results of the proposed structure in a 0.18-μm CMOS technology show that at the input low supply voltage of 0.4 V and the high supply voltage of 1.8 V, the level shifter has a propagation delay of 30 ns, a static power dissipation of 130 pW, and an energy per transition of 327 fJ for a 1-MHz input signal.


Question: An all-digital phase-locked loop operating at 0.6 volts and 800 megahertz with an integrated digital supply regulator.

This paper presents a comprehensive analysis and modeling framework for bang-bang clock and data recovery circuits, specifically focusing on the Alexander phase detector and an LC oscillator. The proposed model, based on a large-signal piecewise-linear approach, accurately predicts key performance indicators of these circuits, including jitter transfer, jitter tolerance, and jitter generation. Validation of the model's predictions is achieved through the testing of 1-Gb/s and 10-Gb/s CMOS prototypes, demonstrating its reliability in characterizing bang-bang phase detectors in high-speed applications.

**Question**: A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator

**Documents**: Design and simulation of a 2.4 GHz CMOS fractional-N frequency synthesizer with a digitally controlled oscillator

**Similar Documents**: This document describes the design and simulation process of a 2.4 GHz CMOS fractional-N frequency synthesizer, featuring a digitally controlled oscillator (DCO). The synthesizer is designed to operate at a high frequency with precise control over the output signal, making it suitable for various wireless communication applications. The digitally controlled oscillator allows for rapid and accurate tuning of the frequency, enhancing the flexibility and performance of the synthesizer in dynamic environments. Through comprehensive simulation, the design's effectiveness in achieving stable and accurate frequency generation is demonstrated, showcasing its potential for integration into advanced wireless systems.

We present an analog subsampling PLL based on a digital-to-time converter (DTC), which operates with almost no performance gap (176/198 fs RMS jitter) between the integer and the worst case fractional operation, achieving -246.6 dB FOM in the worst case fractional mode. The PLL is capable of two-point, 10 Mbit/s GMSK modulation with -40.5 dB EVM around a 10.24 GHz fractional carrier. The analog nonidealities-DTC gain, DTC nonlinearity, modulating VCO bank gain, and nonlinearity-are calibrated in the background while the system operates normally. This results in ~15 dB fractional spur improvement (from -41 dBc to -56.5 dBc) during synthesis and ~15 dB EVM improvement (from -25 dB to -40.5 dB) during modulation. The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them. We demonstrate state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.

It is traditionally challenging to implement higher-order PWM closed-loop Class-D audio amplifiers using analog intensive techniques in deep-submicron, low voltage process technologies. This is primarily attributed to reduced power supply, degraded analog transistor characteristics, including short-channel effects, increased flicker noise, random telegraph noise, transistor reliability concerns and passive component performance. In this paper, we introduce a global closed-loop mixed-signal architecture incorporating digital control and integrate a fourth-order amplifier prototype in 55 nm CMOS. A systematic approach to analyze, design and compensate the feedback loop in the digital domain is also presented. The versatility of implementing the loop gain poles and zeros digitally attains high gain throughout the audio band and attenuates residual high frequency ripples around the loop, simultaneously accomplishing improvements in THD+N and PSRR. The overall architecture is inherently amenable to implementation in deep-submicron and is therefore compatible with scaled CMOS. The measured prototype achieves a high 105 dBA SNR, 0.0031% THD+N, 92 dB PSRR and 85% efficiency when supplying 1 W into emulated 8 Ω speaker load. This performance is competitive with conventional designs using large feature size precision CMOS or specialized BCD technologies and reports the highest output power (1.5 W) for deep-submicron designs.

A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.

New MOS charge pumps utilizing the charge transfer switches (CTS’s) to direct charge flow and generate boosted output voltage are described. Using the internal boosted voltage to backward control the CTS of a previous stage yields charge pumps that are suitable for low-voltage operation. Applying dynamic control to the CTS’s can eliminate the reverse charge sharing phenomenon and further improve the voltage pumping gain. The limitation imposed by the diode-configured output stage can be mitigated by pumping it with a clock of enhanced voltage amplitude. Using the new circuit techniques, a 1.2-V-to-3.5-V charge pump and a 2-V-to-16-V charge pump are demonstrated.

Here, A PID controller plus a novel linear-to-nonlinear translator is proposed and applied to the boost converter to improve the operating performance of the boost converter under large transient variations in load all over the quiescent dc input voltage range. The proposed translator is inserted between the PID controller and the main power stage such that the PID controller considers the behavior of the boost converter to be quasi-linear, thereby suppressing the effect of nonlinear behavior of the boost converter on the PID controller. Besides, variations in dc gain of the control-to-output transfer function with the translator are smaller than those without the translator, thus making system control easy to attain. Also, one-comparator counter-based sampling without any A-D converter is presented herein to realize the proposed control strategy. As mentioned above, the proposed control strategy can make the boost converter stably operated under large load transient responses all over the quiescent dc input voltage range.

A novel on-chip impedance matching and powercombining method, the distributed active transformer is presented. It combines several low-voltage push–pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50match. It also uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any offchip component, such as tuned bonding wires or external inductors. Furthermore, it desensitizes the operation of the amplifier to the inductance of bonding wires making the design more reproducible. To demonstrate the feasibility of this concept, a 2.4-GHz 2-W 2-V truly fully integrated power amplifier with 50input and output matching has been fabricated using 0.35m CMOS transistors. It achieves a power added efficiency (PAE) of 41% at this power level. It can also produce 450 mW using a 1-V supply. Harmonic suppression is 64 dBc or better. This new topology makes possible a truly fully integrated watt-level gigahertz range low-voltage CMOS power amplifier for the first time.

This work presents an ultra-low power event driven wake-up receiver (WuRx) fabricated in a RF CMOS 130 nm process. The receiver consists of an off-chip lumped element matching network, an envelope detector, a decision circuit capable of detecting sub-mV baseband signal voltages and a clock source consuming 1.3 nW. This receiver has demonstrated a sensitivity of −72 dBm while consuming a total of 8.3 nW from 1 V and 0.65 V sources.

A 1.8V CMOS chopper four-quadrant analog multiplier, intending to serve as an autonomous IC block for low-frequency signal processing, is presented. Particular emphasis is laid upon achieving low output noise by means of chopper stabilization, while the multiplier's operation is based on the MOS Translinear Principle. The proposed design has been implemented and simulated in TSMC 0.18 µm CMOS process.

A new charge pump circuit with consideration of gateoxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3 3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulkdriven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) based on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 μW. PSpice simulation results using the 0.18 μm CMOS technology from TSMC are included to verify the design functionality and correspondence with theory.


Question: An 0.6-V 800-MHz fully digital phase-locked loop incorporating a digital supply regulator.

This paper offers a detailed analysis of third-order charge-pump phase-locked loops (CPLLs) through the formulation of state equations. It comprehensively covers both the lock acquisition process under large-signal conditions and the linear tracking behavior under small-signal scenarios. The analysis involves the linearization of the nonlinear state equations under small-signal conditions, leading to the derivation of noise transfer functions in the z-domain. This method is contrasted with other existing analysis techniques, including the impulse-invariant transformation and s-domain analysis, highlighting its precision and effectiveness. The impact of loop parameters and the reference frequency on the phase margin and stability of the loop is also thoroughly investigated. The validity of this analytical approach is confirmed through behavioral simulations conducted in MATLAB and SPECTRE, demonstrating its accuracy in predicting the performance of CPLLs.

A new voltage doubler rectified boost-integrated half bridge converter for digital car audio amplifiers is proposed. The proposed converter shows low conduction loss due to low voltage stress of the secondary diodes, no dc magnetizing current for the transformer, and a lack of stored energy in the transformer. Moreover, since the primary MOSFETs are turned-on under zero voltage switching conditions and the secondary diodes are turned-off under zero current switching conditions, the proposed converter has minimized switching losses. In addition, the input filter can be minimized due to a continuous input current, and an output filter does not need an inductor in the proposed converter. Therefore, the proposed converter has the desired features, high efficiency and low profile, for a viable power supplies for digital car audio amplifiers. A 60-W industrial sample of the proposed converter has been implemented for digital car audio amplifiers with a measured efficiency of 88.3% at nominal input voltage.

The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 μm2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.

This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic preamplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor’s parameters in pre-amplifier’s gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers’ estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results. key words: dynamic amplifier, dynamic comparator, load capacitance, bypass current, calibration, and PVT variation

A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of 43 dB for 900 mVpp at 30 MHz. The OTA, fabricated in 0.5m CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filter’s group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of 46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a 1.65-V power supply.

A low-power FMCW 80 GHz radar transmitter front-end chip is presented, which was fabricated in a SiGe bipolar production technology ( fT=180 GHz, fmax=250 GHz ). Additionally to the fundamental 80 GHz VCO, a 4:1-frequency divider (up to 100 GHz), a 23 GHz local oscillator (VCO) with a low phase noise of -112 dBc/Hz (1 MHz offset), a PLL-mixer and a static frequency divider is integrated together with several output buffers. This chip was designed for low power consumption (in total <; 0.5 W, i.e., 100 mA at 5 V supply voltage), which is dominated by the 80 GHz VCO due to the demands for high output power (≈ 12 dBm) and low phase noise (minimum -97 dBc/Hz at 1 MHz offset) within the total wide tuning range from 68 GHz to 92.5 GHz (Δf = 24.5 GHz). Measurements of the double-PLL system at 80 GHz showed a low phase noise of -88 dBc/Hz at 10 kHz offset frequency.

This brief presents an energy-efficient level shifter (LS) to convert a subthreshold input signal to an above-threshold output signal. In order to achieve a wide range of conversion, a dual current mirror (CM) structure consisting of a virtual CM and an auxiliary CM is proposed. The circuit has been implemented and optimized in SMIC 40-nm technology. The postlayout simulation demonstrates that the new LS can achieve voltage conversion from 0.2 to 1.1 V. Moreover, at the target voltage of 0.3 V, the proposed LS exhibits an average propagation delay of 66.48 ns, a total energy per transition of 72.31 fJ, and a static power consumption of 88.4 pW, demonstrating an improvement of <inline-formula> <tex-math notation="LaTeX">$6.0\times $ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$13.1\times $ </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">$89.0\times $ </tex-math></inline-formula>, respectively, when compared with Wilson CM-based LS.

An improved oped for generating +40 voltage multiplier technique has been develV internally in p-channel MNOS integrated circuits to enrtble them to be operated from standard +5and : 12-V supply rails. With this technique, the multiplication efficiency and current driving capabtilty are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 ~m X 240 pm. It is operated with a clock frequency of 1 MHz and can supManuscript received December 9, 1975; revised February 18, 1976. This paper is based on part of a presentation entitled “A non-volatile MNOS quad-latch,” which was presented at the First European SolidState Circuits Conference, Canterbury, England, September 2-5, 1975. The author is with the Allen Clark Research Centre, The Plessey Company Ltd., CasweJl, Towcester, Northants., England. MNOS Voltage ply a maximum load current of about 10 NA. The output impedance is 3.2 Mfl. INTRODUCTION ALTHOUGH MNOS technology is now well established for fabricating nonvolatile memory circuits, the relatively high potentials necessary to write or erase information, typically 30-40 V, are an obvious disadvantage. In many applications, the need to generate these voltages has prevented the use of MNOS devices being economically viable, especially when only a few bits of nonvolatile data are required. To overcome this problem, a method of on-chip high-voltage generation using a new voltage multiplier technique has been developed, enabling MNOS circuits to be operated with standard DICKSON: ON-CHIP HIGH-VOLTAGEGENERATION 375

In this paper, we present a new approach to integrate in a 0.35 μm BCD technology, low Ron LDMOS power transistors with highly competitive Specific Resistance figure of merit (Rsp, defined as Ron*Area). The LDMOS are fully isolated in order to support applications which may bias the source/drain electrodes below the substrate potential, which is critical for devices used in high-current, high-frequency switching applications. The new devices are suitable for high-efficiency DC-DC converter products with operating voltage of up to 30V, such as mobile PMICs. For maximum performance, two different extended-drain LDMOS structures have been developed to cover the entire operating voltage range: for 16V and below, a planar-gate structure is used and for 20V and above, a non-planar “offset-LOCOS” gate is used for 20V and above.

Switching regulators with ripple-based control (i.e., ¿ripple regulators¿) are conceptually simple, have fast transient responses to both line and load perturbations, and some versions operate with a switching frequency that is proportional to the load current under the discontinuous conduction mode. These characteristics make the ripple regulators well-suited, especially for power management applications in computers and portable electronic devices. Ripple regulators also have some drawbacks, including (in some versions) a poorly defined switching frequency, noise-induced jitter, inadequate dc regulation, and a tendency for fast-scale instability. This paper presents an overview of the various ripple-based control techniques, discusses their merits and limitations, and introduces techniques for reducing the noise sensitivity and the sensitivity to capacitor parameters, improving the frequency stability and the dc regulation, and avoiding fast-scale instability.

This study characterizes the effect of substrate noise on a standard component of the RF front end: the voltage controlled oscillator (VCO), as well as evaluating the effect of VCO bias current and guard rings on noise performance. Frequency effects of substrate noise are also examined through the study of VCOs at three different center frequencies: 900 MHz, 2.4 GHz, and 5.2 GHz. Substrate noise is a serious problem that continues to plague mixed-signal designs. Components of the RF frontend are particularly sensitive to substrate noise as the effectiveness of standard isolation techniques degrades at higher frequencies. This study has shown that the phase noise of a VCO is adversely affected by substrate noise. In the extreme, the VCO can lock to the substrate noise. Guard rings can effectively attenuate substrate noise at lower frequencies. For example, at 900 MHz, as much as 25 dB of isolation is observed. At 5.2 GHz, the isolation reduces to 10 dB. Furthermore, the use of guard rings can improve the response of the VCO to injection locking.


Question: An all-digital phase-locked loop operating at 0.6 volts and 800 megahertz with an integrated digital supply regulator.

This paper introduces a cutting-edge digitally controlled oscillator (DCO)-based framework for radio frequency (RF) synthesis in wireless applications, designed specifically for deep-submicrometer complementary metal-oxide-semiconductor (CMOS) processes. The architecture intentionally eschews the use of analog tuning voltage control lines, achieving precise frequency resolution through high-speed dithering techniques. Analog circuit imperfections are mitigated through digital compensation, paving the way for the integration of fully digital frequency synthesizers that leverage advanced signal processing algorithms. These synthesizers are realized in the most advanced deep-submicrometer digital CMOS processes, which typically lack analog extensions. This approach facilitates cost-effective monolithic integration with the digital backend on a single silicon chip. The prototype test chip was manufactured using a digital 0.13µm CMOS process in conjunction with a digital signal processor (DSP), which functions as a digital baseband processor with a substantial number of digital gates to explore noise coupling effects. The phase noise performance is measured at -112 dBc/Hz at a 500-kHz offset. The nearby spurious signals are suppressed to below 62 dBc, whereas the distant spurs are attenuated to under 80 dBc. The innovative concepts presented have been successfully integrated into a commercial Bluetooth transceiver, showcasing their practical application and effectiveness.

This work presents an ultra-low power event driven wake-up receiver (WuRx) fabricated in a RF CMOS 130 nm process. The receiver consists of an off-chip lumped element matching network, an envelope detector, a decision circuit capable of detecting sub-mV baseband signal voltages and a clock source consuming 1.3 nW. This receiver has demonstrated a sensitivity of −72 dBm while consuming a total of 8.3 nW from 1 V and 0.65 V sources.

This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital sub-sampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DCO edges, thus further reducing power consumption. With a proposed DCO-divider phase rotation in the feedback path, the impact of the digital-to-time converter’s (DTC’s) non-linearity on the PLL is reduced and improves fractional spurs by at least 8 dB across BLE channels. Moreover, a “variable-preconditioned LMS” calibration algorithm is introduced to dynamically correct the DTC gain error with fractional frequency control word (FCW) down to 1/16384. Fabricated in 40 nm CMOS, the SS-DPLL achieves phase noise performance of −109 dBc/Hz at 1 MHz offset, while consuming a record-low power of 1.19 mW.

We present an analog subsampling PLL based on a digital-to-time converter (DTC), which operates with almost no performance gap (176/198 fs RMS jitter) between the integer and the worst case fractional operation, achieving -246.6 dB FOM in the worst case fractional mode. The PLL is capable of two-point, 10 Mbit/s GMSK modulation with -40.5 dB EVM around a 10.24 GHz fractional carrier. The analog nonidealities-DTC gain, DTC nonlinearity, modulating VCO bank gain, and nonlinearity-are calibrated in the background while the system operates normally. This results in ~15 dB fractional spur improvement (from -41 dBc to -56.5 dBc) during synthesis and ~15 dB EVM improvement (from -25 dB to -40.5 dB) during modulation. The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them. We demonstrate state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.

A low-distortion third-order class-D amplifier that is fully integrated into a 0.18-μ m CMOS process was designed for direct battery hookup in a mobile application. A class-D amplifier for direct battery hookup must have a sufficiently high power supply rejection ratio (PSRR) in preparation for noise, such as when a global system for mobile communications (GSM) bursts ripples through the system power line. This amplifier has a high PSRR of 88 dB for 217-Hz power supply ripples, using a third-order loop filter. System performance and stability are improved by applying the design technique of input-feedforward delta-sigma (ΔΣ) modulators to the pulse-width modulation (PWM) class-D amplifier. A filterless method that can remove the external LC filter is employed, which offers great advantages in terms of PCB space and system cost. This amplifier achieves a power efficiency of 85.5% while delivering an output power of 750 mW into an 8-Ω load from a 3.7-V supply voltage. Maximum achieved output power at 1% total harmonic distortion plus noise (THD+N) from a 4.9-V supply voltage into an 8-Ω load is 1.15 W. This class-D amplifier is designed to have a broad operational range of 2.7-4.9 V for the direct use of mobile phone battery power. It has a total area of 1.01 mm2 and achieves a THD+N of 0.018%.

A CMOS voltage reference, which takes advantage of weighted difference of the gate-source voltages between a PMOS and an NMOS transistor operating in saturation region, is presented in this paper. The reference has been implemented in a standard 0.6-µm CMOS process (Vthn≈ |Vthp| ≈ 0.9 V@0° C) and gives a temperature coefficient of not greater than 62 ppm/°C from 0 to 100° C without trimming, while consuming a maximum of 9.7 µA with a minimum supply of 1.4 V. The worst-case line regulation is ±0.17 %/V. The occupied chip area is 0.055 mm2. The proposed reference has been applied to a 10-mA CMOS low dropout regulator, and a temperature coefficient of 94 ppm/°C is achieved when the regulator delivers maximum load current.

A novel transformer feedback featuring wideband input matching and noise cancellation is proposed and demonstrated in a wideband differential LNA for software-defined-radio (SDR) applications. Implemented in 0.13μm CMOS with an area of 0.32mm2, the LNA prototype measures a wideband input matching S11 of less than -10dB from 1.2GHz to 6.6GHz and minimum NF of 1.8dB while consuming 11mA at 1.2V supply.

Non-linear voltage-to-frequency characteristic of a voltage-controlled oscillator (VCO) severely curtails the dynamic range of analog-to-digital converters (ADCs) built with VCOs. Typical approaches to enhance the dynamic range include embedding the VCO-based ADC in a ΔΣ loop or to post-process the digital data for calibration, both of which impose significant power constraints. In contrast, in this work the VCO-based ADC is linearized through a filtered dithering technique, wherein the VCO-based ADC is used as a fine stage that processes the residue from a coarse stage in a 0-1 MASH structure. The proposed filtered dithering technique conditions the signal to the VCO input to appear as white noise thereby eliminating spurious signal content arising out of the VCO nonlinearity. The work resorts to multiple other signal processing techniques to build a high-resolution, wideband prototype, in 65 nm complementary metal-oxide semiconductor (CMOS), that achieves 10 effective number of bits (ENOB) in digitizing signals with 50 MHz bandwidth consuming 8.2 mW at a figure of merit (FoM) of 90 fJ/conv.step.

A microcontroller based advanced technique of generating sine wave with minimized harmonics is implemented in this paper. The proposed technique “impulse-sine product” aims to design and implement a voltage regulated inverter with ripple free and glitch free output sine wave that can operate electronic devices efficiently. The output voltage of the inverter is regulated by a feedback loop using analog to digital protocol of PIC16f877 microcontroller. The design is essentially focused upon low power electronic appliances such as personal computers, chargers, television sets. The inverter output is regulated from 16-volt rms to 220-volt rms for a variation of load between 1-Ω to 180-Ω loads. The designed inverter provides a range of operation from 25 Watts to 250 Watts. The design is mathematically modeled which is simulated in Matlab, Proteus and finally the results are practically verified.

We present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both non-pipelined and functionally pipelined data-paths. The scheduling problem refers to the assignment of a supply voltage level to each operation in a data ow graph so as to minimize the average energy consumption for given computation time or throughput constraints or both. The energy model is accurate and accounts for the input pattern dependencies, re-convergent fanout induced dependencies, and the energy cost of level shifters. Experimental results show that using four supply voltage levels on a number of standard benchmarks, an average energy saving of 53% (with a computation time constraint of 1.5 times the critical path delay) can be obtained compared to using one fixed supply voltage level.

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without lowthreshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 0.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.


Question: Morphological computation - a promising solution for tackling control issues in soft robotics.

This paper offers an extensive review of Reservoir Computing, a concept revolutionizing the training of recurrent neural networks. Traditionally, training these networks has proven to be a complex task. However, a recent breakthrough allows for the construction of a random recurrent topology, with the focus shifted to training solely a linear readout layer. This methodology, known as Reservoir Computing, has been shown to achieve state-of-the-art performance with relative ease. The underlying principle can be further generalized to include any high-dimensional, driven dynamic system operating within a specific dynamic regime. Such systems can serve as temporal 'kernels', enabling the solution of intricate tasks through the application of linear post-processing techniques alone. This review aims to provide a comprehensive insight into the current landscape of Reservoir Computing research, encompassing theoretical foundations, practical applications, and implementation strategies. This approach holds significant potential for addressing the control problem in soft robotics, offering a streamlined and effective solution to the complexities of training and operation.

This paper proposes an effective framework of human-humanoid robot physical interaction. Its key component is a new control technique for full-body balancing in the presence of external forces, which is presented and then validated empirically. We have adopted an integrated system approach to develop humanoid robots. Herein, we describe the importance of replicating human-like capabilities and responses during human-robot interaction in this context. Our balancing controller provides gravity compensation, making the robot passive and thereby facilitating safe physical interactions. The method operates by setting an appropriate ground reaction force and transforming these forces into full-body joint torques. It handles an arbitrary number of force interaction points on the robot. It does not require force measurement at interested contact points. It requires neither inverse kinematics nor inverse dynamics. It can adapt to uneven ground surfaces. It operates as a force control process, and can therefore, accommodate simultaneous control processes using force-, velocity-, or position-based control. Forces are distributed over supporting contact points in an optimal manner. Joint redundancy is resolved by damping injection in the context of passivity. We present various force interaction experiments using our full-sized bipedal humanoid platform, including compliant balance, even when affected by unknown external forces, which demonstrates the effectiveness of the method.

In this paper, we present an algorithm for a shape-shifting robot climbing stairs autonomously. The robot has been used several times for search and rescue missions. Because of the special environment of tasks, the robot must have the ability to climb stairs autonomously to help the operators. Due to the characters of robot in "T" configuration, the mathematical model of force is established and the whole process of climbing stairs is analyzed. Grouser-tread hooking, track-stair edge frictional force et al. are all considered during the process of climbing. A description of its dynamic model is also presented which is involved in the controller. The controller is comprised of center control and heading control, which can help the robot climb stairs safely and quickly. The effectiveness of the algorithms proposed are verified by experiment.

Pneumatic artificial muscles are pneumatic devices with practical and various applications as common actuators. They, as human muscles, work in agonistic-antagonistic way, giving a traction force only when supplied by compressed air. The state of the art of soft pneumatic actuators is here analyzed: different models of pneumatic muscles are considered and evolution lines are presented. Then, the use of Pneumatic Muscles (PAM) in rehabilitation apparatus is described and the general characteristics required in different applications are considered, analyzing the use of proper soft actuators with various technical properties. Therefore, research activity carried out in the Department of Mechanical and Aerospace Engineering in the field of soft and textile actuators is presented here. In particular, pneumatic textile muscles useful for active suits design are described. These components are made of a tubular structure, with an inner layer of latex coated with a deformable outer fabric sewn along the edge. In order to increase pneumatic muscles forces and contractions Braided Pneumatic Muscles are studied. In this paper, new prototypes are presented, based on a fabric construction and various kinds of geometry. Pressure-force-deformation tests results are carried out and analyzed. These actuators are useful for rehabilitation applications. In order to reproduce the whole upper limb movements, new kind of soft actuators are studied, based on the same principle of planar membranes deformation. As an example, the bellows muscle model and worm muscle model are developed and described. In both cases, wide deformations are expected. Another issue for soft actuators is the pressure therapy. Some textile sleeve prototypes developed for massage therapy on patients suffering of lymph edema are analyzed. Different types of fabric and assembly techniques have been tested. In general, these OPEN ACCESS Actuators 2014, 3 85 Pressure Soft Actuators are useful for upper/lower limbs treatments, according to medical requirements. In particular devices useful for arms massage treatments are considered. Finally some applications are considered.

Summary form only given. The design and control of quadruped robots has become a fascinating research field because they have better mobility on unstructured terrains. Until now, many kinds of quadruped robots were developed, such as JROB-1 [1], BISAM [2], BigDog [3], LittleDog [4], HyQ [5] and Cheetah cub [6]. They have shown significant walking performance. However, most of them use serial mechanism legs and have animal like structure: the thigh and the crus. To swing the crus in swing phase and support the body's weight in stance phase, a linear actuator is attached on the thigh [2, 3, 5, 6], or instead, a rotational actuator is installed on the knee joint [1, 4]. To make the robot more useful in the wild environment, e.g., the detection or manipulation tasks, the payload capability is very important. To carry the sensors or tools, heavy load legged robot is very necessary. Thus the knee actuator should be lightweight, powerful and easy to maintain. However, this can be very costly and hard to satisfy at the same time.

Recently, automated robotic systems have become very efficient, thanks to improved coupling between sensor systems and algorithms, of which the latter have been gaining significance thanks to the increase in computing power over the past few decades. However, intelligent automated chemistry platforms for discovery orientated tasks need to be able to cope with the unknown, which is a profoundly hard problem. In this Outlook, we describe how recent advances in the design and application of algorithms, coupled with the increased amount of chemical data available, and automation and control systems may allow more productive chemical research and the development of chemical robots able to target discovery. This is shown through examples of workflow and data processing with automation and control, and through the use of both well-used and cutting-edge algorithms illustrated using recent studies in chemistry. Finally, several algorithms are presented in relation to chemical robots and chemical intelligence for knowledge discovery.

Passively compliant legs have been instrumental in the development of dynamically running legged robots. Having properly tuned leg springs is essential for stable, robust and energetically efficient running at high speeds. Recent simulation studies indicate that having variable stiffness legs, as animals do, can significantly improve the speed and stability of these robots in changing environmental conditions. However, to date, the mechanical complexities of designing usefully robust tunable passive compliance into legs has precluded their implementation on practical running robots. This paper describes a new design of a ”structurally controlled variable stiffness” leg for a hexapedal running robot. This new leg improves on previous designs’ performance and enables runtime modification of leg stiffness in a small, lightweight, and rugged package. Modeling and leg test experiments are presented that characterize the improvement in stiffness range, energy storage, and dynamic coupling properties of these legs. We conclude that this variable stiffness leg design is now ready for implementation and testing on a dynamical running robot.

In this study, we propose integrated control of a robotic hand and arm using only proximity sensing from the fingertips. An integrated control scheme for the fingers and for the arm enables quick control of the position and posture of the arm by placing the fingertips adjacent to the surface of an object to be grasped. The arm control scheme enables adjustments based on errors in hand position and posture that would be impossible to achieve by finger motions alone, thus allowing the fingers to grasp an object in a laterally symmetric grasp. This can prevent grasp failures such as a finger pushing the object out of the hand or knocking the object over. Proposed control of the arm and hand allowed correction of position errors on the order of several centimeters. For example, an object on a workbench that is in an uncertain positional relation with the robot, with an inexpensive optical sensor such as a Kinect, which only provides coarse image data, would be sufficient for grasping an object.

The recent developments of soft robots have inspired a variety of applications that require compliance for safety and softness for biomimetics. With such prevalence and advantages of soft robots, researchers are diverting their interests toward applications like micromanipulation of biological tissue. However, the progress has been thwarted by the difficulty in producing soft robots in miniature scale. In this paper, we present a new kind of microscale soft pneumatic actuators (SPA) made from streamlined and standardized fabrication procedure with customizable bending modalities inspired by shape engineering. Preliminary mathematical models are given to interpret width-based shape engineering for customization and to compare the bending angle and radius of curvature measured from the characterization experiments. The fabricated SPA was tested on the sciatic nerve of a rat in order to show its future potentials in biomedical field. Ultimately, this paper will contribute to the diversification of SPA fabrication and customization, as well as biomedical applications that demand smaller dimensions and higher precision.

A flexible electro-conductive rubber sensor for measuring the length of a McKibben pneumatic actuator has been developed. Mckibben actuators are flexible, lightweight, and widely used to actuate power assisting devices for which compliance is required for safety. The actuator's length needs to be measured to control the devices accurately. However, the flexibility and lightweight properties might be lost if rigid sensors such as linear potentionmeters or encoders are directly attached to the actuators. To keep the desirable properties of McKibben actuators, compact and flexible sensors are necessary. In this paper, a flexible sensor using electro-conductive flexible rubber is proposed to measure the length of McKibben actuators. Using this sensor, a higher accuracy can be obtained by measuring the circumference displacement than directly measuring the axial displacement. The estimation accuracy is evaluated and the usefulness of the proposed method is verified by adopting to a multiple-link robot arm driven by the McKibben actuators.

A tactile sensor is developed with the aim of covering a robot's entire structure, while reducing wiring requirement and ensuring high-speed response. The sensor detects the center point of load distribution on 2-D surfaces as well as the overall load. There are only four signal wires from the sensor. The sensor response time is nearly constant (within 1 ms) regardless of the number of detection elements, their placements or sensor areas. In this paper, the principles behind the operation of this sensor and the results of experiments using the sensor are described.