Question: Computer Vision Accelerators for Mobile Systems utilizing OpenCL GPGPU Co-Processing.

This paper investigates the Energy and Performance Profiling in Mobile Heterogeneous Computing Environments. Contemporary mobile application processors embody a multi-core heterogeneous System-on-Chip (SoC), featuring a Central Processing Unit (CPU) alongside specialized accelerators, such as Graphics Processing Units (GPU) and Digital Signal Processors (DSP). This architecture presents a potential for enhancing performance in compute-heavy applications, yet the effective allocation of tasks across such a diverse computing landscape is a complex endeavor with numerous design considerations. We undertake a detailed analysis of the performance and energy efficiency gains from leveraging integrated GPU and DSP cores to relieve the CPU of its compute-intensive workload. Our study is executed on a trio of cutting-edge mobile platforms: Texas Instruments' OMAP3530, Qualcomm's Snapdragon S2, and Nvidia's Tegra2, using benchmark tasks representative of common mobile applications. We pinpoint crucial elements to be factored into energy-optimized heterogeneous computing on mobile devices. Our findings reveal that, by judiciously engaging all available computing cores in parallel, a mean performance enhancement of 3.7 times can be attained, albeit at a 33% increase in power consumption, relative to CPU-only operation. This translates to a 2.8 times reduction in energy consumption, showcasing the potential of multi-core heterogeneous processing in mobile systems.

Deep Neural Networks (DNNs) have progressed significantly in recent years. Novel DNN methods allow tasks such as image and speech recognition to be conducted easily and efficiently, compared with previous methods that needed to search for valid feature values or algorithms. However, DNN computations typically consume a significant amount of time and high-performance computing resources. To facilitate high-speed object recognition, this article introduces a Deep Convolutional Neural Network (DCNN) accelerator based on a field-programmable gate array (FPGA). Our hardware takes full advantage of the characteristics of convolutional calculation; this allowed us to implement all DCNN layers, from image input to classification, in a single chip. In particular, the dateflow from input to classification is uninterrupted and paralleled. As a result, our implementation achieved a speed of 409.62 giga-operations per second (GOPS), which is approximately twice as fast as the latest reported result. Furthermore, we used the same architecture to implement a Recurrent Convolutional Neural Network (RCNN), which can, in theory, provide better recognition accuracy.

It is our aim in this research to optimize the numerical computation of the Haralick texture features [1] that consists of two steps. Haralick texture features are used as a primary component to discern between different protein structures in microscopic bio-images. The first of these two parts is the construction of the co-occurrence matrix. Upon completion of this implementation, we will attempt to optimize the code using a novel recursive blocking algorithm. We will also use standard practices of optimizing code such as scalar replacement and unrolling. The second part, feature calculation, will be optimized by putting to use information about the data that we will be working with and eliminating any redundancies in the code. We will also apply the practices of unrolling and scalar replacement. With these optimizations in place, we will show that we reduce the runtime by a20% in the co-occurrence construction phase and by a factor of20 in the feature calculation phase of computation.

Data-parallel programming languages are an important component in today's parallel computing landscape. Among those are domain-specific languages like shading languages in graphics (HLSL, GLSL, RenderMan, etc.) and "general-purpose" languages like CUDA or OpenCL. Current implementations of those languages on CPUs solely rely on multi-threading to implement parallelism and ignore the additional intra-core parallelism provided by the SIMD instruction set of those processors (like Intel's SSE and the upcoming AVX or Larrabee instruction sets). In this paper, we discuss several aspects of implementing dataparallel languages on machines with SIMD instruction sets. Our main contribution is a language- and platform-independent code transformation that performs whole-function vectorization on low-level intermediate code given by a control flow graph in SSA form. We evaluate our technique in two scenarios: First, incorporated in a compiler for a domain-specific language used in realtime ray tracing. Second, in a stand-alone OpenCL driver. We observe average speedup factors of 3.9 for the ray tracer and factors between 0.6 and 5.2 for different OpenCL kernels.

Stereo matching, a key element towards extracting depth information from stereo images, is widely used in several embedded consumer electronic and multimedia systems. Such systems demand high processing performance and accurate depth perception, while their deployment in embedded and mobile environments implies that cost, energy and memory overheads need to be minimized. Hardware acceleration has been demonstrated in efficient embedded stereo vision systems. To this end, this paper presents the design and implementation of a hardware-based stereo matching system able to provide high accuracy and concurrently high performance for embedded vision devices, which are associated with limited hardware and power budget. We first implemented a compact and efficient design of the guided image filter, an edge-preserving filter, which reduces the hardware complexity of the implemented stereo algorithm, while at the same time maintains high-quality results. The guided filter design is used in two parts of the stereo matching pipeline, showing that it can simplify the hardware complexity of the Adaptive Support Weight aggregation step, and efficiently enable a powerful disparity refinement unit, which improves matching accuracy, even though cost aggregation is based on simple, fixed support strategies. We implemented several variants of our design on a Kintex-7 FPGA board, which was able to process HD video (1,280 × 720) in real-time (60 fps), using ~57.5k and ~71k of the FPGA's logic (CLB) and register resources, respectively. Additionally, the proposed stereo matching design delivers leading accuracy when compared to state-of-the-art hardware implementations based on the Middlebury evaluation metrics (at least 1.5 percent less bad matching pixels).

Modern graphics hardware architectures excel at compute-intensive tasks such as ray-triangle intersection, making them attractive target platforms for raytracing. To date, most GPU-based raytracers have relied upon uniform grid acceleration structures. In contrast, the kd-tree has gained widespread use in CPU-based raytracers and is regarded as the best general-purpose acceleration structure. We demonstrate two kd-tree traversal algorithms suitable for GPU implementation and integrate them into a streaming raytracer. We show that for scenes with many objects at different scales, our kd-tree algorithms are up to 8 times faster than a uniform grid. In addition, we identify load balancing and input data recirculation as two fundamental sources of inefficiency when raytracing on current graphics hardware.

Design and Optimization of OpenFOAM-based CFD Applications for Modern Hybrid and Heterogeneous HPC Platforms Amani AlOnazi The progress of high performance computing platforms is dramatic, and most of the simulations carried out on these platforms result in improvements on one level, yet expose shortcomings of current CFD packages capabilities. Therefore, hardwareaware design and optimizations are crucial towards exploiting modern computing resources. This thesis proposes optimizations aimed at accelerating numerical simulations, which are illustrated in OpenFOAM solvers. A hybrid MPI and GPGPU parallel conjugate gradient linear solver has been designed and implemented to solve the sparse linear algebraic kernel that derives from two CFD solver: icoFoam, which is an incompressible flow solver, and laplacianFoam, which solves the Poisson equation, for e.g., thermal diffusion. A load-balancing step is applied using heterogeneous decomposition, which decomposes the computations taking into account the performance of each computing device and seeking to minimize communication. In addition, we implemented the recently developed pipeline conjugate gradient as an algorithmic improvement, and parallelized it using MPI, GPGPU, and a hybrid technique. While many questions of ultimately attainable per node performance and multi-node scaling remain, the experimental results show that the hybrid implementation of both solvers significantly outperforms state-of-the-art implementations of a widely used open source package.

Recent advances in computing have led to an explosion in the amount of data being generated. Processing the ever-growing data in a timely manner has made throughput computing an important aspect for emerging applications. Our analysis of a set of important throughput computing kernels shows that there is an ample amount of parallelism in these kernels which makes them suitable for today's multi-core CPUs and GPUs. In the past few years there have been many studies claiming GPUs deliver substantial speedups (between 10X and 1000X) over multi-core CPUs on these kernels. To understand where such large performance difference comes from, we perform a rigorous performance analysis and find that after applying optimizations appropriate for both CPUs and GPUs the performance gap between an Nvidia GTX280 processor and the Intel Core i7-960 processor narrows to only 2.5x on average. In this paper, we discuss optimization techniques for both CPU and GPU, analyze what architecture features contributed to performance differences between the two architectures, and recommend a set of architectural features which provide significant improvement in architectural efficiency for throughput kernels.

We describe a system to detect objects in three-dimensional space using video and inertial sensors (accelerometer and gyrometer), ubiquitous in modern mobile platforms from phones to drones. Inertials afford the ability to impose class-specific scale priors for objects, and provide a global orientation reference. A minimal sufficient representation, the posterior of semantic (identity) and syntactic (pose) attributes of objects in space, can be decomposed into a geometric term, which can be maintained by a localization-and-mapping filter, and a likelihood function, which can be approximated by a discriminatively-trained convolutional neural network The resulting system can process the video stream causally in real time, and provides a representation of objects in the scene that is persistent: Confidence in the presence of objects grows with evidence, and objects previously seen are kept in memory even when temporarily occluded, with their return into view automatically predicted to prime re-detection.

We introduce a parallel GPU implementation of the Simple Linear Iterative Clustering (SLIC) superpixel segmentation. Using a single graphic card, our implementation achieves speedups of up to 83× from the standard sequential implementation. Our implementation is fully compatible with the standard sequential implementation and the software is now available online and is open source.

Convolutional neural networks (CNNs) excel in various computer vision related tasks but are extremely computationally intensive and power hungry to run on mobile and embedded devices. Recent pruning techniques can reduce the computation and memory requirements of CNNs, but a costly retraining step is needed to restore the classification accuracy of the pruned model. In this paper, we present evidence that when only a subset of the classes need to be classified, we could prune a model and achieve reasonable classification accuracy without retraining. The resulting specialist model will require less energy and time to run than the original full model. To compensate for the pruning, we take advantage of the redundancy among filters and class-specific features. We show that even simple methods such as replacing channels with mean or with the most correlated channel can boost the accuracy of the pruned model to reasonable levels.


Question: Computer Vision Accelerators utilizing OpenCL GPGPU Co-Processing for mobile systems.

This paper investigates the acceleration of computer vision algorithms on mobile devices through the application of OpenCL framework for GPGPU (General-Purpose Computing on Graphics Processing Units) co-processing. With the advent of heterogeneous programming models like OpenCL, mobile devices now have the capability to perform GPGPU tasks, paving the way for the execution of complex computer vision algorithms on these platforms. As a practical demonstration, an exemplar-based inpainting algorithm for object removal is optimized and executed on a mobile GPU using OpenCL in this study. The authors delve into the process of identifying and exploiting parallelism within the algorithm, alongside detailing various optimization techniques tailored for mobile GPUs. The experimental findings highlight the effectiveness of the optimization strategies, notably reducing the computational time and making resource-intensive computer vision tasks viable for mobile devices. It is noteworthy that this work represents the pioneering effort in implementing GPGPU computing using OpenCL on mobile GPUs, as per the authors' knowledge.

Next generations of high-resolution automotive radar sensors rely on powerful, real-time capable processing units. High sampling rates, large antenna arrays as well as hard real-time constraints require the use of both parallel architectures and high-bandwidth memory interfaces. This paper presents a novel architecture of a FPGA-based multiple-input multiple-output (MIMO) radar sensor processing unit. Sampling rates up to 250 MSPS and a maximum of 16 parallel receiving channels can be used, resulting in a maximum data rate of 56GBit/s. The processing chain consists of a flexible FIR filter, a range-Doppler processing unit using windowed FFTs and an ordered statistics constant-false-alarm-rate (OS-CFAR) unit for optimal target detection and data reduction. The realized target system is composed of a Virtex7-FPGA and a 1GByte SDRAM memory. The resource usage of the FPGA implementation is analyzed in order to provide estimations for future system designs. Finally, the resulting performance of the system is verified in connection with a prototype MIMO radar front-end. High-resolution measurements of moving scenes have been carried out to validate the correct operation of the system.

The efficient processing of video streams is a key component in many emerging Internet of Things (IoT) and edge applications, such as Virtual and Augmented Reality (V/AR) and self-driving cars. These applications require real-time high-throughput video processing. This can be attained via a collaborative processing model between the edge and the cloud—called an Edge-Cloud model. To this end, many approaches were proposed to optimize the latency and bandwidth consumption of Edge-Cloud video processing, especially for Neural Networks (NN)-based methods. In this demonstration. We investigate the efficiency of these NN techniques, how they can be combined, and whether combining them leads to better performance. Our demonstration invites participants to experiment with the various NN techniques, combine them, and observe how the underlying NN changes with different techniques and how these changes affect accuracy, latency and bandwidth consumption. PVLDB Reference Format: Philipp M. Grulich and Faisal Nawab. Collaborative Edge and Cloud Neural Networks for Real-Time Video Processing. PVLDB, 11 (12): 2046-2049, 2018. DOI: https://doi.org/10.14778/3229863.3236256

Modern graphics hardware architectures excel at compute-intensive tasks such as ray-triangle intersection, making them attractive target platforms for raytracing. To date, most GPU-based raytracers have relied upon uniform grid acceleration structures. In contrast, the kd-tree has gained widespread use in CPU-based raytracers and is regarded as the best general-purpose acceleration structure. We demonstrate two kd-tree traversal algorithms suitable for GPU implementation and integrate them into a streaming raytracer. We show that for scenes with many objects at different scales, our kd-tree algorithms are up to 8 times faster than a uniform grid. In addition, we identify load balancing and input data recirculation as two fundamental sources of inefficiency when raytracing on current graphics hardware.

In the recent years, the Graphics Processing Units (GPUs) have gained popularity for general purpose applications, immensely outperforming traditional optimized CPU based implementations. A class of such applications implemented on GPUs to achieve faster execution than CPUs include cryptographic techniques like the Advanced Encryption Standard (AES) which is a widely deployed symmetric encryption/decryption scheme in various electronic communication domains. With the drastic advancements in electronic communication technology, and growth in the user space, the size of data exchanged electronically has increased substantially. So, such cryptographic techniques become a bottleneck to fast transfers of information. In this work, we implement the AES-128 ECB Encryption on two of the recent and advanced GPUs (NVIDIA Quadro FX 7000 and Tesla K20c) with different memory usage schemes and varying input plaintext sizes and patterns. We obtained a speedup of up to 87x against an advanced CPU (Intel Xeon X5690) based implementation. Moreover, our experiments reveal that the different degrees of pattern repetitions in input plaintext affect the encryption performance on GPU.

In this paper, we introduce the DEEP-SEE FACE framework, an assistive device designed to improve cognition, interaction, and communication of visually impaired (VI) people in social encounters. The proposed approach jointly exploits computer vision algorithms (region proposal networks, ATLAS tracking and global, and low-level image descriptors) and deep convolutional neural networks in order to detect, track, and recognize, in real-time, various persons existent in the video streams. The major contribution of the paper concerns a global, fixed-size face representation that takes into the account of various video frames while remaining independent of the length of the image sequence. To this purpose, we introduce an effective weight adaptation scheme that is able to determine the relevance assigned to each face instance, depending on the frame degree of motion/camera blur, scale variation, and compression artifacts. Another relevant contribution involves a hard negative mining stage that helps us differentiating between known and unknown face identities. The experimental results, carried out on a large-scale data set, validate the proposed methodology with an average accuracy and recognition rates superior to 92%. When tested in real life, indoor/outdoor scenarios, the DEEP-SEE FACE prototype proves to be effective and easy to use, allowing the VI people to access visual information during social events.

The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realization of fast and secure implementations of cryptographic algorithms. Under this work, such an implementation has been done for Advanced Encryption Standard (AES) on fast, efficient and low power Field Programmable Gate Arrays (FPGAs) whereby computational intensive cryptographic processes are offloaded from the main processor thus results in achieving highspeed secure wireless connectivity. The dedicated resources of Spartan-3 FPGAs have been effectively utilized to develop wider logic function which minimizes the critical paths by confining logic to single Configurable Logic Block (CLB), thus improving the performance, density and power consumption of the design. The resultant design consumes only 4 Block RAMs and 487 Slices to fit both AES cores and its key scheduling.

The recent trend towards accelerator-centric architectures has renewed the need for demonstrating new research ideas in prototype systems with custom chips. Unfortunately, building such research prototypes is tremendously challenging, but the emerging RISC-V open-source software and hardware ecosystem can partly address this challenge by reducing design, implementation, and verification effort. This paper briefly describes the Celerity system-on-chip (SoC), a 5× 5mm 385M-transistor chip in TSMC 16 nm, which uses a tiered parallel accelerator fabric to improve both the performance and energy efficiency of embedded applications. The Celerity SoC includes five RV64G cores, a 496-core RV32IM tiled manycore processor, and a complex BNN (binarized neural network) accelerator implemented as a Rocket custom co-processor (RoCC). We describe our experiences using the RISC-V ecosystem to build Celerity, and highlight both key benefits and challenges in leveraging the RISCV instruction set, RISC-V software stack, RISC-V processor and memory system generators, RISC-V on-chip network interfaces, RISC-V verification suite, and RISC-V system-level hardware infrastructure. The RISC-V ecosystem played an important role in enabling a team of junior graduate students to design and tapeout the highest-performance RISC-V SoC to date in just nine months.

The idea described in this paper is to use the built-in cameras of consumer mobile phones as sensors for 2-dimensional visual codes. Such codes can be attached to physical objects in order to retrieve object-related information and functionality. They are also suitable for display on electronic screens. The proposed visual code system allows the simultaneous detection of multiple codes, introduces a position-independent coordinate system, and provides the phone’s orientation as a parameter. The ability to detect objects in the user’s vicinity offers a natural way of interaction and strengthens the role of mobile phones in a large number of application scenarios. We describe the hardware requirements, the design of a suitable visual code, a lightweight recognition algorithm, and present some example applications.

We present a mobile vision system for multi-person tracking in busy environments. Specifically, the system integrates continuous visual odometry computation with tracking-by-detection in order to track pedestrians in spite of frequent occlusions and egomotion of the camera rig. To achieve reliable performance under real-world conditions, it has long been advocated to extract and combine as much visual information as possible. We propose a way to closely integrate the vision modules for visual odometry, pedestrian detection, depth estimation, and tracking. The integration naturally leads to several cognitive feedback loops between the modules. Among others, we propose a novel feedback connection from the object detector to visual odometry which utilizes the semantic knowledge of detection to stabilize localization. Feedback loops always carry the danger that erroneous feedback from one module is amplified and causes the entire system to become instable. We therefore incorporate automatic failure detection and recovery, allowing the system to continue when a module becomes unreliable. The approach is experimentally evaluated on several long and difficult video sequences from busy inner-city locations. Our results show that the proposed integration makes it possible to deliver stable tracking performance in scenes of previously infeasible complexity.

Support Vector Machine (SVM) is a common classifier used for efficient classification with high accuracy. SVM shows high accuracy for classifying melanoma (skin cancer) clinical images within computer-aided diagnosis systems used by skin cancer specialists to detect melanoma early and save lives. We aim to develop a medical low-cost handheld device that runs a real-time embedded SVM-based diagnosis system for use in primary care for early detection of melanoma. In this paper, an optimized SVM classifier is implemented onto a recent FPGA platform using the latest design methodology to be embedded into the proposed device for realizing online efficient melanoma detection on a single system on chip/device. The hardware implementation results demonstrate a high classification accuracy of 97.9% and a significant acceleration factor of 26 from equivalent software implementation on an embedded processor, with 34% of resources utilization and 2 watts for power consumption. Consequently, the implemented system meets crucial embedded systems constraints of high performance and low cost, resources utilization and power consumption, while achieving high classification accuracy.


Question: Computer Vision Accelerators for Mobile Systems utilizing OpenCL GPGPU Co-Processing.

This paper introduces a high-performance and energy-efficient implementation of the Scale-Invariant Feature Transform (SIFT) algorithm optimized for mobile GPUs. The growing demand for robust feature detection in applications like augmented reality necessitates the processing of high frame rates. Our solution leverages the graphics processing unit (GPU) present in mobile devices to significantly enhance the SIFT algorithm's performance. Recognizing the limitations of conventional GPU methods on mobile hardware, we have devised a heterogeneous dataflow approach. This strategy involves carefully dividing the computational tasks, compressing data for efficient memory transfers, and addressing the specific challenges posed by mobile GPUs. As a result, our implementation achieves a remarkable speedup of 4-7 times compared to an optimized CPU version and a 6.4 times improvement over a previously published GPU implementation. Moreover, our method reduces energy consumption by 87 percent per image, ensuring near-real-time feature detection without compromising on the algorithm's original accuracy. This advancement paves the way for more sophisticated and power-efficient computer vision applications in mobile systems.

We introduce and analyze the computational aspects of a hybrid CPU/GPU implementation of the Asynchronous Advantage Actor-Critic (A3C) algorithm, currently the state-of-the-art method in reinforcement learning for various gaming tasks. Our analysis concentrates on the critical aspects to leverage the GPU’s computational power, including the introduction of a system of queues and a dynamic scheduling strategy, potentially helpful for other asynchronous algorithms as well. We also show the potential for the use of larger DNN models on a GPU. Our TensorFlow implementation achieves a significant speed up compared to our CPU-only implementation, and it will be made publicly available to other researchers.

Feature Extraction is a method of capturing visual content of images for indexing & retrieval. Primitive or low level image features can be either general features, such as extraction of color, texture and shape or domain specific features. This paper presents an application of gray level co-occurrence matrix (GLCM) to extract second order statistical texture features for motion estimation of images. The Four features namely, Angular Second Moment, Correlation, Inverse Difference Moment, and Entropy are computed using Xilinx FPGA. The results show that these texture features have high discrimination accuracy, requires less computation time and hence efficiently used for real time Pattern recognition applications.

Stereo matching, a key element towards extracting depth information from stereo images, is widely used in several embedded consumer electronic and multimedia systems. Such systems demand high processing performance and accurate depth perception, while their deployment in embedded and mobile environments implies that cost, energy and memory overheads need to be minimized. Hardware acceleration has been demonstrated in efficient embedded stereo vision systems. To this end, this paper presents the design and implementation of a hardware-based stereo matching system able to provide high accuracy and concurrently high performance for embedded vision devices, which are associated with limited hardware and power budget. We first implemented a compact and efficient design of the guided image filter, an edge-preserving filter, which reduces the hardware complexity of the implemented stereo algorithm, while at the same time maintains high-quality results. The guided filter design is used in two parts of the stereo matching pipeline, showing that it can simplify the hardware complexity of the Adaptive Support Weight aggregation step, and efficiently enable a powerful disparity refinement unit, which improves matching accuracy, even though cost aggregation is based on simple, fixed support strategies. We implemented several variants of our design on a Kintex-7 FPGA board, which was able to process HD video (1,280 × 720) in real-time (60 fps), using ~57.5k and ~71k of the FPGA's logic (CLB) and register resources, respectively. Additionally, the proposed stereo matching design delivers leading accuracy when compared to state-of-the-art hardware implementations based on the Middlebury evaluation metrics (at least 1.5 percent less bad matching pixels).

VLFeat is an open and portable library of computer vision algorithms. It aims at facilitating fast prototyping and reproducible research for computer vision scientists and students. It includes rigorous implementations of common building blocks such as feature detectors, feature extractors, (hierarchical) k-means clustering, randomized kd-tree matching, and super-pixelization. The source code and interfaces are fully documented. The library integrates directly with MATLAB, a popular language for computer vision research.

With the rapid proliferation of smartphones and tablet computers, search has moved beyond text to other modalities like images and voice. For many applications like Fashion, visual search offers a compelling interface that can capture stylistic visual elements beyond color and pattern that cannot be as easily described using text. However, extracting and matching such attributes remains an extremely challenging task due to high variability and deformability of clothing items. In this paper, we propose a fine-grained learning model and multimedia retrieval framework to address this problem. First, an attribute vocabulary is constructed using human annotations obtained on a novel finegrained clothing dataset. This vocabulary is then used to train a fine-grained visual recognition system for clothing styles. We report benchmark recognition and retrieval results on Women’s Fashion Coat Dataset and illustrate potential mobile applications for attribute-based multimedia retrieval of clothing items and image annotation.

Modern personal computers have embraced increasingly powerful Graphics Processing Units (GPUs). Recently, GPU-based graphics acceleration in web apps (i.e., applications running inside a web browser) has become popular. WebGL is the main effort to provide OpenGL-like graphics for web apps and it is currently used in 53% of the top-100 websites. Unfortunately, WebGL has posed serious security concerns as several attack vectors have been demonstrated through WebGL. Web browsers» solutions to these attacks have been reactive: discovered vulnerabilities have been patched and new runtime security checks have been added. Unfortunately, this approach leaves the system vulnerable to zero-day vulnerability exploits, especially given the large size of the Trusted Computing Base of the graphics plane. We present Sugar, a novel operating system solution that enhances the security of GPU acceleration for web apps by design. The key idea behind Sugar is using a dedicated virtual graphics plane for a web app by leveraging modern GPU virtualization solutions. A virtual graphics plane consists of a dedicated virtual GPU (or vGPU) as well as all the software graphics stack (including the device driver). Sugar enhances the system security since a virtual graphics plane is fully isolated from the rest of the system. Despite GPU virtualization overhead, we show that Sugar achieves high performance. Moreover, unlike current systems, Sugar is able to use two underlying physical GPUs, when available, to co-render the User Interface (UI): one GPU is used to provide virtual graphics planes for web apps and the other to provide the primary graphics plane for the rest of the system. Such a design not only provides strong security guarantees, it also provides enhanced performance isolation.

Smith-Waterman is a dynamic programming algorithm that plays a key role in the modern genomics pipeline as it is guaranteed to find the optimal local alignment between two strings of data. The state of the art presents many hardware acceleration solutions that have been implemented in order to exploit the high degree of parallelism available in this algorithm. The majority of these implementations use heuristics to increase the performance of the system at the expense of the accuracy of the result. In this work, we present an implementation of the pure version of the algorithm. We include the key architectural optimizations to achieve highest possible performance for a given platform and leverage the Berkeley roofline model to track the performance and guide the optimizations. To achieve scalability, our custom design comprises of systolic arrays, data compression features and shift registers, while a custom port mapping strategy aims to maximize performance. Our designs are built leveraging an OpenCL-based design entry, namely Xilinx SDAccel, in conjunction with a Xilinx Virtex 7 and Kintex Ultrascale platform. Our final design achieves a performance of 42.47 GCUPS (giga cell updates per second) with an energy efficiency of 1.6988 GCUPS/W. This represents an improvement of 1.72x in performance and energy efficiency over previously published FPGA implementations and 8.49x better in energy efficiency over comparable GPU implementations.

More and more real-time applications need to handle dynamic continuous queries over streaming data of high density. Conventional data and query indexing approaches generally do not apply for excessive costs in either maintenance or space. Aiming at these problems, this study first proposes a new indexing structure by fusing an adaptive cell and KDB-tree, namely CKDB-tree. A cell-tree indexing approach has been developed on the basis of the CKDB-tree that supports dynamic continuous queries. The approach significantly reduces the space costs and scales well with the increasing data size. Towards providing a scalable solution to filtering massive steaming data, this study has explored the feasibility to utilize the contemporary general-purpose computing on the graphics processing unit (GPGPU). The CKDB-tree-based approach has been extended to operate on both the CPU (host) and the GPU (device). The GPGPU-aided approach performs query indexing on the host while perform streaming data filtering on the device in a massively parallel manner. The two heterogeneous tasks execute in parallel and the latency of streaming data transfer between the host and the device is hidden. The experimental results indicate that (1) CKDB-tree can reduce the space cost comparing to the cell-based indexing structure by 60 percent on average, (2) the approach upon the CKDB-tree outperforms the traditional counterparts upon the KDB-tree by 66, 75 and 79 percent in average for uniform, skewed and hyper-skewed data in terms of update costs, and (3) the GPGPU-aided approach greatly improves the approach upon the CKDB-tree with the support of only a single Kepler GPU, and it provides real-time filtering of streaming data with 2.5M data tuples per second. The massively parallel computing technology exhibits great potentials in streaming data monitoring.

Convolutional neural network (CNN) is the state-of-the-art deep learning approach employed in various applications. Real-time CNN implementations in resource limited embedded systems are becoming highly desired recently. To ensure the programmable flexibility and shorten the development period, field programmable gate array is appropriate to implement the CNN models. However, the limited bandwidth and on-chip memory storage are the bottlenecks of the CNN acceleration. In this paper, we propose efficient hardware architectures to accelerate deep CNN models. The theoretical derivation of parallel fast finite impulse response algorithm (FFA) is introduced. Based on FFAs, the corresponding fast convolution units (FCUs) are developed for the computation of convolutions in the CNN models. Novel data storage and reuse schemes are proposed, where all intermediate pixels are stored on-chip and the bandwidth requirement is reduced. We choose one of the largest and most accurate networks, VGG16, and implement it on Xilinx Zynq ZC706 and Virtex VC707 boards, respectively. We achieve the top-5 accuracy of 86.25% using an equal distance non-uniform quantization method. It is estimated that the average performances are 316.23 GOP/s under 172-MHz working frequency on Xilinx ZC706 and 1250.21 GOP/s under 170-MHz working frequency on VC707, respectively. In brief, the proposed design outperforms the existing works significantly, in particular, surpassing related designs by more than two times in terms of resource efficiency.

We present Gazture, a light-weight gaze based real-time gesture control system on commercial tablets. Unlike existing approaches that require dedicated hardware (e.g., high resolution camera), high computation overhead (powerful CPU) or specific user behavior (keeping head steady), Gazture provides gesture recognition based on easy-to-control user gaze input with a small overhead. To achieve this goal, Gazture incorporates a two-layer structure: The first layer focuses on real-time gaze estimation with acceptable tracking accuracy while incurring a small overhead. The second layer implements a robust gesture recognition algorithm while compensating gaze estimation error. To address user posture change while using mobile device, we design a online transfer function based method to convert current eye features into corresponding eye features in reference posture, which then facilitates efficient gaze position estimation. We implement Gazture on Lenovo Tab3 8 Plus tablet with Android 6.0.1, and evaluate its performance in different scenarios. The evaluation results show that Gazture can achieve a high accuracy in gesture recognition while incurring a low overhead.


Question: OpenCL GPGPU co-processing-based computer vision accelerators for mobile systems.

This paper introduces a novel technique for texture synthesis that eschews parametric models in favor of a non-parametric approach. The texture synthesis procedure is initiated from a seed and progressively expands by adding pixels one by one. Under the assumption of a Markov random field model, the conditional probability of each new pixel, given the context of its already synthesized neighbors, is estimated. This estimation is achieved by querying the source image to locate neighborhoods with similar characteristics. The level of randomness in the synthesis is governed by a single parameter that is directly linked to perceptual intuition. The technique prioritizes the preservation of local structure, resulting in high-quality synthesis for a broad spectrum of textures, both synthetic and derived from real-world scenarios.

Improving the efficiency of edge detection in embedded applications, such as UAV control, is critical for reducing system cost and power dissipation. Field programmable gate arrays (FPGA) are a good platform for making improvements because of their specialised internal structure. However, current FPGA edge detectors do not exploit this structure well. A new edge detection architecture is proposed that is better optimised for FPGAs. The basis of the architecture is the Sobel edge kernels that are shown to be the most suitable because of their separability and absence of multiplications. Edge intensities are calculated with a new 4:2 compressor that consists of two custom-designed 3:2 compressors. Addition speed is increased by breaking carry propagation chains with look-ahead logic. Testing of the design showed it gives a 28% increase in speed and 4.4% reduction in area over previous equivalent designs, which demonstrated that it will lower the cost of edge detection systems, dissipate less power and still maintain highspeed control. Keywords—edge detection; FPGA; compressor; low-cost; UAV

The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realization of fast and secure implementations of cryptographic algorithms. Under this work, such an implementation has been done for Advanced Encryption Standard (AES) on fast, efficient and low power Field Programmable Gate Arrays (FPGAs) whereby computational intensive cryptographic processes are offloaded from the main processor thus results in achieving highspeed secure wireless connectivity. The dedicated resources of Spartan-3 FPGAs have been effectively utilized to develop wider logic function which minimizes the critical paths by confining logic to single Configurable Logic Block (CLB), thus improving the performance, density and power consumption of the design. The resultant design consumes only 4 Block RAMs and 487 Slices to fit both AES cores and its key scheduling.

The 3-D reconstruction involves the construction of a 3-D model from a set of images. The 3-D reconstruction has varied uses that include 3-D printing, the generation of 3-D models that can be shared through social media, and more. The 3-D reconstruction involves complex computations in mobile phones that must determine the pose estimation. The pose estimation involves the process of transforming a 2-D object into 3-D space. Once the pose estimation is done, then the mesh generation is performed using the graphics processing unit. This helps render the 3-D object. The competitive advantages of using hardware processors are to accelerate the intensive computation using graphics processors and digital signal processors. The stated problem that this technical paper addresses is the need for a reliable automated test for the 3-D reconstruction feature. The solution to this problem involved the design and development of an automated test system using a programmable robotic arm and rotor for precisely testing the quality of 3-D reconstruction features. The 3-D reconstruction testing involves using a robotic arm lab to accurately test the algorithmic integrity and end-to-end validation of the generated 3-D models. The robotic arm can move the hardware at different panning speeds, specific angles, fixed distances from the object, and more. The ability to reproduce the scanning at a fixed distance and the same panning speed helps to generate test results that can be benchmarked by different software builds. The 3-D reconstruction also requires a depth sensor to be mounted onto the device under examination. We use this robotic arm lab for functional, high performance, and stable validation of the 3-D reconstruction feature. This paper addresses the computer vision use case testing for 3-D reconstruction features and how we have used the robotic arm lab for automating these use cases.

Convolutional neural networks (CNNs) have gained great success in various computer vision applications. However, state-of-the-art CNN models are computation-intensive and hence are mainly processed on high performance processors like server CPUs and GPUs. Owing to the advantages of high performance, energy efficiency and reconfigurability, Field-Programmable Gate Arrays (FPGAs) have been widely explored as CNN accelerators. In this paper, we propose parallel structures to exploit the inherent parallelism and efficient computation units to perform operations in convolutional and fully-connected layers. Further, an automatic generator is proposed to generate Verilog HDL source code automatically according to high-level hardware description language. Execution time, DSP consumption and performance are analytically modeled based on some critical design variables. We demonstrate the automatic methodology by implementing two representative CNNs (LeNet and AlexNet) and evaluate the execution time models by comparing estimated and measured values. Our results show that the proposed automatic methodology yields hardware design with good performance and saves much developing round time.

Convolutional Neural Networks (CNN) are verycomputation-intensive. Recently, a lot of CNN accelerators based on the CNN intrinsic parallelism are proposed. However, we observed that there is a big mismatch between the parallel types supported by computing engine and the dominant parallel types of CNN workloads. This mismatch seriously degrades resource utilization of existing accelerators. In this paper, we propose aflexible dataflow architecture (FlexFlow) that can leverage the complementary effects among feature map, neuron, and synapse parallelism to mitigate the mismatch. We evaluated our design with six typical practical workloads, it acquires 2-10x performance speedup and 2.5-10x power efficiency improvement compared with three state-of-the-art accelerator architectures. Meanwhile, FlexFlow is highly scalable with growing computing engine scale.

Caffe provides multimedia scientists and practitioners with a clean and modifiable framework for state-of-the-art deep learning algorithms and a collection of reference models. The framework is a BSD-licensed C++ library with Python and MATLAB bindings for training and deploying general-purpose convolutional neural networks and other deep models efficiently on commodity architectures. Caffe fits industry and internet-scale media needs by CUDA GPU computation, processing over 40 million images a day on a single K40 or Titan GPU (approx 2 ms per image). By separating model representation from actual implementation, Caffe allows experimentation and seamless switching among platforms for ease of development and deployment from prototyping machines to cloud environments.
 Caffe is maintained and developed by the Berkeley Vision and Learning Center (BVLC) with the help of an active community of contributors on GitHub. It powers ongoing research projects, large-scale industrial applications, and startup prototypes in vision, speech, and multimedia.

It is our aim in this research to optimize the numerical computation of the Haralick texture features [1] that consists of two steps. Haralick texture features are used as a primary component to discern between different protein structures in microscopic bio-images. The first of these two parts is the construction of the co-occurrence matrix. Upon completion of this implementation, we will attempt to optimize the code using a novel recursive blocking algorithm. We will also use standard practices of optimizing code such as scalar replacement and unrolling. The second part, feature calculation, will be optimized by putting to use information about the data that we will be working with and eliminating any redundancies in the code. We will also apply the practices of unrolling and scalar replacement. With these optimizations in place, we will show that we reduce the runtime by a20% in the co-occurrence construction phase and by a factor of20 in the feature calculation phase of computation.

GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a challenge for programmers. Furthermore, optimizing for power consumption is even more difficult. Unfortunately, as a result of the high number of processors, the power consumption of many-core processors such as GPUs has increased significantly.
 Hence, in this paper, we propose an integrated power and performance (IPP) prediction model for a GPU architecture to predict the optimal number of active processors for a given application. The basic intuition is that when an application reaches the peak memory bandwidth, using more cores does not result in performance improvement.
 We develop an empirical power model for the GPU. Unlike most previous models, which require measured execution times, hardware performance counters, or architectural simulations, IPP predicts execution times to calculate dynamic power events. We then use the outcome of IPP to control the number of running cores. We also model the increases in power consumption that resulted from the increases in temperature.
 With the predicted optimal number of active cores, we show that we can save up to 22.09%of runtime GPU energy consumption and on average 10.99% of that for the five memory bandwidth-limited benchmarks.

In this article, we describe how to ease memory management between a Central Processing Unit (CPU) and one or multiple discrete Graphic Processing Units (GPUs) by architecting a novel hardware-based Unified Memory Hierarchy (UMH). Adopting UMH, a GPU accesses the CPU memory only if it does not find its required data in the directories associated with its high-bandwidth memory, or the NMOESI coherency protocol limits the access to that data. Using UMH with NMOESI improves performance of a CPU-multiGPU system by at least 1.92 × in comparison to alternative software-based approaches. It also allows the CPU to access GPUs modified data by at least 13 × faster.

Convolutional neural network (CNN) has been widely employed for image recognition because it can achieve high accuracy by emulating behavior of optic nerves in living creatures. Recently, rapid growth of modern applications based on deep learning algorithms has further improved research and implementations. Especially, various accelerators for deep CNN have been proposed based on FPGA platform because it has advantages of high performance, reconfigurability, and fast development round, etc. Although current FPGA accelerators have demonstrated better performance over generic processors, the accelerator design space has not been well exploited. One critical problem is that the computation throughput may not well match the memory bandwidth provided an FPGA platform. Consequently, existing approaches cannot achieve best performance due to under-utilization of either logic resource or memory bandwidth. At the same time, the increasing complexity and scalability of deep learning applications aggravate this problem. In order to overcome this problem, we propose an analytical design scheme using the roofline model. For any solution of a CNN design, we quantitatively analyze its computing throughput and required memory bandwidth using various optimization techniques, such as loop tiling and transformation. Then, with the help of rooine model, we can identify the solution with best performance and lowest FPGA resource requirement. As a case study, we implement a CNN accelerator on a VC707 FPGA board and compare it to previous approaches. Our implementation achieves a peak performance of 61.62 GFLOPS under 100MHz working frequency, which outperform previous approaches significantly.


Question: OpenCL GPGPU co-processing based computer vision accelerators for mobile systems.

This paper introduces an innovative algorithm for high-quality texture synthesis that significantly outperforms existing methods in terms of efficiency. Addressing the ongoing challenge of creating algorithms that are both rapid and produce superior outcomes in computer graphics, vision, and image processing, our solution requires merely a sample texture as input, making it user-friendly. The generated textures boast a perceived quality that surpasses or matches previous techniques, yet the process is accelerated by a factor of one hundred, opening up new applications where texture synthesis was previously deemed impractical. Specifically, we have successfully applied this algorithm to tasks such as image editing with constrained synthesis and the generation of textures over time. Our method is rooted in Markov Random Field texture models, utilizing a deterministic searching process for texture generation. A crucial element of our acceleration strategy is the employment of tree-structured vector quantization, which optimizes the synthesis procedure.

**Question**: Evaluating the Performance of Blockchain Consensus Algorithms in Distributed Ledger Systems

**Documents**: An analysis of the performance of different blockchain consensus algorithms
The performance of blockchain systems is heavily influenced by the consensus algorithm used. In this paper, we present an analysis of several popular blockchain consensus algorithms, including Proof of Work (PoW), Proof of Stake (PoS), Delegated Proof of Stake (DPoS), and Practical Byzantine Fault Tolerance (PBFT). We compare these algorithms based on several performance metrics such as transaction throughput, latency, and energy consumption. Our results show that PoW, the consensus algorithm used by Bitcoin, has the lowest transaction throughput and the highest energy consumption. PoS, on the other hand, has a significantly higher transaction throughput and lower energy consumption. DPoS and PBFT have the highest transaction throughput and lowest latency among the algorithms we analyzed. However, DPoS is vulnerable to centralization, while PBFT is not suitable for large-scale networks due to its high communication overhead. Our analysis provides insights into the trade-offs between different blockchain consensus algorithms and can help in selecting the appropriate algorithm for a given application.

**Similar Documents**: This study delves into the comparative analysis of prominent blockchain consensus algorithms, evaluating their performance in distributed ledger systems. Among the algorithms scrutinized are Proof of Work (PoW), Proof of Stake (PoS), Delegated Proof of Stake (DPoS), and Practical Byzantine Fault Tolerance (PBFT). We assess these mechanisms based on critical performance indicators, including transaction throughput, latency, and energy efficiency. Our findings reveal that PoW, famously utilized by Bitcoin, exhibits the lowest transaction throughput and

The graphics processors (GPUs) have recently emerged as a low-cost alternative for parallel programming. Since modern GPUs have great computational power as well as high memory bandwidth, running ray tracing on them has been an active field of research in computer graphics in recent years. Furthermore, the introduction of CUDA, a novel GPGPU architecture, has removed several limitations that the traditional GPU-based ray tracing suffered. In this paper, an implementation of high performance CUDA ray tracing is demonstrated. We focus on the performance and show how our design choices in various optimization lead to an implementation that outperforms the previous works. For reasonably complex scenes with simple shading, our implementation achieves the performance of 30 to 43 million traced rays per second. Our implementation also includes the effects of recursive specular reflection and refraction, which were less discussed in previous GPU-based ray tracing works.

Modern graphics hardware architectures excel at compute-intensive tasks such as ray-triangle intersection, making them attractive target platforms for raytracing. To date, most GPU-based raytracers have relied upon uniform grid acceleration structures. In contrast, the kd-tree has gained widespread use in CPU-based raytracers and is regarded as the best general-purpose acceleration structure. We demonstrate two kd-tree traversal algorithms suitable for GPU implementation and integrate them into a streaming raytracer. We show that for scenes with many objects at different scales, our kd-tree algorithms are up to 8 times faster than a uniform grid. In addition, we identify load balancing and input data recirculation as two fundamental sources of inefficiency when raytracing on current graphics hardware.

Recent advances in multi-core and many-core processors requires programmers to exploit an increasing amount of parallelism from their applications. Data parallel languages such as CUDA and OpenCL make it possible to take advantage of such processors, but still require a large amount of effort from programmers.
 A number of parallelizing source-to-source compilers have recently been developed to ease programming of multi-core and many-core processors. This work presents and evaluates a number of such tools, focused in particular on C-to-CUDA transformations targeting GPUs. We compare these tools both qualitatively and quantitatively to each other and identify their strengths and weaknesses.
 In this paper, we address the weaknesses by presenting a new classification of algorithms. This classification is used in a new source-to-source compiler, which is based on the algorithmic skeletons technique. The compiler generates target code based on skeletons of parallel structures, which can be seen as parameterisable library implementations for a set of algorithm classes. We furthermore demonstrate that the presented compiler requires little modifications to the original sequential source code, generates readable code for further fine-tuning, and delivers superior performance compared to other tools for a set of 8 image processing kernels.

Crowd anomaly detection is a key research area in vision-based surveillance. Most of the crowd anomaly detection algorithms are either too slow, bulky, or power-hungry to be applicable for battery-powered surveillance cameras. In this paper, we present a new crowd anomaly detection algorithm. The proposed algorithm creates a feature for every superpixel that includes the contribution from the neighboring superpixels only if their direction of motion conforms with the dominant direction of motion in the region. We also propose using univariate Gaussian discriminant analysis with the K-means algorithm for classification. Our method provides superior accuracy over numerous deep learning-based and handcrafted feature-based approaches. We also present a low-power FPGA implementation of the proposed method. The algorithm is developed such that features are extracted over non-overlapping pixels. This allows gating inputs to numerous modules resulting in higher power efficiency. The maximum energy required per pixel is 2.43 nJ in our implementation. 126.65 Mpixels can be processed per second by the proposed implementation. The speed, power, and accuracy performance of our method make it competitive for surveillance applications, especially battery-powered surveillance cameras.

Large graphs involving millions of vertices are common in many practical applications and are challenging to process. Practical-time implementations using high-end computers are reported but are accessible only to a few. Graphics Processing Units (GPUs) of today have high computation power and low price. They have a restrictive programming model and are tricky to use. The G80 line of Nvidia GPUs can be treated as a SIMD processor array using the CUDA programming model. We present a few fundamental algorithms – including breadth first search, single source shortest path, and all-pairs shortest path – using CUDA on large graphs. We can compute the single source shortest path on a 10 million vertex graph in 1.5 seconds using the Nvidia 8800GTX GPU costing $600. In some cases optimal sequential algorithm is not the fastest on the GPU architecture. GPUs have great potential as high-performance co-processors.

In this article, we describe how to ease memory management between a Central Processing Unit (CPU) and one or multiple discrete Graphic Processing Units (GPUs) by architecting a novel hardware-based Unified Memory Hierarchy (UMH). Adopting UMH, a GPU accesses the CPU memory only if it does not find its required data in the directories associated with its high-bandwidth memory, or the NMOESI coherency protocol limits the access to that data. Using UMH with NMOESI improves performance of a CPU-multiGPU system by at least 1.92 × in comparison to alternative software-based approaches. It also allows the CPU to access GPUs modified data by at least 13 × faster.

As applications such as Apple Siri, Google Now, Microsoft Cortana, and Amazon Echo continue to gain traction, web-service companies are adopting large deep neural networks (DNN) for machine learning challenges such as image processing, speech recognition, natural language processing, among others. A number of open questions arise as to the design of a server platform specialized for DNN and how modern warehouse scale computers (WSCs) should be outfitted to provide DNN as a service for these applications.
 In this paper, we present DjiNN, an open infrastructure for DNN as a service in WSCs, and Tonic Suite, a suite of 7 end-to-end applications that span image, speech, and language processing. We use DjiNN to design a high throughput DNN system based on massive GPU server designs and provide insights as to the varying characteristics across applications. After studying the throughput, bandwidth, and power properties of DjiNN and Tonic Suite, we investigate several design points for future WSC architectures. We investigate the total cost of ownership implications of having a WSC with a disaggregated GPU pool versus a WSC composed of homogeneous integrated GPU servers. We improve DNN throughput by over 120x for all but one application (40x for Facial Recognition) on an NVIDIA K40 GPU. On a GPU server composed of 8 NVIDIA K40s, we achieve near-linear scaling (around 1000x throughput improvement) for 3 of the 7 applications. Through our analysis, we also find that GPU-enabled WSCs improve total cost of ownership over CPU-only designs by 4-20x, depending on the composition of the workload

High Efficiency Video Coding (HEVC) uses a very flexible tree structure to organize coding units, which leads to a superior coding efficiency compared with previous video coding standards. However, such a flexible coding unit tree structure also places a great challenge for encoders. In order to fully exploit the coding efficiency brought by this structure, huge amount of computational complexity is needed for an encoder to decide the optimal coding unit tree for each image block. One way to achieve this is to use parallel computing enabled by many-core processors. In this paper, we analyze the challenge to use many-core processors to make coding unit tree decision. Through in-depth understanding of the dependency among different coding units, we propose a parallel framework to decide coding unit trees. Experimental results show that, on the Tile64 platform, our proposed method achieves averagely more than 11 and 16 times speedup for 1920x1080 and 2560x1600 video sequences, respectively, without any coding efficiency degradation.

Emerging 3D stacked memory systems provide significantly more bandwidth than current DDR modules. However, general purpose processors do not take full advantage of these resources offered by the memory modules. Taking advantage of the increased bandwidth requires the use of specialized processing units. In this paper, we evaluate the benefits of placing hardware accelerators at the bottom layer of a 3D stacked memory system compared to accelerators that are placed external to the memory stack. Our evaluation of the design using cycle-accurate simulation and RTL synthesis shows that, for important data intensive kernels, near-memory accelerators inside a single 3D memory package provide 3x-13x speedup over a Quad-core Xeon processor. Most of the benefits are from the application of accelerators, as the near-memory configurations provide marginal benefits compared to the same number of accelerators placed on a die external to the memory package. This comparable performance for external accelerators is due to the high bandwidth afforded by the high-speed off-chip links. On the other hand, near-memory accelerators consume 7%-39% less energy than the external accelerators.

The massive parallelism of graphics processing units (GPUs) offers tremendous performance in many high-performance computing applications. While dense linear algebra readily maps to such platforms, harnessing this potential for sparse matrix computations presents additional challenges. Given its role in iterative methods for solving sparse linear systems and eigenvalue problems, sparse matrix-vector multiplication (SpMV) is of singular importance in sparse linear algebra. In this paper we discuss data structures and algorithms for SpMV that are efficiently implemented on the CUDA platform for the fine-grained parallel architecture of the GPU. Given the memory-bound nature of SpMV, we emphasize memory bandwidth efficiency and compact storage formats. We consider a broad spectrum of sparse matrices, from those that are well-structured and regular to highly irregular matrices with large imbalances in the distribution of nonzeros per matrix row. We develop methods to exploit several common forms of matrix structure while offering alternatives which accommodate greater irregularity. On structured, grid-based matrices we achieve performance of 36 GFLOP/s in single precision and 16 GFLOP/s in double precision on a GeForce GTX 280 GPU. For unstructured finite-element matrices, we observe performance in excess of 15 GFLOP/s and 10 GFLOP/s in single and double precision respectively. These results compare favorably to prior state-of-the-art studies of SpMV methods on conventional multicore processors. Our double precision SpMV performance is generally two and a half times that of a Cell BE with 8 SPEs and more than ten times greater than that of a quad-core Intel Clovertown system.


Question: Mobile device management for secure and manageable health data collection in resource-constrained regions.

This paper explores the evolution of data collection methods in social programs, particularly the transition from traditional pen-paper surveys to mobile-based systems. The widespread adoption of smartphones, coupled with affordable mobile connectivity and the availability of robust data collection apps that can function even in areas with limited connectivity, has prompted this shift. We present an improved version of the Open Data Kit (ODK), a popular mobile data collection tool, which now includes features like pre-filling and validation via SMS. These enhancements were driven by practical needs observed in a project aimed at disseminating information to beneficiaries of the National Rural Employment Guarantee Scheme (NREGS), an Indian government initiative. The modified ODK is currently being utilized in two districts across two Indian states. Early findings from one deployment reveal a significant reduction in errors—16.1%—even with only 8% of the form fields pre-filled. Moreover, the time required to complete a survey decreased with the pre-filling option. Results from another deployment indicate that 35% of the pre-filled forms contained discrepancies or updated information compared to government records, highlighting the tool's effectiveness in identifying and correcting outdated data.

In the realm of health data collection in under-resourced areas, mobile device administration plays a crucial role in ensuring secure and manageable data acquisition. This study highlights the adaptation of the Open Data Kit (ODK), a mobile data collection application, to better suit the needs of health programs. The introduction of features such as pre-filling and validation through SMS has been driven by the practical requirements of collecting demographic and program-related information for a health initiative in India. The enhanced ODK is currently being tested in two districts across two states, demonstrating its potential to reduce data collection errors and improve efficiency. Initial results from one deployment show a 16.1% decrease in errors with just 8% of fields pre-filled, and the time per survey has also been reduced. Additionally, the comparison of pre-filled forms with government records in another deployment reveals that 35% contained updated or corrected information, illustrating the tool's capacity to enhance data accuracy in real-world health data collection scenarios.

Mobile cloud computing (MCC) has become a significant paradigm for bringing the benefits of cloud computing to mobile devices’ proximity. Service availability along with performance enhancement and energy efficiency are primary targets in MCC. This paper proposes a code offloading framework, called mCloud, which consists of mobile devices, nearby cloudlets and public cloud services, to improve the performance and availability of the MCC services. The effect of the mobile device context (e.g., network conditions) on offloading decisions is studied by proposing a context-aware offloading decision algorithm aiming to provide code offloading decisions at runtime on selecting wireless medium and appropriate cloud resources for offloading. We also investigate failure detection and recovery policies for our mCloud system. We explain in details the design and implementation of the mCloud prototype framework. We conduct real experiments on the implemented system to evaluate the performance of the algorithm. Results indicate the system and embedded decision algorithm are able to provide decisions on selecting wireless medium and cloud resources based on different context of the mobile devices, and achieve significant reduction on makespan and energy, with the improved service availability when compared with existing offloading schemes.

Patient tracking is an important component toward creating smart cities. In this demo we use Bluetooth Low Energy beacons and single board computers to track patients in the emerging field of smart care facilities. Our model utilizes a fixed scanner moving transmitter method for wireless tracking of patients through the facility. The data collected by all scanners is stored within a central database that is designed to be efficiently queried. We show how inexpensive components in conjunction with free open source software can be used to implement a patient tracking system. We focus on the pipeline between acquisition and display of the location data. Additionally, we also discuss the manipulation of the data required for usability, and optional filtering operations that improve accuracy.

This paper presents an Internet of Things (IoT) approach to Human Activity Recognition (HAR) using remote monitoring of vital signs in the context of a healthcare system for self-managed chronic heart patients. Our goal is to create a HAR-IoT system using learning algorithms to infer the activity done within 4 categories (lie, sit, walk and run) as well as the time consumed performing these activities and, finally giving feedback during and after the activity. Alike in this work, we provide a comprehensive insight on the cloud-based system implemented and the conclusions after implementing two different learning algorithms and the results of the overall system for larger implementations.

Miniaturization of devices has brought a lot of improvements in the healthcare delivery as a result of advancenments in Integrated circuit technologies. As a result, proper and effective way of analyzing various body conditions and diseases can be achieved. When the heart muscles repolarize and depolarize, it generates electrical impulses which could help the doctor or the health professional to diagnose various heart abnormalities. The aim of this project is to design and develop a miniaturized ECG system displayed on both PC and Tablet for preliminary diagnoses of the heart. This system utilizes a programmable single-chip microcontroller for analysing the biosignals to indicate the condition of the heart. The system is incomporated with alarm systems which prompt the doctor if there is any abnormality from a patient's heart. These abnormalities could be bradycardia or tachycardia. This system is built with a provision of enabling wireless transmission of ECG signals to a PC or TABLET through BLUETOOTH and ANDROID PLATFORM. The android application can be installed and tested on any smart phone or tablet and screen resolution can be adjusted later as per requirement. This helps the doctor to have visual description of the patient ECG without the need of mounted monitors. The experimental results show that device is clinically useful, compact, cost effective and user friendly.

Resource and information protection plays a relevant role in distributed systems like the ones present in the Internet of Things (IoT). Authorization frameworks like RBAC and ABAC do not provide scalable, manageable, effective, and efficient mechanisms to support distributed systems with many interacting services and are not able to effectively support the dynamicity and scaling needs of IoT contexts that envisage a potentially unbound number of sensors, actuators and related resources, services and subjects, as well as a more relevance of short-lived, unplanned and dynamic interaction patterns. Furthermore, as more end-users start using smart devices (e.g. smart phones, smart home appliances, etc.) the need to have more scalable, manageable, understandable and easy to use access control mechanisms increases. This paper describes a capability based access control system that enterprises, or even individuals, can use to manage their own access control processes to services and information. The proposed mechanism supports rights delegation and a more sophisticated access control customization. The proposed approach is being developed within the European FP7 IoT@Work project to manage access control to some of the project’s services deployed in the shop floor.

In Europe, in a context of growing population and decreasing resources, ageing related diseases represent one of the most relevant challenges in terms of healthcare organization complexity, plus care levels and system financing balancing. Nowadays there are several researches that are studying the application of the IoT (Internet of Things) paradigm in the e-health field. This paper explains how a solution, built on the top of the VIRTUS IoT middleware, provides a valid alternative to current IoT solutions, which are mainly based on SOA (Service Oriented Architecture). VIRTUS leverage an Instant Messaging protocol (XMPP) to guarantee a (near) real-time, secure and reliable communication channel among heterogeneous devices. The presented development has been exploited in a healthcare case study: an implementation of a cost-savvy remote body movement monitoring system, aimed at classify daily patients' activities, designed as a modular architecture and deployed in a large scale scenario. The paper analyzes the features offered by the VIRTUS middleware, if used within a e-health solution, providing a comparison with other well-known systems.

As mobile computing has been developed for decades, a new model for mobile computing, namely, mobile cloud computing, emerges resulting from the marriage of powerful yet affordable mobile devices and cloud computing. In this paper we survey existing mobile cloud computing applications, as well as speculate future generation mobile cloud computing applications. We provide insights for the enabling technologies and challenges that lie ahead for us to move forward from mobile computing to mobile cloud computing for building the next generation mobile cloud applications. For each of the challenges, we provide a survey of existing solutions, identify research gaps, and suggest future research areas.

eHealth is the provision of healthcare with the inclusion of telecommunication techniques. This project looks at the construction of a simple device that will be capable of transferring the data of a patient's vital signs to a remote device wirelessly. The necessity of this project is to alleviate the difficulty that is encountered by medical experts in monitoring multiple patients simultaneously. This project will enable them to observe patients without having to be physically present at their bedside, be it in the hospital or in their home. A patient's body temperature, heart rate and electrocardiography (ECG) are transferred wirelessly through an agent such as Bluetooth technology.

Wireless body area networks (BANs) have drawn much attention from research community and industry in recent years. Multimedia healthcare services provided by BANs can be available to anyone, anywhere, and anytime seamlessly. A critical issue in BANs is how to preserve the integrity and privacy of a person's medical data over wireless environments in a resource efficient manner. This paper presents a novel key agreement scheme that allows neighboring nodes in BANs to share a common key generated by electrocardiogram (ECG) signals. The improved Jules Sudan (IJS) algorithm is proposed to set up the key agreement for the message authentication. The proposed ECG-IJS key agreement can secure data commnications over BANs in a plug-n-play manner without any key distribution overheads. Both the simulation and experimental results are presented, which demonstrate that the proposed ECG-IJS scheme can achieve better security performance in terms of serval performance metrics such as false acceptance rate (FAR) and false rejection rate (FRR) than other existing approaches. In addition, the power consumption analysis also shows that the proposed ECG-IJS scheme can achieve energy efficiency for BANs.

With the adoption of 2G and 3G cellular network technologies, mobile phones now have the bandwidth capability to stream data back to monitoring stations in real-time. Our paper describes the design and evaluation of a Bluetooth electrocardiogram sensor that transmits medical data to a cell phone. This data is displayed and stored on the phone. Future development of the system will relay this data over a cellular GPRS network. The current system provides a low cost and lightweight alternative to existing EKG event monitors. The final GPRS connected system will provide continuous monitoring of a patient 's heart anywhere cellular coverage is available


Question: A mobile device administration strategy to ensure secure and manageable health data collection in under-resourced regions.

DakNet: Paving the Way for Affordable Broadband in Underdeveloped Areas DakNet, a pioneering initiative, is revolutionizing digital communication in remote and under-resourced regions by offering ultra-low-cost connectivity options. This breakthrough solution enables villages to bypass the prohibitive costs associated with conventional connectivity methods and initiate the development of a comprehensive broadband wireless infrastructure. The question remains: how can we transition from e-governance to a sustainable, market-driven model of universal broadband connectivity that is affordable for local populations? DakNet, an ad hoc network that harnesses wireless technology to provide asynchronous digital connectivity, serves as a compelling example of how combining wireless and asynchronous services can lead to the establishment of universal broadband connectivity. Demonstrating its effectiveness, DakNet has been successfully implemented in isolated areas of India and Cambodia, delivering connectivity at a cost that is significantly lower—by two orders of magnitude—compared to traditional landline solutions. This approach not only addresses the immediate need for connectivity but also lays the groundwork for a future where digital access is not a luxury but a basic and affordable service for all.

Mobile systems have limited resources, such as battery life, network bandwidth, storage capacity, and processor performance. These restrictions may be alleviated by computation of f loading: sending heavy computation to resourceful servers and receiving the results from these servers. Many issues related to offloading have been investigated in the past decade. This survey paper provides an overview of the background, techniques, systems, and research areas for offloading computation. We also describe directions for future research.

This research addresses the implementation of encryption and digital signature technique for electronic health record to prevent cybercrime problem such as robbery, modification and unauthorized access. In this research, RSA 2048-bit algorithm, AES 256-bit and SHA 256 will be implemented in Java programming. Secure Electronic Health Record Information (SEHR) application design is intended to combine given services, such as confidentiality, integrity, authentication, and non-repudiation. Cryptography is used to ensure the file records and electronic documents for detailed information on the medical past, present and future forecasts that have been given only for the patients. The document will be encrypted using an encryption algorithm based on NIST Standard. In the application, there are two schemes, namely the protection and verification scheme. This research uses black-box testing and white-box testing to test the software input, output, and code without testing the process and design that occurs in the system. We demonstrated the implementation of cryptography in Secure Electronic Health Record Information (SEHR). The implementation of encryption and digital signature in this research can prevent archive thievery which is shown on implementation and is proven on the test.

With the progress in mobile computing, web services are increasingly delivered to their users through mobile apps, instead of web browsers. However, unlike the browser, which enforces origin-based security policies to mediate the interactions between the web content from different sources, today's mobile OSes do not have a comparable security mechanism to control the cross-origin communications between apps, as well as those between an app and the web. As a result, a mobile user's sensitive web resources could be exposed to the harms from a malicious origin. In this paper, we report the first systematic study on this mobile cross-origin risk. Our study inspects the main cross-origin channels on Android and iOS, including intent, scheme and web-accessing utility classes, and further analyzes the ways popular web services (e.g., Facebook, Dropbox, etc.) and their apps utilize those channels to serve other apps. The research shows that lack of origin-based protection opens the door to a wide spectrum of cross-origin attacks. These attacks are unique to mobile platforms, and their consequences are serious: for example, using carefully designed techniques for mobile cross-site scripting and request forgery, an unauthorized party can obtain a mobile user's Facebook/Dropbox authentication credentials and record her text input. We report our findings to related software vendors, who all acknowledged their importance. To address this threat, we designed an origin-based protection mechanism, called Morbs, for mobile OSes. Morbs labels every message with its origin information, lets developers easily specify security policies, and enforce the policies on the mobile channels based on origins. Our evaluation demonstrates the effectiveness of our new technique in defeating unauthorized origin crossing, its efficiency and the convenience for the developers to use such protection.

With the Internet of Things, sensors are becoming ever more ubiquitous, but interacting with them continues to present numerous challenges, particularly for applications running on resource-constrained devices like smartphones. The SOUL abstractions in this paper address two issues faced by such applications: (1) access to sensors with the levels of convenience needed for their ubiquitous, dynamic use, and only by parties authorized to do so, and (2) scalability in sensor access, given today's multitude of sensors. Toward this end, SOUL, first, introduces a new abstraction for the applications to transparently and uniformly access both on-device and ambient sensors with associated actuators. Second, potentially expensive sensor-related processing needs not just occur on smartphones, but can also leverage edge-and remote-cloud resources. Finally, SOUL provides access control methods that permit users to easily define access permissions for sensors, which leverages users' social ties and captures the context in which access requests are made. SOUL demonstrates that the applications on Android platforms can scale the use of 100s of sensors with performance and energy efficiency.

This study of mobile persuasion system explores the use of a mobile phone, when attached to an everyday object used by an everyday behavior, becomes a tool to sense and influence that behavior. This mobile persuasion system, called Playful Bottle system, makes use of a mobile phone attached to an everyday drinking mug and motivates office workers to drink healthy quantities of water. A camera and accelerometer sensors in the phone are used to build a vision/motion-based water intake tracker to detect the amount and regularity of water consumed by the user. Additionally, the phone includes hydration games in which natural drinking actions are used as game input. Two hydration games are developed: a single-user TreeGame with automated computer reminders and a multi-user ForestGame with computer-mediated social reminders from members of the group playing the game. Results from 7-week user study with 16 test subjects suggest that both hydration games are effective for encouraging adequate and regular water intake by users. Additionally, results of this study suggest that adding social reminders to the hydration game is more effective than system reminders alone.

The current evolution of the traditional medical model toward the participatory medicine can be boosted by the Internet of Things (IoT) paradigm involving sensors (environmental, wearable, and implanted) spread inside domestic environments with the purpose to monitor the user's health and activate remote assistance. RF identification (RFID) technology is now mature to provide part of the IoT physical layer for the personal healthcare in smart environments through low-cost, energy-autonomous, and disposable sensors. It is here presented a survey on the state-of-the-art of RFID for application to body centric systems and for gathering information (temperature, humidity, and other gases) about the user's living environment. Many available options are described up to the application level with some examples of RFID systems able to collect and process multichannel data about the human behavior in compliance with the power exposure and sanitary regulations. Open challenges and possible new research trends are finally discussed.

Rich client-side applications written in HTML5 proliferate diverse platforms such as mobile devices, commodity PCs, and the web platform. These client-side HTML5 applications are increasingly accessing sensitive data, including users’ personal and social data, sensor data, and capability-bearing tokens. To fulfill their security and privacy guarantees, these applications need to maintain certain data-confinement invariants. These invariants are not explicitly stated in today’s HTML5 applications and are enforced using ad-hoc mechanisms. The complexity of web applications, coupled with hard-to-analyze client-side languages, leads to low-assurance data-confinement mechanisms in which the whole application needs to be in the TCB to ensure data-confinement in-

The need for more security on mobile devices is increasing with new functionalities and features made available. To improve the device security we propose gait recognition as a protection mechanism. Unlike previous work on gait recognition, which was based on the use of video sources, floor sensors or dedicated high-grade accelerometers, this paper reports the performance when the data is collected with a commercially available mobile device containing low-grade accelerometers. To be more specific, the used mobile device is the Google G1 phone containing the AK8976A embedded accelerometer sensor. The mobile device was placed at the hip on each volunteer to collect gait data. Preproccesing, cycle detection and recognition-analysis were applied to the acceleration signal. The performance of the system was evaluated having 51 volunteers and resulted in an equal error rate (EER) of 20%.

As Information and Communication Technologies (ICT) are developing frequently, new learning approaches have been introduced to facilitate teaching and learning processes. Mobile devices are growing in popularity and there has been an increasing interest in their potential as innovative tools for learning. Mobile learning or shortly (M-learning) is a new learning approach intending to use mobile devices such as laptops, smart phones and personal digital assistant (PDA) in learning process in any place and at any time. M-learning application needs to be designed in a way that considers the special features and constraints of mobile devices such as screen size, available storage, processor speed and battery life. This paper explores the existing design approaches for M-learning and highlights their main limitations. As a step forward in this direction, this paper also proposes a new design approach for M-learning applications focusing mainly on three main aspects: learner, learning content and technology. The approach consists of three phases: starting dimensions (SD) phase, M-learning Development (MLD) phase and Learning Content Design (LCD) phase. Finally, this paper provides a case study scenario to demonstrate the feasibility of the proposed approach.

Nowadays, new tools and technologies are emerging rapidly. They are often used cross-culturally before being tested for suitability and validity. However, they must be validated to ensure that they work with all users, not just part of them. Mobile banking (as a new technology tool) has been introduced assuming that it performs well concerning authentication, among all members of the society. Our research aimed to evaluate authentication mobile banking user acceptance, through Technology Acceptance Model (TAM), in Arabic countries, namely Yemen. The results confirm the previous studies that have shown the importance of perceived ease of use and perceived usefulness. Furthermore, perceived ease of use plays a determinant role. KeywordsTechnology acceptance models; Mobile Banking;